tests: Avoid 'do/while(false); ' in vhost-user-bridge
[qemu/ar7.git] / hw / pci-host / gpex.c
blobedf305b1fda2aa2d17b2679d2b1c2e007c6d451b
1 /*
2 * QEMU Generic PCI Express Bridge Emulation
4 * Copyright (C) 2015 Alexander Graf <agraf@suse.de>
6 * Code loosely based on q35.c.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
26 * Check out these documents for more information on the device:
28 * http://www.kernel.org/doc/Documentation/devicetree/bindings/pci/host-generic-pci.txt
29 * http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
31 #include "qemu/osdep.h"
32 #include "hw/hw.h"
33 #include "hw/pci-host/gpex.h"
35 /****************************************************************************
36 * GPEX host
39 static void gpex_set_irq(void *opaque, int irq_num, int level)
41 GPEXHost *s = opaque;
43 qemu_set_irq(s->irq[irq_num], level);
46 int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
48 if (index >= GPEX_NUM_IRQS) {
49 return -EINVAL;
52 s->irq_num[index] = gsi;
53 return 0;
56 static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
58 PCIINTxRoute route;
59 GPEXHost *s = opaque;
60 int gsi = s->irq_num[pin];
62 route.irq = gsi;
63 if (gsi < 0) {
64 route.mode = PCI_INTX_DISABLED;
65 } else {
66 route.mode = PCI_INTX_ENABLED;
69 return route;
72 static void gpex_host_realize(DeviceState *dev, Error **errp)
74 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
75 GPEXHost *s = GPEX_HOST(dev);
76 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
77 PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
78 int i;
80 pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
81 memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
82 memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
84 sysbus_init_mmio(sbd, &pex->mmio);
85 sysbus_init_mmio(sbd, &s->io_mmio);
86 sysbus_init_mmio(sbd, &s->io_ioport);
87 for (i = 0; i < GPEX_NUM_IRQS; i++) {
88 sysbus_init_irq(sbd, &s->irq[i]);
89 s->irq_num[i] = -1;
92 pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq,
93 pci_swizzle_map_irq_fn, s, &s->io_mmio,
94 &s->io_ioport, 0, 4, TYPE_PCIE_BUS);
96 qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
97 pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
98 qdev_init_nofail(DEVICE(&s->gpex_root));
101 static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
102 PCIBus *rootbus)
104 return "0000:00";
107 static void gpex_host_class_init(ObjectClass *klass, void *data)
109 DeviceClass *dc = DEVICE_CLASS(klass);
110 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
112 hc->root_bus_path = gpex_host_root_bus_path;
113 dc->realize = gpex_host_realize;
114 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
115 dc->fw_name = "pci";
118 static void gpex_host_initfn(Object *obj)
120 GPEXHost *s = GPEX_HOST(obj);
121 GPEXRootState *root = &s->gpex_root;
123 object_initialize(root, sizeof(*root), TYPE_GPEX_ROOT_DEVICE);
124 object_property_add_child(obj, "gpex_root", OBJECT(root), NULL);
125 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
126 qdev_prop_set_bit(DEVICE(root), "multifunction", false);
129 static const TypeInfo gpex_host_info = {
130 .name = TYPE_GPEX_HOST,
131 .parent = TYPE_PCIE_HOST_BRIDGE,
132 .instance_size = sizeof(GPEXHost),
133 .instance_init = gpex_host_initfn,
134 .class_init = gpex_host_class_init,
137 /****************************************************************************
138 * GPEX Root D0:F0
141 static const VMStateDescription vmstate_gpex_root = {
142 .name = "gpex_root",
143 .version_id = 1,
144 .minimum_version_id = 1,
145 .fields = (VMStateField[]) {
146 VMSTATE_PCI_DEVICE(parent_obj, GPEXRootState),
147 VMSTATE_END_OF_LIST()
151 static void gpex_root_class_init(ObjectClass *klass, void *data)
153 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
154 DeviceClass *dc = DEVICE_CLASS(klass);
156 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
157 dc->desc = "QEMU generic PCIe host bridge";
158 dc->vmsd = &vmstate_gpex_root;
159 k->vendor_id = PCI_VENDOR_ID_REDHAT;
160 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_HOST;
161 k->revision = 0;
162 k->class_id = PCI_CLASS_BRIDGE_HOST;
164 * PCI-facing part of the host bridge, not usable without the
165 * host-facing part, which can't be device_add'ed, yet.
167 dc->user_creatable = false;
170 static const TypeInfo gpex_root_info = {
171 .name = TYPE_GPEX_ROOT_DEVICE,
172 .parent = TYPE_PCI_DEVICE,
173 .instance_size = sizeof(GPEXRootState),
174 .class_init = gpex_root_class_init,
175 .interfaces = (InterfaceInfo[]) {
176 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
177 { },
181 static void gpex_register(void)
183 type_register_static(&gpex_root_info);
184 type_register_static(&gpex_host_info);
187 type_init(gpex_register)