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keymap: record multiple keysym -> keycode mappings
[qemu/ar7.git] / hw / ppc / spapr.c
blob83c9d66dd56f5f3e50c97a5b1715125271ce3a67
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
32 #include "hw/hw.h"
33 #include "qemu/log.h"
34 #include "hw/fw-path-provider.h"
35 #include "elf.h"
36 #include "net/net.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/cpus.h"
40 #include "sysemu/hw_accel.h"
41 #include "kvm_ppc.h"
42 #include "migration/misc.h"
43 #include "migration/global_state.h"
44 #include "migration/register.h"
45 #include "mmu-hash64.h"
46 #include "mmu-book3s-v3.h"
47 #include "cpu-models.h"
48 #include "qom/cpu.h"
49
50 #include "hw/boards.h"
51 #include "hw/ppc/ppc.h"
52 #include "hw/loader.h"
53
54 #include "hw/ppc/fdt.h"
55 #include "hw/ppc/spapr.h"
56 #include "hw/ppc/spapr_vio.h"
57 #include "hw/pci-host/spapr.h"
58 #include "hw/ppc/xics.h"
59 #include "hw/pci/msi.h"
60
61 #include "hw/pci/pci.h"
62 #include "hw/scsi/scsi.h"
63 #include "hw/virtio/virtio-scsi.h"
64 #include "hw/virtio/vhost-scsi-common.h"
65
66 #include "exec/address-spaces.h"
67 #include "hw/usb.h"
68 #include "qemu/config-file.h"
69 #include "qemu/error-report.h"
70 #include "trace.h"
71 #include "hw/nmi.h"
72 #include "hw/intc/intc.h"
73
74 #include "hw/compat.h"
75 #include "qemu/cutils.h"
76 #include "hw/ppc/spapr_cpu_core.h"
77
78 #include <libfdt.h>
79
80 /* SLOF memory layout:
81 *
82 * SLOF raw image loaded at 0, copies its romfs right below the flat
83 * device-tree, then position SLOF itself 31M below that
84 *
85 * So we set FW_OVERHEAD to 40MB which should account for all of that
86 * and more
87 *
88 * We load our kernel at 4M, leaving space for SLOF initial image
89 */
90 #define FDT_MAX_SIZE 0x100000
91 #define RTAS_MAX_SIZE 0x10000
92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
93 #define FW_MAX_SIZE 0x400000
94 #define FW_FILE_NAME "slof.bin"
95 #define FW_OVERHEAD 0x2800000
96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
97
98 #define MIN_RMA_SLOF 128UL
99
100 #define PHANDLE_XICP 0x00001111
101
102 /* These two functions implement the VCPU id numbering: one to compute them
103 * all and one to identify thread 0 of a VCORE. Any change to the first one
104 * is likely to have an impact on the second one, so let's keep them close.
105 */
106 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index)
107 {
108 return
109 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
110 }
111 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr,
112 PowerPCCPU *cpu)
113 {
114 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
115 }
116
117 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
118 const char *type_ics,
119 int nr_irqs, Error **errp)
120 {
121 Error *local_err = NULL;
122 Object *obj;
123
124 obj = object_new(type_ics);
125 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
126 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
127 &error_abort);
128 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
129 if (local_err) {
130 goto error;
131 }
132 object_property_set_bool(obj, true, "realized", &local_err);
133 if (local_err) {
134 goto error;
135 }
136
137 return ICS_SIMPLE(obj);
138
139 error:
140 error_propagate(errp, local_err);
141 return NULL;
142 }
143
144 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
145 {
146 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
147 * and newer QEMUs don't even have them. In both cases, we don't want
148 * to send anything on the wire.
149 */
150 return false;
151 }
152
153 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
154 .name = "icp/server",
155 .version_id = 1,
156 .minimum_version_id = 1,
157 .needed = pre_2_10_vmstate_dummy_icp_needed,
158 .fields = (VMStateField[]) {
159 VMSTATE_UNUSED(4), /* uint32_t xirr */
160 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
161 VMSTATE_UNUSED(1), /* uint8_t mfrr */
162 VMSTATE_END_OF_LIST()
163 },
164 };
165
166 static void pre_2_10_vmstate_register_dummy_icp(int i)
167 {
168 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
169 (void *)(uintptr_t) i);
170 }
171
172 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
173 {
174 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
175 (void *)(uintptr_t) i);
176 }
177
178 static int xics_max_server_number(sPAPRMachineState *spapr)
179 {
180 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads);
181 }
182
183 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
184 {
185 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
186 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
187
188 if (kvm_enabled()) {
189 if (machine_kernel_irqchip_allowed(machine) &&
190 !xics_kvm_init(spapr, errp)) {
191 spapr->icp_type = TYPE_KVM_ICP;
192 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
193 }
194 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
195 error_prepend(errp, "kernel_irqchip requested but unavailable: ");
196 return;
197 }
198 }
199
200 if (!spapr->ics) {
201 xics_spapr_init(spapr);
202 spapr->icp_type = TYPE_ICP;
203 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
204 if (!spapr->ics) {
205 return;
206 }
207 }
208
209 if (smc->pre_2_10_has_unused_icps) {
210 int i;
211
212 for (i = 0; i < xics_max_server_number(spapr); i++) {
213 /* Dummy entries get deregistered when real ICPState objects
214 * are registered during CPU core hotplug.
215 */
216 pre_2_10_vmstate_register_dummy_icp(i);
217 }
218 }
219 }
220
221 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
222 int smt_threads)
223 {
224 int i, ret = 0;
225 uint32_t servers_prop[smt_threads];
226 uint32_t gservers_prop[smt_threads * 2];
227 int index = spapr_get_vcpu_id(cpu);
228
229 if (cpu->compat_pvr) {
230 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
231 if (ret < 0) {
232 return ret;
233 }
234 }
235
236 /* Build interrupt servers and gservers properties */
237 for (i = 0; i < smt_threads; i++) {
238 servers_prop[i] = cpu_to_be32(index + i);
239 /* Hack, direct the group queues back to cpu 0 */
240 gservers_prop[i*2] = cpu_to_be32(index + i);
241 gservers_prop[i*2 + 1] = 0;
242 }
243 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(servers_prop));
245 if (ret < 0) {
246 return ret;
247 }
248 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
249 gservers_prop, sizeof(gservers_prop));
250
251 return ret;
252 }
253
254 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
255 {
256 int index = spapr_get_vcpu_id(cpu);
257 uint32_t associativity[] = {cpu_to_be32(0x5),
258 cpu_to_be32(0x0),
259 cpu_to_be32(0x0),
260 cpu_to_be32(0x0),
261 cpu_to_be32(cpu->node_id),
262 cpu_to_be32(index)};
263
264 /* Advertise NUMA via ibm,associativity */
265 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
266 sizeof(associativity));
267 }
268
269 /* Populate the "ibm,pa-features" property */
270 static void spapr_populate_pa_features(sPAPRMachineState *spapr,
271 PowerPCCPU *cpu,
272 void *fdt, int offset,
273 bool legacy_guest)
274 {
275 CPUPPCState *env = &cpu->env;
276 uint8_t pa_features_206[] = { 6, 0,
277 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
278 uint8_t pa_features_207[] = { 24, 0,
279 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
280 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
281 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
282 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
283 uint8_t pa_features_300[] = { 66, 0,
284 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
285 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
286 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
287 /* 6: DS207 */
288 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
289 /* 16: Vector */
290 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
291 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
292 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
293 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
294 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
295 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
296 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
297 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
298 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
299 /* 42: PM, 44: PC RA, 46: SC vec'd */
300 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
301 /* 48: SIMD, 50: QP BFP, 52: String */
302 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
303 /* 54: DecFP, 56: DecI, 58: SHA */
304 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
305 /* 60: NM atomic, 62: RNG */
306 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
307 };
308 uint8_t *pa_features = NULL;
309 size_t pa_size;
310
311 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
312 pa_features = pa_features_206;
313 pa_size = sizeof(pa_features_206);
314 }
315 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
316 pa_features = pa_features_207;
317 pa_size = sizeof(pa_features_207);
318 }
319 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
320 pa_features = pa_features_300;
321 pa_size = sizeof(pa_features_300);
322 }
323 if (!pa_features) {
324 return;
325 }
326
327 if (env->ci_large_pages) {
328 /*
329 * Note: we keep CI large pages off by default because a 64K capable
330 * guest provisioned with large pages might otherwise try to map a qemu
331 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
332 * even if that qemu runs on a 4k host.
333 * We dd this bit back here if we are confident this is not an issue
334 */
335 pa_features[3] |= 0x20;
336 }
337 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
338 pa_features[24] |= 0x80; /* Transactional memory support */
339 }
340 if (legacy_guest && pa_size > 40) {
341 /* Workaround for broken kernels that attempt (guest) radix
342 * mode when they can't handle it, if they see the radix bit set
343 * in pa-features. So hide it from them. */
344 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
345 }
346
347 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
348 }
349
350 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
351 {
352 int ret = 0, offset, cpus_offset;
353 CPUState *cs;
354 char cpu_model[32];
355 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
356
357 CPU_FOREACH(cs) {
358 PowerPCCPU *cpu = POWERPC_CPU(cs);
359 DeviceClass *dc = DEVICE_GET_CLASS(cs);
360 int index = spapr_get_vcpu_id(cpu);
361 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
362
363 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
364 continue;
365 }
366
367 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
368
369 cpus_offset = fdt_path_offset(fdt, "/cpus");
370 if (cpus_offset < 0) {
371 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
372 if (cpus_offset < 0) {
373 return cpus_offset;
374 }
375 }
376 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
377 if (offset < 0) {
378 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
379 if (offset < 0) {
380 return offset;
381 }
382 }
383
384 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
385 pft_size_prop, sizeof(pft_size_prop));
386 if (ret < 0) {
387 return ret;
388 }
389
390 if (nb_numa_nodes > 1) {
391 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
392 if (ret < 0) {
393 return ret;
394 }
395 }
396
397 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
398 if (ret < 0) {
399 return ret;
400 }
401
402 spapr_populate_pa_features(spapr, cpu, fdt, offset,
403 spapr->cas_legacy_guest_workaround);
404 }
405 return ret;
406 }
407
408 static hwaddr spapr_node0_size(MachineState *machine)
409 {
410 if (nb_numa_nodes) {
411 int i;
412 for (i = 0; i < nb_numa_nodes; ++i) {
413 if (numa_info[i].node_mem) {
414 return MIN(pow2floor(numa_info[i].node_mem),
415 machine->ram_size);
416 }
417 }
418 }
419 return machine->ram_size;
420 }
421
422 static void add_str(GString *s, const gchar *s1)
423 {
424 g_string_append_len(s, s1, strlen(s1) + 1);
425 }
426
427 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
428 hwaddr size)
429 {
430 uint32_t associativity[] = {
431 cpu_to_be32(0x4), /* length */
432 cpu_to_be32(0x0), cpu_to_be32(0x0),
433 cpu_to_be32(0x0), cpu_to_be32(nodeid)
434 };
435 char mem_name[32];
436 uint64_t mem_reg_property[2];
437 int off;
438
439 mem_reg_property[0] = cpu_to_be64(start);
440 mem_reg_property[1] = cpu_to_be64(size);
441
442 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
443 off = fdt_add_subnode(fdt, 0, mem_name);
444 _FDT(off);
445 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
446 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
447 sizeof(mem_reg_property))));
448 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
449 sizeof(associativity))));
450 return off;
451 }
452
453 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
454 {
455 MachineState *machine = MACHINE(spapr);
456 hwaddr mem_start, node_size;
457 int i, nb_nodes = nb_numa_nodes;
458 NodeInfo *nodes = numa_info;
459 NodeInfo ramnode;
460
461 /* No NUMA nodes, assume there is just one node with whole RAM */
462 if (!nb_numa_nodes) {
463 nb_nodes = 1;
464 ramnode.node_mem = machine->ram_size;
465 nodes = &ramnode;
466 }
467
468 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
469 if (!nodes[i].node_mem) {
470 continue;
471 }
472 if (mem_start >= machine->ram_size) {
473 node_size = 0;
474 } else {
475 node_size = nodes[i].node_mem;
476 if (node_size > machine->ram_size - mem_start) {
477 node_size = machine->ram_size - mem_start;
478 }
479 }
480 if (!mem_start) {
481 /* spapr_machine_init() checks for rma_size <= node0_size
482 * already */
483 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
484 mem_start += spapr->rma_size;
485 node_size -= spapr->rma_size;
486 }
487 for ( ; node_size; ) {
488 hwaddr sizetmp = pow2floor(node_size);
489
490 /* mem_start != 0 here */
491 if (ctzl(mem_start) < ctzl(sizetmp)) {
492 sizetmp = 1ULL << ctzl(mem_start);
493 }
494
495 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
496 node_size -= sizetmp;
497 mem_start += sizetmp;
498 }
499 }
500
501 return 0;
502 }
503
504 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
505 sPAPRMachineState *spapr)
506 {
507 PowerPCCPU *cpu = POWERPC_CPU(cs);
508 CPUPPCState *env = &cpu->env;
509 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
510 int index = spapr_get_vcpu_id(cpu);
511 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
512 0xffffffff, 0xffffffff};
513 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
514 : SPAPR_TIMEBASE_FREQ;
515 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
516 uint32_t page_sizes_prop[64];
517 size_t page_sizes_prop_size;
518 uint32_t vcpus_per_socket = smp_threads * smp_cores;
519 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
520 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
521 sPAPRDRConnector *drc;
522 int drc_index;
523 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
524 int i;
525
526 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
527 if (drc) {
528 drc_index = spapr_drc_index(drc);
529 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
530 }
531
532 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
533 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
534
535 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
536 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
537 env->dcache_line_size)));
538 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
539 env->dcache_line_size)));
540 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
541 env->icache_line_size)));
542 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
543 env->icache_line_size)));
544
545 if (pcc->l1_dcache_size) {
546 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
547 pcc->l1_dcache_size)));
548 } else {
549 warn_report("Unknown L1 dcache size for cpu");
550 }
551 if (pcc->l1_icache_size) {
552 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
553 pcc->l1_icache_size)));
554 } else {
555 warn_report("Unknown L1 icache size for cpu");
556 }
557
558 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
559 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
560 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
561 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
562 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
563 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
564
565 if (env->spr_cb[SPR_PURR].oea_read) {
566 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
567 }
568
569 if (env->mmu_model & POWERPC_MMU_1TSEG) {
570 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
571 segs, sizeof(segs))));
572 }
573
574 /* Advertise VSX (vector extensions) if available
575 * 1 == VMX / Altivec available
576 * 2 == VSX available
577 *
578 * Only CPUs for which we create core types in spapr_cpu_core.c
579 * are possible, and all of those have VMX */
580 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
581 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
582 } else {
583 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
584 }
585
586 /* Advertise DFP (Decimal Floating Point) if available
587 * 0 / no property == no DFP
588 * 1 == DFP available */
589 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
590 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
591 }
592
593 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
594 sizeof(page_sizes_prop));
595 if (page_sizes_prop_size) {
596 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
597 page_sizes_prop, page_sizes_prop_size)));
598 }
599
600 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
601
602 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
603 cs->cpu_index / vcpus_per_socket)));
604
605 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
606 pft_size_prop, sizeof(pft_size_prop))));
607
608 if (nb_numa_nodes > 1) {
609 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
610 }
611
612 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
613
614 if (pcc->radix_page_info) {
615 for (i = 0; i < pcc->radix_page_info->count; i++) {
616 radix_AP_encodings[i] =
617 cpu_to_be32(pcc->radix_page_info->entries[i]);
618 }
619 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
620 radix_AP_encodings,
621 pcc->radix_page_info->count *
622 sizeof(radix_AP_encodings[0]))));
623 }
624 }
625
626 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
627 {
628 CPUState *cs;
629 int cpus_offset;
630 char *nodename;
631
632 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
633 _FDT(cpus_offset);
634 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
635 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
636
637 /*
638 * We walk the CPUs in reverse order to ensure that CPU DT nodes
639 * created by fdt_add_subnode() end up in the right order in FDT
640 * for the guest kernel the enumerate the CPUs correctly.
641 */
642 CPU_FOREACH_REVERSE(cs) {
643 PowerPCCPU *cpu = POWERPC_CPU(cs);
644 int index = spapr_get_vcpu_id(cpu);
645 DeviceClass *dc = DEVICE_GET_CLASS(cs);
646 int offset;
647
648 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
649 continue;
650 }
651
652 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
653 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
654 g_free(nodename);
655 _FDT(offset);
656 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
657 }
658
659 }
660
661 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
662 {
663 MemoryDeviceInfoList *info;
664
665 for (info = list; info; info = info->next) {
666 MemoryDeviceInfo *value = info->value;
667
668 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
669 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
670
671 if (pcdimm_info->addr >= addr &&
672 addr < (pcdimm_info->addr + pcdimm_info->size)) {
673 return pcdimm_info->node;
674 }
675 }
676 }
677
678 return -1;
679 }
680
681 /*
682 * Adds ibm,dynamic-reconfiguration-memory node.
683 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
684 * of this device tree node.
685 */
686 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
687 {
688 MachineState *machine = MACHINE(spapr);
689 int ret, i, offset;
690 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
691 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
692 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
693 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
694 memory_region_size(&spapr->hotplug_memory.mr)) /
695 lmb_size;
696 uint32_t *int_buf, *cur_index, buf_len;
697 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
698 MemoryDeviceInfoList *dimms = NULL;
699
700 /*
701 * Don't create the node if there is no hotpluggable memory
702 */
703 if (machine->ram_size == machine->maxram_size) {
704 return 0;
705 }
706
707 /*
708 * Allocate enough buffer size to fit in ibm,dynamic-memory
709 * or ibm,associativity-lookup-arrays
710 */
711 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
712 * sizeof(uint32_t);
713 cur_index = int_buf = g_malloc0(buf_len);
714
715 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
716
717 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
718 sizeof(prop_lmb_size));
719 if (ret < 0) {
720 goto out;
721 }
722
723 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
724 if (ret < 0) {
725 goto out;
726 }
727
728 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
729 if (ret < 0) {
730 goto out;
731 }
732
733 if (hotplug_lmb_start) {
734 MemoryDeviceInfoList **prev = &dimms;
735 qmp_pc_dimm_device_list(qdev_get_machine(), &prev);
736 }
737
738 /* ibm,dynamic-memory */
739 int_buf[0] = cpu_to_be32(nr_lmbs);
740 cur_index++;
741 for (i = 0; i < nr_lmbs; i++) {
742 uint64_t addr = i * lmb_size;
743 uint32_t *dynamic_memory = cur_index;
744
745 if (i >= hotplug_lmb_start) {
746 sPAPRDRConnector *drc;
747
748 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
749 g_assert(drc);
750
751 dynamic_memory[0] = cpu_to_be32(addr >> 32);
752 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
753 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
754 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
755 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
756 if (memory_region_present(get_system_memory(), addr)) {
757 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
758 } else {
759 dynamic_memory[5] = cpu_to_be32(0);
760 }
761 } else {
762 /*
763 * LMB information for RMA, boot time RAM and gap b/n RAM and
764 * hotplug memory region -- all these are marked as reserved
765 * and as having no valid DRC.
766 */
767 dynamic_memory[0] = cpu_to_be32(addr >> 32);
768 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
769 dynamic_memory[2] = cpu_to_be32(0);
770 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
771 dynamic_memory[4] = cpu_to_be32(-1);
772 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
773 SPAPR_LMB_FLAGS_DRC_INVALID);
774 }
775
776 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
777 }
778 qapi_free_MemoryDeviceInfoList(dimms);
779 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
780 if (ret < 0) {
781 goto out;
782 }
783
784 /* ibm,associativity-lookup-arrays */
785 cur_index = int_buf;
786 int_buf[0] = cpu_to_be32(nr_nodes);
787 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
788 cur_index += 2;
789 for (i = 0; i < nr_nodes; i++) {
790 uint32_t associativity[] = {
791 cpu_to_be32(0x0),
792 cpu_to_be32(0x0),
793 cpu_to_be32(0x0),
794 cpu_to_be32(i)
795 };
796 memcpy(cur_index, associativity, sizeof(associativity));
797 cur_index += 4;
798 }
799 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
800 (cur_index - int_buf) * sizeof(uint32_t));
801 out:
802 g_free(int_buf);
803 return ret;
804 }
805
806 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
807 sPAPROptionVector *ov5_updates)
808 {
809 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
810 int ret = 0, offset;
811
812 /* Generate ibm,dynamic-reconfiguration-memory node if required */
813 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
814 g_assert(smc->dr_lmb_enabled);
815 ret = spapr_populate_drconf_memory(spapr, fdt);
816 if (ret) {
817 goto out;
818 }
819 }
820
821 offset = fdt_path_offset(fdt, "/chosen");
822 if (offset < 0) {
823 offset = fdt_add_subnode(fdt, 0, "chosen");
824 if (offset < 0) {
825 return offset;
826 }
827 }
828 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
829 "ibm,architecture-vec-5");
830
831 out:
832 return ret;
833 }
834
835 static bool spapr_hotplugged_dev_before_cas(void)
836 {
837 Object *drc_container, *obj;
838 ObjectProperty *prop;
839 ObjectPropertyIterator iter;
840
841 drc_container = container_get(object_get_root(), "/dr-connector");
842 object_property_iter_init(&iter, drc_container);
843 while ((prop = object_property_iter_next(&iter))) {
844 if (!strstart(prop->type, "link<", NULL)) {
845 continue;
846 }
847 obj = object_property_get_link(drc_container, prop->name, NULL);
848 if (spapr_drc_needed(obj)) {
849 return true;
850 }
851 }
852 return false;
853 }
854
855 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
856 target_ulong addr, target_ulong size,
857 sPAPROptionVector *ov5_updates)
858 {
859 void *fdt, *fdt_skel;
860 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
861
862 if (spapr_hotplugged_dev_before_cas()) {
863 return 1;
864 }
865
866 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
867 error_report("SLOF provided an unexpected CAS buffer size "
868 TARGET_FMT_lu " (min: %zu, max: %u)",
869 size, sizeof(hdr), FW_MAX_SIZE);
870 exit(EXIT_FAILURE);
871 }
872
873 size -= sizeof(hdr);
874
875 /* Create skeleton */
876 fdt_skel = g_malloc0(size);
877 _FDT((fdt_create(fdt_skel, size)));
878 _FDT((fdt_begin_node(fdt_skel, "")));
879 _FDT((fdt_end_node(fdt_skel)));
880 _FDT((fdt_finish(fdt_skel)));
881 fdt = g_malloc0(size);
882 _FDT((fdt_open_into(fdt_skel, fdt, size)));
883 g_free(fdt_skel);
884
885 /* Fixup cpu nodes */
886 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
887
888 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
889 return -1;
890 }
891
892 /* Pack resulting tree */
893 _FDT((fdt_pack(fdt)));
894
895 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
896 trace_spapr_cas_failed(size);
897 return -1;
898 }
899
900 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
901 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
902 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
903 g_free(fdt);
904
905 return 0;
906 }
907
908 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
909 {
910 int rtas;
911 GString *hypertas = g_string_sized_new(256);
912 GString *qemu_hypertas = g_string_sized_new(256);
913 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
914 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
915 memory_region_size(&spapr->hotplug_memory.mr);
916 uint32_t lrdr_capacity[] = {
917 cpu_to_be32(max_hotplug_addr >> 32),
918 cpu_to_be32(max_hotplug_addr & 0xffffffff),
919 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
920 cpu_to_be32(max_cpus / smp_threads),
921 };
922
923 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
924
925 /* hypertas */
926 add_str(hypertas, "hcall-pft");
927 add_str(hypertas, "hcall-term");
928 add_str(hypertas, "hcall-dabr");
929 add_str(hypertas, "hcall-interrupt");
930 add_str(hypertas, "hcall-tce");
931 add_str(hypertas, "hcall-vio");
932 add_str(hypertas, "hcall-splpar");
933 add_str(hypertas, "hcall-bulk");
934 add_str(hypertas, "hcall-set-mode");
935 add_str(hypertas, "hcall-sprg0");
936 add_str(hypertas, "hcall-copy");
937 add_str(hypertas, "hcall-debug");
938 add_str(qemu_hypertas, "hcall-memop1");
939
940 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
941 add_str(hypertas, "hcall-multi-tce");
942 }
943
944 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
945 add_str(hypertas, "hcall-hpt-resize");
946 }
947
948 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
949 hypertas->str, hypertas->len));
950 g_string_free(hypertas, TRUE);
951 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
952 qemu_hypertas->str, qemu_hypertas->len));
953 g_string_free(qemu_hypertas, TRUE);
954
955 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
956 refpoints, sizeof(refpoints)));
957
958 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
959 RTAS_ERROR_LOG_MAX));
960 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
961 RTAS_EVENT_SCAN_RATE));
962
963 g_assert(msi_nonbroken);
964 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
965
966 /*
967 * According to PAPR, rtas ibm,os-term does not guarantee a return
968 * back to the guest cpu.
969 *
970 * While an additional ibm,extended-os-term property indicates
971 * that rtas call return will always occur. Set this property.
972 */
973 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
974
975 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
976 lrdr_capacity, sizeof(lrdr_capacity)));
977
978 spapr_dt_rtas_tokens(fdt, rtas);
979 }
980
981 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
982 * that the guest may request and thus the valid values for bytes 24..26 of
983 * option vector 5: */
984 static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
985 {
986 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
987
988 char val[2 * 4] = {
989 23, 0x00, /* Xive mode, filled in below. */
990 24, 0x00, /* Hash/Radix, filled in below. */
991 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
992 26, 0x40, /* Radix options: GTSE == yes. */
993 };
994
995 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
996 first_ppc_cpu->compat_pvr)) {
997 /* If we're in a pre POWER9 compat mode then the guest should do hash */
998 val[3] = 0x00; /* Hash */
999 } else if (kvm_enabled()) {
1000 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1001 val[3] = 0x80; /* OV5_MMU_BOTH */
1002 } else if (kvmppc_has_cap_mmu_radix()) {
1003 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
1004 } else {
1005 val[3] = 0x00; /* Hash */
1006 }
1007 } else {
1008 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1009 val[3] = 0xC0;
1010 }
1011 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1012 val, sizeof(val)));
1013 }
1014
1015 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
1016 {
1017 MachineState *machine = MACHINE(spapr);
1018 int chosen;
1019 const char *boot_device = machine->boot_order;
1020 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1021 size_t cb = 0;
1022 char *bootlist = get_boot_devices_list(&cb, true);
1023
1024 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1025
1026 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1027 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1028 spapr->initrd_base));
1029 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1030 spapr->initrd_base + spapr->initrd_size));
1031
1032 if (spapr->kernel_size) {
1033 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1034 cpu_to_be64(spapr->kernel_size) };
1035
1036 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1037 &kprop, sizeof(kprop)));
1038 if (spapr->kernel_le) {
1039 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1040 }
1041 }
1042 if (boot_menu) {
1043 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1044 }
1045 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1046 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1047 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1048
1049 if (cb && bootlist) {
1050 int i;
1051
1052 for (i = 0; i < cb; i++) {
1053 if (bootlist[i] == '\n') {
1054 bootlist[i] = ' ';
1055 }
1056 }
1057 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1058 }
1059
1060 if (boot_device && strlen(boot_device)) {
1061 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1062 }
1063
1064 if (!spapr->has_graphics && stdout_path) {
1065 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1066 }
1067
1068 spapr_dt_ov5_platform_support(fdt, chosen);
1069
1070 g_free(stdout_path);
1071 g_free(bootlist);
1072 }
1073
1074 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1075 {
1076 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1077 * KVM to work under pHyp with some guest co-operation */
1078 int hypervisor;
1079 uint8_t hypercall[16];
1080
1081 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1082 /* indicate KVM hypercall interface */
1083 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1084 if (kvmppc_has_cap_fixup_hcalls()) {
1085 /*
1086 * Older KVM versions with older guest kernels were broken
1087 * with the magic page, don't allow the guest to map it.
1088 */
1089 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1090 sizeof(hypercall))) {
1091 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1092 hypercall, sizeof(hypercall)));
1093 }
1094 }
1095 }
1096
1097 static void *spapr_build_fdt(sPAPRMachineState *spapr,
1098 hwaddr rtas_addr,
1099 hwaddr rtas_size)
1100 {
1101 MachineState *machine = MACHINE(spapr);
1102 MachineClass *mc = MACHINE_GET_CLASS(machine);
1103 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1104 int ret;
1105 void *fdt;
1106 sPAPRPHBState *phb;
1107 char *buf;
1108
1109 fdt = g_malloc0(FDT_MAX_SIZE);
1110 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1111
1112 /* Root node */
1113 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1114 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1115 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1116
1117 /*
1118 * Add info to guest to indentify which host is it being run on
1119 * and what is the uuid of the guest
1120 */
1121 if (kvmppc_get_host_model(&buf)) {
1122 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1123 g_free(buf);
1124 }
1125 if (kvmppc_get_host_serial(&buf)) {
1126 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1127 g_free(buf);
1128 }
1129
1130 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1131
1132 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1133 if (qemu_uuid_set) {
1134 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1135 }
1136 g_free(buf);
1137
1138 if (qemu_get_vm_name()) {
1139 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1140 qemu_get_vm_name()));
1141 }
1142
1143 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1144 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1145
1146 /* /interrupt controller */
1147 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP);
1148
1149 ret = spapr_populate_memory(spapr, fdt);
1150 if (ret < 0) {
1151 error_report("couldn't setup memory nodes in fdt");
1152 exit(1);
1153 }
1154
1155 /* /vdevice */
1156 spapr_dt_vdevice(spapr->vio_bus, fdt);
1157
1158 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1159 ret = spapr_rng_populate_dt(fdt);
1160 if (ret < 0) {
1161 error_report("could not set up rng device in the fdt");
1162 exit(1);
1163 }
1164 }
1165
1166 QLIST_FOREACH(phb, &spapr->phbs, list) {
1167 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1168 if (ret < 0) {
1169 error_report("couldn't setup PCI devices in fdt");
1170 exit(1);
1171 }
1172 }
1173
1174 /* cpus */
1175 spapr_populate_cpus_dt_node(fdt, spapr);
1176
1177 if (smc->dr_lmb_enabled) {
1178 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1179 }
1180
1181 if (mc->has_hotpluggable_cpus) {
1182 int offset = fdt_path_offset(fdt, "/cpus");
1183 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1184 SPAPR_DR_CONNECTOR_TYPE_CPU);
1185 if (ret < 0) {
1186 error_report("Couldn't set up CPU DR device tree properties");
1187 exit(1);
1188 }
1189 }
1190
1191 /* /event-sources */
1192 spapr_dt_events(spapr, fdt);
1193
1194 /* /rtas */
1195 spapr_dt_rtas(spapr, fdt);
1196
1197 /* /chosen */
1198 spapr_dt_chosen(spapr, fdt);
1199
1200 /* /hypervisor */
1201 if (kvm_enabled()) {
1202 spapr_dt_hypervisor(spapr, fdt);
1203 }
1204
1205 /* Build memory reserve map */
1206 if (spapr->kernel_size) {
1207 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1208 }
1209 if (spapr->initrd_size) {
1210 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1211 }
1212
1213 /* ibm,client-architecture-support updates */
1214 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1215 if (ret < 0) {
1216 error_report("couldn't setup CAS properties fdt");
1217 exit(1);
1218 }
1219
1220 return fdt;
1221 }
1222
1223 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1224 {
1225 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1226 }
1227
1228 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1229 PowerPCCPU *cpu)
1230 {
1231 CPUPPCState *env = &cpu->env;
1232
1233 /* The TCG path should also be holding the BQL at this point */
1234 g_assert(qemu_mutex_iothread_locked());
1235
1236 if (msr_pr) {
1237 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1238 env->gpr[3] = H_PRIVILEGE;
1239 } else {
1240 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1241 }
1242 }
1243
1244 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1245 {
1246 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1247
1248 return spapr->patb_entry;
1249 }
1250
1251 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1252 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1253 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1254 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1255 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1256
1257 /*
1258 * Get the fd to access the kernel htab, re-opening it if necessary
1259 */
1260 static int get_htab_fd(sPAPRMachineState *spapr)
1261 {
1262 Error *local_err = NULL;
1263
1264 if (spapr->htab_fd >= 0) {
1265 return spapr->htab_fd;
1266 }
1267
1268 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1269 if (spapr->htab_fd < 0) {
1270 error_report_err(local_err);
1271 }
1272
1273 return spapr->htab_fd;
1274 }
1275
1276 void close_htab_fd(sPAPRMachineState *spapr)
1277 {
1278 if (spapr->htab_fd >= 0) {
1279 close(spapr->htab_fd);
1280 }
1281 spapr->htab_fd = -1;
1282 }
1283
1284 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1285 {
1286 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1287
1288 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1289 }
1290
1291 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1292 {
1293 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1294
1295 assert(kvm_enabled());
1296
1297 if (!spapr->htab) {
1298 return 0;
1299 }
1300
1301 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1302 }
1303
1304 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1305 hwaddr ptex, int n)
1306 {
1307 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1308 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1309
1310 if (!spapr->htab) {
1311 /*
1312 * HTAB is controlled by KVM. Fetch into temporary buffer
1313 */
1314 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1315 kvmppc_read_hptes(hptes, ptex, n);
1316 return hptes;
1317 }
1318
1319 /*
1320 * HTAB is controlled by QEMU. Just point to the internally
1321 * accessible PTEG.
1322 */
1323 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1324 }
1325
1326 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1327 const ppc_hash_pte64_t *hptes,
1328 hwaddr ptex, int n)
1329 {
1330 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1331
1332 if (!spapr->htab) {
1333 g_free((void *)hptes);
1334 }
1335
1336 /* Nothing to do for qemu managed HPT */
1337 }
1338
1339 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1340 uint64_t pte0, uint64_t pte1)
1341 {
1342 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1343 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1344
1345 if (!spapr->htab) {
1346 kvmppc_write_hpte(ptex, pte0, pte1);
1347 } else {
1348 stq_p(spapr->htab + offset, pte0);
1349 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1350 }
1351 }
1352
1353 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1354 {
1355 int shift;
1356
1357 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1358 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1359 * that's much more than is needed for Linux guests */
1360 shift = ctz64(pow2ceil(ramsize)) - 7;
1361 shift = MAX(shift, 18); /* Minimum architected size */
1362 shift = MIN(shift, 46); /* Maximum architected size */
1363 return shift;
1364 }
1365
1366 void spapr_free_hpt(sPAPRMachineState *spapr)
1367 {
1368 g_free(spapr->htab);
1369 spapr->htab = NULL;
1370 spapr->htab_shift = 0;
1371 close_htab_fd(spapr);
1372 }
1373
1374 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1375 Error **errp)
1376 {
1377 long rc;
1378
1379 /* Clean up any HPT info from a previous boot */
1380 spapr_free_hpt(spapr);
1381
1382 rc = kvmppc_reset_htab(shift);
1383 if (rc < 0) {
1384 /* kernel-side HPT needed, but couldn't allocate one */
1385 error_setg_errno(errp, errno,
1386 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1387 shift);
1388 /* This is almost certainly fatal, but if the caller really
1389 * wants to carry on with shift == 0, it's welcome to try */
1390 } else if (rc > 0) {
1391 /* kernel-side HPT allocated */
1392 if (rc != shift) {
1393 error_setg(errp,
1394 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1395 shift, rc);
1396 }
1397
1398 spapr->htab_shift = shift;
1399 spapr->htab = NULL;
1400 } else {
1401 /* kernel-side HPT not needed, allocate in userspace instead */
1402 size_t size = 1ULL << shift;
1403 int i;
1404
1405 spapr->htab = qemu_memalign(size, size);
1406 if (!spapr->htab) {
1407 error_setg_errno(errp, errno,
1408 "Could not allocate HPT of order %d", shift);
1409 return;
1410 }
1411
1412 memset(spapr->htab, 0, size);
1413 spapr->htab_shift = shift;
1414
1415 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1416 DIRTY_HPTE(HPTE(spapr->htab, i));
1417 }
1418 }
1419 /* We're setting up a hash table, so that means we're not radix */
1420 spapr->patb_entry = 0;
1421 }
1422
1423 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1424 {
1425 int hpt_shift;
1426
1427 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1428 || (spapr->cas_reboot
1429 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1430 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1431 } else {
1432 uint64_t current_ram_size;
1433
1434 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1435 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1436 }
1437 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1438
1439 if (spapr->vrma_adjust) {
1440 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1441 spapr->htab_shift);
1442 }
1443 }
1444
1445 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1446 {
1447 bool matched = false;
1448
1449 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1450 matched = true;
1451 }
1452
1453 if (!matched) {
1454 error_report("Device %s is not supported by this machine yet.",
1455 qdev_fw_name(DEVICE(sbdev)));
1456 exit(1);
1457 }
1458 }
1459
1460 static int spapr_reset_drcs(Object *child, void *opaque)
1461 {
1462 sPAPRDRConnector *drc =
1463 (sPAPRDRConnector *) object_dynamic_cast(child,
1464 TYPE_SPAPR_DR_CONNECTOR);
1465
1466 if (drc) {
1467 spapr_drc_reset(drc);
1468 }
1469
1470 return 0;
1471 }
1472
1473 static void spapr_machine_reset(void)
1474 {
1475 MachineState *machine = MACHINE(qdev_get_machine());
1476 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1477 PowerPCCPU *first_ppc_cpu;
1478 uint32_t rtas_limit;
1479 hwaddr rtas_addr, fdt_addr;
1480 void *fdt;
1481 int rc;
1482
1483 /* Check for unknown sysbus devices */
1484 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1485
1486 spapr_caps_reset(spapr);
1487
1488 first_ppc_cpu = POWERPC_CPU(first_cpu);
1489 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1490 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1491 spapr->max_compat_pvr)) {
1492 /* If using KVM with radix mode available, VCPUs can be started
1493 * without a HPT because KVM will start them in radix mode.
1494 * Set the GR bit in PATB so that we know there is no HPT. */
1495 spapr->patb_entry = PATBE1_GR;
1496 } else {
1497 spapr_setup_hpt_and_vrma(spapr);
1498 }
1499
1500 /* if this reset wasn't generated by CAS, we should reset our
1501 * negotiated options and start from scratch */
1502 if (!spapr->cas_reboot) {
1503 spapr_ovec_cleanup(spapr->ov5_cas);
1504 spapr->ov5_cas = spapr_ovec_new();
1505
1506 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1507 }
1508
1509 qemu_devices_reset();
1510
1511 /* DRC reset may cause a device to be unplugged. This will cause troubles
1512 * if this device is used by another device (eg, a running vhost backend
1513 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1514 * situations, we reset DRCs after all devices have been reset.
1515 */
1516 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1517
1518 spapr_clear_pending_events(spapr);
1519
1520 /*
1521 * We place the device tree and RTAS just below either the top of the RMA,
1522 * or just below 2GB, whichever is lowere, so that it can be
1523 * processed with 32-bit real mode code if necessary
1524 */
1525 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1526 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1527 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1528
1529 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1530
1531 spapr_load_rtas(spapr, fdt, rtas_addr);
1532
1533 rc = fdt_pack(fdt);
1534
1535 /* Should only fail if we've built a corrupted tree */
1536 assert(rc == 0);
1537
1538 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1539 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1540 fdt_totalsize(fdt), FDT_MAX_SIZE);
1541 exit(1);
1542 }
1543
1544 /* Load the fdt */
1545 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1546 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1547 g_free(fdt);
1548
1549 /* Set up the entry state */
1550 first_ppc_cpu->env.gpr[3] = fdt_addr;
1551 first_ppc_cpu->env.gpr[5] = 0;
1552 first_cpu->halted = 0;
1553 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1554
1555 spapr->cas_reboot = false;
1556 }
1557
1558 static void spapr_create_nvram(sPAPRMachineState *spapr)
1559 {
1560 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1561 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1562
1563 if (dinfo) {
1564 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1565 &error_fatal);
1566 }
1567
1568 qdev_init_nofail(dev);
1569
1570 spapr->nvram = (struct sPAPRNVRAM *)dev;
1571 }
1572
1573 static void spapr_rtc_create(sPAPRMachineState *spapr)
1574 {
1575 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1576 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1577 &error_fatal);
1578 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1579 &error_fatal);
1580 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1581 "date", &error_fatal);
1582 }
1583
1584 /* Returns whether we want to use VGA or not */
1585 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1586 {
1587 switch (vga_interface_type) {
1588 case VGA_NONE:
1589 return false;
1590 case VGA_DEVICE:
1591 return true;
1592 case VGA_STD:
1593 case VGA_VIRTIO:
1594 return pci_vga_init(pci_bus) != NULL;
1595 default:
1596 error_setg(errp,
1597 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1598 return false;
1599 }
1600 }
1601
1602 static int spapr_pre_load(void *opaque)
1603 {
1604 int rc;
1605
1606 rc = spapr_caps_pre_load(opaque);
1607 if (rc) {
1608 return rc;
1609 }
1610
1611 return 0;
1612 }
1613
1614 static int spapr_post_load(void *opaque, int version_id)
1615 {
1616 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1617 int err = 0;
1618
1619 err = spapr_caps_post_migration(spapr);
1620 if (err) {
1621 return err;
1622 }
1623
1624 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1625 CPUState *cs;
1626 CPU_FOREACH(cs) {
1627 PowerPCCPU *cpu = POWERPC_CPU(cs);
1628 icp_resend(ICP(cpu->intc));
1629 }
1630 }
1631
1632 /* In earlier versions, there was no separate qdev for the PAPR
1633 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1634 * So when migrating from those versions, poke the incoming offset
1635 * value into the RTC device */
1636 if (version_id < 3) {
1637 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1638 }
1639
1640 if (kvm_enabled() && spapr->patb_entry) {
1641 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1642 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1643 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1644
1645 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1646 if (err) {
1647 error_report("Process table config unsupported by the host");
1648 return -EINVAL;
1649 }
1650 }
1651
1652 return err;
1653 }
1654
1655 static int spapr_pre_save(void *opaque)
1656 {
1657 int rc;
1658
1659 rc = spapr_caps_pre_save(opaque);
1660 if (rc) {
1661 return rc;
1662 }
1663
1664 return 0;
1665 }
1666
1667 static bool version_before_3(void *opaque, int version_id)
1668 {
1669 return version_id < 3;
1670 }
1671
1672 static bool spapr_pending_events_needed(void *opaque)
1673 {
1674 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1675 return !QTAILQ_EMPTY(&spapr->pending_events);
1676 }
1677
1678 static const VMStateDescription vmstate_spapr_event_entry = {
1679 .name = "spapr_event_log_entry",
1680 .version_id = 1,
1681 .minimum_version_id = 1,
1682 .fields = (VMStateField[]) {
1683 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1684 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1685 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1686 NULL, extended_length),
1687 VMSTATE_END_OF_LIST()
1688 },
1689 };
1690
1691 static const VMStateDescription vmstate_spapr_pending_events = {
1692 .name = "spapr_pending_events",
1693 .version_id = 1,
1694 .minimum_version_id = 1,
1695 .needed = spapr_pending_events_needed,
1696 .fields = (VMStateField[]) {
1697 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1698 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1699 VMSTATE_END_OF_LIST()
1700 },
1701 };
1702
1703 static bool spapr_ov5_cas_needed(void *opaque)
1704 {
1705 sPAPRMachineState *spapr = opaque;
1706 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1707 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1708 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1709 bool cas_needed;
1710
1711 /* Prior to the introduction of sPAPROptionVector, we had two option
1712 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1713 * Both of these options encode machine topology into the device-tree
1714 * in such a way that the now-booted OS should still be able to interact
1715 * appropriately with QEMU regardless of what options were actually
1716 * negotiatied on the source side.
1717 *
1718 * As such, we can avoid migrating the CAS-negotiated options if these
1719 * are the only options available on the current machine/platform.
1720 * Since these are the only options available for pseries-2.7 and
1721 * earlier, this allows us to maintain old->new/new->old migration
1722 * compatibility.
1723 *
1724 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1725 * via default pseries-2.8 machines and explicit command-line parameters.
1726 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1727 * of the actual CAS-negotiated values to continue working properly. For
1728 * example, availability of memory unplug depends on knowing whether
1729 * OV5_HP_EVT was negotiated via CAS.
1730 *
1731 * Thus, for any cases where the set of available CAS-negotiatable
1732 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1733 * include the CAS-negotiated options in the migration stream.
1734 */
1735 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1736 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1737
1738 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1739 * the mask itself since in the future it's possible "legacy" bits may be
1740 * removed via machine options, which could generate a false positive
1741 * that breaks migration.
1742 */
1743 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1744 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1745
1746 spapr_ovec_cleanup(ov5_mask);
1747 spapr_ovec_cleanup(ov5_legacy);
1748 spapr_ovec_cleanup(ov5_removed);
1749
1750 return cas_needed;
1751 }
1752
1753 static const VMStateDescription vmstate_spapr_ov5_cas = {
1754 .name = "spapr_option_vector_ov5_cas",
1755 .version_id = 1,
1756 .minimum_version_id = 1,
1757 .needed = spapr_ov5_cas_needed,
1758 .fields = (VMStateField[]) {
1759 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1760 vmstate_spapr_ovec, sPAPROptionVector),
1761 VMSTATE_END_OF_LIST()
1762 },
1763 };
1764
1765 static bool spapr_patb_entry_needed(void *opaque)
1766 {
1767 sPAPRMachineState *spapr = opaque;
1768
1769 return !!spapr->patb_entry;
1770 }
1771
1772 static const VMStateDescription vmstate_spapr_patb_entry = {
1773 .name = "spapr_patb_entry",
1774 .version_id = 1,
1775 .minimum_version_id = 1,
1776 .needed = spapr_patb_entry_needed,
1777 .fields = (VMStateField[]) {
1778 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1779 VMSTATE_END_OF_LIST()
1780 },
1781 };
1782
1783 static const VMStateDescription vmstate_spapr = {
1784 .name = "spapr",
1785 .version_id = 3,
1786 .minimum_version_id = 1,
1787 .pre_load = spapr_pre_load,
1788 .post_load = spapr_post_load,
1789 .pre_save = spapr_pre_save,
1790 .fields = (VMStateField[]) {
1791 /* used to be @next_irq */
1792 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1793
1794 /* RTC offset */
1795 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1796
1797 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1798 VMSTATE_END_OF_LIST()
1799 },
1800 .subsections = (const VMStateDescription*[]) {
1801 &vmstate_spapr_ov5_cas,
1802 &vmstate_spapr_patb_entry,
1803 &vmstate_spapr_pending_events,
1804 &vmstate_spapr_cap_htm,
1805 &vmstate_spapr_cap_vsx,
1806 &vmstate_spapr_cap_dfp,
1807 &vmstate_spapr_cap_cfpc,
1808 &vmstate_spapr_cap_sbbc,
1809 &vmstate_spapr_cap_ibs,
1810 NULL
1811 }
1812 };
1813
1814 static int htab_save_setup(QEMUFile *f, void *opaque)
1815 {
1816 sPAPRMachineState *spapr = opaque;
1817
1818 /* "Iteration" header */
1819 if (!spapr->htab_shift) {
1820 qemu_put_be32(f, -1);
1821 } else {
1822 qemu_put_be32(f, spapr->htab_shift);
1823 }
1824
1825 if (spapr->htab) {
1826 spapr->htab_save_index = 0;
1827 spapr->htab_first_pass = true;
1828 } else {
1829 if (spapr->htab_shift) {
1830 assert(kvm_enabled());
1831 }
1832 }
1833
1834
1835 return 0;
1836 }
1837
1838 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
1839 int chunkstart, int n_valid, int n_invalid)
1840 {
1841 qemu_put_be32(f, chunkstart);
1842 qemu_put_be16(f, n_valid);
1843 qemu_put_be16(f, n_invalid);
1844 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1845 HASH_PTE_SIZE_64 * n_valid);
1846 }
1847
1848 static void htab_save_end_marker(QEMUFile *f)
1849 {
1850 qemu_put_be32(f, 0);
1851 qemu_put_be16(f, 0);
1852 qemu_put_be16(f, 0);
1853 }
1854
1855 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1856 int64_t max_ns)
1857 {
1858 bool has_timeout = max_ns != -1;
1859 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1860 int index = spapr->htab_save_index;
1861 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1862
1863 assert(spapr->htab_first_pass);
1864
1865 do {
1866 int chunkstart;
1867
1868 /* Consume invalid HPTEs */
1869 while ((index < htabslots)
1870 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1871 CLEAN_HPTE(HPTE(spapr->htab, index));
1872 index++;
1873 }
1874
1875 /* Consume valid HPTEs */
1876 chunkstart = index;
1877 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1878 && HPTE_VALID(HPTE(spapr->htab, index))) {
1879 CLEAN_HPTE(HPTE(spapr->htab, index));
1880 index++;
1881 }
1882
1883 if (index > chunkstart) {
1884 int n_valid = index - chunkstart;
1885
1886 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
1887
1888 if (has_timeout &&
1889 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1890 break;
1891 }
1892 }
1893 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1894
1895 if (index >= htabslots) {
1896 assert(index == htabslots);
1897 index = 0;
1898 spapr->htab_first_pass = false;
1899 }
1900 spapr->htab_save_index = index;
1901 }
1902
1903 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1904 int64_t max_ns)
1905 {
1906 bool final = max_ns < 0;
1907 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1908 int examined = 0, sent = 0;
1909 int index = spapr->htab_save_index;
1910 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1911
1912 assert(!spapr->htab_first_pass);
1913
1914 do {
1915 int chunkstart, invalidstart;
1916
1917 /* Consume non-dirty HPTEs */
1918 while ((index < htabslots)
1919 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1920 index++;
1921 examined++;
1922 }
1923
1924 chunkstart = index;
1925 /* Consume valid dirty HPTEs */
1926 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1927 && HPTE_DIRTY(HPTE(spapr->htab, index))
1928 && HPTE_VALID(HPTE(spapr->htab, index))) {
1929 CLEAN_HPTE(HPTE(spapr->htab, index));
1930 index++;
1931 examined++;
1932 }
1933
1934 invalidstart = index;
1935 /* Consume invalid dirty HPTEs */
1936 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1937 && HPTE_DIRTY(HPTE(spapr->htab, index))
1938 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1939 CLEAN_HPTE(HPTE(spapr->htab, index));
1940 index++;
1941 examined++;
1942 }
1943
1944 if (index > chunkstart) {
1945 int n_valid = invalidstart - chunkstart;
1946 int n_invalid = index - invalidstart;
1947
1948 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
1949 sent += index - chunkstart;
1950
1951 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1952 break;
1953 }
1954 }
1955
1956 if (examined >= htabslots) {
1957 break;
1958 }
1959
1960 if (index >= htabslots) {
1961 assert(index == htabslots);
1962 index = 0;
1963 }
1964 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1965
1966 if (index >= htabslots) {
1967 assert(index == htabslots);
1968 index = 0;
1969 }
1970
1971 spapr->htab_save_index = index;
1972
1973 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1974 }
1975
1976 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1977 #define MAX_KVM_BUF_SIZE 2048
1978
1979 static int htab_save_iterate(QEMUFile *f, void *opaque)
1980 {
1981 sPAPRMachineState *spapr = opaque;
1982 int fd;
1983 int rc = 0;
1984
1985 /* Iteration header */
1986 if (!spapr->htab_shift) {
1987 qemu_put_be32(f, -1);
1988 return 1;
1989 } else {
1990 qemu_put_be32(f, 0);
1991 }
1992
1993 if (!spapr->htab) {
1994 assert(kvm_enabled());
1995
1996 fd = get_htab_fd(spapr);
1997 if (fd < 0) {
1998 return fd;
1999 }
2000
2001 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2002 if (rc < 0) {
2003 return rc;
2004 }
2005 } else if (spapr->htab_first_pass) {
2006 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2007 } else {
2008 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2009 }
2010
2011 htab_save_end_marker(f);
2012
2013 return rc;
2014 }
2015
2016 static int htab_save_complete(QEMUFile *f, void *opaque)
2017 {
2018 sPAPRMachineState *spapr = opaque;
2019 int fd;
2020
2021 /* Iteration header */
2022 if (!spapr->htab_shift) {
2023 qemu_put_be32(f, -1);
2024 return 0;
2025 } else {
2026 qemu_put_be32(f, 0);
2027 }
2028
2029 if (!spapr->htab) {
2030 int rc;
2031
2032 assert(kvm_enabled());
2033
2034 fd = get_htab_fd(spapr);
2035 if (fd < 0) {
2036 return fd;
2037 }
2038
2039 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2040 if (rc < 0) {
2041 return rc;
2042 }
2043 } else {
2044 if (spapr->htab_first_pass) {
2045 htab_save_first_pass(f, spapr, -1);
2046 }
2047 htab_save_later_pass(f, spapr, -1);
2048 }
2049
2050 /* End marker */
2051 htab_save_end_marker(f);
2052
2053 return 0;
2054 }
2055
2056 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2057 {
2058 sPAPRMachineState *spapr = opaque;
2059 uint32_t section_hdr;
2060 int fd = -1;
2061 Error *local_err = NULL;
2062
2063 if (version_id < 1 || version_id > 1) {
2064 error_report("htab_load() bad version");
2065 return -EINVAL;
2066 }
2067
2068 section_hdr = qemu_get_be32(f);
2069
2070 if (section_hdr == -1) {
2071 spapr_free_hpt(spapr);
2072 return 0;
2073 }
2074
2075 if (section_hdr) {
2076 /* First section gives the htab size */
2077 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2078 if (local_err) {
2079 error_report_err(local_err);
2080 return -EINVAL;
2081 }
2082 return 0;
2083 }
2084
2085 if (!spapr->htab) {
2086 assert(kvm_enabled());
2087
2088 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2089 if (fd < 0) {
2090 error_report_err(local_err);
2091 return fd;
2092 }
2093 }
2094
2095 while (true) {
2096 uint32_t index;
2097 uint16_t n_valid, n_invalid;
2098
2099 index = qemu_get_be32(f);
2100 n_valid = qemu_get_be16(f);
2101 n_invalid = qemu_get_be16(f);
2102
2103 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2104 /* End of Stream */
2105 break;
2106 }
2107
2108 if ((index + n_valid + n_invalid) >
2109 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2110 /* Bad index in stream */
2111 error_report(
2112 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2113 index, n_valid, n_invalid, spapr->htab_shift);
2114 return -EINVAL;
2115 }
2116
2117 if (spapr->htab) {
2118 if (n_valid) {
2119 qemu_get_buffer(f, HPTE(spapr->htab, index),
2120 HASH_PTE_SIZE_64 * n_valid);
2121 }
2122 if (n_invalid) {
2123 memset(HPTE(spapr->htab, index + n_valid), 0,
2124 HASH_PTE_SIZE_64 * n_invalid);
2125 }
2126 } else {
2127 int rc;
2128
2129 assert(fd >= 0);
2130
2131 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2132 if (rc < 0) {
2133 return rc;
2134 }
2135 }
2136 }
2137
2138 if (!spapr->htab) {
2139 assert(fd >= 0);
2140 close(fd);
2141 }
2142
2143 return 0;
2144 }
2145
2146 static void htab_save_cleanup(void *opaque)
2147 {
2148 sPAPRMachineState *spapr = opaque;
2149
2150 close_htab_fd(spapr);
2151 }
2152
2153 static SaveVMHandlers savevm_htab_handlers = {
2154 .save_setup = htab_save_setup,
2155 .save_live_iterate = htab_save_iterate,
2156 .save_live_complete_precopy = htab_save_complete,
2157 .save_cleanup = htab_save_cleanup,
2158 .load_state = htab_load,
2159 };
2160
2161 static void spapr_boot_set(void *opaque, const char *boot_device,
2162 Error **errp)
2163 {
2164 MachineState *machine = MACHINE(opaque);
2165 machine->boot_order = g_strdup(boot_device);
2166 }
2167
2168 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2169 {
2170 MachineState *machine = MACHINE(spapr);
2171 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2172 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2173 int i;
2174
2175 for (i = 0; i < nr_lmbs; i++) {
2176 uint64_t addr;
2177
2178 addr = i * lmb_size + spapr->hotplug_memory.base;
2179 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2180 addr / lmb_size);
2181 }
2182 }
2183
2184 /*
2185 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2186 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2187 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2188 */
2189 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2190 {
2191 int i;
2192
2193 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2194 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2195 " is not aligned to %llu MiB",
2196 machine->ram_size,
2197 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2198 return;
2199 }
2200
2201 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2202 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2203 " is not aligned to %llu MiB",
2204 machine->ram_size,
2205 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2206 return;
2207 }
2208
2209 for (i = 0; i < nb_numa_nodes; i++) {
2210 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2211 error_setg(errp,
2212 "Node %d memory size 0x%" PRIx64
2213 " is not aligned to %llu MiB",
2214 i, numa_info[i].node_mem,
2215 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2216 return;
2217 }
2218 }
2219 }
2220
2221 /* find cpu slot in machine->possible_cpus by core_id */
2222 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2223 {
2224 int index = id / smp_threads;
2225
2226 if (index >= ms->possible_cpus->len) {
2227 return NULL;
2228 }
2229 if (idx) {
2230 *idx = index;
2231 }
2232 return &ms->possible_cpus->cpus[index];
2233 }
2234
2235 static void spapr_init_cpus(sPAPRMachineState *spapr)
2236 {
2237 MachineState *machine = MACHINE(spapr);
2238 MachineClass *mc = MACHINE_GET_CLASS(machine);
2239 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2240 const CPUArchIdList *possible_cpus;
2241 int boot_cores_nr = smp_cpus / smp_threads;
2242 int i;
2243
2244 possible_cpus = mc->possible_cpu_arch_ids(machine);
2245 if (mc->has_hotpluggable_cpus) {
2246 if (smp_cpus % smp_threads) {
2247 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2248 smp_cpus, smp_threads);
2249 exit(1);
2250 }
2251 if (max_cpus % smp_threads) {
2252 error_report("max_cpus (%u) must be multiple of threads (%u)",
2253 max_cpus, smp_threads);
2254 exit(1);
2255 }
2256 } else {
2257 if (max_cpus != smp_cpus) {
2258 error_report("This machine version does not support CPU hotplug");
2259 exit(1);
2260 }
2261 boot_cores_nr = possible_cpus->len;
2262 }
2263
2264 for (i = 0; i < possible_cpus->len; i++) {
2265 int core_id = i * smp_threads;
2266
2267 if (mc->has_hotpluggable_cpus) {
2268 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2269 spapr_vcpu_id(spapr, core_id));
2270 }
2271
2272 if (i < boot_cores_nr) {
2273 Object *core = object_new(type);
2274 int nr_threads = smp_threads;
2275
2276 /* Handle the partially filled core for older machine types */
2277 if ((i + 1) * smp_threads >= smp_cpus) {
2278 nr_threads = smp_cpus - i * smp_threads;
2279 }
2280
2281 object_property_set_int(core, nr_threads, "nr-threads",
2282 &error_fatal);
2283 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2284 &error_fatal);
2285 object_property_set_bool(core, true, "realized", &error_fatal);
2286 }
2287 }
2288 }
2289
2290 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2291 {
2292 Error *local_err = NULL;
2293 bool vsmt_user = !!spapr->vsmt;
2294 int kvm_smt = kvmppc_smt_threads();
2295 int ret;
2296
2297 if (!kvm_enabled() && (smp_threads > 1)) {
2298 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2299 "on a pseries machine");
2300 goto out;
2301 }
2302 if (!is_power_of_2(smp_threads)) {
2303 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2304 "machine because it must be a power of 2", smp_threads);
2305 goto out;
2306 }
2307
2308 /* Detemine the VSMT mode to use: */
2309 if (vsmt_user) {
2310 if (spapr->vsmt < smp_threads) {
2311 error_setg(&local_err, "Cannot support VSMT mode %d"
2312 " because it must be >= threads/core (%d)",
2313 spapr->vsmt, smp_threads);
2314 goto out;
2315 }
2316 /* In this case, spapr->vsmt has been set by the command line */
2317 } else {
2318 /*
2319 * Default VSMT value is tricky, because we need it to be as
2320 * consistent as possible (for migration), but this requires
2321 * changing it for at least some existing cases. We pick 8 as
2322 * the value that we'd get with KVM on POWER8, the
2323 * overwhelmingly common case in production systems.
2324 */
2325 spapr->vsmt = MAX(8, smp_threads);
2326 }
2327
2328 /* KVM: If necessary, set the SMT mode: */
2329 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2330 ret = kvmppc_set_smt_threads(spapr->vsmt);
2331 if (ret) {
2332 /* Looks like KVM isn't able to change VSMT mode */
2333 error_setg(&local_err,
2334 "Failed to set KVM's VSMT mode to %d (errno %d)",
2335 spapr->vsmt, ret);
2336 /* We can live with that if the default one is big enough
2337 * for the number of threads, and a submultiple of the one
2338 * we want. In this case we'll waste some vcpu ids, but
2339 * behaviour will be correct */
2340 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2341 warn_report_err(local_err);
2342 local_err = NULL;
2343 goto out;
2344 } else {
2345 if (!vsmt_user) {
2346 error_append_hint(&local_err,
2347 "On PPC, a VM with %d threads/core"
2348 " on a host with %d threads/core"
2349 " requires the use of VSMT mode %d.\n",
2350 smp_threads, kvm_smt, spapr->vsmt);
2351 }
2352 kvmppc_hint_smt_possible(&local_err);
2353 goto out;
2354 }
2355 }
2356 }
2357 /* else TCG: nothing to do currently */
2358 out:
2359 error_propagate(errp, local_err);
2360 }
2361
2362 /* pSeries LPAR / sPAPR hardware init */
2363 static void spapr_machine_init(MachineState *machine)
2364 {
2365 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2366 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2367 const char *kernel_filename = machine->kernel_filename;
2368 const char *initrd_filename = machine->initrd_filename;
2369 PCIHostState *phb;
2370 int i;
2371 MemoryRegion *sysmem = get_system_memory();
2372 MemoryRegion *ram = g_new(MemoryRegion, 1);
2373 MemoryRegion *rma_region;
2374 void *rma = NULL;
2375 hwaddr rma_alloc_size;
2376 hwaddr node0_size = spapr_node0_size(machine);
2377 long load_limit, fw_size;
2378 char *filename;
2379 Error *resize_hpt_err = NULL;
2380
2381 msi_nonbroken = true;
2382
2383 QLIST_INIT(&spapr->phbs);
2384 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2385
2386 /* Check HPT resizing availability */
2387 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2388 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2389 /*
2390 * If the user explicitly requested a mode we should either
2391 * supply it, or fail completely (which we do below). But if
2392 * it's not set explicitly, we reset our mode to something
2393 * that works
2394 */
2395 if (resize_hpt_err) {
2396 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2397 error_free(resize_hpt_err);
2398 resize_hpt_err = NULL;
2399 } else {
2400 spapr->resize_hpt = smc->resize_hpt_default;
2401 }
2402 }
2403
2404 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2405
2406 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2407 /*
2408 * User requested HPT resize, but this host can't supply it. Bail out
2409 */
2410 error_report_err(resize_hpt_err);
2411 exit(1);
2412 }
2413
2414 /* Allocate RMA if necessary */
2415 rma_alloc_size = kvmppc_alloc_rma(&rma);
2416
2417 if (rma_alloc_size == -1) {
2418 error_report("Unable to create RMA");
2419 exit(1);
2420 }
2421
2422 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2423 spapr->rma_size = rma_alloc_size;
2424 } else {
2425 spapr->rma_size = node0_size;
2426
2427 /* With KVM, we don't actually know whether KVM supports an
2428 * unbounded RMA (PR KVM) or is limited by the hash table size
2429 * (HV KVM using VRMA), so we always assume the latter
2430 *
2431 * In that case, we also limit the initial allocations for RTAS
2432 * etc... to 256M since we have no way to know what the VRMA size
2433 * is going to be as it depends on the size of the hash table
2434 * isn't determined yet.
2435 */
2436 if (kvm_enabled()) {
2437 spapr->vrma_adjust = 1;
2438 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2439 }
2440
2441 /* Actually we don't support unbounded RMA anymore since we
2442 * added proper emulation of HV mode. The max we can get is
2443 * 16G which also happens to be what we configure for PAPR
2444 * mode so make sure we don't do anything bigger than that
2445 */
2446 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2447 }
2448
2449 if (spapr->rma_size > node0_size) {
2450 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2451 spapr->rma_size);
2452 exit(1);
2453 }
2454
2455 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2456 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2457
2458 /* Set up Interrupt Controller before we create the VCPUs */
2459 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2460
2461 /* Set up containers for ibm,client-architecture-support negotiated options
2462 */
2463 spapr->ov5 = spapr_ovec_new();
2464 spapr->ov5_cas = spapr_ovec_new();
2465
2466 if (smc->dr_lmb_enabled) {
2467 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2468 spapr_validate_node_memory(machine, &error_fatal);
2469 }
2470
2471 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2472 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2473 /* KVM and TCG always allow GTSE with radix... */
2474 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2475 }
2476 /* ... but not with hash (currently). */
2477
2478 /* advertise support for dedicated HP event source to guests */
2479 if (spapr->use_hotplug_event_source) {
2480 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2481 }
2482
2483 /* advertise support for HPT resizing */
2484 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2485 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2486 }
2487
2488 /* init CPUs */
2489 spapr_set_vsmt_mode(spapr, &error_fatal);
2490
2491 spapr_init_cpus(spapr);
2492
2493 if (kvm_enabled()) {
2494 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2495 kvmppc_enable_logical_ci_hcalls();
2496 kvmppc_enable_set_mode_hcall();
2497
2498 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2499 kvmppc_enable_clear_ref_mod_hcalls();
2500 }
2501
2502 /* allocate RAM */
2503 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2504 machine->ram_size);
2505 memory_region_add_subregion(sysmem, 0, ram);
2506
2507 if (rma_alloc_size && rma) {
2508 rma_region = g_new(MemoryRegion, 1);
2509 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2510 rma_alloc_size, rma);
2511 vmstate_register_ram_global(rma_region);
2512 memory_region_add_subregion(sysmem, 0, rma_region);
2513 }
2514
2515 /* initialize hotplug memory address space */
2516 if (machine->ram_size < machine->maxram_size) {
2517 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2518 /*
2519 * Limit the number of hotpluggable memory slots to half the number
2520 * slots that KVM supports, leaving the other half for PCI and other
2521 * devices. However ensure that number of slots doesn't drop below 32.
2522 */
2523 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2524 SPAPR_MAX_RAM_SLOTS;
2525
2526 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2527 max_memslots = SPAPR_MAX_RAM_SLOTS;
2528 }
2529 if (machine->ram_slots > max_memslots) {
2530 error_report("Specified number of memory slots %"
2531 PRIu64" exceeds max supported %d",
2532 machine->ram_slots, max_memslots);
2533 exit(1);
2534 }
2535
2536 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2537 SPAPR_HOTPLUG_MEM_ALIGN);
2538 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2539 "hotplug-memory", hotplug_mem_size);
2540 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2541 &spapr->hotplug_memory.mr);
2542 }
2543
2544 if (smc->dr_lmb_enabled) {
2545 spapr_create_lmb_dr_connectors(spapr);
2546 }
2547
2548 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2549 if (!filename) {
2550 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2551 exit(1);
2552 }
2553 spapr->rtas_size = get_image_size(filename);
2554 if (spapr->rtas_size < 0) {
2555 error_report("Could not get size of LPAR rtas '%s'", filename);
2556 exit(1);
2557 }
2558 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2559 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2560 error_report("Could not load LPAR rtas '%s'", filename);
2561 exit(1);
2562 }
2563 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2564 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2565 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2566 exit(1);
2567 }
2568 g_free(filename);
2569
2570 /* Set up RTAS event infrastructure */
2571 spapr_events_init(spapr);
2572
2573 /* Set up the RTC RTAS interfaces */
2574 spapr_rtc_create(spapr);
2575
2576 /* Set up VIO bus */
2577 spapr->vio_bus = spapr_vio_bus_init();
2578
2579 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2580 if (serial_hds[i]) {
2581 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2582 }
2583 }
2584
2585 /* We always have at least the nvram device on VIO */
2586 spapr_create_nvram(spapr);
2587
2588 /* Set up PCI */
2589 spapr_pci_rtas_init();
2590
2591 phb = spapr_create_phb(spapr, 0);
2592
2593 for (i = 0; i < nb_nics; i++) {
2594 NICInfo *nd = &nd_table[i];
2595
2596 if (!nd->model) {
2597 nd->model = g_strdup("ibmveth");
2598 }
2599
2600 if (strcmp(nd->model, "ibmveth") == 0) {
2601 spapr_vlan_create(spapr->vio_bus, nd);
2602 } else {
2603 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2604 }
2605 }
2606
2607 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2608 spapr_vscsi_create(spapr->vio_bus);
2609 }
2610
2611 /* Graphics */
2612 if (spapr_vga_init(phb->bus, &error_fatal)) {
2613 spapr->has_graphics = true;
2614 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2615 }
2616
2617 if (machine->usb) {
2618 if (smc->use_ohci_by_default) {
2619 pci_create_simple(phb->bus, -1, "pci-ohci");
2620 } else {
2621 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2622 }
2623
2624 if (spapr->has_graphics) {
2625 USBBus *usb_bus = usb_bus_find(-1);
2626
2627 usb_create_simple(usb_bus, "usb-kbd");
2628 usb_create_simple(usb_bus, "usb-mouse");
2629 }
2630 }
2631
2632 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2633 error_report(
2634 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2635 MIN_RMA_SLOF);
2636 exit(1);
2637 }
2638
2639 if (kernel_filename) {
2640 uint64_t lowaddr = 0;
2641
2642 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2643 NULL, NULL, &lowaddr, NULL, 1,
2644 PPC_ELF_MACHINE, 0, 0);
2645 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2646 spapr->kernel_size = load_elf(kernel_filename,
2647 translate_kernel_address, NULL, NULL,
2648 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2649 0, 0);
2650 spapr->kernel_le = spapr->kernel_size > 0;
2651 }
2652 if (spapr->kernel_size < 0) {
2653 error_report("error loading %s: %s", kernel_filename,
2654 load_elf_strerror(spapr->kernel_size));
2655 exit(1);
2656 }
2657
2658 /* load initrd */
2659 if (initrd_filename) {
2660 /* Try to locate the initrd in the gap between the kernel
2661 * and the firmware. Add a bit of space just in case
2662 */
2663 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2664 + 0x1ffff) & ~0xffff;
2665 spapr->initrd_size = load_image_targphys(initrd_filename,
2666 spapr->initrd_base,
2667 load_limit
2668 - spapr->initrd_base);
2669 if (spapr->initrd_size < 0) {
2670 error_report("could not load initial ram disk '%s'",
2671 initrd_filename);
2672 exit(1);
2673 }
2674 }
2675 }
2676
2677 if (bios_name == NULL) {
2678 bios_name = FW_FILE_NAME;
2679 }
2680 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2681 if (!filename) {
2682 error_report("Could not find LPAR firmware '%s'", bios_name);
2683 exit(1);
2684 }
2685 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2686 if (fw_size <= 0) {
2687 error_report("Could not load LPAR firmware '%s'", filename);
2688 exit(1);
2689 }
2690 g_free(filename);
2691
2692 /* FIXME: Should register things through the MachineState's qdev
2693 * interface, this is a legacy from the sPAPREnvironment structure
2694 * which predated MachineState but had a similar function */
2695 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2696 register_savevm_live(NULL, "spapr/htab", -1, 1,
2697 &savevm_htab_handlers, spapr);
2698
2699 qemu_register_boot_set(spapr_boot_set, spapr);
2700
2701 if (kvm_enabled()) {
2702 /* to stop and start vmclock */
2703 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2704 &spapr->tb);
2705
2706 kvmppc_spapr_enable_inkernel_multitce();
2707 }
2708 }
2709
2710 static int spapr_kvm_type(const char *vm_type)
2711 {
2712 if (!vm_type) {
2713 return 0;
2714 }
2715
2716 if (!strcmp(vm_type, "HV")) {
2717 return 1;
2718 }
2719
2720 if (!strcmp(vm_type, "PR")) {
2721 return 2;
2722 }
2723
2724 error_report("Unknown kvm-type specified '%s'", vm_type);
2725 exit(1);
2726 }
2727
2728 /*
2729 * Implementation of an interface to adjust firmware path
2730 * for the bootindex property handling.
2731 */
2732 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2733 DeviceState *dev)
2734 {
2735 #define CAST(type, obj, name) \
2736 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2737 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2738 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2739 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2740
2741 if (d) {
2742 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2743 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2744 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2745
2746 if (spapr) {
2747 /*
2748 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2749 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2750 * in the top 16 bits of the 64-bit LUN
2751 */
2752 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2753 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2754 (uint64_t)id << 48);
2755 } else if (virtio) {
2756 /*
2757 * We use SRP luns of the form 01000000 | (target << 8) | lun
2758 * in the top 32 bits of the 64-bit LUN
2759 * Note: the quote above is from SLOF and it is wrong,
2760 * the actual binding is:
2761 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2762 */
2763 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2764 if (d->lun >= 256) {
2765 /* Use the LUN "flat space addressing method" */
2766 id |= 0x4000;
2767 }
2768 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2769 (uint64_t)id << 32);
2770 } else if (usb) {
2771 /*
2772 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2773 * in the top 32 bits of the 64-bit LUN
2774 */
2775 unsigned usb_port = atoi(usb->port->path);
2776 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2777 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2778 (uint64_t)id << 32);
2779 }
2780 }
2781
2782 /*
2783 * SLOF probes the USB devices, and if it recognizes that the device is a
2784 * storage device, it changes its name to "storage" instead of "usb-host",
2785 * and additionally adds a child node for the SCSI LUN, so the correct
2786 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2787 */
2788 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2789 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2790 if (usb_host_dev_is_scsi_storage(usbdev)) {
2791 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2792 }
2793 }
2794
2795 if (phb) {
2796 /* Replace "pci" with "pci@800000020000000" */
2797 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2798 }
2799
2800 if (vsc) {
2801 /* Same logic as virtio above */
2802 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2803 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2804 }
2805
2806 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2807 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
2808 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2809 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2810 }
2811
2812 return NULL;
2813 }
2814
2815 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2816 {
2817 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2818
2819 return g_strdup(spapr->kvm_type);
2820 }
2821
2822 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2823 {
2824 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2825
2826 g_free(spapr->kvm_type);
2827 spapr->kvm_type = g_strdup(value);
2828 }
2829
2830 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2831 {
2832 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2833
2834 return spapr->use_hotplug_event_source;
2835 }
2836
2837 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2838 Error **errp)
2839 {
2840 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2841
2842 spapr->use_hotplug_event_source = value;
2843 }
2844
2845 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2846 {
2847 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2848
2849 switch (spapr->resize_hpt) {
2850 case SPAPR_RESIZE_HPT_DEFAULT:
2851 return g_strdup("default");
2852 case SPAPR_RESIZE_HPT_DISABLED:
2853 return g_strdup("disabled");
2854 case SPAPR_RESIZE_HPT_ENABLED:
2855 return g_strdup("enabled");
2856 case SPAPR_RESIZE_HPT_REQUIRED:
2857 return g_strdup("required");
2858 }
2859 g_assert_not_reached();
2860 }
2861
2862 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
2863 {
2864 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2865
2866 if (strcmp(value, "default") == 0) {
2867 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
2868 } else if (strcmp(value, "disabled") == 0) {
2869 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2870 } else if (strcmp(value, "enabled") == 0) {
2871 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
2872 } else if (strcmp(value, "required") == 0) {
2873 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
2874 } else {
2875 error_setg(errp, "Bad value for \"resize-hpt\" property");
2876 }
2877 }
2878
2879 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
2880 void *opaque, Error **errp)
2881 {
2882 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2883 }
2884
2885 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
2886 void *opaque, Error **errp)
2887 {
2888 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2889 }
2890
2891 static void spapr_instance_init(Object *obj)
2892 {
2893 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2894
2895 spapr->htab_fd = -1;
2896 spapr->use_hotplug_event_source = true;
2897 object_property_add_str(obj, "kvm-type",
2898 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2899 object_property_set_description(obj, "kvm-type",
2900 "Specifies the KVM virtualization mode (HV, PR)",
2901 NULL);
2902 object_property_add_bool(obj, "modern-hotplug-events",
2903 spapr_get_modern_hotplug_events,
2904 spapr_set_modern_hotplug_events,
2905 NULL);
2906 object_property_set_description(obj, "modern-hotplug-events",
2907 "Use dedicated hotplug event mechanism in"
2908 " place of standard EPOW events when possible"
2909 " (required for memory hot-unplug support)",
2910 NULL);
2911
2912 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
2913 "Maximum permitted CPU compatibility mode",
2914 &error_fatal);
2915
2916 object_property_add_str(obj, "resize-hpt",
2917 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
2918 object_property_set_description(obj, "resize-hpt",
2919 "Resizing of the Hash Page Table (enabled, disabled, required)",
2920 NULL);
2921 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
2922 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
2923 object_property_set_description(obj, "vsmt",
2924 "Virtual SMT: KVM behaves as if this were"
2925 " the host's SMT mode", &error_abort);
2926 }
2927
2928 static void spapr_machine_finalizefn(Object *obj)
2929 {
2930 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2931
2932 g_free(spapr->kvm_type);
2933 }
2934
2935 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2936 {
2937 cpu_synchronize_state(cs);
2938 ppc_cpu_do_system_reset(cs);
2939 }
2940
2941 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2942 {
2943 CPUState *cs;
2944
2945 CPU_FOREACH(cs) {
2946 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2947 }
2948 }
2949
2950 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2951 uint32_t node, bool dedicated_hp_event_source,
2952 Error **errp)
2953 {
2954 sPAPRDRConnector *drc;
2955 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2956 int i, fdt_offset, fdt_size;
2957 void *fdt;
2958 uint64_t addr = addr_start;
2959 bool hotplugged = spapr_drc_hotplugged(dev);
2960 Error *local_err = NULL;
2961
2962 for (i = 0; i < nr_lmbs; i++) {
2963 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2964 addr / SPAPR_MEMORY_BLOCK_SIZE);
2965 g_assert(drc);
2966
2967 fdt = create_device_tree(&fdt_size);
2968 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2969 SPAPR_MEMORY_BLOCK_SIZE);
2970
2971 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
2972 if (local_err) {
2973 while (addr > addr_start) {
2974 addr -= SPAPR_MEMORY_BLOCK_SIZE;
2975 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2976 addr / SPAPR_MEMORY_BLOCK_SIZE);
2977 spapr_drc_detach(drc);
2978 }
2979 g_free(fdt);
2980 error_propagate(errp, local_err);
2981 return;
2982 }
2983 if (!hotplugged) {
2984 spapr_drc_reset(drc);
2985 }
2986 addr += SPAPR_MEMORY_BLOCK_SIZE;
2987 }
2988 /* send hotplug notification to the
2989 * guest only in case of hotplugged memory
2990 */
2991 if (hotplugged) {
2992 if (dedicated_hp_event_source) {
2993 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2994 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2995 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2996 nr_lmbs,
2997 spapr_drc_index(drc));
2998 } else {
2999 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3000 nr_lmbs);
3001 }
3002 }
3003 }
3004
3005 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3006 uint32_t node, Error **errp)
3007 {
3008 Error *local_err = NULL;
3009 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3010 PCDIMMDevice *dimm = PC_DIMM(dev);
3011 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3012 MemoryRegion *mr;
3013 uint64_t align, size, addr;
3014
3015 mr = ddc->get_memory_region(dimm, &local_err);
3016 if (local_err) {
3017 goto out;
3018 }
3019 align = memory_region_get_alignment(mr);
3020 size = memory_region_size(mr);
3021
3022 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
3023 if (local_err) {
3024 goto out;
3025 }
3026
3027 addr = object_property_get_uint(OBJECT(dimm),
3028 PC_DIMM_ADDR_PROP, &local_err);
3029 if (local_err) {
3030 goto out_unplug;
3031 }
3032
3033 spapr_add_lmbs(dev, addr, size, node,
3034 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3035 &local_err);
3036 if (local_err) {
3037 goto out_unplug;
3038 }
3039
3040 return;
3041
3042 out_unplug:
3043 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
3044 out:
3045 error_propagate(errp, local_err);
3046 }
3047
3048 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3049 Error **errp)
3050 {
3051 PCDIMMDevice *dimm = PC_DIMM(dev);
3052 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3053 MemoryRegion *mr;
3054 uint64_t size;
3055 char *mem_dev;
3056
3057 mr = ddc->get_memory_region(dimm, errp);
3058 if (!mr) {
3059 return;
3060 }
3061 size = memory_region_size(mr);
3062
3063 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3064 error_setg(errp, "Hotplugged memory size must be a multiple of "
3065 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
3066 return;
3067 }
3068
3069 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
3070 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
3071 error_setg(errp, "Memory backend has bad page size. "
3072 "Use 'memory-backend-file' with correct mem-path.");
3073 goto out;
3074 }
3075
3076 out:
3077 g_free(mem_dev);
3078 }
3079
3080 struct sPAPRDIMMState {
3081 PCDIMMDevice *dimm;
3082 uint32_t nr_lmbs;
3083 QTAILQ_ENTRY(sPAPRDIMMState) next;
3084 };
3085
3086 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
3087 PCDIMMDevice *dimm)
3088 {
3089 sPAPRDIMMState *dimm_state = NULL;
3090
3091 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3092 if (dimm_state->dimm == dimm) {
3093 break;
3094 }
3095 }
3096 return dimm_state;
3097 }
3098
3099 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
3100 uint32_t nr_lmbs,
3101 PCDIMMDevice *dimm)
3102 {
3103 sPAPRDIMMState *ds = NULL;
3104
3105 /*
3106 * If this request is for a DIMM whose removal had failed earlier
3107 * (due to guest's refusal to remove the LMBs), we would have this
3108 * dimm already in the pending_dimm_unplugs list. In that
3109 * case don't add again.
3110 */
3111 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3112 if (!ds) {
3113 ds = g_malloc0(sizeof(sPAPRDIMMState));
3114 ds->nr_lmbs = nr_lmbs;
3115 ds->dimm = dimm;
3116 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3117 }
3118 return ds;
3119 }
3120
3121 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
3122 sPAPRDIMMState *dimm_state)
3123 {
3124 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3125 g_free(dimm_state);
3126 }
3127
3128 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
3129 PCDIMMDevice *dimm)
3130 {
3131 sPAPRDRConnector *drc;
3132 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3133 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3134 uint64_t size = memory_region_size(mr);
3135 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3136 uint32_t avail_lmbs = 0;
3137 uint64_t addr_start, addr;
3138 int i;
3139
3140 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3141 &error_abort);
3142
3143 addr = addr_start;
3144 for (i = 0; i < nr_lmbs; i++) {
3145 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3146 addr / SPAPR_MEMORY_BLOCK_SIZE);
3147 g_assert(drc);
3148 if (drc->dev) {
3149 avail_lmbs++;
3150 }
3151 addr += SPAPR_MEMORY_BLOCK_SIZE;
3152 }
3153
3154 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3155 }
3156
3157 /* Callback to be called during DRC release. */
3158 void spapr_lmb_release(DeviceState *dev)
3159 {
3160 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev));
3161 PCDIMMDevice *dimm = PC_DIMM(dev);
3162 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3163 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3164 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3165
3166 /* This information will get lost if a migration occurs
3167 * during the unplug process. In this case recover it. */
3168 if (ds == NULL) {
3169 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3170 g_assert(ds);
3171 /* The DRC being examined by the caller at least must be counted */
3172 g_assert(ds->nr_lmbs);
3173 }
3174
3175 if (--ds->nr_lmbs) {
3176 return;
3177 }
3178
3179 /*
3180 * Now that all the LMBs have been removed by the guest, call the
3181 * pc-dimm unplug handler to cleanup up the pc-dimm device.
3182 */
3183 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr);
3184 object_unparent(OBJECT(dev));
3185 spapr_pending_dimm_unplugs_remove(spapr, ds);
3186 }
3187
3188 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3189 DeviceState *dev, Error **errp)
3190 {
3191 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3192 Error *local_err = NULL;
3193 PCDIMMDevice *dimm = PC_DIMM(dev);
3194 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3195 MemoryRegion *mr;
3196 uint32_t nr_lmbs;
3197 uint64_t size, addr_start, addr;
3198 int i;
3199 sPAPRDRConnector *drc;
3200
3201 mr = ddc->get_memory_region(dimm, &local_err);
3202 if (local_err) {
3203 goto out;
3204 }
3205 size = memory_region_size(mr);
3206 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3207
3208 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3209 &local_err);
3210 if (local_err) {
3211 goto out;
3212 }
3213
3214 /*
3215 * An existing pending dimm state for this DIMM means that there is an
3216 * unplug operation in progress, waiting for the spapr_lmb_release
3217 * callback to complete the job (BQL can't cover that far). In this case,
3218 * bail out to avoid detaching DRCs that were already released.
3219 */
3220 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3221 error_setg(&local_err,
3222 "Memory unplug already in progress for device %s",
3223 dev->id);
3224 goto out;
3225 }
3226
3227 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3228
3229 addr = addr_start;
3230 for (i = 0; i < nr_lmbs; i++) {
3231 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3232 addr / SPAPR_MEMORY_BLOCK_SIZE);
3233 g_assert(drc);
3234
3235 spapr_drc_detach(drc);
3236 addr += SPAPR_MEMORY_BLOCK_SIZE;
3237 }
3238
3239 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3240 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3241 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3242 nr_lmbs, spapr_drc_index(drc));
3243 out:
3244 error_propagate(errp, local_err);
3245 }
3246
3247 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3248 sPAPRMachineState *spapr)
3249 {
3250 PowerPCCPU *cpu = POWERPC_CPU(cs);
3251 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3252 int id = spapr_get_vcpu_id(cpu);
3253 void *fdt;
3254 int offset, fdt_size;
3255 char *nodename;
3256
3257 fdt = create_device_tree(&fdt_size);
3258 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3259 offset = fdt_add_subnode(fdt, 0, nodename);
3260
3261 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3262 g_free(nodename);
3263
3264 *fdt_offset = offset;
3265 return fdt;
3266 }
3267
3268 /* Callback to be called during DRC release. */
3269 void spapr_core_release(DeviceState *dev)
3270 {
3271 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev));
3272 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3273 CPUCore *cc = CPU_CORE(dev);
3274 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3275
3276 if (smc->pre_2_10_has_unused_icps) {
3277 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3278 int i;
3279
3280 for (i = 0; i < cc->nr_threads; i++) {
3281 CPUState *cs = CPU(sc->threads[i]);
3282
3283 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3284 }
3285 }
3286
3287 assert(core_slot);
3288 core_slot->cpu = NULL;
3289 object_unparent(OBJECT(dev));
3290 }
3291
3292 static
3293 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3294 Error **errp)
3295 {
3296 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3297 int index;
3298 sPAPRDRConnector *drc;
3299 CPUCore *cc = CPU_CORE(dev);
3300
3301 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3302 error_setg(errp, "Unable to find CPU core with core-id: %d",
3303 cc->core_id);
3304 return;
3305 }
3306 if (index == 0) {
3307 error_setg(errp, "Boot CPU core may not be unplugged");
3308 return;
3309 }
3310
3311 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3312 spapr_vcpu_id(spapr, cc->core_id));
3313 g_assert(drc);
3314
3315 spapr_drc_detach(drc);
3316
3317 spapr_hotplug_req_remove_by_index(drc);
3318 }
3319
3320 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3321 Error **errp)
3322 {
3323 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3324 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3325 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3326 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3327 CPUCore *cc = CPU_CORE(dev);
3328 CPUState *cs = CPU(core->threads[0]);
3329 sPAPRDRConnector *drc;
3330 Error *local_err = NULL;
3331 CPUArchId *core_slot;
3332 int index;
3333 bool hotplugged = spapr_drc_hotplugged(dev);
3334
3335 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3336 if (!core_slot) {
3337 error_setg(errp, "Unable to find CPU core with core-id: %d",
3338 cc->core_id);
3339 return;
3340 }
3341 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3342 spapr_vcpu_id(spapr, cc->core_id));
3343
3344 g_assert(drc || !mc->has_hotpluggable_cpus);
3345
3346 if (drc) {
3347 void *fdt;
3348 int fdt_offset;
3349
3350 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3351
3352 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3353 if (local_err) {
3354 g_free(fdt);
3355 error_propagate(errp, local_err);
3356 return;
3357 }
3358
3359 if (hotplugged) {
3360 /*
3361 * Send hotplug notification interrupt to the guest only
3362 * in case of hotplugged CPUs.
3363 */
3364 spapr_hotplug_req_add_by_index(drc);
3365 } else {
3366 spapr_drc_reset(drc);
3367 }
3368 }
3369
3370 core_slot->cpu = OBJECT(dev);
3371
3372 if (smc->pre_2_10_has_unused_icps) {
3373 int i;
3374
3375 for (i = 0; i < cc->nr_threads; i++) {
3376 cs = CPU(core->threads[i]);
3377 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3378 }
3379 }
3380 }
3381
3382 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3383 Error **errp)
3384 {
3385 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3386 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3387 Error *local_err = NULL;
3388 CPUCore *cc = CPU_CORE(dev);
3389 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3390 const char *type = object_get_typename(OBJECT(dev));
3391 CPUArchId *core_slot;
3392 int index;
3393
3394 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3395 error_setg(&local_err, "CPU hotplug not supported for this machine");
3396 goto out;
3397 }
3398
3399 if (strcmp(base_core_type, type)) {
3400 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3401 goto out;
3402 }
3403
3404 if (cc->core_id % smp_threads) {
3405 error_setg(&local_err, "invalid core id %d", cc->core_id);
3406 goto out;
3407 }
3408
3409 /*
3410 * In general we should have homogeneous threads-per-core, but old
3411 * (pre hotplug support) machine types allow the last core to have
3412 * reduced threads as a compatibility hack for when we allowed
3413 * total vcpus not a multiple of threads-per-core.
3414 */
3415 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3416 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3417 cc->nr_threads, smp_threads);
3418 goto out;
3419 }
3420
3421 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3422 if (!core_slot) {
3423 error_setg(&local_err, "core id %d out of range", cc->core_id);
3424 goto out;
3425 }
3426
3427 if (core_slot->cpu) {
3428 error_setg(&local_err, "core %d already populated", cc->core_id);
3429 goto out;
3430 }
3431
3432 numa_cpu_pre_plug(core_slot, dev, &local_err);
3433
3434 out:
3435 error_propagate(errp, local_err);
3436 }
3437
3438 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3439 DeviceState *dev, Error **errp)
3440 {
3441 MachineState *ms = MACHINE(hotplug_dev);
3442 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3443
3444 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3445 int node;
3446
3447 if (!smc->dr_lmb_enabled) {
3448 error_setg(errp, "Memory hotplug not supported for this machine");
3449 return;
3450 }
3451 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
3452 if (*errp) {
3453 return;
3454 }
3455 if (node < 0 || node >= MAX_NODES) {
3456 error_setg(errp, "Invaild node %d", node);
3457 return;
3458 }
3459
3460 /*
3461 * Currently PowerPC kernel doesn't allow hot-adding memory to
3462 * memory-less node, but instead will silently add the memory
3463 * to the first node that has some memory. This causes two
3464 * unexpected behaviours for the user.
3465 *
3466 * - Memory gets hotplugged to a different node than what the user
3467 * specified.
3468 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
3469 * to memory-less node, a reboot will set things accordingly
3470 * and the previously hotplugged memory now ends in the right node.
3471 * This appears as if some memory moved from one node to another.
3472 *
3473 * So until kernel starts supporting memory hotplug to memory-less
3474 * nodes, just prevent such attempts upfront in QEMU.
3475 */
3476 if (nb_numa_nodes && !numa_info[node].node_mem) {
3477 error_setg(errp, "Can't hotplug memory to memory-less node %d",
3478 node);
3479 return;
3480 }
3481
3482 spapr_memory_plug(hotplug_dev, dev, node, errp);
3483 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3484 spapr_core_plug(hotplug_dev, dev, errp);
3485 }
3486 }
3487
3488 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3489 DeviceState *dev, Error **errp)
3490 {
3491 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
3492 MachineClass *mc = MACHINE_GET_CLASS(sms);
3493
3494 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3495 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3496 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3497 } else {
3498 /* NOTE: this means there is a window after guest reset, prior to
3499 * CAS negotiation, where unplug requests will fail due to the
3500 * capability not being detected yet. This is a bit different than
3501 * the case with PCI unplug, where the events will be queued and
3502 * eventually handled by the guest after boot
3503 */
3504 error_setg(errp, "Memory hot unplug not supported for this guest");
3505 }
3506 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3507 if (!mc->has_hotpluggable_cpus) {
3508 error_setg(errp, "CPU hot unplug not supported on this machine");
3509 return;
3510 }
3511 spapr_core_unplug_request(hotplug_dev, dev, errp);
3512 }
3513 }
3514
3515 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3516 DeviceState *dev, Error **errp)
3517 {
3518 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3519 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3520 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3521 spapr_core_pre_plug(hotplug_dev, dev, errp);
3522 }
3523 }
3524
3525 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3526 DeviceState *dev)
3527 {
3528 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3529 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3530 return HOTPLUG_HANDLER(machine);
3531 }
3532 return NULL;
3533 }
3534
3535 static CpuInstanceProperties
3536 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3537 {
3538 CPUArchId *core_slot;
3539 MachineClass *mc = MACHINE_GET_CLASS(machine);
3540
3541 /* make sure possible_cpu are intialized */
3542 mc->possible_cpu_arch_ids(machine);
3543 /* get CPU core slot containing thread that matches cpu_index */
3544 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3545 assert(core_slot);
3546 return core_slot->props;
3547 }
3548
3549 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
3550 {
3551 return idx / smp_cores % nb_numa_nodes;
3552 }
3553
3554 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3555 {
3556 int i;
3557 const char *core_type;
3558 int spapr_max_cores = max_cpus / smp_threads;
3559 MachineClass *mc = MACHINE_GET_CLASS(machine);
3560
3561 if (!mc->has_hotpluggable_cpus) {
3562 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3563 }
3564 if (machine->possible_cpus) {
3565 assert(machine->possible_cpus->len == spapr_max_cores);
3566 return machine->possible_cpus;
3567 }
3568
3569 core_type = spapr_get_cpu_core_type(machine->cpu_type);
3570 if (!core_type) {
3571 error_report("Unable to find sPAPR CPU Core definition");
3572 exit(1);
3573 }
3574
3575 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3576 sizeof(CPUArchId) * spapr_max_cores);
3577 machine->possible_cpus->len = spapr_max_cores;
3578 for (i = 0; i < machine->possible_cpus->len; i++) {
3579 int core_id = i * smp_threads;
3580
3581 machine->possible_cpus->cpus[i].type = core_type;
3582 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3583 machine->possible_cpus->cpus[i].arch_id = core_id;
3584 machine->possible_cpus->cpus[i].props.has_core_id = true;
3585 machine->possible_cpus->cpus[i].props.core_id = core_id;
3586 }
3587 return machine->possible_cpus;
3588 }
3589
3590 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3591 uint64_t *buid, hwaddr *pio,
3592 hwaddr *mmio32, hwaddr *mmio64,
3593 unsigned n_dma, uint32_t *liobns, Error **errp)
3594 {
3595 /*
3596 * New-style PHB window placement.
3597 *
3598 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3599 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3600 * windows.
3601 *
3602 * Some guest kernels can't work with MMIO windows above 1<<46
3603 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3604 *
3605 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3606 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3607 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3608 * 1TiB 64-bit MMIO windows for each PHB.
3609 */
3610 const uint64_t base_buid = 0x800000020000000ULL;
3611 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3612 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3613 int i;
3614
3615 /* Sanity check natural alignments */
3616 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3617 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3618 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3619 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3620 /* Sanity check bounds */
3621 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3622 SPAPR_PCI_MEM32_WIN_SIZE);
3623 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3624 SPAPR_PCI_MEM64_WIN_SIZE);
3625
3626 if (index >= SPAPR_MAX_PHBS) {
3627 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3628 SPAPR_MAX_PHBS - 1);
3629 return;
3630 }
3631
3632 *buid = base_buid + index;
3633 for (i = 0; i < n_dma; ++i) {
3634 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3635 }
3636
3637 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3638 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3639 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3640 }
3641
3642 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3643 {
3644 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3645
3646 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3647 }
3648
3649 static void spapr_ics_resend(XICSFabric *dev)
3650 {
3651 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3652
3653 ics_resend(spapr->ics);
3654 }
3655
3656 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
3657 {
3658 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
3659
3660 return cpu ? ICP(cpu->intc) : NULL;
3661 }
3662
3663 #define ICS_IRQ_FREE(ics, srcno) \
3664 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
3665
3666 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
3667 {
3668 int first, i;
3669
3670 for (first = 0; first < ics->nr_irqs; first += alignnum) {
3671 if (num > (ics->nr_irqs - first)) {
3672 return -1;
3673 }
3674 for (i = first; i < first + num; ++i) {
3675 if (!ICS_IRQ_FREE(ics, i)) {
3676 break;
3677 }
3678 }
3679 if (i == (first + num)) {
3680 return first;
3681 }
3682 }
3683
3684 return -1;
3685 }
3686
3687 /*
3688 * Allocate the IRQ number and set the IRQ type, LSI or MSI
3689 */
3690 static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi)
3691 {
3692 ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi);
3693 }
3694
3695 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
3696 Error **errp)
3697 {
3698 ICSState *ics = spapr->ics;
3699 int irq;
3700
3701 if (!ics) {
3702 return -1;
3703 }
3704 if (irq_hint) {
3705 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
3706 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
3707 return -1;
3708 }
3709 irq = irq_hint;
3710 } else {
3711 irq = ics_find_free_block(ics, 1, 1);
3712 if (irq < 0) {
3713 error_setg(errp, "can't allocate IRQ: no IRQ left");
3714 return -1;
3715 }
3716 irq += ics->offset;
3717 }
3718
3719 spapr_irq_set_lsi(spapr, irq, lsi);
3720 trace_spapr_irq_alloc(irq);
3721
3722 return irq;
3723 }
3724
3725 /*
3726 * Allocate block of consecutive IRQs, and return the number of the first IRQ in
3727 * the block. If align==true, aligns the first IRQ number to num.
3728 */
3729 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi,
3730 bool align, Error **errp)
3731 {
3732 ICSState *ics = spapr->ics;
3733 int i, first = -1;
3734
3735 if (!ics) {
3736 return -1;
3737 }
3738
3739 /*
3740 * MSIMesage::data is used for storing VIRQ so
3741 * it has to be aligned to num to support multiple
3742 * MSI vectors. MSI-X is not affected by this.
3743 * The hint is used for the first IRQ, the rest should
3744 * be allocated continuously.
3745 */
3746 if (align) {
3747 assert((num == 1) || (num == 2) || (num == 4) ||
3748 (num == 8) || (num == 16) || (num == 32));
3749 first = ics_find_free_block(ics, num, num);
3750 } else {
3751 first = ics_find_free_block(ics, num, 1);
3752 }
3753 if (first < 0) {
3754 error_setg(errp, "can't find a free %d-IRQ block", num);
3755 return -1;
3756 }
3757
3758 first += ics->offset;
3759 for (i = first; i < first + num; ++i) {
3760 spapr_irq_set_lsi(spapr, i, lsi);
3761 }
3762
3763 trace_spapr_irq_alloc_block(first, num, lsi, align);
3764
3765 return first;
3766 }
3767
3768 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
3769 {
3770 ICSState *ics = spapr->ics;
3771 int srcno = irq - ics->offset;
3772 int i;
3773
3774 if (ics_valid_irq(ics, irq)) {
3775 trace_spapr_irq_free(0, irq, num);
3776 for (i = srcno; i < srcno + num; ++i) {
3777 if (ICS_IRQ_FREE(ics, i)) {
3778 trace_spapr_irq_free_warn(0, i + ics->offset);
3779 }
3780 memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
3781 }
3782 }
3783 }
3784
3785 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
3786 {
3787 ICSState *ics = spapr->ics;
3788
3789 if (ics_valid_irq(ics, irq)) {
3790 return ics->qirqs[irq - ics->offset];
3791 }
3792
3793 return NULL;
3794 }
3795
3796 static void spapr_pic_print_info(InterruptStatsProvider *obj,
3797 Monitor *mon)
3798 {
3799 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3800 CPUState *cs;
3801
3802 CPU_FOREACH(cs) {
3803 PowerPCCPU *cpu = POWERPC_CPU(cs);
3804
3805 icp_pic_print_info(ICP(cpu->intc), mon);
3806 }
3807
3808 ics_pic_print_info(spapr->ics, mon);
3809 }
3810
3811 int spapr_get_vcpu_id(PowerPCCPU *cpu)
3812 {
3813 CPUState *cs = CPU(cpu);
3814
3815 if (kvm_enabled()) {
3816 return kvm_arch_vcpu_id(cs);
3817 } else {
3818 return cs->cpu_index;
3819 }
3820 }
3821
3822 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
3823 {
3824 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
3825 int vcpu_id;
3826
3827 vcpu_id = spapr_vcpu_id(spapr, cpu_index);
3828
3829 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
3830 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
3831 error_append_hint(errp, "Adjust the number of cpus to %d "
3832 "or try to raise the number of threads per core\n",
3833 vcpu_id * smp_threads / spapr->vsmt);
3834 return;
3835 }
3836
3837 cpu->vcpu_id = vcpu_id;
3838 }
3839
3840 PowerPCCPU *spapr_find_cpu(int vcpu_id)
3841 {
3842 CPUState *cs;
3843
3844 CPU_FOREACH(cs) {
3845 PowerPCCPU *cpu = POWERPC_CPU(cs);
3846
3847 if (spapr_get_vcpu_id(cpu) == vcpu_id) {
3848 return cpu;
3849 }
3850 }
3851
3852 return NULL;
3853 }
3854
3855 static void spapr_machine_class_init(ObjectClass *oc, void *data)
3856 {
3857 MachineClass *mc = MACHINE_CLASS(oc);
3858 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3859 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3860 NMIClass *nc = NMI_CLASS(oc);
3861 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3862 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3863 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3864 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3865
3866 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3867
3868 /*
3869 * We set up the default / latest behaviour here. The class_init
3870 * functions for the specific versioned machine types can override
3871 * these details for backwards compatibility
3872 */
3873 mc->init = spapr_machine_init;
3874 mc->reset = spapr_machine_reset;
3875 mc->block_default_type = IF_SCSI;
3876 mc->max_cpus = 1024;
3877 mc->no_parallel = 1;
3878 mc->default_boot_order = "";
3879 mc->default_ram_size = 512 * M_BYTE;
3880 mc->kvm_type = spapr_kvm_type;
3881 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
3882 mc->pci_allow_0_address = true;
3883 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3884 hc->pre_plug = spapr_machine_device_pre_plug;
3885 hc->plug = spapr_machine_device_plug;
3886 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3887 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
3888 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3889 hc->unplug_request = spapr_machine_device_unplug_request;
3890
3891 smc->dr_lmb_enabled = true;
3892 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
3893 mc->has_hotpluggable_cpus = true;
3894 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3895 fwc->get_dev_path = spapr_get_fw_dev_path;
3896 nc->nmi_monitor_handler = spapr_nmi;
3897 smc->phb_placement = spapr_phb_placement;
3898 vhc->hypercall = emulate_spapr_hypercall;
3899 vhc->hpt_mask = spapr_hpt_mask;
3900 vhc->map_hptes = spapr_map_hptes;
3901 vhc->unmap_hptes = spapr_unmap_hptes;
3902 vhc->store_hpte = spapr_store_hpte;
3903 vhc->get_patbe = spapr_get_patbe;
3904 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
3905 xic->ics_get = spapr_ics_get;
3906 xic->ics_resend = spapr_ics_resend;
3907 xic->icp_get = spapr_icp_get;
3908 ispc->print_info = spapr_pic_print_info;
3909 /* Force NUMA node memory size to be a multiple of
3910 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3911 * in which LMBs are represented and hot-added
3912 */
3913 mc->numa_mem_align_shift = 28;
3914
3915 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
3916 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
3917 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
3918 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
3919 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
3920 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
3921 spapr_caps_add_properties(smc, &error_abort);
3922 }
3923
3924 static const TypeInfo spapr_machine_info = {
3925 .name = TYPE_SPAPR_MACHINE,
3926 .parent = TYPE_MACHINE,
3927 .abstract = true,
3928 .instance_size = sizeof(sPAPRMachineState),
3929 .instance_init = spapr_instance_init,
3930 .instance_finalize = spapr_machine_finalizefn,
3931 .class_size = sizeof(sPAPRMachineClass),
3932 .class_init = spapr_machine_class_init,
3933 .interfaces = (InterfaceInfo[]) {
3934 { TYPE_FW_PATH_PROVIDER },
3935 { TYPE_NMI },
3936 { TYPE_HOTPLUG_HANDLER },
3937 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3938 { TYPE_XICS_FABRIC },
3939 { TYPE_INTERRUPT_STATS_PROVIDER },
3940 { }
3941 },
3942 };
3943
3944 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3945 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3946 void *data) \
3947 { \
3948 MachineClass *mc = MACHINE_CLASS(oc); \
3949 spapr_machine_##suffix##_class_options(mc); \
3950 if (latest) { \
3951 mc->alias = "pseries"; \
3952 mc->is_default = 1; \
3953 } \
3954 } \
3955 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3956 { \
3957 MachineState *machine = MACHINE(obj); \
3958 spapr_machine_##suffix##_instance_options(machine); \
3959 } \
3960 static const TypeInfo spapr_machine_##suffix##_info = { \
3961 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3962 .parent = TYPE_SPAPR_MACHINE, \
3963 .class_init = spapr_machine_##suffix##_class_init, \
3964 .instance_init = spapr_machine_##suffix##_instance_init, \
3965 }; \
3966 static void spapr_machine_register_##suffix(void) \
3967 { \
3968 type_register(&spapr_machine_##suffix##_info); \
3969 } \
3970 type_init(spapr_machine_register_##suffix)
3971
3972 /*
3973 * pseries-2.12
3974 */
3975 static void spapr_machine_2_12_instance_options(MachineState *machine)
3976 {
3977 }
3978
3979 static void spapr_machine_2_12_class_options(MachineClass *mc)
3980 {
3981 /* Defaults for the latest behaviour inherited from the base class */
3982 }
3983
3984 DEFINE_SPAPR_MACHINE(2_12, "2.12", true);
3985
3986 /*
3987 * pseries-2.11
3988 */
3989 #define SPAPR_COMPAT_2_11 \
3990 HW_COMPAT_2_11
3991
3992 static void spapr_machine_2_11_instance_options(MachineState *machine)
3993 {
3994 spapr_machine_2_12_instance_options(machine);
3995 }
3996
3997 static void spapr_machine_2_11_class_options(MachineClass *mc)
3998 {
3999 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4000
4001 spapr_machine_2_12_class_options(mc);
4002 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4003 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11);
4004 }
4005
4006 DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4007
4008 /*
4009 * pseries-2.10
4010 */
4011 #define SPAPR_COMPAT_2_10 \
4012 HW_COMPAT_2_10
4013
4014 static void spapr_machine_2_10_instance_options(MachineState *machine)
4015 {
4016 spapr_machine_2_11_instance_options(machine);
4017 }
4018
4019 static void spapr_machine_2_10_class_options(MachineClass *mc)
4020 {
4021 spapr_machine_2_11_class_options(mc);
4022 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
4023 }
4024
4025 DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4026
4027 /*
4028 * pseries-2.9
4029 */
4030 #define SPAPR_COMPAT_2_9 \
4031 HW_COMPAT_2_9 \
4032 { \
4033 .driver = TYPE_POWERPC_CPU, \
4034 .property = "pre-2.10-migration", \
4035 .value = "on", \
4036 }, \
4037
4038 static void spapr_machine_2_9_instance_options(MachineState *machine)
4039 {
4040 spapr_machine_2_10_instance_options(machine);
4041 }
4042
4043 static void spapr_machine_2_9_class_options(MachineClass *mc)
4044 {
4045 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4046
4047 spapr_machine_2_10_class_options(mc);
4048 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
4049 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4050 smc->pre_2_10_has_unused_icps = true;
4051 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4052 }
4053
4054 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4055
4056 /*
4057 * pseries-2.8
4058 */
4059 #define SPAPR_COMPAT_2_8 \
4060 HW_COMPAT_2_8 \
4061 { \
4062 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4063 .property = "pcie-extended-configuration-space", \
4064 .value = "off", \
4065 },
4066
4067 static void spapr_machine_2_8_instance_options(MachineState *machine)
4068 {
4069 spapr_machine_2_9_instance_options(machine);
4070 }
4071
4072 static void spapr_machine_2_8_class_options(MachineClass *mc)
4073 {
4074 spapr_machine_2_9_class_options(mc);
4075 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
4076 mc->numa_mem_align_shift = 23;
4077 }
4078
4079 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4080
4081 /*
4082 * pseries-2.7
4083 */
4084 #define SPAPR_COMPAT_2_7 \
4085 HW_COMPAT_2_7 \
4086 { \
4087 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4088 .property = "mem_win_size", \
4089 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
4090 }, \
4091 { \
4092 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4093 .property = "mem64_win_size", \
4094 .value = "0", \
4095 }, \
4096 { \
4097 .driver = TYPE_POWERPC_CPU, \
4098 .property = "pre-2.8-migration", \
4099 .value = "on", \
4100 }, \
4101 { \
4102 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4103 .property = "pre-2.8-migration", \
4104 .value = "on", \
4105 },
4106
4107 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
4108 uint64_t *buid, hwaddr *pio,
4109 hwaddr *mmio32, hwaddr *mmio64,
4110 unsigned n_dma, uint32_t *liobns, Error **errp)
4111 {
4112 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4113 const uint64_t base_buid = 0x800000020000000ULL;
4114 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
4115 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
4116 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
4117 const uint32_t max_index = 255;
4118 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
4119
4120 uint64_t ram_top = MACHINE(spapr)->ram_size;
4121 hwaddr phb0_base, phb_base;
4122 int i;
4123
4124 /* Do we have hotpluggable memory? */
4125 if (MACHINE(spapr)->maxram_size > ram_top) {
4126 /* Can't just use maxram_size, because there may be an
4127 * alignment gap between normal and hotpluggable memory
4128 * regions */
4129 ram_top = spapr->hotplug_memory.base +
4130 memory_region_size(&spapr->hotplug_memory.mr);
4131 }
4132
4133 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4134
4135 if (index > max_index) {
4136 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4137 max_index);
4138 return;
4139 }
4140
4141 *buid = base_buid + index;
4142 for (i = 0; i < n_dma; ++i) {
4143 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4144 }
4145
4146 phb_base = phb0_base + index * phb_spacing;
4147 *pio = phb_base + pio_offset;
4148 *mmio32 = phb_base + mmio_offset;
4149 /*
4150 * We don't set the 64-bit MMIO window, relying on the PHB's
4151 * fallback behaviour of automatically splitting a large "32-bit"
4152 * window into contiguous 32-bit and 64-bit windows
4153 */
4154 }
4155
4156 static void spapr_machine_2_7_instance_options(MachineState *machine)
4157 {
4158 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
4159
4160 spapr_machine_2_8_instance_options(machine);
4161 spapr->use_hotplug_event_source = false;
4162 }
4163
4164 static void spapr_machine_2_7_class_options(MachineClass *mc)
4165 {
4166 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4167
4168 spapr_machine_2_8_class_options(mc);
4169 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4170 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
4171 smc->phb_placement = phb_placement_2_7;
4172 }
4173
4174 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4175
4176 /*
4177 * pseries-2.6
4178 */
4179 #define SPAPR_COMPAT_2_6 \
4180 HW_COMPAT_2_6 \
4181 { \
4182 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4183 .property = "ddw",\
4184 .value = stringify(off),\
4185 },
4186
4187 static void spapr_machine_2_6_instance_options(MachineState *machine)
4188 {
4189 spapr_machine_2_7_instance_options(machine);
4190 }
4191
4192 static void spapr_machine_2_6_class_options(MachineClass *mc)
4193 {
4194 spapr_machine_2_7_class_options(mc);
4195 mc->has_hotpluggable_cpus = false;
4196 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4197 }
4198
4199 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4200
4201 /*
4202 * pseries-2.5
4203 */
4204 #define SPAPR_COMPAT_2_5 \
4205 HW_COMPAT_2_5 \
4206 { \
4207 .driver = "spapr-vlan", \
4208 .property = "use-rx-buffer-pools", \
4209 .value = "off", \
4210 },
4211
4212 static void spapr_machine_2_5_instance_options(MachineState *machine)
4213 {
4214 spapr_machine_2_6_instance_options(machine);
4215 }
4216
4217 static void spapr_machine_2_5_class_options(MachineClass *mc)
4218 {
4219 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4220
4221 spapr_machine_2_6_class_options(mc);
4222 smc->use_ohci_by_default = true;
4223 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
4224 }
4225
4226 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4227
4228 /*
4229 * pseries-2.4
4230 */
4231 #define SPAPR_COMPAT_2_4 \
4232 HW_COMPAT_2_4
4233
4234 static void spapr_machine_2_4_instance_options(MachineState *machine)
4235 {
4236 spapr_machine_2_5_instance_options(machine);
4237 }
4238
4239 static void spapr_machine_2_4_class_options(MachineClass *mc)
4240 {
4241 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4242
4243 spapr_machine_2_5_class_options(mc);
4244 smc->dr_lmb_enabled = false;
4245 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
4246 }
4247
4248 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4249
4250 /*
4251 * pseries-2.3
4252 */
4253 #define SPAPR_COMPAT_2_3 \
4254 HW_COMPAT_2_3 \
4255 {\
4256 .driver = "spapr-pci-host-bridge",\
4257 .property = "dynamic-reconfiguration",\
4258 .value = "off",\
4259 },
4260
4261 static void spapr_machine_2_3_instance_options(MachineState *machine)
4262 {
4263 spapr_machine_2_4_instance_options(machine);
4264 }
4265
4266 static void spapr_machine_2_3_class_options(MachineClass *mc)
4267 {
4268 spapr_machine_2_4_class_options(mc);
4269 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
4270 }
4271 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4272
4273 /*
4274 * pseries-2.2
4275 */
4276
4277 #define SPAPR_COMPAT_2_2 \
4278 HW_COMPAT_2_2 \
4279 {\
4280 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4281 .property = "mem_win_size",\
4282 .value = "0x20000000",\
4283 },
4284
4285 static void spapr_machine_2_2_instance_options(MachineState *machine)
4286 {
4287 spapr_machine_2_3_instance_options(machine);
4288 machine->suppress_vmdesc = true;
4289 }
4290
4291 static void spapr_machine_2_2_class_options(MachineClass *mc)
4292 {
4293 spapr_machine_2_3_class_options(mc);
4294 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4295 }
4296 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4297
4298 /*
4299 * pseries-2.1
4300 */
4301 #define SPAPR_COMPAT_2_1 \
4302 HW_COMPAT_2_1
4303
4304 static void spapr_machine_2_1_instance_options(MachineState *machine)
4305 {
4306 spapr_machine_2_2_instance_options(machine);
4307 }
4308
4309 static void spapr_machine_2_1_class_options(MachineClass *mc)
4310 {
4311 spapr_machine_2_2_class_options(mc);
4312 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
4313 }
4314 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4315
4316 static void spapr_machine_register_types(void)
4317 {
4318 type_register_static(&spapr_machine_info);
4319 }
4320
4321 type_init(spapr_machine_register_types)
AR7 emulation for QEMU