hw/sd/omap_mmc.c

   1 /*
   2  * OMAP on-chip MMC/SD host emulation.
   3  *
   4  * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A)
   5  *
   6  * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 or
  11  * (at your option) version 3 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "hw/hw.h"
  24 #include "hw/arm/omap.h"
  25 #include "hw/sd/sd.h"
  26
  27 struct omap_mmc_s {
  28     qemu_irq irq;
  29     qemu_irq *dma;
  30     qemu_irq coverswitch;
  31     MemoryRegion iomem;
  32     omap_clk clk;
  33     SDState *card;
  34     uint16_t last_cmd;
  35     uint16_t sdio;
  36     uint16_t rsp[8];
  37     uint32_t arg;
  38     int lines;
  39     int dw;
  40     int mode;
  41     int enable;
  42     int be;
  43     int rev;
  44     uint16_t status;
  45     uint16_t mask;
  46     uint8_t cto;
  47     uint16_t dto;
  48     int clkdiv;
  49     uint16_t fifo[32];
  50     int fifo_start;
  51     int fifo_len;
  52     uint16_t blen;
  53     uint16_t blen_counter;
  54     uint16_t nblk;
  55     uint16_t nblk_counter;
  56     int tx_dma;
  57     int rx_dma;
  58     int af_level;
  59     int ae_level;
  60
  61     int ddir;
  62     int transfer;
  63
  64     int cdet_wakeup;
  65     int cdet_enable;
  66     int cdet_state;
  67     qemu_irq cdet;
  68 };
  69
  70 static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
  71 {
  72     qemu_set_irq(s->irq, !!(s->status & s->mask));
  73 }
  74
  75 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
  76 {
  77     if (!host->transfer && !host->fifo_len) {
  78         host->status &= 0xf3ff;
  79         return;
  80     }
  81
  82     if (host->fifo_len > host->af_level && host->ddir) {
  83         if (host->rx_dma) {
  84             host->status &= 0xfbff;
  85             qemu_irq_raise(host->dma[1]);
  86         } else
  87             host->status |= 0x0400;
  88     } else {
  89         host->status &= 0xfbff;
  90         qemu_irq_lower(host->dma[1]);
  91     }
  92
  93     if (host->fifo_len < host->ae_level && !host->ddir) {
  94         if (host->tx_dma) {
  95             host->status &= 0xf7ff;
  96             qemu_irq_raise(host->dma[0]);
  97         } else
  98             host->status |= 0x0800;
  99     } else {
 100         qemu_irq_lower(host->dma[0]);
 101         host->status &= 0xf7ff;
 102     }
 103 }
 104
 105 typedef enum {
 106     sd_nore = 0,        /* no response */
 107     sd_r1,              /* normal response command */
 108     sd_r2,              /* CID, CSD registers */
 109     sd_r3,              /* OCR register */
 110     sd_r6 = 6,          /* Published RCA response */
 111     sd_r1b = -1,
 112 } sd_rsp_type_t;
 113
 114 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
 115                 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
 116 {
 117     uint32_t rspstatus, mask;
 118     int rsplen, timeout;
 119     SDRequest request;
 120     uint8_t response[16];
 121
 122     if (init && cmd == 0) {
 123         host->status |= 0x0001;
 124         return;
 125     }
 126
 127     if (resptype == sd_r1 && busy)
 128         resptype = sd_r1b;
 129
 130     if (type == sd_adtc) {
 131         host->fifo_start = 0;
 132         host->fifo_len = 0;
 133         host->transfer = 1;
 134         host->ddir = dir;
 135     } else
 136         host->transfer = 0;
 137     timeout = 0;
 138     mask = 0;
 139     rspstatus = 0;
 140
 141     request.cmd = cmd;
 142     request.arg = host->arg;
 143     request.crc = 0; /* FIXME */
 144
 145     rsplen = sd_do_command(host->card, &request, response);
 146
 147     /* TODO: validate CRCs */
 148     switch (resptype) {
 149     case sd_nore:
 150         rsplen = 0;
 151         break;
 152
 153     case sd_r1:
 154     case sd_r1b:
 155         if (rsplen < 4) {
 156             timeout = 1;
 157             break;
 158         }
 159         rsplen = 4;
 160
 161         mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
 162                 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
 163                 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
 164                 CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
 165                 CID_CSD_OVERWRITE;
 166         if (host->sdio & (1 << 13))
 167             mask |= AKE_SEQ_ERROR;
 168         rspstatus = ldl_be_p(response);
 169         break;
 170
 171     case sd_r2:
 172         if (rsplen < 16) {
 173             timeout = 1;
 174             break;
 175         }
 176         rsplen = 16;
 177         break;
 178
 179     case sd_r3:
 180         if (rsplen < 4) {
 181             timeout = 1;
 182             break;
 183         }
 184         rsplen = 4;
 185
 186         rspstatus = ldl_be_p(response);
 187         if (rspstatus & 0x80000000)
 188             host->status &= 0xe000;
 189         else
 190             host->status |= 0x1000;
 191         break;
 192
 193     case sd_r6:
 194         if (rsplen < 4) {
 195             timeout = 1;
 196             break;
 197         }
 198         rsplen = 4;
 199
 200         mask = 0xe000 | AKE_SEQ_ERROR;
 201         rspstatus = (response[2] << 8) | (response[3] << 0);
 202     }
 203
 204     if (rspstatus & mask)
 205         host->status |= 0x4000;
 206     else
 207         host->status &= 0xb000;
 208
 209     if (rsplen)
 210         for (rsplen = 0; rsplen < 8; rsplen ++)
 211             host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
 212                     (response[(rsplen << 1) | 0] << 8);
 213
 214     if (timeout)
 215         host->status |= 0x0080;
 216     else if (cmd == 12)
 217         host->status |= 0x0005; /* Makes it more real */
 218     else
 219         host->status |= 0x0001;
 220 }
 221
 222 static void omap_mmc_transfer(struct omap_mmc_s *host)
 223 {
 224     uint8_t value;
 225
 226     if (!host->transfer)
 227         return;
 228
 229     while (1) {
 230         if (host->ddir) {
 231             if (host->fifo_len > host->af_level)
 232                 break;
 233
 234             value = sd_read_data(host->card);
 235             host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
 236             if (-- host->blen_counter) {
 237                 value = sd_read_data(host->card);
 238                 host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
 239                         value << 8;
 240                 host->blen_counter --;
 241             }
 242
 243             host->fifo_len ++;
 244         } else {
 245             if (!host->fifo_len)
 246                 break;
 247
 248             value = host->fifo[host->fifo_start] & 0xff;
 249             sd_write_data(host->card, value);
 250             if (-- host->blen_counter) {
 251                 value = host->fifo[host->fifo_start] >> 8;
 252                 sd_write_data(host->card, value);
 253                 host->blen_counter --;
 254             }
 255
 256             host->fifo_start ++;
 257             host->fifo_len --;
 258             host->fifo_start &= 31;
 259         }
 260
 261         if (host->blen_counter == 0) {
 262             host->nblk_counter --;
 263             host->blen_counter = host->blen;
 264
 265             if (host->nblk_counter == 0) {
 266                 host->nblk_counter = host->nblk;
 267                 host->transfer = 0;
 268                 host->status |= 0x0008;
 269                 break;
 270             }
 271         }
 272     }
 273 }
 274
 275 static void omap_mmc_update(void *opaque)
 276 {
 277     struct omap_mmc_s *s = opaque;
 278     omap_mmc_transfer(s);
 279     omap_mmc_fifolevel_update(s);
 280     omap_mmc_interrupts_update(s);
 281 }
 282
 283 static void omap_mmc_pseudo_reset(struct omap_mmc_s *host)
 284 {
 285     host->status = 0;
 286     host->fifo_len = 0;
 287 }
 288
 289 void omap_mmc_reset(struct omap_mmc_s *host)
 290 {
 291     host->last_cmd = 0;
 292     memset(host->rsp, 0, sizeof(host->rsp));
 293     host->arg = 0;
 294     host->dw = 0;
 295     host->mode = 0;
 296     host->enable = 0;
 297     host->mask = 0;
 298     host->cto = 0;
 299     host->dto = 0;
 300     host->blen = 0;
 301     host->blen_counter = 0;
 302     host->nblk = 0;
 303     host->nblk_counter = 0;
 304     host->tx_dma = 0;
 305     host->rx_dma = 0;
 306     host->ae_level = 0x00;
 307     host->af_level = 0x1f;
 308     host->transfer = 0;
 309     host->cdet_wakeup = 0;
 310     host->cdet_enable = 0;
 311     qemu_set_irq(host->coverswitch, host->cdet_state);
 312     host->clkdiv = 0;
 313
 314     omap_mmc_pseudo_reset(host);
 315
 316     /* Since we're still using the legacy SD API the card is not plugged
 317      * into any bus, and we must reset it manually. When omap_mmc is
 318      * QOMified this must move into the QOM reset function.
 319      */
 320     device_reset(DEVICE(host->card));
 321 }
 322
 323 static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
 324                               unsigned size)
 325 {
 326     uint16_t i;
 327     struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
 328
 329     if (size != 2) {
 330         return omap_badwidth_read16(opaque, offset);
 331     }
 332
 333     switch (offset) {
 334     case 0x00:  /* MMC_CMD */
 335         return s->last_cmd;
 336
 337     case 0x04:  /* MMC_ARGL */
 338         return s->arg & 0x0000ffff;
 339
 340     case 0x08:  /* MMC_ARGH */
 341         return s->arg >> 16;
 342
 343     case 0x0c:  /* MMC_CON */
 344         return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) |
 345                 (s->be << 10) | s->clkdiv;
 346
 347     case 0x10:  /* MMC_STAT */
 348         return s->status;
 349
 350     case 0x14:  /* MMC_IE */
 351         return s->mask;
 352
 353     case 0x18:  /* MMC_CTO */
 354         return s->cto;
 355
 356     case 0x1c:  /* MMC_DTO */
 357         return s->dto;
 358
 359     case 0x20:  /* MMC_DATA */
 360         /* TODO: support 8-bit access */
 361         i = s->fifo[s->fifo_start];
 362         if (s->fifo_len == 0) {
 363             printf("MMC: FIFO underrun\n");
 364             return i;
 365         }
 366         s->fifo_start ++;
 367         s->fifo_len --;
 368         s->fifo_start &= 31;
 369         omap_mmc_transfer(s);
 370         omap_mmc_fifolevel_update(s);
 371         omap_mmc_interrupts_update(s);
 372         return i;
 373
 374     case 0x24:  /* MMC_BLEN */
 375         return s->blen_counter;
 376
 377     case 0x28:  /* MMC_NBLK */
 378         return s->nblk_counter;
 379
 380     case 0x2c:  /* MMC_BUF */
 381         return (s->rx_dma << 15) | (s->af_level << 8) |
 382             (s->tx_dma << 7) | s->ae_level;
 383
 384     case 0x30:  /* MMC_SPI */
 385         return 0x0000;
 386     case 0x34:  /* MMC_SDIO */
 387         return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
 388     case 0x38:  /* MMC_SYST */
 389         return 0x0000;
 390
 391     case 0x3c:  /* MMC_REV */
 392         return s->rev;
 393
 394     case 0x40:  /* MMC_RSP0 */
 395     case 0x44:  /* MMC_RSP1 */
 396     case 0x48:  /* MMC_RSP2 */
 397     case 0x4c:  /* MMC_RSP3 */
 398     case 0x50:  /* MMC_RSP4 */
 399     case 0x54:  /* MMC_RSP5 */
 400     case 0x58:  /* MMC_RSP6 */
 401     case 0x5c:  /* MMC_RSP7 */
 402         return s->rsp[(offset - 0x40) >> 2];
 403
 404     /* OMAP2-specific */
 405     case 0x60:  /* MMC_IOSR */
 406     case 0x64:  /* MMC_SYSC */
 407         return 0;
 408     case 0x68:  /* MMC_SYSS */
 409         return 1;                                               /* RSTD */
 410     }
 411
 412     OMAP_BAD_REG(offset);
 413     return 0;
 414 }
 415
 416 static void omap_mmc_write(void *opaque, hwaddr offset,
 417                            uint64_t value, unsigned size)
 418 {
 419     int i;
 420     struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
 421
 422     if (size != 2) {
 423         omap_badwidth_write16(opaque, offset, value);
 424         return;
 425     }
 426
 427     switch (offset) {
 428     case 0x00:  /* MMC_CMD */
 429         if (!s->enable)
 430             break;
 431
 432         s->last_cmd = value;
 433         for (i = 0; i < 8; i ++)
 434             s->rsp[i] = 0x0000;
 435         omap_mmc_command(s, value & 63, (value >> 15) & 1,
 436                 (sd_cmd_type_t) ((value >> 12) & 3),
 437                 (value >> 11) & 1,
 438                 (sd_rsp_type_t) ((value >> 8) & 7),
 439                 (value >> 7) & 1);
 440         omap_mmc_update(s);
 441         break;
 442
 443     case 0x04:  /* MMC_ARGL */
 444         s->arg &= 0xffff0000;
 445         s->arg |= 0x0000ffff & value;
 446         break;
 447
 448     case 0x08:  /* MMC_ARGH */
 449         s->arg &= 0x0000ffff;
 450         s->arg |= value << 16;
 451         break;
 452
 453     case 0x0c:  /* MMC_CON */
 454         s->dw = (value >> 15) & 1;
 455         s->mode = (value >> 12) & 3;
 456         s->enable = (value >> 11) & 1;
 457         s->be = (value >> 10) & 1;
 458         s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
 459         if (s->mode != 0) {
 460             qemu_log_mask(LOG_UNIMP,
 461                           "omap_mmc_wr: mode #%i unimplemented\n", s->mode);
 462         }
 463         if (s->be != 0) {
 464             qemu_log_mask(LOG_UNIMP,
 465                           "omap_mmc_wr: Big Endian not implemented\n");
 466         }
 467         if (s->dw != 0 && s->lines < 4)
 468             printf("4-bit SD bus enabled\n");
 469         if (!s->enable)
 470             omap_mmc_pseudo_reset(s);
 471         break;
 472
 473     case 0x10:  /* MMC_STAT */
 474         s->status &= ~value;
 475         omap_mmc_interrupts_update(s);
 476         break;
 477
 478     case 0x14:  /* MMC_IE */
 479         s->mask = value & 0x7fff;
 480         omap_mmc_interrupts_update(s);
 481         break;
 482
 483     case 0x18:  /* MMC_CTO */
 484         s->cto = value & 0xff;
 485         if (s->cto > 0xfd && s->rev <= 1)
 486             printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
 487         break;
 488
 489     case 0x1c:  /* MMC_DTO */
 490         s->dto = value & 0xffff;
 491         break;
 492
 493     case 0x20:  /* MMC_DATA */
 494         /* TODO: support 8-bit access */
 495         if (s->fifo_len == 32)
 496             break;
 497         s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
 498         s->fifo_len ++;
 499         omap_mmc_transfer(s);
 500         omap_mmc_fifolevel_update(s);
 501         omap_mmc_interrupts_update(s);
 502         break;
 503
 504     case 0x24:  /* MMC_BLEN */
 505         s->blen = (value & 0x07ff) + 1;
 506         s->blen_counter = s->blen;
 507         break;
 508
 509     case 0x28:  /* MMC_NBLK */
 510         s->nblk = (value & 0x07ff) + 1;
 511         s->nblk_counter = s->nblk;
 512         s->blen_counter = s->blen;
 513         break;
 514
 515     case 0x2c:  /* MMC_BUF */
 516         s->rx_dma = (value >> 15) & 1;
 517         s->af_level = (value >> 8) & 0x1f;
 518         s->tx_dma = (value >> 7) & 1;
 519         s->ae_level = value & 0x1f;
 520
 521         if (s->rx_dma)
 522             s->status &= 0xfbff;
 523         if (s->tx_dma)
 524             s->status &= 0xf7ff;
 525         omap_mmc_fifolevel_update(s);
 526         omap_mmc_interrupts_update(s);
 527         break;
 528
 529     /* SPI, SDIO and TEST modes unimplemented */
 530     case 0x30:  /* MMC_SPI (OMAP1 only) */
 531         break;
 532     case 0x34:  /* MMC_SDIO */
 533         s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
 534         s->cdet_wakeup = (value >> 9) & 1;
 535         s->cdet_enable = (value >> 2) & 1;
 536         break;
 537     case 0x38:  /* MMC_SYST */
 538         break;
 539
 540     case 0x3c:  /* MMC_REV */
 541     case 0x40:  /* MMC_RSP0 */
 542     case 0x44:  /* MMC_RSP1 */
 543     case 0x48:  /* MMC_RSP2 */
 544     case 0x4c:  /* MMC_RSP3 */
 545     case 0x50:  /* MMC_RSP4 */
 546     case 0x54:  /* MMC_RSP5 */
 547     case 0x58:  /* MMC_RSP6 */
 548     case 0x5c:  /* MMC_RSP7 */
 549         OMAP_RO_REG(offset);
 550         break;
 551
 552     /* OMAP2-specific */
 553     case 0x60:  /* MMC_IOSR */
 554         if (value & 0xf)
 555             printf("MMC: SDIO bits used!\n");
 556         break;
 557     case 0x64:  /* MMC_SYSC */
 558         if (value & (1 << 2))                                   /* SRTS */
 559             omap_mmc_reset(s);
 560         break;
 561     case 0x68:  /* MMC_SYSS */
 562         OMAP_RO_REG(offset);
 563         break;
 564
 565     default:
 566         OMAP_BAD_REG(offset);
 567     }
 568 }
 569
 570 static const MemoryRegionOps omap_mmc_ops = {
 571     .read = omap_mmc_read,
 572     .write = omap_mmc_write,
 573     .endianness = DEVICE_NATIVE_ENDIAN,
 574 };
 575
 576 static void omap_mmc_cover_cb(void *opaque, int line, int level)
 577 {
 578     struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
 579
 580     if (!host->cdet_state && level) {
 581         host->status |= 0x0002;
 582         omap_mmc_interrupts_update(host);
 583         if (host->cdet_wakeup) {
 584             /* TODO: Assert wake-up */
 585         }
 586     }
 587
 588     if (host->cdet_state != level) {
 589         qemu_set_irq(host->coverswitch, level);
 590         host->cdet_state = level;
 591     }
 592 }
 593
 594 struct omap_mmc_s *omap_mmc_init(hwaddr base,
 595                 MemoryRegion *sysmem,
 596                 BlockBackend *blk,
 597                 qemu_irq irq, qemu_irq dma[], omap_clk clk)
 598 {
 599     struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
 600
 601     s->irq = irq;
 602     s->dma = dma;
 603     s->clk = clk;
 604     s->lines = 1;       /* TODO: needs to be settable per-board */
 605     s->rev = 1;
 606
 607     memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
 608     memory_region_add_subregion(sysmem, base, &s->iomem);
 609
 610     /* Instantiate the storage */
 611     s->card = sd_init(blk, false);
 612     if (s->card == NULL) {
 613         exit(1);
 614     }
 615
 616     omap_mmc_reset(s);
 617
 618     return s;
 619 }
 620
 621 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
 622                 BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
 623                 omap_clk fclk, omap_clk iclk)
 624 {
 625     struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
 626
 627     s->irq = irq;
 628     s->dma = dma;
 629     s->clk = fclk;
 630     s->lines = 4;
 631     s->rev = 2;
 632
 633     memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
 634                           omap_l4_region_size(ta, 0));
 635     omap_l4_attach(ta, 0, &s->iomem);
 636
 637     /* Instantiate the storage */
 638     s->card = sd_init(blk, false);
 639     if (s->card == NULL) {
 640         exit(1);
 641     }
 642
 643     s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
 644     sd_set_cb(s->card, NULL, s->cdet);
 645
 646     omap_mmc_reset(s);
 647
 648     return s;
 649 }
 650
 651 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
 652 {
 653     if (s->cdet) {
 654         sd_set_cb(s->card, ro, s->cdet);
 655         s->coverswitch = cover;
 656         qemu_set_irq(cover, s->cdet_state);
 657     } else
 658         sd_set_cb(s->card, ro, cover);
 659 }
 660
 661 void omap_mmc_enable(struct omap_mmc_s *s, int enable)
 662 {
 663     sd_enable(s->card, enable);
 664 }