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Merge remote-tracking branch 'remotes/armbru/tags/pull-build-2019-07-02-v2' into...
[qemu/ar7.git] / hw / riscv / spike.c
blobe68be00a5fe8edebccdf93be2708e73a94ccf49d
1 /*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *
9 * 0) HTIF Console and Poweroff
10 * 1) CLINT (Timer and IPI)
11 * 2) PLIC (Platform Level Interrupt Controller)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2 or later, as published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along with
23 * this program. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/log.h"
28 #include "qemu/error-report.h"
29 #include "qapi/error.h"
30 #include "hw/hw.h"
31 #include "hw/boards.h"
32 #include "hw/loader.h"
33 #include "hw/sysbus.h"
34 #include "target/riscv/cpu.h"
35 #include "hw/riscv/riscv_htif.h"
36 #include "hw/riscv/riscv_hart.h"
37 #include "hw/riscv/sifive_clint.h"
38 #include "hw/riscv/spike.h"
39 #include "hw/riscv/boot.h"
40 #include "chardev/char.h"
41 #include "sysemu/arch_init.h"
42 #include "sysemu/device_tree.h"
43 #include "sysemu/qtest.h"
44 #include "exec/address-spaces.h"
45
46 #include <libfdt.h>
47
48 static const struct MemmapEntry {
49 hwaddr base;
50 hwaddr size;
51 } spike_memmap[] = {
52 [SPIKE_MROM] = { 0x1000, 0x11000 },
53 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
54 [SPIKE_DRAM] = { 0x80000000, 0x0 },
55 };
56
57 static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
58 uint64_t mem_size, const char *cmdline)
59 {
60 void *fdt;
61 int cpu;
62 uint32_t *cells;
63 char *nodename;
64
65 fdt = s->fdt = create_device_tree(&s->fdt_size);
66 if (!fdt) {
67 error_report("create_device_tree() failed");
68 exit(1);
69 }
70
71 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
72 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
73 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
74 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
75
76 qemu_fdt_add_subnode(fdt, "/htif");
77 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
78
79 qemu_fdt_add_subnode(fdt, "/soc");
80 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
81 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
82 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
83 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
84
85 nodename = g_strdup_printf("/memory@%lx",
86 (long)memmap[SPIKE_DRAM].base);
87 qemu_fdt_add_subnode(fdt, nodename);
88 qemu_fdt_setprop_cells(fdt, nodename, "reg",
89 memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
90 mem_size >> 32, mem_size);
91 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
92 g_free(nodename);
93
94 qemu_fdt_add_subnode(fdt, "/cpus");
95 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
96 SIFIVE_CLINT_TIMEBASE_FREQ);
97 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
98 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
99
100 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
101 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
102 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
103 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
104 qemu_fdt_add_subnode(fdt, nodename);
105 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
106 SPIKE_CLOCK_FREQ);
107 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
108 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
109 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
110 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
111 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
112 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
113 qemu_fdt_add_subnode(fdt, intc);
114 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
115 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
116 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
117 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
118 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
119 g_free(isa);
120 g_free(intc);
121 g_free(nodename);
122 }
123
124 cells = g_new0(uint32_t, s->soc.num_harts * 4);
125 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
126 nodename =
127 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
128 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
129 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
130 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
131 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
132 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
133 g_free(nodename);
134 }
135 nodename = g_strdup_printf("/soc/clint@%lx",
136 (long)memmap[SPIKE_CLINT].base);
137 qemu_fdt_add_subnode(fdt, nodename);
138 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
139 qemu_fdt_setprop_cells(fdt, nodename, "reg",
140 0x0, memmap[SPIKE_CLINT].base,
141 0x0, memmap[SPIKE_CLINT].size);
142 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
143 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
144 g_free(cells);
145 g_free(nodename);
146
147 if (cmdline) {
148 qemu_fdt_add_subnode(fdt, "/chosen");
149 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
150 }
151 }
152
153 static void spike_board_init(MachineState *machine)
154 {
155 const struct MemmapEntry *memmap = spike_memmap;
156
157 SpikeState *s = g_new0(SpikeState, 1);
158 MemoryRegion *system_memory = get_system_memory();
159 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
160 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
161 int i;
162
163 /* Initialize SOC */
164 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
165 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
166 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
167 &error_abort);
168 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
169 &error_abort);
170 object_property_set_bool(OBJECT(&s->soc), true, "realized",
171 &error_abort);
172
173 /* register system main memory (actual RAM) */
174 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
175 machine->ram_size, &error_fatal);
176 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
177 main_mem);
178
179 /* create device tree */
180 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
181
182 /* boot rom */
183 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
184 memmap[SPIKE_MROM].size, &error_fatal);
185 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
186 mask_rom);
187
188 if (machine->kernel_filename) {
189 riscv_load_kernel(machine->kernel_filename);
190 }
191
192 /* reset vector */
193 uint32_t reset_vec[8] = {
194 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
195 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
196 0xf1402573, /* csrr a0, mhartid */
197 #if defined(TARGET_RISCV32)
198 0x0182a283, /* lw t0, 24(t0) */
199 #elif defined(TARGET_RISCV64)
200 0x0182b283, /* ld t0, 24(t0) */
201 #endif
202 0x00028067, /* jr t0 */
203 0x00000000,
204 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
205 0x00000000,
206 /* dtb: */
207 };
208
209 /* copy in the reset vector in little_endian byte order */
210 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
211 reset_vec[i] = cpu_to_le32(reset_vec[i]);
212 }
213 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
214 memmap[SPIKE_MROM].base, &address_space_memory);
215
216 /* copy in the device tree */
217 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
218 memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
219 error_report("not enough space to store device-tree");
220 exit(1);
221 }
222 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
223 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
224 memmap[SPIKE_MROM].base + sizeof(reset_vec),
225 &address_space_memory);
226
227 /* initialize HTIF using symbols found in load_kernel */
228 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
229
230 /* Core Local Interruptor (timer and IPI) */
231 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
232 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
233 }
234
235 static void spike_v1_10_0_board_init(MachineState *machine)
236 {
237 const struct MemmapEntry *memmap = spike_memmap;
238
239 SpikeState *s = g_new0(SpikeState, 1);
240 MemoryRegion *system_memory = get_system_memory();
241 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
242 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
243 int i;
244
245 if (!qtest_enabled()) {
246 info_report("The Spike v1.10.0 machine has been deprecated. "
247 "Please use the generic spike machine and specify the ISA "
248 "versions using -cpu.");
249 }
250
251 /* Initialize SOC */
252 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
253 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
254 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
255 &error_abort);
256 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
257 &error_abort);
258 object_property_set_bool(OBJECT(&s->soc), true, "realized",
259 &error_abort);
260
261 /* register system main memory (actual RAM) */
262 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
263 machine->ram_size, &error_fatal);
264 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
265 main_mem);
266
267 /* create device tree */
268 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
269
270 /* boot rom */
271 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
272 memmap[SPIKE_MROM].size, &error_fatal);
273 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
274 mask_rom);
275
276 if (machine->kernel_filename) {
277 riscv_load_kernel(machine->kernel_filename);
278 }
279
280 /* reset vector */
281 uint32_t reset_vec[8] = {
282 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
283 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
284 0xf1402573, /* csrr a0, mhartid */
285 #if defined(TARGET_RISCV32)
286 0x0182a283, /* lw t0, 24(t0) */
287 #elif defined(TARGET_RISCV64)
288 0x0182b283, /* ld t0, 24(t0) */
289 #endif
290 0x00028067, /* jr t0 */
291 0x00000000,
292 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
293 0x00000000,
294 /* dtb: */
295 };
296
297 /* copy in the reset vector in little_endian byte order */
298 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
299 reset_vec[i] = cpu_to_le32(reset_vec[i]);
300 }
301 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
302 memmap[SPIKE_MROM].base, &address_space_memory);
303
304 /* copy in the device tree */
305 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
306 memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
307 error_report("not enough space to store device-tree");
308 exit(1);
309 }
310 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
311 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
312 memmap[SPIKE_MROM].base + sizeof(reset_vec),
313 &address_space_memory);
314
315 /* initialize HTIF using symbols found in load_kernel */
316 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
317
318 /* Core Local Interruptor (timer and IPI) */
319 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
320 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
321 }
322
323 static void spike_v1_09_1_board_init(MachineState *machine)
324 {
325 const struct MemmapEntry *memmap = spike_memmap;
326
327 SpikeState *s = g_new0(SpikeState, 1);
328 MemoryRegion *system_memory = get_system_memory();
329 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
330 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
331 int i;
332
333 if (!qtest_enabled()) {
334 info_report("The Spike v1.09.1 machine has been deprecated. "
335 "Please use the generic spike machine and specify the ISA "
336 "versions using -cpu.");
337 }
338
339 /* Initialize SOC */
340 object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
341 TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
342 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
343 &error_abort);
344 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
345 &error_abort);
346 object_property_set_bool(OBJECT(&s->soc), true, "realized",
347 &error_abort);
348
349 /* register system main memory (actual RAM) */
350 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
351 machine->ram_size, &error_fatal);
352 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
353 main_mem);
354
355 /* boot rom */
356 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
357 memmap[SPIKE_MROM].size, &error_fatal);
358 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
359 mask_rom);
360
361 if (machine->kernel_filename) {
362 riscv_load_kernel(machine->kernel_filename);
363 }
364
365 /* reset vector */
366 uint32_t reset_vec[8] = {
367 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
368 0x00028067, /* jump to DRAM_BASE */
369 0x00000000, /* reserved */
370 memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
371 0, 0, 0, 0 /* trap vector */
372 };
373
374 /* part one of config string - before memory size specified */
375 const char *config_string_tmpl =
376 "platform {\n"
377 " vendor ucb;\n"
378 " arch spike;\n"
379 "};\n"
380 "rtc {\n"
381 " addr 0x%" PRIx64 "x;\n"
382 "};\n"
383 "ram {\n"
384 " 0 {\n"
385 " addr 0x%" PRIx64 "x;\n"
386 " size 0x%" PRIx64 "x;\n"
387 " };\n"
388 "};\n"
389 "core {\n"
390 " 0" " {\n"
391 " " "0 {\n"
392 " isa %s;\n"
393 " timecmp 0x%" PRIx64 "x;\n"
394 " ipi 0x%" PRIx64 "x;\n"
395 " };\n"
396 " };\n"
397 "};\n";
398
399 /* build config string with supplied memory size */
400 char *isa = riscv_isa_string(&s->soc.harts[0]);
401 char *config_string = g_strdup_printf(config_string_tmpl,
402 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
403 (uint64_t)memmap[SPIKE_DRAM].base,
404 (uint64_t)ram_size, isa,
405 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
406 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
407 g_free(isa);
408 size_t config_string_len = strlen(config_string);
409
410 /* copy in the reset vector in little_endian byte order */
411 for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
412 reset_vec[i] = cpu_to_le32(reset_vec[i]);
413 }
414 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
415 memmap[SPIKE_MROM].base, &address_space_memory);
416
417 /* copy in the config string */
418 rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
419 memmap[SPIKE_MROM].base + sizeof(reset_vec),
420 &address_space_memory);
421
422 /* initialize HTIF using symbols found in load_kernel */
423 htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
424
425 /* Core Local Interruptor (timer and IPI) */
426 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
427 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
428
429 g_free(config_string);
430 }
431
432 static void spike_v1_09_1_machine_init(MachineClass *mc)
433 {
434 mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
435 mc->init = spike_v1_09_1_board_init;
436 mc->max_cpus = 1;
437 }
438
439 static void spike_v1_10_0_machine_init(MachineClass *mc)
440 {
441 mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
442 mc->init = spike_v1_10_0_board_init;
443 mc->max_cpus = 1;
444 }
445
446 static void spike_machine_init(MachineClass *mc)
447 {
448 mc->desc = "RISC-V Spike Board";
449 mc->init = spike_board_init;
450 mc->max_cpus = 1;
451 mc->is_default = 1;
452 mc->default_cpu_type = SPIKE_V1_10_0_CPU;
453 }
454
455 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
456 DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
457 DEFINE_MACHINE("spike", spike_machine_init)
AR7 emulation for QEMU