hw/riscv/sifive_plic.c

   1 /*
   2  * SiFive PLIC (Platform Level Interrupt Controller)
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This provides a parameterizable interrupt controller based on SiFive's PLIC.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24 #include "qemu/error-report.h"
  25 #include "hw/sysbus.h"
  26 #include "hw/pci/msi.h"
  27 #include "target/riscv/cpu.h"
  28 #include "sysemu/sysemu.h"
  29 #include "hw/riscv/sifive_plic.h"
  30
  31 #define RISCV_DEBUG_PLIC 0
  32
  33 static PLICMode char_to_mode(char c)
  34 {
  35     switch (c) {
  36     case 'U': return PLICMode_U;
  37     case 'S': return PLICMode_S;
  38     case 'H': return PLICMode_H;
  39     case 'M': return PLICMode_M;
  40     default:
  41         error_report("plic: invalid mode '%c'", c);
  42         exit(1);
  43     }
  44 }
  45
  46 static char mode_to_char(PLICMode m)
  47 {
  48     switch (m) {
  49     case PLICMode_U: return 'U';
  50     case PLICMode_S: return 'S';
  51     case PLICMode_H: return 'H';
  52     case PLICMode_M: return 'M';
  53     default: return '?';
  54     }
  55 }
  56
  57 static void sifive_plic_print_state(SiFivePLICState *plic)
  58 {
  59     int i;
  60     int addrid;
  61
  62     /* pending */
  63     qemu_log("pending       : ");
  64     for (i = plic->bitfield_words - 1; i >= 0; i--) {
  65         qemu_log("%08x", plic->pending[i]);
  66     }
  67     qemu_log("\n");
  68
  69     /* pending */
  70     qemu_log("claimed       : ");
  71     for (i = plic->bitfield_words - 1; i >= 0; i--) {
  72         qemu_log("%08x", plic->claimed[i]);
  73     }
  74     qemu_log("\n");
  75
  76     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
  77         qemu_log("hart%d-%c enable: ",
  78             plic->addr_config[addrid].hartid,
  79             mode_to_char(plic->addr_config[addrid].mode));
  80         for (i = plic->bitfield_words - 1; i >= 0; i--) {
  81             qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
  82         }
  83         qemu_log("\n");
  84     }
  85 }
  86
  87 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
  88 {
  89     uint32_t old, new, cmp = atomic_read(a);
  90
  91     do {
  92         old = cmp;
  93         new = (old & ~mask) | (value & mask);
  94         cmp = atomic_cmpxchg(a, old, new);
  95     } while (old != cmp);
  96
  97     return old;
  98 }
  99
 100 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
 101 {
 102     atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
 103 }
 104
 105 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
 106 {
 107     atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
 108 }
 109
 110 static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
 111 {
 112     int i, j;
 113     for (i = 0; i < plic->bitfield_words; i++) {
 114         uint32_t pending_enabled_not_claimed =
 115             (plic->pending[i] & ~plic->claimed[i]) &
 116             plic->enable[addrid * plic->bitfield_words + i];
 117         if (!pending_enabled_not_claimed) {
 118             continue;
 119         }
 120         for (j = 0; j < 32; j++) {
 121             int irq = (i << 5) + j;
 122             uint32_t prio = plic->source_priority[irq];
 123             int enabled = pending_enabled_not_claimed & (1 << j);
 124             if (enabled && prio > plic->target_priority[addrid]) {
 125                 return 1;
 126             }
 127         }
 128     }
 129     return 0;
 130 }
 131
 132 static void sifive_plic_update(SiFivePLICState *plic)
 133 {
 134     int addrid;
 135
 136     /* raise irq on harts where this irq is enabled */
 137     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
 138         uint32_t hartid = plic->addr_config[addrid].hartid;
 139         PLICMode mode = plic->addr_config[addrid].mode;
 140         CPUState *cpu = qemu_get_cpu(hartid);
 141         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
 142         if (!env) {
 143             continue;
 144         }
 145         int level = sifive_plic_irqs_pending(plic, addrid);
 146         switch (mode) {
 147         case PLICMode_M:
 148             riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
 149             break;
 150         case PLICMode_S:
 151             riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
 152             break;
 153         default:
 154             break;
 155         }
 156     }
 157
 158     if (RISCV_DEBUG_PLIC) {
 159         sifive_plic_print_state(plic);
 160     }
 161 }
 162
 163 void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq)
 164 {
 165     sifive_plic_set_pending(plic, irq, true);
 166     sifive_plic_update(plic);
 167 }
 168
 169 void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq)
 170 {
 171     sifive_plic_set_pending(plic, irq, false);
 172     sifive_plic_update(plic);
 173 }
 174
 175 static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
 176 {
 177     int i, j;
 178     for (i = 0; i < plic->bitfield_words; i++) {
 179         uint32_t pending_enabled_not_claimed =
 180             (plic->pending[i] & ~plic->claimed[i]) &
 181             plic->enable[addrid * plic->bitfield_words + i];
 182         if (!pending_enabled_not_claimed) {
 183             continue;
 184         }
 185         for (j = 0; j < 32; j++) {
 186             int irq = (i << 5) + j;
 187             uint32_t prio = plic->source_priority[irq];
 188             int enabled = pending_enabled_not_claimed & (1 << j);
 189             if (enabled && prio > plic->target_priority[addrid]) {
 190                 sifive_plic_set_pending(plic, irq, false);
 191                 sifive_plic_set_claimed(plic, irq, true);
 192                 return irq;
 193             }
 194         }
 195     }
 196     return 0;
 197 }
 198
 199 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
 200 {
 201     SiFivePLICState *plic = opaque;
 202
 203     /* writes must be 4 byte words */
 204     if ((addr & 0x3) != 0) {
 205         goto err;
 206     }
 207
 208     if (addr >= plic->priority_base && /* 4 bytes per source */
 209         addr < plic->priority_base + (plic->num_sources << 2))
 210     {
 211         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 212         if (RISCV_DEBUG_PLIC) {
 213             qemu_log("plic: read priority: irq=%d priority=%d\n",
 214                 irq, plic->source_priority[irq]);
 215         }
 216         return plic->source_priority[irq];
 217     } else if (addr >= plic->pending_base && /* 1 bit per source */
 218                addr < plic->pending_base + (plic->num_sources >> 3))
 219     {
 220         uint32_t word = (addr - plic->pending_base) >> 2;
 221         if (RISCV_DEBUG_PLIC) {
 222             qemu_log("plic: read pending: word=%d value=%d\n",
 223                 word, plic->pending[word]);
 224         }
 225         return plic->pending[word];
 226     } else if (addr >= plic->enable_base && /* 1 bit per source */
 227              addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
 228     {
 229         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
 230         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
 231         if (wordid < plic->bitfield_words) {
 232             if (RISCV_DEBUG_PLIC) {
 233                 qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
 234                     plic->addr_config[addrid].hartid,
 235                     mode_to_char(plic->addr_config[addrid].mode), wordid,
 236                     plic->enable[addrid * plic->bitfield_words + wordid]);
 237             }
 238             return plic->enable[addrid * plic->bitfield_words + wordid];
 239         }
 240     } else if (addr >= plic->context_base && /* 1 bit per source */
 241              addr < plic->context_base + plic->num_addrs * plic->context_stride)
 242     {
 243         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
 244         uint32_t contextid = (addr & (plic->context_stride - 1));
 245         if (contextid == 0) {
 246             if (RISCV_DEBUG_PLIC) {
 247                 qemu_log("plic: read priority: hart%d-%c priority=%x\n",
 248                     plic->addr_config[addrid].hartid,
 249                     mode_to_char(plic->addr_config[addrid].mode),
 250                     plic->target_priority[addrid]);
 251             }
 252             return plic->target_priority[addrid];
 253         } else if (contextid == 4) {
 254             uint32_t value = sifive_plic_claim(plic, addrid);
 255             if (RISCV_DEBUG_PLIC) {
 256                 qemu_log("plic: read claim: hart%d-%c irq=%x\n",
 257                     plic->addr_config[addrid].hartid,
 258                     mode_to_char(plic->addr_config[addrid].mode),
 259                     value);
 260                 sifive_plic_print_state(plic);
 261             }
 262             return value;
 263         }
 264     }
 265
 266 err:
 267     qemu_log_mask(LOG_GUEST_ERROR,
 268                   "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
 269                   __func__, addr);
 270     return 0;
 271 }
 272
 273 static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
 274         unsigned size)
 275 {
 276     SiFivePLICState *plic = opaque;
 277
 278     /* writes must be 4 byte words */
 279     if ((addr & 0x3) != 0) {
 280         goto err;
 281     }
 282
 283     if (addr >= plic->priority_base && /* 4 bytes per source */
 284         addr < plic->priority_base + (plic->num_sources << 2))
 285     {
 286         uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
 287         plic->source_priority[irq] = value & 7;
 288         if (RISCV_DEBUG_PLIC) {
 289             qemu_log("plic: write priority: irq=%d priority=%d\n",
 290                 irq, plic->source_priority[irq]);
 291         }
 292         return;
 293     } else if (addr >= plic->pending_base && /* 1 bit per source */
 294                addr < plic->pending_base + (plic->num_sources >> 3))
 295     {
 296         qemu_log_mask(LOG_GUEST_ERROR,
 297                       "%s: invalid pending write: 0x%" HWADDR_PRIx "",
 298                       __func__, addr);
 299         return;
 300     } else if (addr >= plic->enable_base && /* 1 bit per source */
 301         addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
 302     {
 303         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
 304         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
 305         if (wordid < plic->bitfield_words) {
 306             plic->enable[addrid * plic->bitfield_words + wordid] = value;
 307             if (RISCV_DEBUG_PLIC) {
 308                 qemu_log("plic: write enable: hart%d-%c word=%d value=%x\n",
 309                     plic->addr_config[addrid].hartid,
 310                     mode_to_char(plic->addr_config[addrid].mode), wordid,
 311                     plic->enable[addrid * plic->bitfield_words + wordid]);
 312             }
 313             return;
 314         }
 315     } else if (addr >= plic->context_base && /* 4 bytes per reg */
 316         addr < plic->context_base + plic->num_addrs * plic->context_stride)
 317     {
 318         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
 319         uint32_t contextid = (addr & (plic->context_stride - 1));
 320         if (contextid == 0) {
 321             if (RISCV_DEBUG_PLIC) {
 322                 qemu_log("plic: write priority: hart%d-%c priority=%x\n",
 323                     plic->addr_config[addrid].hartid,
 324                     mode_to_char(plic->addr_config[addrid].mode),
 325                     plic->target_priority[addrid]);
 326             }
 327             if (value <= plic->num_priorities) {
 328                 plic->target_priority[addrid] = value;
 329                 sifive_plic_update(plic);
 330             }
 331             return;
 332         } else if (contextid == 4) {
 333             if (RISCV_DEBUG_PLIC) {
 334                 qemu_log("plic: write claim: hart%d-%c irq=%x\n",
 335                     plic->addr_config[addrid].hartid,
 336                     mode_to_char(plic->addr_config[addrid].mode),
 337                     (uint32_t)value);
 338             }
 339             if (value < plic->num_sources) {
 340                 sifive_plic_set_claimed(plic, value, false);
 341                 sifive_plic_update(plic);
 342             }
 343             return;
 344         }
 345     }
 346
 347 err:
 348     qemu_log_mask(LOG_GUEST_ERROR,
 349                   "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
 350                   __func__, addr);
 351 }
 352
 353 static const MemoryRegionOps sifive_plic_ops = {
 354     .read = sifive_plic_read,
 355     .write = sifive_plic_write,
 356     .endianness = DEVICE_LITTLE_ENDIAN,
 357     .valid = {
 358         .min_access_size = 4,
 359         .max_access_size = 4
 360     }
 361 };
 362
 363 static Property sifive_plic_properties[] = {
 364     DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
 365     DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
 366     DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
 367     DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
 368     DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
 369     DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
 370     DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
 371     DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
 372     DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
 373     DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
 374     DEFINE_PROP_END_OF_LIST(),
 375 };
 376
 377 /*
 378  * parse PLIC hart/mode address offset config
 379  *
 380  * "M"              1 hart with M mode
 381  * "MS,MS"          2 harts, 0-1 with M and S mode
 382  * "M,MS,MS,MS,MS"  5 harts, 0 with M mode, 1-5 with M and S mode
 383  */
 384 static void parse_hart_config(SiFivePLICState *plic)
 385 {
 386     int addrid, hartid, modes;
 387     const char *p;
 388     char c;
 389
 390     /* count and validate hart/mode combinations */
 391     addrid = 0, hartid = 0, modes = 0;
 392     p = plic->hart_config;
 393     while ((c = *p++)) {
 394         if (c == ',') {
 395             addrid += ctpop8(modes);
 396             modes = 0;
 397             hartid++;
 398         } else {
 399             int m = 1 << char_to_mode(c);
 400             if (modes == (modes | m)) {
 401                 error_report("plic: duplicate mode '%c' in config: %s",
 402                              c, plic->hart_config);
 403                 exit(1);
 404             }
 405             modes |= m;
 406         }
 407     }
 408     if (modes) {
 409         addrid += ctpop8(modes);
 410     }
 411     hartid++;
 412
 413     /* store hart/mode combinations */
 414     plic->num_addrs = addrid;
 415     plic->addr_config = g_new(PLICAddr, plic->num_addrs);
 416     addrid = 0, hartid = 0;
 417     p = plic->hart_config;
 418     while ((c = *p++)) {
 419         if (c == ',') {
 420             hartid++;
 421         } else {
 422             plic->addr_config[addrid].addrid = addrid;
 423             plic->addr_config[addrid].hartid = hartid;
 424             plic->addr_config[addrid].mode = char_to_mode(c);
 425             addrid++;
 426         }
 427     }
 428 }
 429
 430 static void sifive_plic_irq_request(void *opaque, int irq, int level)
 431 {
 432     SiFivePLICState *plic = opaque;
 433     if (RISCV_DEBUG_PLIC) {
 434         qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
 435     }
 436     sifive_plic_set_pending(plic, irq, level > 0);
 437     sifive_plic_update(plic);
 438 }
 439
 440 static void sifive_plic_realize(DeviceState *dev, Error **errp)
 441 {
 442     SiFivePLICState *plic = SIFIVE_PLIC(dev);
 443     int i;
 444
 445     memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
 446                           TYPE_SIFIVE_PLIC, plic->aperture_size);
 447     parse_hart_config(plic);
 448     plic->bitfield_words = (plic->num_sources + 31) >> 5;
 449     plic->source_priority = g_new0(uint32_t, plic->num_sources);
 450     plic->target_priority = g_new(uint32_t, plic->num_addrs);
 451     plic->pending = g_new0(uint32_t, plic->bitfield_words);
 452     plic->claimed = g_new0(uint32_t, plic->bitfield_words);
 453     plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs);
 454     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
 455     qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
 456
 457     /* We can't allow the supervisor to control SEIP as this would allow the
 458      * supervisor to clear a pending external interrupt which will result in
 459      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
 460      * hardware controlled when a PLIC is attached.
 461      */
 462     for (i = 0; i < smp_cpus; i++) {
 463         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 464         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 465             error_report("SEIP already claimed");
 466             exit(1);
 467         }
 468     }
 469
 470     msi_nonbroken = true;
 471 }
 472
 473 static void sifive_plic_class_init(ObjectClass *klass, void *data)
 474 {
 475     DeviceClass *dc = DEVICE_CLASS(klass);
 476
 477     dc->props = sifive_plic_properties;
 478     dc->realize = sifive_plic_realize;
 479 }
 480
 481 static const TypeInfo sifive_plic_info = {
 482     .name          = TYPE_SIFIVE_PLIC,
 483     .parent        = TYPE_SYS_BUS_DEVICE,
 484     .instance_size = sizeof(SiFivePLICState),
 485     .class_init    = sifive_plic_class_init,
 486 };
 487
 488 static void sifive_plic_register_types(void)
 489 {
 490     type_register_static(&sifive_plic_info);
 491 }
 492
 493 type_init(sifive_plic_register_types)
 494
 495 /*
 496  * Create PLIC device.
 497  */
 498 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
 499     uint32_t num_sources, uint32_t num_priorities,
 500     uint32_t priority_base, uint32_t pending_base,
 501     uint32_t enable_base, uint32_t enable_stride,
 502     uint32_t context_base, uint32_t context_stride,
 503     uint32_t aperture_size)
 504 {
 505     DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PLIC);
 506     assert(enable_stride == (enable_stride & -enable_stride));
 507     assert(context_stride == (context_stride & -context_stride));
 508     qdev_prop_set_string(dev, "hart-config", hart_config);
 509     qdev_prop_set_uint32(dev, "num-sources", num_sources);
 510     qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
 511     qdev_prop_set_uint32(dev, "priority-base", priority_base);
 512     qdev_prop_set_uint32(dev, "pending-base", pending_base);
 513     qdev_prop_set_uint32(dev, "enable-base", enable_base);
 514     qdev_prop_set_uint32(dev, "enable-stride", enable_stride);
 515     qdev_prop_set_uint32(dev, "context-base", context_base);
 516     qdev_prop_set_uint32(dev, "context-stride", context_stride);
 517     qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
 518     qdev_init_nofail(dev);
 519     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
 520     return dev;
 521 }