hw/misc/exynos4210_rng.c

   1 /*
   2  *  Exynos4210 Pseudo Random Nubmer Generator Emulation
   3  *
   4  *  Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License as published by the
   8  *  Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/sysbus.h"
  22 #include "qapi/error.h"
  23 #include "qemu/log.h"
  24 #include "qemu/guest-random.h"
  25 #include "qemu/module.h"
  26
  27 #define DEBUG_EXYNOS_RNG 0
  28
  29 #define DPRINTF(fmt, ...) \
  30     do { \
  31         if (DEBUG_EXYNOS_RNG) { \
  32             printf("exynos4210_rng: " fmt, ## __VA_ARGS__); \
  33         } \
  34     } while (0)
  35
  36 #define TYPE_EXYNOS4210_RNG             "exynos4210.rng"
  37 #define EXYNOS4210_RNG(obj) \
  38     OBJECT_CHECK(Exynos4210RngState, (obj), TYPE_EXYNOS4210_RNG)
  39
  40 /*
  41  * Exynos4220, PRNG, only polling mode is supported.
  42  */
  43
  44 /* RNG_CONTROL_1 register bitfields, reset value: 0x0 */
  45 #define EXYNOS4210_RNG_CONTROL_1_PRNG           0x8
  46 #define EXYNOS4210_RNG_CONTROL_1_START_INIT     BIT(4)
  47 /* RNG_STATUS register bitfields, reset value: 0x1 */
  48 #define EXYNOS4210_RNG_STATUS_PRNG_ERROR        BIT(7)
  49 #define EXYNOS4210_RNG_STATUS_PRNG_DONE         BIT(5)
  50 #define EXYNOS4210_RNG_STATUS_MSG_DONE          BIT(4)
  51 #define EXYNOS4210_RNG_STATUS_PARTIAL_DONE      BIT(3)
  52 #define EXYNOS4210_RNG_STATUS_PRNG_BUSY         BIT(2)
  53 #define EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE BIT(1)
  54 #define EXYNOS4210_RNG_STATUS_BUFFER_READY      BIT(0)
  55 #define EXYNOS4210_RNG_STATUS_WRITE_MASK   (EXYNOS4210_RNG_STATUS_PRNG_DONE \
  56                                            | EXYNOS4210_RNG_STATUS_MSG_DONE \
  57                                            | EXYNOS4210_RNG_STATUS_PARTIAL_DONE)
  58
  59 #define EXYNOS4210_RNG_CONTROL_1                  0x0
  60 #define EXYNOS4210_RNG_STATUS                    0x10
  61 #define EXYNOS4210_RNG_SEED_IN                  0x140
  62 #define EXYNOS4210_RNG_SEED_IN_OFFSET(n)   (EXYNOS4210_RNG_SEED_IN + (n * 0x4))
  63 #define EXYNOS4210_RNG_PRNG                     0x160
  64 #define EXYNOS4210_RNG_PRNG_OFFSET(n)      (EXYNOS4210_RNG_PRNG + (n * 0x4))
  65
  66 #define EXYNOS4210_RNG_PRNG_NUM                 5
  67
  68 #define EXYNOS4210_RNG_REGS_MEM_SIZE            0x200
  69
  70 typedef struct Exynos4210RngState {
  71     SysBusDevice parent_obj;
  72     MemoryRegion iomem;
  73
  74     int32_t randr_value[EXYNOS4210_RNG_PRNG_NUM];
  75     /* bits from 0 to EXYNOS4210_RNG_PRNG_NUM if given seed register was set */
  76     uint32_t seed_set;
  77
  78     /* Register values */
  79     uint32_t reg_control;
  80     uint32_t reg_status;
  81 } Exynos4210RngState;
  82
  83 static bool exynos4210_rng_seed_ready(const Exynos4210RngState *s)
  84 {
  85     uint32_t mask = MAKE_64BIT_MASK(0, EXYNOS4210_RNG_PRNG_NUM);
  86
  87     /* Return true if all the seed-set bits are set. */
  88     return (s->seed_set & mask) == mask;
  89 }
  90
  91 static void exynos4210_rng_set_seed(Exynos4210RngState *s, unsigned int i,
  92                                     uint64_t val)
  93 {
  94     /*
  95      * We actually ignore the seed and always generate true random numbers.
  96      * Theoretically this should not match the device as Exynos has
  97      * a Pseudo Random Number Generator but testing shown that it always
  98      * generates random numbers regardless of the seed value.
  99      */
 100     s->seed_set |= BIT(i);
 101
 102     /* If all seeds were written, update the status to reflect it */
 103     if (exynos4210_rng_seed_ready(s)) {
 104         s->reg_status |= EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
 105     } else {
 106         s->reg_status &= ~EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
 107     }
 108 }
 109
 110 static void exynos4210_rng_run_engine(Exynos4210RngState *s)
 111 {
 112     Error *err = NULL;
 113
 114     /* Seed set? */
 115     if ((s->reg_status & EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE) == 0) {
 116         goto out;
 117     }
 118
 119     /* PRNG engine chosen? */
 120     if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_PRNG) == 0) {
 121         goto out;
 122     }
 123
 124     /* PRNG engine started? */
 125     if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_START_INIT) == 0) {
 126         goto out;
 127     }
 128
 129     /* Get randoms */
 130     if (qemu_guest_getrandom(s->randr_value, sizeof(s->randr_value), &err)) {
 131         error_report_err(err);
 132     } else {
 133         /* Notify that PRNG is ready */
 134         s->reg_status |= EXYNOS4210_RNG_STATUS_PRNG_DONE;
 135     }
 136
 137 out:
 138     /* Always clear start engine bit */
 139     s->reg_control &= ~EXYNOS4210_RNG_CONTROL_1_START_INIT;
 140 }
 141
 142 static uint64_t exynos4210_rng_read(void *opaque, hwaddr offset,
 143                                     unsigned size)
 144 {
 145     Exynos4210RngState *s = (Exynos4210RngState *)opaque;
 146     uint32_t val = 0;
 147
 148     assert(size == 4);
 149
 150     switch (offset) {
 151     case EXYNOS4210_RNG_CONTROL_1:
 152         val = s->reg_control;
 153         break;
 154
 155     case EXYNOS4210_RNG_STATUS:
 156         val = s->reg_status;
 157         break;
 158
 159     case EXYNOS4210_RNG_PRNG_OFFSET(0):
 160     case EXYNOS4210_RNG_PRNG_OFFSET(1):
 161     case EXYNOS4210_RNG_PRNG_OFFSET(2):
 162     case EXYNOS4210_RNG_PRNG_OFFSET(3):
 163     case EXYNOS4210_RNG_PRNG_OFFSET(4):
 164         val = s->randr_value[(offset - EXYNOS4210_RNG_PRNG_OFFSET(0)) / 4];
 165         DPRINTF("returning random @0x%" HWADDR_PRIx ": 0x%" PRIx32 "\n",
 166                 offset, val);
 167         break;
 168
 169     default:
 170         qemu_log_mask(LOG_GUEST_ERROR,
 171                       "%s: bad read offset 0x%" HWADDR_PRIx "\n",
 172                       __func__, offset);
 173     }
 174
 175     return val;
 176 }
 177
 178 static void exynos4210_rng_write(void *opaque, hwaddr offset,
 179                                  uint64_t val, unsigned size)
 180 {
 181     Exynos4210RngState *s = (Exynos4210RngState *)opaque;
 182
 183     assert(size == 4);
 184
 185     switch (offset) {
 186     case EXYNOS4210_RNG_CONTROL_1:
 187         DPRINTF("RNG_CONTROL_1 = 0x%" PRIx64 "\n", val);
 188         s->reg_control = val;
 189         exynos4210_rng_run_engine(s);
 190         break;
 191
 192     case EXYNOS4210_RNG_STATUS:
 193         /* For clearing status fields */
 194         s->reg_status &= ~EXYNOS4210_RNG_STATUS_WRITE_MASK;
 195         s->reg_status |= val & EXYNOS4210_RNG_STATUS_WRITE_MASK;
 196         break;
 197
 198     case EXYNOS4210_RNG_SEED_IN_OFFSET(0):
 199     case EXYNOS4210_RNG_SEED_IN_OFFSET(1):
 200     case EXYNOS4210_RNG_SEED_IN_OFFSET(2):
 201     case EXYNOS4210_RNG_SEED_IN_OFFSET(3):
 202     case EXYNOS4210_RNG_SEED_IN_OFFSET(4):
 203         exynos4210_rng_set_seed(s,
 204                                 (offset - EXYNOS4210_RNG_SEED_IN_OFFSET(0)) / 4,
 205                                 val);
 206         break;
 207
 208     default:
 209         qemu_log_mask(LOG_GUEST_ERROR,
 210                       "%s: bad write offset 0x%" HWADDR_PRIx "\n",
 211                       __func__, offset);
 212     }
 213 }
 214
 215 static const MemoryRegionOps exynos4210_rng_ops = {
 216     .read = exynos4210_rng_read,
 217     .write = exynos4210_rng_write,
 218     .endianness = DEVICE_NATIVE_ENDIAN,
 219 };
 220
 221 static void exynos4210_rng_reset(DeviceState *dev)
 222 {
 223     Exynos4210RngState *s = EXYNOS4210_RNG(dev);
 224
 225     s->reg_control = 0;
 226     s->reg_status = EXYNOS4210_RNG_STATUS_BUFFER_READY;
 227     memset(s->randr_value, 0, sizeof(s->randr_value));
 228     s->seed_set = 0;
 229 }
 230
 231 static void exynos4210_rng_init(Object *obj)
 232 {
 233     Exynos4210RngState *s = EXYNOS4210_RNG(obj);
 234     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 235
 236     memory_region_init_io(&s->iomem, obj, &exynos4210_rng_ops, s,
 237                           TYPE_EXYNOS4210_RNG, EXYNOS4210_RNG_REGS_MEM_SIZE);
 238     sysbus_init_mmio(dev, &s->iomem);
 239 }
 240
 241 static const VMStateDescription exynos4210_rng_vmstate = {
 242     .name = TYPE_EXYNOS4210_RNG,
 243     .version_id = 1,
 244     .minimum_version_id = 1,
 245     .fields = (VMStateField[]) {
 246         VMSTATE_INT32_ARRAY(randr_value, Exynos4210RngState,
 247                             EXYNOS4210_RNG_PRNG_NUM),
 248         VMSTATE_UINT32(seed_set, Exynos4210RngState),
 249         VMSTATE_UINT32(reg_status, Exynos4210RngState),
 250         VMSTATE_UINT32(reg_control, Exynos4210RngState),
 251         VMSTATE_END_OF_LIST()
 252     }
 253 };
 254
 255 static void exynos4210_rng_class_init(ObjectClass *klass, void *data)
 256 {
 257     DeviceClass *dc = DEVICE_CLASS(klass);
 258
 259     dc->reset = exynos4210_rng_reset;
 260     dc->vmsd = &exynos4210_rng_vmstate;
 261 }
 262
 263 static const TypeInfo exynos4210_rng_info = {
 264     .name          = TYPE_EXYNOS4210_RNG,
 265     .parent        = TYPE_SYS_BUS_DEVICE,
 266     .instance_size = sizeof(Exynos4210RngState),
 267     .instance_init = exynos4210_rng_init,
 268     .class_init    = exynos4210_rng_class_init,
 269 };
 270
 271 static void exynos4210_rng_register(void)
 272 {
 273     type_register_static(&exynos4210_rng_info);
 274 }
 275
 276 type_init(exynos4210_rng_register)