hw/misc/exynos4210_clk.c

   1 /*
   2  *  Exynos4210 Clock Controller Emulation
   3  *
   4  *  Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License as published by the
   8  *  Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/sysbus.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24
  25 #define TYPE_EXYNOS4210_CLK             "exynos4210.clk"
  26 #define EXYNOS4210_CLK(obj) \
  27     OBJECT_CHECK(Exynos4210ClkState, (obj), TYPE_EXYNOS4210_CLK)
  28
  29 #define CLK_PLL_LOCKED                  BIT(29)
  30
  31 #define EXYNOS4210_CLK_REGS_MEM_SIZE    0x15104
  32
  33 typedef struct Exynos4210Reg {
  34     const char   *name; /* for debug only */
  35     uint32_t     offset;
  36     uint32_t     reset_value;
  37 } Exynos4210Reg;
  38
  39 /* Clock controller register base: 0x10030000 */
  40 static const Exynos4210Reg exynos4210_clk_regs[] = {
  41     {"EPLL_LOCK",                     0xc010, 0x00000fff},
  42     {"VPLL_LOCK",                     0xc020, 0x00000fff},
  43     {"EPLL_CON0",                     0xc110, 0x00300301 | CLK_PLL_LOCKED},
  44     {"EPLL_CON1",                     0xc114, 0x00000000},
  45     {"VPLL_CON0",                     0xc120, 0x00240201 | CLK_PLL_LOCKED},
  46     {"VPLL_CON1",                     0xc124, 0x66010464},
  47     {"APLL_LOCK",                    0x14000, 0x00000fff},
  48     {"MPLL_LOCK",                    0x14004, 0x00000fff},
  49     {"APLL_CON0",                    0x14100, 0x00c80601 | CLK_PLL_LOCKED},
  50     {"APLL_CON1",                    0x14104, 0x0000001c},
  51     {"MPLL_CON0",                    0x14108, 0x00c80601 | CLK_PLL_LOCKED},
  52     {"MPLL_CON1",                    0x1410c, 0x0000001c},
  53 };
  54
  55 #define EXYNOS4210_REGS_NUM       ARRAY_SIZE(exynos4210_clk_regs)
  56
  57 typedef struct Exynos4210ClkState {
  58     SysBusDevice parent_obj;
  59
  60     MemoryRegion iomem;
  61     uint32_t reg[EXYNOS4210_REGS_NUM];
  62 } Exynos4210ClkState;
  63
  64 static uint64_t exynos4210_clk_read(void *opaque, hwaddr offset,
  65                                     unsigned size)
  66 {
  67     const Exynos4210ClkState *s = (Exynos4210ClkState *)opaque;
  68     const Exynos4210Reg *regs = exynos4210_clk_regs;
  69     unsigned int i;
  70
  71     for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
  72         if (regs->offset == offset) {
  73             return s->reg[i];
  74         }
  75         regs++;
  76     }
  77     qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read offset 0x%04x\n",
  78                   __func__, (uint32_t)offset);
  79     return 0;
  80 }
  81
  82 static void exynos4210_clk_write(void *opaque, hwaddr offset,
  83                                  uint64_t val, unsigned size)
  84 {
  85     Exynos4210ClkState *s = (Exynos4210ClkState *)opaque;
  86     const Exynos4210Reg *regs = exynos4210_clk_regs;
  87     unsigned int i;
  88
  89     for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
  90         if (regs->offset == offset) {
  91             s->reg[i] = val;
  92             return;
  93         }
  94         regs++;
  95     }
  96     qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write offset 0x%04x\n",
  97                   __func__, (uint32_t)offset);
  98 }
  99
 100 static const MemoryRegionOps exynos4210_clk_ops = {
 101     .read = exynos4210_clk_read,
 102     .write = exynos4210_clk_write,
 103     .endianness = DEVICE_NATIVE_ENDIAN,
 104     .valid = {
 105         .min_access_size = 4,
 106         .max_access_size = 4,
 107         .unaligned = false
 108     }
 109 };
 110
 111 static void exynos4210_clk_reset(DeviceState *dev)
 112 {
 113     Exynos4210ClkState *s = EXYNOS4210_CLK(dev);
 114     unsigned int i;
 115
 116     /* Set default values for registers */
 117     for (i = 0; i < EXYNOS4210_REGS_NUM; i++) {
 118         s->reg[i] = exynos4210_clk_regs[i].reset_value;
 119     }
 120 }
 121
 122 static void exynos4210_clk_init(Object *obj)
 123 {
 124     Exynos4210ClkState *s = EXYNOS4210_CLK(obj);
 125     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 126
 127     /* memory mapping */
 128     memory_region_init_io(&s->iomem, obj, &exynos4210_clk_ops, s,
 129                           TYPE_EXYNOS4210_CLK, EXYNOS4210_CLK_REGS_MEM_SIZE);
 130     sysbus_init_mmio(dev, &s->iomem);
 131 }
 132
 133 static const VMStateDescription exynos4210_clk_vmstate = {
 134     .name = TYPE_EXYNOS4210_CLK,
 135     .version_id = 1,
 136     .minimum_version_id = 1,
 137     .fields = (VMStateField[]) {
 138         VMSTATE_UINT32_ARRAY(reg, Exynos4210ClkState, EXYNOS4210_REGS_NUM),
 139         VMSTATE_END_OF_LIST()
 140     }
 141 };
 142
 143 static void exynos4210_clk_class_init(ObjectClass *klass, void *data)
 144 {
 145     DeviceClass *dc = DEVICE_CLASS(klass);
 146
 147     dc->reset = exynos4210_clk_reset;
 148     dc->vmsd = &exynos4210_clk_vmstate;
 149 }
 150
 151 static const TypeInfo exynos4210_clk_info = {
 152     .name          = TYPE_EXYNOS4210_CLK,
 153     .parent        = TYPE_SYS_BUS_DEVICE,
 154     .instance_size = sizeof(Exynos4210ClkState),
 155     .instance_init = exynos4210_clk_init,
 156     .class_init    = exynos4210_clk_class_init,
 157 };
 158
 159 static void exynos4210_clk_register(void)
 160 {
 161     qemu_log_mask(LOG_GUEST_ERROR, "Clock init\n");
 162     type_register_static(&exynos4210_clk_info);
 163 }
 164
 165 type_init(exynos4210_clk_register)