target-s390x/ioinst.c

   1 /*
   2  * I/O instructions for S/390
   3  *
   4  * Copyright 2012, 2015 IBM Corp.
   5  * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or (at
   8  * your option) any later version. See the COPYING file in the top-level
   9  * directory.
  10  */
  11
  12 #include <sys/types.h>
  13
  14 #include "cpu.h"
  15 #include "ioinst.h"
  16 #include "trace.h"
  17 #include "hw/s390x/s390-pci-bus.h"
  18
  19 int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
  20                                  int *schid)
  21 {
  22     if (!IOINST_SCHID_ONE(value)) {
  23         return -EINVAL;
  24     }
  25     if (!IOINST_SCHID_M(value)) {
  26         if (IOINST_SCHID_CSSID(value)) {
  27             return -EINVAL;
  28         }
  29         *cssid = 0;
  30         *m = 0;
  31     } else {
  32         *cssid = IOINST_SCHID_CSSID(value);
  33         *m = 1;
  34     }
  35     *ssid = IOINST_SCHID_SSID(value);
  36     *schid = IOINST_SCHID_NR(value);
  37     return 0;
  38 }
  39
  40 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1)
  41 {
  42     int cssid, ssid, schid, m;
  43     SubchDev *sch;
  44     int ret = -ENODEV;
  45     int cc;
  46
  47     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  48         program_interrupt(&cpu->env, PGM_OPERAND, 2);
  49         return;
  50     }
  51     trace_ioinst_sch_id("xsch", cssid, ssid, schid);
  52     sch = css_find_subch(m, cssid, ssid, schid);
  53     if (sch && css_subch_visible(sch)) {
  54         ret = css_do_xsch(sch);
  55     }
  56     switch (ret) {
  57     case -ENODEV:
  58         cc = 3;
  59         break;
  60     case -EBUSY:
  61         cc = 2;
  62         break;
  63     case 0:
  64         cc = 0;
  65         break;
  66     default:
  67         cc = 1;
  68         break;
  69     }
  70     setcc(cpu, cc);
  71 }
  72
  73 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1)
  74 {
  75     int cssid, ssid, schid, m;
  76     SubchDev *sch;
  77     int ret = -ENODEV;
  78     int cc;
  79
  80     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
  81         program_interrupt(&cpu->env, PGM_OPERAND, 2);
  82         return;
  83     }
  84     trace_ioinst_sch_id("csch", cssid, ssid, schid);
  85     sch = css_find_subch(m, cssid, ssid, schid);
  86     if (sch && css_subch_visible(sch)) {
  87         ret = css_do_csch(sch);
  88     }
  89     if (ret == -ENODEV) {
  90         cc = 3;
  91     } else {
  92         cc = 0;
  93     }
  94     setcc(cpu, cc);
  95 }
  96
  97 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1)
  98 {
  99     int cssid, ssid, schid, m;
 100     SubchDev *sch;
 101     int ret = -ENODEV;
 102     int cc;
 103
 104     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 105         program_interrupt(&cpu->env, PGM_OPERAND, 2);
 106         return;
 107     }
 108     trace_ioinst_sch_id("hsch", cssid, ssid, schid);
 109     sch = css_find_subch(m, cssid, ssid, schid);
 110     if (sch && css_subch_visible(sch)) {
 111         ret = css_do_hsch(sch);
 112     }
 113     switch (ret) {
 114     case -ENODEV:
 115         cc = 3;
 116         break;
 117     case -EBUSY:
 118         cc = 2;
 119         break;
 120     case 0:
 121         cc = 0;
 122         break;
 123     default:
 124         cc = 1;
 125         break;
 126     }
 127     setcc(cpu, cc);
 128 }
 129
 130 static int ioinst_schib_valid(SCHIB *schib)
 131 {
 132     if ((schib->pmcw.flags & PMCW_FLAGS_MASK_INVALID) ||
 133         (schib->pmcw.chars & PMCW_CHARS_MASK_INVALID)) {
 134         return 0;
 135     }
 136     /* Disallow extended measurements for now. */
 137     if (schib->pmcw.chars & PMCW_CHARS_MASK_XMWME) {
 138         return 0;
 139     }
 140     return 1;
 141 }
 142
 143 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 144 {
 145     int cssid, ssid, schid, m;
 146     SubchDev *sch;
 147     SCHIB schib;
 148     uint64_t addr;
 149     int ret = -ENODEV;
 150     int cc;
 151     CPUS390XState *env = &cpu->env;
 152
 153     addr = decode_basedisp_s(env, ipb);
 154     if (addr & 3) {
 155         program_interrupt(env, PGM_SPECIFICATION, 2);
 156         return;
 157     }
 158     if (s390_cpu_virt_mem_read(cpu, addr, &schib, sizeof(schib))) {
 159         return;
 160     }
 161     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid) ||
 162         !ioinst_schib_valid(&schib)) {
 163         program_interrupt(env, PGM_OPERAND, 2);
 164         return;
 165     }
 166     trace_ioinst_sch_id("msch", cssid, ssid, schid);
 167     sch = css_find_subch(m, cssid, ssid, schid);
 168     if (sch && css_subch_visible(sch)) {
 169         ret = css_do_msch(sch, &schib);
 170     }
 171     switch (ret) {
 172     case -ENODEV:
 173         cc = 3;
 174         break;
 175     case -EBUSY:
 176         cc = 2;
 177         break;
 178     case 0:
 179         cc = 0;
 180         break;
 181     default:
 182         cc = 1;
 183         break;
 184     }
 185     setcc(cpu, cc);
 186 }
 187
 188 static void copy_orb_from_guest(ORB *dest, const ORB *src)
 189 {
 190     dest->intparm = be32_to_cpu(src->intparm);
 191     dest->ctrl0 = be16_to_cpu(src->ctrl0);
 192     dest->lpm = src->lpm;
 193     dest->ctrl1 = src->ctrl1;
 194     dest->cpa = be32_to_cpu(src->cpa);
 195 }
 196
 197 static int ioinst_orb_valid(ORB *orb)
 198 {
 199     if ((orb->ctrl0 & ORB_CTRL0_MASK_INVALID) ||
 200         (orb->ctrl1 & ORB_CTRL1_MASK_INVALID)) {
 201         return 0;
 202     }
 203     if ((orb->cpa & HIGH_ORDER_BIT) != 0) {
 204         return 0;
 205     }
 206     return 1;
 207 }
 208
 209 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 210 {
 211     int cssid, ssid, schid, m;
 212     SubchDev *sch;
 213     ORB orig_orb, orb;
 214     uint64_t addr;
 215     int ret = -ENODEV;
 216     int cc;
 217     CPUS390XState *env = &cpu->env;
 218
 219     addr = decode_basedisp_s(env, ipb);
 220     if (addr & 3) {
 221         program_interrupt(env, PGM_SPECIFICATION, 2);
 222         return;
 223     }
 224     if (s390_cpu_virt_mem_read(cpu, addr, &orig_orb, sizeof(orb))) {
 225         return;
 226     }
 227     copy_orb_from_guest(&orb, &orig_orb);
 228     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid) ||
 229         !ioinst_orb_valid(&orb)) {
 230         program_interrupt(env, PGM_OPERAND, 2);
 231         return;
 232     }
 233     trace_ioinst_sch_id("ssch", cssid, ssid, schid);
 234     sch = css_find_subch(m, cssid, ssid, schid);
 235     if (sch && css_subch_visible(sch)) {
 236         ret = css_do_ssch(sch, &orb);
 237     }
 238     switch (ret) {
 239     case -ENODEV:
 240         cc = 3;
 241         break;
 242     case -EBUSY:
 243         cc = 2;
 244         break;
 245     case 0:
 246         cc = 0;
 247         break;
 248     default:
 249         cc = 1;
 250         break;
 251     }
 252     setcc(cpu, cc);
 253 }
 254
 255 void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb)
 256 {
 257     CRW *crw;
 258     uint64_t addr;
 259     int cc;
 260     hwaddr len = sizeof(*crw);
 261     CPUS390XState *env = &cpu->env;
 262
 263     addr = decode_basedisp_s(env, ipb);
 264     if (addr & 3) {
 265         program_interrupt(env, PGM_SPECIFICATION, 2);
 266         return;
 267     }
 268     crw = s390_cpu_physical_memory_map(env, addr, &len, 1);
 269     if (!crw || len != sizeof(*crw)) {
 270         program_interrupt(env, PGM_ADDRESSING, 2);
 271         goto out;
 272     }
 273     cc = css_do_stcrw(crw);
 274     /* 0 - crw stored, 1 - zeroes stored */
 275     setcc(cpu, cc);
 276
 277 out:
 278     s390_cpu_physical_memory_unmap(env, crw, len, 1);
 279 }
 280
 281 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)
 282 {
 283     int cssid, ssid, schid, m;
 284     SubchDev *sch;
 285     uint64_t addr;
 286     int cc;
 287     SCHIB *schib;
 288     hwaddr len = sizeof(*schib);
 289     CPUS390XState *env = &cpu->env;
 290
 291     addr = decode_basedisp_s(env, ipb);
 292     if (addr & 3) {
 293         program_interrupt(env, PGM_SPECIFICATION, 2);
 294         return;
 295     }
 296     schib = s390_cpu_physical_memory_map(env, addr, &len, 1);
 297     if (!schib || len != sizeof(*schib)) {
 298         program_interrupt(env, PGM_ADDRESSING, 2);
 299         goto out;
 300     }
 301
 302     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 303         program_interrupt(env, PGM_OPERAND, 2);
 304         goto out;
 305     }
 306     trace_ioinst_sch_id("stsch", cssid, ssid, schid);
 307     sch = css_find_subch(m, cssid, ssid, schid);
 308     if (sch) {
 309         if (css_subch_visible(sch)) {
 310             css_do_stsch(sch, schib);
 311             cc = 0;
 312         } else {
 313             /* Indicate no more subchannels in this css/ss */
 314             cc = 3;
 315         }
 316     } else {
 317         if (css_schid_final(m, cssid, ssid, schid)) {
 318             cc = 3; /* No more subchannels in this css/ss */
 319         } else {
 320             /* Store an empty schib. */
 321             memset(schib, 0, sizeof(*schib));
 322             cc = 0;
 323         }
 324     }
 325     setcc(cpu, cc);
 326
 327 out:
 328     s390_cpu_physical_memory_unmap(env, schib, len, 1);
 329 }
 330
 331 int ioinst_handle_tsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb)
 332 {
 333     int cssid, ssid, schid, m;
 334     SubchDev *sch;
 335     IRB *irb;
 336     uint64_t addr;
 337     int ret = -ENODEV;
 338     int cc;
 339     hwaddr len = sizeof(*irb);
 340
 341     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 342         program_interrupt(env, PGM_OPERAND, 2);
 343         return -EIO;
 344     }
 345     trace_ioinst_sch_id("tsch", cssid, ssid, schid);
 346     addr = decode_basedisp_s(env, ipb);
 347     if (addr & 3) {
 348         program_interrupt(env, PGM_SPECIFICATION, 2);
 349         return -EIO;
 350     }
 351     irb = s390_cpu_physical_memory_map(env, addr, &len, 1);
 352     if (!irb || len != sizeof(*irb)) {
 353         program_interrupt(env, PGM_ADDRESSING, 2);
 354         cc = -EIO;
 355         goto out;
 356     }
 357     sch = css_find_subch(m, cssid, ssid, schid);
 358     if (sch && css_subch_visible(sch)) {
 359         ret = css_do_tsch(sch, irb);
 360         /* 0 - status pending, 1 - not status pending */
 361         cc = ret;
 362     } else {
 363         cc = 3;
 364     }
 365 out:
 366     s390_cpu_physical_memory_unmap(env, irb, sizeof(*irb), 1);
 367     return cc;
 368 }
 369
 370 typedef struct ChscReq {
 371     uint16_t len;
 372     uint16_t command;
 373     uint32_t param0;
 374     uint32_t param1;
 375     uint32_t param2;
 376 } QEMU_PACKED ChscReq;
 377
 378 typedef struct ChscResp {
 379     uint16_t len;
 380     uint16_t code;
 381     uint32_t param;
 382     char data[0];
 383 } QEMU_PACKED ChscResp;
 384
 385 #define CHSC_MIN_RESP_LEN 0x0008
 386
 387 #define CHSC_SCPD 0x0002
 388 #define CHSC_SCSC 0x0010
 389 #define CHSC_SDA  0x0031
 390 #define CHSC_SEI  0x000e
 391
 392 #define CHSC_SCPD_0_M 0x20000000
 393 #define CHSC_SCPD_0_C 0x10000000
 394 #define CHSC_SCPD_0_FMT 0x0f000000
 395 #define CHSC_SCPD_0_CSSID 0x00ff0000
 396 #define CHSC_SCPD_0_RFMT 0x00000f00
 397 #define CHSC_SCPD_0_RES 0xc000f000
 398 #define CHSC_SCPD_1_RES 0xffffff00
 399 #define CHSC_SCPD_01_CHPID 0x000000ff
 400 static void ioinst_handle_chsc_scpd(ChscReq *req, ChscResp *res)
 401 {
 402     uint16_t len = be16_to_cpu(req->len);
 403     uint32_t param0 = be32_to_cpu(req->param0);
 404     uint32_t param1 = be32_to_cpu(req->param1);
 405     uint16_t resp_code;
 406     int rfmt;
 407     uint16_t cssid;
 408     uint8_t f_chpid, l_chpid;
 409     int desc_size;
 410     int m;
 411
 412     rfmt = (param0 & CHSC_SCPD_0_RFMT) >> 8;
 413     if ((rfmt == 0) ||  (rfmt == 1)) {
 414         rfmt = !!(param0 & CHSC_SCPD_0_C);
 415     }
 416     if ((len != 0x0010) || (param0 & CHSC_SCPD_0_RES) ||
 417         (param1 & CHSC_SCPD_1_RES) || req->param2) {
 418         resp_code = 0x0003;
 419         goto out_err;
 420     }
 421     if (param0 & CHSC_SCPD_0_FMT) {
 422         resp_code = 0x0007;
 423         goto out_err;
 424     }
 425     cssid = (param0 & CHSC_SCPD_0_CSSID) >> 16;
 426     m = param0 & CHSC_SCPD_0_M;
 427     if (cssid != 0) {
 428         if (!m || !css_present(cssid)) {
 429             resp_code = 0x0008;
 430             goto out_err;
 431         }
 432     }
 433     f_chpid = param0 & CHSC_SCPD_01_CHPID;
 434     l_chpid = param1 & CHSC_SCPD_01_CHPID;
 435     if (l_chpid < f_chpid) {
 436         resp_code = 0x0003;
 437         goto out_err;
 438     }
 439     /* css_collect_chp_desc() is endian-aware */
 440     desc_size = css_collect_chp_desc(m, cssid, f_chpid, l_chpid, rfmt,
 441                                      &res->data);
 442     res->code = cpu_to_be16(0x0001);
 443     res->len = cpu_to_be16(8 + desc_size);
 444     res->param = cpu_to_be32(rfmt);
 445     return;
 446
 447   out_err:
 448     res->code = cpu_to_be16(resp_code);
 449     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 450     res->param = cpu_to_be32(rfmt);
 451 }
 452
 453 #define CHSC_SCSC_0_M 0x20000000
 454 #define CHSC_SCSC_0_FMT 0x000f0000
 455 #define CHSC_SCSC_0_CSSID 0x0000ff00
 456 #define CHSC_SCSC_0_RES 0xdff000ff
 457 static void ioinst_handle_chsc_scsc(ChscReq *req, ChscResp *res)
 458 {
 459     uint16_t len = be16_to_cpu(req->len);
 460     uint32_t param0 = be32_to_cpu(req->param0);
 461     uint8_t cssid;
 462     uint16_t resp_code;
 463     uint32_t general_chars[510];
 464     uint32_t chsc_chars[508];
 465
 466     if (len != 0x0010) {
 467         resp_code = 0x0003;
 468         goto out_err;
 469     }
 470
 471     if (param0 & CHSC_SCSC_0_FMT) {
 472         resp_code = 0x0007;
 473         goto out_err;
 474     }
 475     cssid = (param0 & CHSC_SCSC_0_CSSID) >> 8;
 476     if (cssid != 0) {
 477         if (!(param0 & CHSC_SCSC_0_M) || !css_present(cssid)) {
 478             resp_code = 0x0008;
 479             goto out_err;
 480         }
 481     }
 482     if ((param0 & CHSC_SCSC_0_RES) || req->param1 || req->param2) {
 483         resp_code = 0x0003;
 484         goto out_err;
 485     }
 486     res->code = cpu_to_be16(0x0001);
 487     res->len = cpu_to_be16(4080);
 488     res->param = 0;
 489
 490     memset(general_chars, 0, sizeof(general_chars));
 491     memset(chsc_chars, 0, sizeof(chsc_chars));
 492
 493     general_chars[0] = cpu_to_be32(0x03000000);
 494     general_chars[1] = cpu_to_be32(0x00059000);
 495
 496     chsc_chars[0] = cpu_to_be32(0x40000000);
 497     chsc_chars[3] = cpu_to_be32(0x00040000);
 498
 499     memcpy(res->data, general_chars, sizeof(general_chars));
 500     memcpy(res->data + sizeof(general_chars), chsc_chars, sizeof(chsc_chars));
 501     return;
 502
 503   out_err:
 504     res->code = cpu_to_be16(resp_code);
 505     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 506     res->param = 0;
 507 }
 508
 509 #define CHSC_SDA_0_FMT 0x0f000000
 510 #define CHSC_SDA_0_OC 0x0000ffff
 511 #define CHSC_SDA_0_RES 0xf0ff0000
 512 #define CHSC_SDA_OC_MCSSE 0x0
 513 #define CHSC_SDA_OC_MSS 0x2
 514 static void ioinst_handle_chsc_sda(ChscReq *req, ChscResp *res)
 515 {
 516     uint16_t resp_code = 0x0001;
 517     uint16_t len = be16_to_cpu(req->len);
 518     uint32_t param0 = be32_to_cpu(req->param0);
 519     uint16_t oc;
 520     int ret;
 521
 522     if ((len != 0x0400) || (param0 & CHSC_SDA_0_RES)) {
 523         resp_code = 0x0003;
 524         goto out;
 525     }
 526
 527     if (param0 & CHSC_SDA_0_FMT) {
 528         resp_code = 0x0007;
 529         goto out;
 530     }
 531
 532     oc = param0 & CHSC_SDA_0_OC;
 533     switch (oc) {
 534     case CHSC_SDA_OC_MCSSE:
 535         ret = css_enable_mcsse();
 536         if (ret == -EINVAL) {
 537             resp_code = 0x0101;
 538             goto out;
 539         }
 540         break;
 541     case CHSC_SDA_OC_MSS:
 542         ret = css_enable_mss();
 543         if (ret == -EINVAL) {
 544             resp_code = 0x0101;
 545             goto out;
 546         }
 547         break;
 548     default:
 549         resp_code = 0x0003;
 550         goto out;
 551     }
 552
 553 out:
 554     res->code = cpu_to_be16(resp_code);
 555     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 556     res->param = 0;
 557 }
 558
 559 static int chsc_sei_nt0_get_event(void *res)
 560 {
 561     /* no events yet */
 562     return 1;
 563 }
 564
 565 static int chsc_sei_nt0_have_event(void)
 566 {
 567     /* no events yet */
 568     return 0;
 569 }
 570
 571 #define CHSC_SEI_NT0    (1ULL << 63)
 572 #define CHSC_SEI_NT2    (1ULL << 61)
 573 static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res)
 574 {
 575     uint64_t selection_mask = ldq_p(&req->param1);
 576     uint8_t *res_flags = (uint8_t *)res->data;
 577     int have_event = 0;
 578     int have_more = 0;
 579
 580     /* regarding architecture nt0 can not be masked */
 581     have_event = !chsc_sei_nt0_get_event(res);
 582     have_more = chsc_sei_nt0_have_event();
 583
 584     if (selection_mask & CHSC_SEI_NT2) {
 585         if (!have_event) {
 586             have_event = !chsc_sei_nt2_get_event(res);
 587         }
 588
 589         if (!have_more) {
 590             have_more = chsc_sei_nt2_have_event();
 591         }
 592     }
 593
 594     if (have_event) {
 595         res->code = cpu_to_be16(0x0001);
 596         if (have_more) {
 597             (*res_flags) |= 0x80;
 598         } else {
 599             (*res_flags) &= ~0x80;
 600         }
 601     } else {
 602         res->code = cpu_to_be16(0x0004);
 603     }
 604 }
 605
 606 static void ioinst_handle_chsc_unimplemented(ChscResp *res)
 607 {
 608     res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
 609     res->code = cpu_to_be16(0x0004);
 610     res->param = 0;
 611 }
 612
 613 void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb)
 614 {
 615     ChscReq *req;
 616     ChscResp *res;
 617     uint64_t addr;
 618     int reg;
 619     uint16_t len;
 620     uint16_t command;
 621     hwaddr map_size = TARGET_PAGE_SIZE;
 622     CPUS390XState *env = &cpu->env;
 623
 624     trace_ioinst("chsc");
 625     reg = (ipb >> 20) & 0x00f;
 626     addr = env->regs[reg];
 627     /* Page boundary? */
 628     if (addr & 0xfff) {
 629         program_interrupt(env, PGM_SPECIFICATION, 2);
 630         return;
 631     }
 632     req = s390_cpu_physical_memory_map(env, addr, &map_size, 1);
 633     if (!req || map_size != TARGET_PAGE_SIZE) {
 634         program_interrupt(env, PGM_ADDRESSING, 2);
 635         goto out;
 636     }
 637     len = be16_to_cpu(req->len);
 638     /* Length field valid? */
 639     if ((len < 16) || (len > 4088) || (len & 7)) {
 640         program_interrupt(env, PGM_OPERAND, 2);
 641         goto out;
 642     }
 643     memset((char *)req + len, 0, TARGET_PAGE_SIZE - len);
 644     res = (void *)((char *)req + len);
 645     command = be16_to_cpu(req->command);
 646     trace_ioinst_chsc_cmd(command, len);
 647     switch (command) {
 648     case CHSC_SCSC:
 649         ioinst_handle_chsc_scsc(req, res);
 650         break;
 651     case CHSC_SCPD:
 652         ioinst_handle_chsc_scpd(req, res);
 653         break;
 654     case CHSC_SDA:
 655         ioinst_handle_chsc_sda(req, res);
 656         break;
 657     case CHSC_SEI:
 658         ioinst_handle_chsc_sei(req, res);
 659         break;
 660     default:
 661         ioinst_handle_chsc_unimplemented(res);
 662         break;
 663     }
 664
 665     setcc(cpu, 0);    /* Command execution complete */
 666 out:
 667     s390_cpu_physical_memory_unmap(env, req, map_size, 1);
 668 }
 669
 670 int ioinst_handle_tpi(CPUS390XState *env, uint32_t ipb)
 671 {
 672     uint64_t addr;
 673     int lowcore;
 674     IOIntCode *int_code;
 675     hwaddr len, orig_len;
 676     int ret;
 677
 678     trace_ioinst("tpi");
 679     addr = decode_basedisp_s(env, ipb);
 680     if (addr & 3) {
 681         program_interrupt(env, PGM_SPECIFICATION, 2);
 682         return -EIO;
 683     }
 684
 685     lowcore = addr ? 0 : 1;
 686     len = lowcore ? 8 /* two words */ : 12 /* three words */;
 687     orig_len = len;
 688     int_code = s390_cpu_physical_memory_map(env, addr, &len, 1);
 689     if (!int_code || (len != orig_len)) {
 690         program_interrupt(env, PGM_ADDRESSING, 2);
 691         ret = -EIO;
 692         goto out;
 693     }
 694     ret = css_do_tpi(int_code, lowcore);
 695 out:
 696     s390_cpu_physical_memory_unmap(env, int_code, len, 1);
 697     return ret;
 698 }
 699
 700 #define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc)
 701 #define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28)
 702 #define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1)
 703 #define SCHM_REG1_DCT(_reg) (_reg & 0x0000000000000001)
 704
 705 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
 706                         uint32_t ipb)
 707 {
 708     uint8_t mbk;
 709     int update;
 710     int dct;
 711     CPUS390XState *env = &cpu->env;
 712
 713     trace_ioinst("schm");
 714
 715     if (SCHM_REG1_RES(reg1)) {
 716         program_interrupt(env, PGM_OPERAND, 2);
 717         return;
 718     }
 719
 720     mbk = SCHM_REG1_MBK(reg1);
 721     update = SCHM_REG1_UPD(reg1);
 722     dct = SCHM_REG1_DCT(reg1);
 723
 724     if (update && (reg2 & 0x000000000000001f)) {
 725         program_interrupt(env, PGM_OPERAND, 2);
 726         return;
 727     }
 728
 729     css_do_schm(mbk, update, dct, update ? reg2 : 0);
 730 }
 731
 732 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1)
 733 {
 734     int cssid, ssid, schid, m;
 735     SubchDev *sch;
 736     int ret = -ENODEV;
 737     int cc;
 738
 739     if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {
 740         program_interrupt(&cpu->env, PGM_OPERAND, 2);
 741         return;
 742     }
 743     trace_ioinst_sch_id("rsch", cssid, ssid, schid);
 744     sch = css_find_subch(m, cssid, ssid, schid);
 745     if (sch && css_subch_visible(sch)) {
 746         ret = css_do_rsch(sch);
 747     }
 748     switch (ret) {
 749     case -ENODEV:
 750         cc = 3;
 751         break;
 752     case -EINVAL:
 753         cc = 2;
 754         break;
 755     case 0:
 756         cc = 0;
 757         break;
 758     default:
 759         cc = 1;
 760         break;
 761     }
 762     setcc(cpu, cc);
 763 }
 764
 765 #define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00)
 766 #define RCHP_REG1_CSSID(_reg) ((_reg & 0x0000000000ff0000) >> 16)
 767 #define RCHP_REG1_CHPID(_reg) (_reg & 0x00000000000000ff)
 768 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1)
 769 {
 770     int cc;
 771     uint8_t cssid;
 772     uint8_t chpid;
 773     int ret;
 774     CPUS390XState *env = &cpu->env;
 775
 776     if (RCHP_REG1_RES(reg1)) {
 777         program_interrupt(env, PGM_OPERAND, 2);
 778         return;
 779     }
 780
 781     cssid = RCHP_REG1_CSSID(reg1);
 782     chpid = RCHP_REG1_CHPID(reg1);
 783
 784     trace_ioinst_chp_id("rchp", cssid, chpid);
 785
 786     ret = css_do_rchp(cssid, chpid);
 787
 788     switch (ret) {
 789     case -ENODEV:
 790         cc = 3;
 791         break;
 792     case -EBUSY:
 793         cc = 2;
 794         break;
 795     case 0:
 796         cc = 0;
 797         break;
 798     default:
 799         /* Invalid channel subsystem. */
 800         program_interrupt(env, PGM_OPERAND, 2);
 801         return;
 802     }
 803     setcc(cpu, cc);
 804 }
 805
 806 #define SAL_REG1_INVALID(_reg) (_reg & 0x0000000080000000)
 807 void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1)
 808 {
 809     /* We do not provide address limit checking, so let's suppress it. */
 810     if (SAL_REG1_INVALID(reg1) || reg1 & 0x000000000000ffff) {
 811         program_interrupt(&cpu->env, PGM_OPERAND, 2);
 812     }
 813 }