hw/isa/piix4.c

   1 /*
   2  * QEMU PIIX4 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/isa/isa.h"
  29 #include "hw/sysbus.h"
  30
  31 PCIDevice *piix4_dev;
  32
  33 typedef struct PIIX4State {
  34     PCIDevice dev;
  35 } PIIX4State;
  36
  37 static void piix4_reset(void *opaque)
  38 {
  39     PIIX4State *d = opaque;
  40     uint8_t *pci_conf = d->dev.config;
  41
  42     pci_conf[0x04] = 0x07; // master, memory and I/O
  43     pci_conf[0x05] = 0x00;
  44     pci_conf[0x06] = 0x00;
  45     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
  46     pci_conf[0x4c] = 0x4d;
  47     pci_conf[0x4e] = 0x03;
  48     pci_conf[0x4f] = 0x00;
  49     pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
  50     pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
  51     pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
  52     pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
  53     pci_conf[0x69] = 0x02;
  54     pci_conf[0x70] = 0x80;
  55     pci_conf[0x76] = 0x0c;
  56     pci_conf[0x77] = 0x0c;
  57     pci_conf[0x78] = 0x02;
  58     pci_conf[0x79] = 0x00;
  59     pci_conf[0x80] = 0x00;
  60     pci_conf[0x82] = 0x00;
  61     pci_conf[0xa0] = 0x08;
  62     pci_conf[0xa2] = 0x00;
  63     pci_conf[0xa3] = 0x00;
  64     pci_conf[0xa4] = 0x00;
  65     pci_conf[0xa5] = 0x00;
  66     pci_conf[0xa6] = 0x00;
  67     pci_conf[0xa7] = 0x00;
  68     pci_conf[0xa8] = 0x0f;
  69     pci_conf[0xaa] = 0x00;
  70     pci_conf[0xab] = 0x00;
  71     pci_conf[0xac] = 0x00;
  72     pci_conf[0xae] = 0x00;
  73 }
  74
  75 static const VMStateDescription vmstate_piix4 = {
  76     .name = "PIIX4",
  77     .version_id = 2,
  78     .minimum_version_id = 2,
  79     .fields = (VMStateField[]) {
  80         VMSTATE_PCI_DEVICE(dev, PIIX4State),
  81         VMSTATE_END_OF_LIST()
  82     }
  83 };
  84
  85 static void piix4_realize(PCIDevice *dev, Error **errp)
  86 {
  87     PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev);
  88
  89     isa_bus_new(DEVICE(d), pci_address_space(dev),
  90                 pci_address_space_io(dev));
  91     piix4_dev = &d->dev;
  92     qemu_register_reset(piix4_reset, d);
  93 }
  94
  95 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
  96 {
  97     PCIDevice *d;
  98
  99     d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
 100     *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
 101     return d->devfn;
 102 }
 103
 104 static void piix4_class_init(ObjectClass *klass, void *data)
 105 {
 106     DeviceClass *dc = DEVICE_CLASS(klass);
 107     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 108
 109     k->realize = piix4_realize;
 110     k->vendor_id = PCI_VENDOR_ID_INTEL;
 111     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
 112     k->class_id = PCI_CLASS_BRIDGE_ISA;
 113     dc->desc = "ISA bridge";
 114     dc->vmsd = &vmstate_piix4;
 115     /*
 116      * Reason: part of PIIX4 southbridge, needs to be wired up,
 117      * e.g. by mips_malta_init()
 118      */
 119     dc->cannot_instantiate_with_device_add_yet = true;
 120     dc->hotpluggable = false;
 121 }
 122
 123 static const TypeInfo piix4_info = {
 124     .name          = "PIIX4",
 125     .parent        = TYPE_PCI_DEVICE,
 126     .instance_size = sizeof(PIIX4State),
 127     .class_init    = piix4_class_init,
 128 };
 129
 130 static void piix4_register_types(void)
 131 {
 132     type_register_static(&piix4_info);
 133 }
 134
 135 type_init(piix4_register_types)