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target-sparc: Unify asi handling between 32 and 64-bit
[qemu/ar7.git] / target-i386 / kvm.c
blob93275231ec1a85a1e435dd99e39a318d5874db60
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
27 #include "kvm_i386.h"
28 #include "hyperv.h"
29
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38
39 #include "exec/ioport.h"
40 #include "standard-headers/asm-x86/hyperv.h"
41 #include "hw/pci/pci.h"
42 #include "hw/pci/msi.h"
43 #include "migration/migration.h"
44 #include "exec/memattrs.h"
45
46 //#define DEBUG_KVM
47
48 #ifdef DEBUG_KVM
49 #define DPRINTF(fmt, ...) \
50 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
51 #else
52 #define DPRINTF(fmt, ...) \
53 do { } while (0)
54 #endif
55
56 #define MSR_KVM_WALL_CLOCK 0x11
57 #define MSR_KVM_SYSTEM_TIME 0x12
58
59 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
60 * 255 kvm_msr_entry structs */
61 #define MSR_BUF_SIZE 4096
62
63 #ifndef BUS_MCEERR_AR
64 #define BUS_MCEERR_AR 4
65 #endif
66 #ifndef BUS_MCEERR_AO
67 #define BUS_MCEERR_AO 5
68 #endif
69
70 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR),
72 KVM_CAP_INFO(EXT_CPUID),
73 KVM_CAP_INFO(MP_STATE),
74 KVM_CAP_LAST_INFO
75 };
76
77 static bool has_msr_star;
78 static bool has_msr_hsave_pa;
79 static bool has_msr_tsc_aux;
80 static bool has_msr_tsc_adjust;
81 static bool has_msr_tsc_deadline;
82 static bool has_msr_feature_control;
83 static bool has_msr_async_pf_en;
84 static bool has_msr_pv_eoi_en;
85 static bool has_msr_misc_enable;
86 static bool has_msr_smbase;
87 static bool has_msr_bndcfgs;
88 static bool has_msr_kvm_steal_time;
89 static int lm_capable_kernel;
90 static bool has_msr_hv_hypercall;
91 static bool has_msr_hv_vapic;
92 static bool has_msr_hv_tsc;
93 static bool has_msr_hv_crash;
94 static bool has_msr_hv_reset;
95 static bool has_msr_hv_vpindex;
96 static bool has_msr_hv_runtime;
97 static bool has_msr_hv_synic;
98 static bool has_msr_hv_stimer;
99 static bool has_msr_mtrr;
100 static bool has_msr_xss;
101
102 static bool has_msr_architectural_pmu;
103 static uint32_t num_architectural_pmu_counters;
104
105 static int has_xsave;
106 static int has_xcrs;
107 static int has_pit_state2;
108
109 static bool has_msr_mcg_ext_ctl;
110
111 static struct kvm_cpuid2 *cpuid_cache;
112
113 int kvm_has_pit_state2(void)
114 {
115 return has_pit_state2;
116 }
117
118 bool kvm_has_smm(void)
119 {
120 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
121 }
122
123 bool kvm_allows_irq0_override(void)
124 {
125 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
126 }
127
128 static int kvm_get_tsc(CPUState *cs)
129 {
130 X86CPU *cpu = X86_CPU(cs);
131 CPUX86State *env = &cpu->env;
132 struct {
133 struct kvm_msrs info;
134 struct kvm_msr_entry entries[1];
135 } msr_data;
136 int ret;
137
138 if (env->tsc_valid) {
139 return 0;
140 }
141
142 msr_data.info.nmsrs = 1;
143 msr_data.entries[0].index = MSR_IA32_TSC;
144 env->tsc_valid = !runstate_is_running();
145
146 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
147 if (ret < 0) {
148 return ret;
149 }
150
151 assert(ret == 1);
152 env->tsc = msr_data.entries[0].data;
153 return 0;
154 }
155
156 static inline void do_kvm_synchronize_tsc(void *arg)
157 {
158 CPUState *cpu = arg;
159
160 kvm_get_tsc(cpu);
161 }
162
163 void kvm_synchronize_all_tsc(void)
164 {
165 CPUState *cpu;
166
167 if (kvm_enabled()) {
168 CPU_FOREACH(cpu) {
169 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
170 }
171 }
172 }
173
174 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
175 {
176 struct kvm_cpuid2 *cpuid;
177 int r, size;
178
179 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
180 cpuid = g_malloc0(size);
181 cpuid->nent = max;
182 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
183 if (r == 0 && cpuid->nent >= max) {
184 r = -E2BIG;
185 }
186 if (r < 0) {
187 if (r == -E2BIG) {
188 g_free(cpuid);
189 return NULL;
190 } else {
191 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
192 strerror(-r));
193 exit(1);
194 }
195 }
196 return cpuid;
197 }
198
199 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
200 * for all entries.
201 */
202 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
203 {
204 struct kvm_cpuid2 *cpuid;
205 int max = 1;
206
207 if (cpuid_cache != NULL) {
208 return cpuid_cache;
209 }
210 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
211 max *= 2;
212 }
213 cpuid_cache = cpuid;
214 return cpuid;
215 }
216
217 static const struct kvm_para_features {
218 int cap;
219 int feature;
220 } para_features[] = {
221 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
222 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
223 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
224 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
225 };
226
227 static int get_para_features(KVMState *s)
228 {
229 int i, features = 0;
230
231 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
232 if (kvm_check_extension(s, para_features[i].cap)) {
233 features |= (1 << para_features[i].feature);
234 }
235 }
236
237 return features;
238 }
239
240
241 /* Returns the value for a specific register on the cpuid entry
242 */
243 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
244 {
245 uint32_t ret = 0;
246 switch (reg) {
247 case R_EAX:
248 ret = entry->eax;
249 break;
250 case R_EBX:
251 ret = entry->ebx;
252 break;
253 case R_ECX:
254 ret = entry->ecx;
255 break;
256 case R_EDX:
257 ret = entry->edx;
258 break;
259 }
260 return ret;
261 }
262
263 /* Find matching entry for function/index on kvm_cpuid2 struct
264 */
265 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
266 uint32_t function,
267 uint32_t index)
268 {
269 int i;
270 for (i = 0; i < cpuid->nent; ++i) {
271 if (cpuid->entries[i].function == function &&
272 cpuid->entries[i].index == index) {
273 return &cpuid->entries[i];
274 }
275 }
276 /* not found: */
277 return NULL;
278 }
279
280 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
281 uint32_t index, int reg)
282 {
283 struct kvm_cpuid2 *cpuid;
284 uint32_t ret = 0;
285 uint32_t cpuid_1_edx;
286 bool found = false;
287
288 cpuid = get_supported_cpuid(s);
289
290 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
291 if (entry) {
292 found = true;
293 ret = cpuid_entry_get_reg(entry, reg);
294 }
295
296 /* Fixups for the data returned by KVM, below */
297
298 if (function == 1 && reg == R_EDX) {
299 /* KVM before 2.6.30 misreports the following features */
300 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
301 } else if (function == 1 && reg == R_ECX) {
302 /* We can set the hypervisor flag, even if KVM does not return it on
303 * GET_SUPPORTED_CPUID
304 */
305 ret |= CPUID_EXT_HYPERVISOR;
306 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
307 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
308 * and the irqchip is in the kernel.
309 */
310 if (kvm_irqchip_in_kernel() &&
311 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
312 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
313 }
314
315 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
316 * without the in-kernel irqchip
317 */
318 if (!kvm_irqchip_in_kernel()) {
319 ret &= ~CPUID_EXT_X2APIC;
320 }
321 } else if (function == 6 && reg == R_EAX) {
322 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
323 } else if (function == 0x80000001 && reg == R_EDX) {
324 /* On Intel, kvm returns cpuid according to the Intel spec,
325 * so add missing bits according to the AMD spec:
326 */
327 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
328 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
329 }
330
331 /* fallback for older kernels */
332 if ((function == KVM_CPUID_FEATURES) && !found) {
333 ret = get_para_features(s);
334 }
335
336 return ret;
337 }
338
339 typedef struct HWPoisonPage {
340 ram_addr_t ram_addr;
341 QLIST_ENTRY(HWPoisonPage) list;
342 } HWPoisonPage;
343
344 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
345 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
346
347 static void kvm_unpoison_all(void *param)
348 {
349 HWPoisonPage *page, *next_page;
350
351 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
352 QLIST_REMOVE(page, list);
353 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
354 g_free(page);
355 }
356 }
357
358 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
359 {
360 HWPoisonPage *page;
361
362 QLIST_FOREACH(page, &hwpoison_page_list, list) {
363 if (page->ram_addr == ram_addr) {
364 return;
365 }
366 }
367 page = g_new(HWPoisonPage, 1);
368 page->ram_addr = ram_addr;
369 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
370 }
371
372 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
373 int *max_banks)
374 {
375 int r;
376
377 r = kvm_check_extension(s, KVM_CAP_MCE);
378 if (r > 0) {
379 *max_banks = r;
380 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
381 }
382 return -ENOSYS;
383 }
384
385 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
386 {
387 CPUState *cs = CPU(cpu);
388 CPUX86State *env = &cpu->env;
389 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
390 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
391 uint64_t mcg_status = MCG_STATUS_MCIP;
392 int flags = 0;
393
394 if (code == BUS_MCEERR_AR) {
395 status |= MCI_STATUS_AR | 0x134;
396 mcg_status |= MCG_STATUS_EIPV;
397 } else {
398 status |= 0xc0;
399 mcg_status |= MCG_STATUS_RIPV;
400 }
401
402 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
403 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
404 * guest kernel back into env->mcg_ext_ctl.
405 */
406 cpu_synchronize_state(cs);
407 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
408 mcg_status |= MCG_STATUS_LMCE;
409 flags = 0;
410 }
411
412 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
413 (MCM_ADDR_PHYS << 6) | 0xc, flags);
414 }
415
416 static void hardware_memory_error(void)
417 {
418 fprintf(stderr, "Hardware memory error!\n");
419 exit(1);
420 }
421
422 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
423 {
424 X86CPU *cpu = X86_CPU(c);
425 CPUX86State *env = &cpu->env;
426 ram_addr_t ram_addr;
427 hwaddr paddr;
428
429 if ((env->mcg_cap & MCG_SER_P) && addr
430 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
431 ram_addr = qemu_ram_addr_from_host(addr);
432 if (ram_addr == RAM_ADDR_INVALID ||
433 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
434 fprintf(stderr, "Hardware memory error for memory used by "
435 "QEMU itself instead of guest system!\n");
436 /* Hope we are lucky for AO MCE */
437 if (code == BUS_MCEERR_AO) {
438 return 0;
439 } else {
440 hardware_memory_error();
441 }
442 }
443 kvm_hwpoison_page_add(ram_addr);
444 kvm_mce_inject(cpu, paddr, code);
445 } else {
446 if (code == BUS_MCEERR_AO) {
447 return 0;
448 } else if (code == BUS_MCEERR_AR) {
449 hardware_memory_error();
450 } else {
451 return 1;
452 }
453 }
454 return 0;
455 }
456
457 int kvm_arch_on_sigbus(int code, void *addr)
458 {
459 X86CPU *cpu = X86_CPU(first_cpu);
460
461 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
462 ram_addr_t ram_addr;
463 hwaddr paddr;
464
465 /* Hope we are lucky for AO MCE */
466 ram_addr = qemu_ram_addr_from_host(addr);
467 if (ram_addr == RAM_ADDR_INVALID ||
468 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
469 addr, &paddr)) {
470 fprintf(stderr, "Hardware memory error for memory used by "
471 "QEMU itself instead of guest system!: %p\n", addr);
472 return 0;
473 }
474 kvm_hwpoison_page_add(ram_addr);
475 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
476 } else {
477 if (code == BUS_MCEERR_AO) {
478 return 0;
479 } else if (code == BUS_MCEERR_AR) {
480 hardware_memory_error();
481 } else {
482 return 1;
483 }
484 }
485 return 0;
486 }
487
488 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
489 {
490 CPUX86State *env = &cpu->env;
491
492 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
493 unsigned int bank, bank_num = env->mcg_cap & 0xff;
494 struct kvm_x86_mce mce;
495
496 env->exception_injected = -1;
497
498 /*
499 * There must be at least one bank in use if an MCE is pending.
500 * Find it and use its values for the event injection.
501 */
502 for (bank = 0; bank < bank_num; bank++) {
503 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
504 break;
505 }
506 }
507 assert(bank < bank_num);
508
509 mce.bank = bank;
510 mce.status = env->mce_banks[bank * 4 + 1];
511 mce.mcg_status = env->mcg_status;
512 mce.addr = env->mce_banks[bank * 4 + 2];
513 mce.misc = env->mce_banks[bank * 4 + 3];
514
515 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
516 }
517 return 0;
518 }
519
520 static void cpu_update_state(void *opaque, int running, RunState state)
521 {
522 CPUX86State *env = opaque;
523
524 if (running) {
525 env->tsc_valid = false;
526 }
527 }
528
529 unsigned long kvm_arch_vcpu_id(CPUState *cs)
530 {
531 X86CPU *cpu = X86_CPU(cs);
532 return cpu->apic_id;
533 }
534
535 #ifndef KVM_CPUID_SIGNATURE_NEXT
536 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
537 #endif
538
539 static bool hyperv_hypercall_available(X86CPU *cpu)
540 {
541 return cpu->hyperv_vapic ||
542 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
543 }
544
545 static bool hyperv_enabled(X86CPU *cpu)
546 {
547 CPUState *cs = CPU(cpu);
548 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
549 (hyperv_hypercall_available(cpu) ||
550 cpu->hyperv_time ||
551 cpu->hyperv_relaxed_timing ||
552 cpu->hyperv_crash ||
553 cpu->hyperv_reset ||
554 cpu->hyperv_vpindex ||
555 cpu->hyperv_runtime ||
556 cpu->hyperv_synic ||
557 cpu->hyperv_stimer);
558 }
559
560 static int kvm_arch_set_tsc_khz(CPUState *cs)
561 {
562 X86CPU *cpu = X86_CPU(cs);
563 CPUX86State *env = &cpu->env;
564 int r;
565
566 if (!env->tsc_khz) {
567 return 0;
568 }
569
570 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
571 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
572 -ENOTSUP;
573 if (r < 0) {
574 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
575 * TSC frequency doesn't match the one we want.
576 */
577 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
578 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
579 -ENOTSUP;
580 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
581 error_report("warning: TSC frequency mismatch between "
582 "VM (%" PRId64 " kHz) and host (%d kHz), "
583 "and TSC scaling unavailable",
584 env->tsc_khz, cur_freq);
585 return r;
586 }
587 }
588
589 return 0;
590 }
591
592 static int hyperv_handle_properties(CPUState *cs)
593 {
594 X86CPU *cpu = X86_CPU(cs);
595 CPUX86State *env = &cpu->env;
596
597 if (cpu->hyperv_relaxed_timing) {
598 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
599 }
600 if (cpu->hyperv_vapic) {
601 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
602 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
603 has_msr_hv_vapic = true;
604 }
605 if (cpu->hyperv_time &&
606 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
607 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
608 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
609 env->features[FEAT_HYPERV_EAX] |= 0x200;
610 has_msr_hv_tsc = true;
611 }
612 if (cpu->hyperv_crash && has_msr_hv_crash) {
613 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
614 }
615 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
616 if (cpu->hyperv_reset && has_msr_hv_reset) {
617 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
618 }
619 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
620 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
621 }
622 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
623 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
624 }
625 if (cpu->hyperv_synic) {
626 int sint;
627
628 if (!has_msr_hv_synic ||
629 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
630 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
631 return -ENOSYS;
632 }
633
634 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
635 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
636 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
637 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
638 }
639 }
640 if (cpu->hyperv_stimer) {
641 if (!has_msr_hv_stimer) {
642 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
643 return -ENOSYS;
644 }
645 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
646 }
647 return 0;
648 }
649
650 static Error *invtsc_mig_blocker;
651
652 #define KVM_MAX_CPUID_ENTRIES 100
653
654 int kvm_arch_init_vcpu(CPUState *cs)
655 {
656 struct {
657 struct kvm_cpuid2 cpuid;
658 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
659 } QEMU_PACKED cpuid_data;
660 X86CPU *cpu = X86_CPU(cs);
661 CPUX86State *env = &cpu->env;
662 uint32_t limit, i, j, cpuid_i;
663 uint32_t unused;
664 struct kvm_cpuid_entry2 *c;
665 uint32_t signature[3];
666 int kvm_base = KVM_CPUID_SIGNATURE;
667 int r;
668
669 memset(&cpuid_data, 0, sizeof(cpuid_data));
670
671 cpuid_i = 0;
672
673 /* Paravirtualization CPUIDs */
674 if (hyperv_enabled(cpu)) {
675 c = &cpuid_data.entries[cpuid_i++];
676 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
677 if (!cpu->hyperv_vendor_id) {
678 memcpy(signature, "Microsoft Hv", 12);
679 } else {
680 size_t len = strlen(cpu->hyperv_vendor_id);
681
682 if (len > 12) {
683 error_report("hv-vendor-id truncated to 12 characters");
684 len = 12;
685 }
686 memset(signature, 0, 12);
687 memcpy(signature, cpu->hyperv_vendor_id, len);
688 }
689 c->eax = HYPERV_CPUID_MIN;
690 c->ebx = signature[0];
691 c->ecx = signature[1];
692 c->edx = signature[2];
693
694 c = &cpuid_data.entries[cpuid_i++];
695 c->function = HYPERV_CPUID_INTERFACE;
696 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
697 c->eax = signature[0];
698 c->ebx = 0;
699 c->ecx = 0;
700 c->edx = 0;
701
702 c = &cpuid_data.entries[cpuid_i++];
703 c->function = HYPERV_CPUID_VERSION;
704 c->eax = 0x00001bbc;
705 c->ebx = 0x00060001;
706
707 c = &cpuid_data.entries[cpuid_i++];
708 c->function = HYPERV_CPUID_FEATURES;
709 r = hyperv_handle_properties(cs);
710 if (r) {
711 return r;
712 }
713 c->eax = env->features[FEAT_HYPERV_EAX];
714 c->ebx = env->features[FEAT_HYPERV_EBX];
715 c->edx = env->features[FEAT_HYPERV_EDX];
716
717 c = &cpuid_data.entries[cpuid_i++];
718 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
719 if (cpu->hyperv_relaxed_timing) {
720 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
721 }
722 if (has_msr_hv_vapic) {
723 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
724 }
725 c->ebx = cpu->hyperv_spinlock_attempts;
726
727 c = &cpuid_data.entries[cpuid_i++];
728 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
729 c->eax = 0x40;
730 c->ebx = 0x40;
731
732 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
733 has_msr_hv_hypercall = true;
734 }
735
736 if (cpu->expose_kvm) {
737 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
738 c = &cpuid_data.entries[cpuid_i++];
739 c->function = KVM_CPUID_SIGNATURE | kvm_base;
740 c->eax = KVM_CPUID_FEATURES | kvm_base;
741 c->ebx = signature[0];
742 c->ecx = signature[1];
743 c->edx = signature[2];
744
745 c = &cpuid_data.entries[cpuid_i++];
746 c->function = KVM_CPUID_FEATURES | kvm_base;
747 c->eax = env->features[FEAT_KVM];
748
749 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
750
751 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
752
753 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
754 }
755
756 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
757
758 for (i = 0; i <= limit; i++) {
759 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
760 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
761 abort();
762 }
763 c = &cpuid_data.entries[cpuid_i++];
764
765 switch (i) {
766 case 2: {
767 /* Keep reading function 2 till all the input is received */
768 int times;
769
770 c->function = i;
771 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
772 KVM_CPUID_FLAG_STATE_READ_NEXT;
773 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
774 times = c->eax & 0xff;
775
776 for (j = 1; j < times; ++j) {
777 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
778 fprintf(stderr, "cpuid_data is full, no space for "
779 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
780 abort();
781 }
782 c = &cpuid_data.entries[cpuid_i++];
783 c->function = i;
784 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
785 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
786 }
787 break;
788 }
789 case 4:
790 case 0xb:
791 case 0xd:
792 for (j = 0; ; j++) {
793 if (i == 0xd && j == 64) {
794 break;
795 }
796 c->function = i;
797 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
798 c->index = j;
799 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
800
801 if (i == 4 && c->eax == 0) {
802 break;
803 }
804 if (i == 0xb && !(c->ecx & 0xff00)) {
805 break;
806 }
807 if (i == 0xd && c->eax == 0) {
808 continue;
809 }
810 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
811 fprintf(stderr, "cpuid_data is full, no space for "
812 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
813 abort();
814 }
815 c = &cpuid_data.entries[cpuid_i++];
816 }
817 break;
818 default:
819 c->function = i;
820 c->flags = 0;
821 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
822 break;
823 }
824 }
825
826 if (limit >= 0x0a) {
827 uint32_t ver;
828
829 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
830 if ((ver & 0xff) > 0) {
831 has_msr_architectural_pmu = true;
832 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
833
834 /* Shouldn't be more than 32, since that's the number of bits
835 * available in EBX to tell us _which_ counters are available.
836 * Play it safe.
837 */
838 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
839 num_architectural_pmu_counters = MAX_GP_COUNTERS;
840 }
841 }
842 }
843
844 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
845
846 for (i = 0x80000000; i <= limit; i++) {
847 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
848 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
849 abort();
850 }
851 c = &cpuid_data.entries[cpuid_i++];
852
853 c->function = i;
854 c->flags = 0;
855 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
856 }
857
858 /* Call Centaur's CPUID instructions they are supported. */
859 if (env->cpuid_xlevel2 > 0) {
860 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
861
862 for (i = 0xC0000000; i <= limit; i++) {
863 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
864 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
865 abort();
866 }
867 c = &cpuid_data.entries[cpuid_i++];
868
869 c->function = i;
870 c->flags = 0;
871 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
872 }
873 }
874
875 cpuid_data.cpuid.nent = cpuid_i;
876
877 if (((env->cpuid_version >> 8)&0xF) >= 6
878 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
879 (CPUID_MCE | CPUID_MCA)
880 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
881 uint64_t mcg_cap, unsupported_caps;
882 int banks;
883 int ret;
884
885 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
886 if (ret < 0) {
887 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
888 return ret;
889 }
890
891 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
892 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
893 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
894 return -ENOTSUP;
895 }
896
897 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
898 if (unsupported_caps) {
899 if (unsupported_caps & MCG_LMCE_P) {
900 error_report("kvm: LMCE not supported");
901 return -ENOTSUP;
902 }
903 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
904 unsupported_caps);
905 }
906
907 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
908 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
909 if (ret < 0) {
910 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
911 return ret;
912 }
913 }
914
915 qemu_add_vm_change_state_handler(cpu_update_state, env);
916
917 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
918 if (c) {
919 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
920 !!(c->ecx & CPUID_EXT_SMX);
921 }
922
923 if (env->mcg_cap & MCG_LMCE_P) {
924 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
925 }
926
927 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
928 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
929 /* for migration */
930 error_setg(&invtsc_mig_blocker,
931 "State blocked by non-migratable CPU device"
932 " (invtsc flag)");
933 migrate_add_blocker(invtsc_mig_blocker);
934 /* for savevm */
935 vmstate_x86_cpu.unmigratable = 1;
936 }
937
938 cpuid_data.cpuid.padding = 0;
939 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
940 if (r) {
941 return r;
942 }
943
944 r = kvm_arch_set_tsc_khz(cs);
945 if (r < 0) {
946 return r;
947 }
948
949 /* vcpu's TSC frequency is either specified by user, or following
950 * the value used by KVM if the former is not present. In the
951 * latter case, we query it from KVM and record in env->tsc_khz,
952 * so that vcpu's TSC frequency can be migrated later via this field.
953 */
954 if (!env->tsc_khz) {
955 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
956 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
957 -ENOTSUP;
958 if (r > 0) {
959 env->tsc_khz = r;
960 }
961 }
962
963 if (has_xsave) {
964 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
965 }
966 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
967
968 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
969 has_msr_mtrr = true;
970 }
971 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
972 has_msr_tsc_aux = false;
973 }
974
975 return 0;
976 }
977
978 void kvm_arch_reset_vcpu(X86CPU *cpu)
979 {
980 CPUX86State *env = &cpu->env;
981
982 env->exception_injected = -1;
983 env->interrupt_injected = -1;
984 env->xcr0 = 1;
985 if (kvm_irqchip_in_kernel()) {
986 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
987 KVM_MP_STATE_UNINITIALIZED;
988 } else {
989 env->mp_state = KVM_MP_STATE_RUNNABLE;
990 }
991 }
992
993 void kvm_arch_do_init_vcpu(X86CPU *cpu)
994 {
995 CPUX86State *env = &cpu->env;
996
997 /* APs get directly into wait-for-SIPI state. */
998 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
999 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1000 }
1001 }
1002
1003 static int kvm_get_supported_msrs(KVMState *s)
1004 {
1005 static int kvm_supported_msrs;
1006 int ret = 0;
1007
1008 /* first time */
1009 if (kvm_supported_msrs == 0) {
1010 struct kvm_msr_list msr_list, *kvm_msr_list;
1011
1012 kvm_supported_msrs = -1;
1013
1014 /* Obtain MSR list from KVM. These are the MSRs that we must
1015 * save/restore */
1016 msr_list.nmsrs = 0;
1017 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1018 if (ret < 0 && ret != -E2BIG) {
1019 return ret;
1020 }
1021 /* Old kernel modules had a bug and could write beyond the provided
1022 memory. Allocate at least a safe amount of 1K. */
1023 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1024 msr_list.nmsrs *
1025 sizeof(msr_list.indices[0])));
1026
1027 kvm_msr_list->nmsrs = msr_list.nmsrs;
1028 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1029 if (ret >= 0) {
1030 int i;
1031
1032 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1033 if (kvm_msr_list->indices[i] == MSR_STAR) {
1034 has_msr_star = true;
1035 continue;
1036 }
1037 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1038 has_msr_hsave_pa = true;
1039 continue;
1040 }
1041 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1042 has_msr_tsc_aux = true;
1043 continue;
1044 }
1045 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1046 has_msr_tsc_adjust = true;
1047 continue;
1048 }
1049 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1050 has_msr_tsc_deadline = true;
1051 continue;
1052 }
1053 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1054 has_msr_smbase = true;
1055 continue;
1056 }
1057 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1058 has_msr_misc_enable = true;
1059 continue;
1060 }
1061 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1062 has_msr_bndcfgs = true;
1063 continue;
1064 }
1065 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1066 has_msr_xss = true;
1067 continue;
1068 }
1069 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1070 has_msr_hv_crash = true;
1071 continue;
1072 }
1073 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1074 has_msr_hv_reset = true;
1075 continue;
1076 }
1077 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1078 has_msr_hv_vpindex = true;
1079 continue;
1080 }
1081 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1082 has_msr_hv_runtime = true;
1083 continue;
1084 }
1085 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1086 has_msr_hv_synic = true;
1087 continue;
1088 }
1089 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1090 has_msr_hv_stimer = true;
1091 continue;
1092 }
1093 }
1094 }
1095
1096 g_free(kvm_msr_list);
1097 }
1098
1099 return ret;
1100 }
1101
1102 static Notifier smram_machine_done;
1103 static KVMMemoryListener smram_listener;
1104 static AddressSpace smram_address_space;
1105 static MemoryRegion smram_as_root;
1106 static MemoryRegion smram_as_mem;
1107
1108 static void register_smram_listener(Notifier *n, void *unused)
1109 {
1110 MemoryRegion *smram =
1111 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1112
1113 /* Outer container... */
1114 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1115 memory_region_set_enabled(&smram_as_root, true);
1116
1117 /* ... with two regions inside: normal system memory with low
1118 * priority, and...
1119 */
1120 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1121 get_system_memory(), 0, ~0ull);
1122 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1123 memory_region_set_enabled(&smram_as_mem, true);
1124
1125 if (smram) {
1126 /* ... SMRAM with higher priority */
1127 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1128 memory_region_set_enabled(smram, true);
1129 }
1130
1131 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1132 kvm_memory_listener_register(kvm_state, &smram_listener,
1133 &smram_address_space, 1);
1134 }
1135
1136 int kvm_arch_init(MachineState *ms, KVMState *s)
1137 {
1138 uint64_t identity_base = 0xfffbc000;
1139 uint64_t shadow_mem;
1140 int ret;
1141 struct utsname utsname;
1142
1143 #ifdef KVM_CAP_XSAVE
1144 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1145 #endif
1146
1147 #ifdef KVM_CAP_XCRS
1148 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1149 #endif
1150
1151 #ifdef KVM_CAP_PIT_STATE2
1152 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1153 #endif
1154
1155 ret = kvm_get_supported_msrs(s);
1156 if (ret < 0) {
1157 return ret;
1158 }
1159
1160 uname(&utsname);
1161 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1162
1163 /*
1164 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1165 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1166 * Since these must be part of guest physical memory, we need to allocate
1167 * them, both by setting their start addresses in the kernel and by
1168 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1169 *
1170 * Older KVM versions may not support setting the identity map base. In
1171 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1172 * size.
1173 */
1174 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1175 /* Allows up to 16M BIOSes. */
1176 identity_base = 0xfeffc000;
1177
1178 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1179 if (ret < 0) {
1180 return ret;
1181 }
1182 }
1183
1184 /* Set TSS base one page after EPT identity map. */
1185 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1186 if (ret < 0) {
1187 return ret;
1188 }
1189
1190 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1191 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1192 if (ret < 0) {
1193 fprintf(stderr, "e820_add_entry() table is full\n");
1194 return ret;
1195 }
1196 qemu_register_reset(kvm_unpoison_all, NULL);
1197
1198 shadow_mem = machine_kvm_shadow_mem(ms);
1199 if (shadow_mem != -1) {
1200 shadow_mem /= 4096;
1201 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1202 if (ret < 0) {
1203 return ret;
1204 }
1205 }
1206
1207 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1208 smram_machine_done.notify = register_smram_listener;
1209 qemu_add_machine_init_done_notifier(&smram_machine_done);
1210 }
1211 return 0;
1212 }
1213
1214 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1215 {
1216 lhs->selector = rhs->selector;
1217 lhs->base = rhs->base;
1218 lhs->limit = rhs->limit;
1219 lhs->type = 3;
1220 lhs->present = 1;
1221 lhs->dpl = 3;
1222 lhs->db = 0;
1223 lhs->s = 1;
1224 lhs->l = 0;
1225 lhs->g = 0;
1226 lhs->avl = 0;
1227 lhs->unusable = 0;
1228 }
1229
1230 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1231 {
1232 unsigned flags = rhs->flags;
1233 lhs->selector = rhs->selector;
1234 lhs->base = rhs->base;
1235 lhs->limit = rhs->limit;
1236 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1237 lhs->present = (flags & DESC_P_MASK) != 0;
1238 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1239 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1240 lhs->s = (flags & DESC_S_MASK) != 0;
1241 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1242 lhs->g = (flags & DESC_G_MASK) != 0;
1243 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1244 lhs->unusable = !lhs->present;
1245 lhs->padding = 0;
1246 }
1247
1248 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1249 {
1250 lhs->selector = rhs->selector;
1251 lhs->base = rhs->base;
1252 lhs->limit = rhs->limit;
1253 if (rhs->unusable) {
1254 lhs->flags = 0;
1255 } else {
1256 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1257 (rhs->present * DESC_P_MASK) |
1258 (rhs->dpl << DESC_DPL_SHIFT) |
1259 (rhs->db << DESC_B_SHIFT) |
1260 (rhs->s * DESC_S_MASK) |
1261 (rhs->l << DESC_L_SHIFT) |
1262 (rhs->g * DESC_G_MASK) |
1263 (rhs->avl * DESC_AVL_MASK);
1264 }
1265 }
1266
1267 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1268 {
1269 if (set) {
1270 *kvm_reg = *qemu_reg;
1271 } else {
1272 *qemu_reg = *kvm_reg;
1273 }
1274 }
1275
1276 static int kvm_getput_regs(X86CPU *cpu, int set)
1277 {
1278 CPUX86State *env = &cpu->env;
1279 struct kvm_regs regs;
1280 int ret = 0;
1281
1282 if (!set) {
1283 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1284 if (ret < 0) {
1285 return ret;
1286 }
1287 }
1288
1289 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1290 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1291 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1292 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1293 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1294 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1295 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1296 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1297 #ifdef TARGET_X86_64
1298 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1299 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1300 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1301 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1302 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1303 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1304 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1305 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1306 #endif
1307
1308 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1309 kvm_getput_reg(&regs.rip, &env->eip, set);
1310
1311 if (set) {
1312 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1313 }
1314
1315 return ret;
1316 }
1317
1318 static int kvm_put_fpu(X86CPU *cpu)
1319 {
1320 CPUX86State *env = &cpu->env;
1321 struct kvm_fpu fpu;
1322 int i;
1323
1324 memset(&fpu, 0, sizeof fpu);
1325 fpu.fsw = env->fpus & ~(7 << 11);
1326 fpu.fsw |= (env->fpstt & 7) << 11;
1327 fpu.fcw = env->fpuc;
1328 fpu.last_opcode = env->fpop;
1329 fpu.last_ip = env->fpip;
1330 fpu.last_dp = env->fpdp;
1331 for (i = 0; i < 8; ++i) {
1332 fpu.ftwx |= (!env->fptags[i]) << i;
1333 }
1334 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1335 for (i = 0; i < CPU_NB_REGS; i++) {
1336 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1337 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1338 }
1339 fpu.mxcsr = env->mxcsr;
1340
1341 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1342 }
1343
1344 #define XSAVE_FCW_FSW 0
1345 #define XSAVE_FTW_FOP 1
1346 #define XSAVE_CWD_RIP 2
1347 #define XSAVE_CWD_RDP 4
1348 #define XSAVE_MXCSR 6
1349 #define XSAVE_ST_SPACE 8
1350 #define XSAVE_XMM_SPACE 40
1351 #define XSAVE_XSTATE_BV 128
1352 #define XSAVE_YMMH_SPACE 144
1353 #define XSAVE_BNDREGS 240
1354 #define XSAVE_BNDCSR 256
1355 #define XSAVE_OPMASK 272
1356 #define XSAVE_ZMM_Hi256 288
1357 #define XSAVE_Hi16_ZMM 416
1358 #define XSAVE_PKRU 672
1359
1360 #define XSAVE_BYTE_OFFSET(word_offset) \
1361 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1362
1363 #define ASSERT_OFFSET(word_offset, field) \
1364 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1365 offsetof(X86XSaveArea, field))
1366
1367 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1368 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1369 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1370 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1371 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1372 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1373 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1374 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1375 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1376 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1377 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1378 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1379 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1380 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1381 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1382
1383 static int kvm_put_xsave(X86CPU *cpu)
1384 {
1385 CPUX86State *env = &cpu->env;
1386 X86XSaveArea *xsave = env->kvm_xsave_buf;
1387 uint16_t cwd, swd, twd;
1388 int i;
1389
1390 if (!has_xsave) {
1391 return kvm_put_fpu(cpu);
1392 }
1393
1394 memset(xsave, 0, sizeof(struct kvm_xsave));
1395 twd = 0;
1396 swd = env->fpus & ~(7 << 11);
1397 swd |= (env->fpstt & 7) << 11;
1398 cwd = env->fpuc;
1399 for (i = 0; i < 8; ++i) {
1400 twd |= (!env->fptags[i]) << i;
1401 }
1402 xsave->legacy.fcw = cwd;
1403 xsave->legacy.fsw = swd;
1404 xsave->legacy.ftw = twd;
1405 xsave->legacy.fpop = env->fpop;
1406 xsave->legacy.fpip = env->fpip;
1407 xsave->legacy.fpdp = env->fpdp;
1408 memcpy(&xsave->legacy.fpregs, env->fpregs,
1409 sizeof env->fpregs);
1410 xsave->legacy.mxcsr = env->mxcsr;
1411 xsave->header.xstate_bv = env->xstate_bv;
1412 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1413 sizeof env->bnd_regs);
1414 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1415 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1416 sizeof env->opmask_regs);
1417
1418 for (i = 0; i < CPU_NB_REGS; i++) {
1419 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1420 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1421 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1422 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1423 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1424 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1425 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1426 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1427 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1428 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1429 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1430 }
1431
1432 #ifdef TARGET_X86_64
1433 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1434 16 * sizeof env->xmm_regs[16]);
1435 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1436 #endif
1437 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1438 }
1439
1440 static int kvm_put_xcrs(X86CPU *cpu)
1441 {
1442 CPUX86State *env = &cpu->env;
1443 struct kvm_xcrs xcrs = {};
1444
1445 if (!has_xcrs) {
1446 return 0;
1447 }
1448
1449 xcrs.nr_xcrs = 1;
1450 xcrs.flags = 0;
1451 xcrs.xcrs[0].xcr = 0;
1452 xcrs.xcrs[0].value = env->xcr0;
1453 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1454 }
1455
1456 static int kvm_put_sregs(X86CPU *cpu)
1457 {
1458 CPUX86State *env = &cpu->env;
1459 struct kvm_sregs sregs;
1460
1461 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1462 if (env->interrupt_injected >= 0) {
1463 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1464 (uint64_t)1 << (env->interrupt_injected % 64);
1465 }
1466
1467 if ((env->eflags & VM_MASK)) {
1468 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1469 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1470 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1471 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1472 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1473 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1474 } else {
1475 set_seg(&sregs.cs, &env->segs[R_CS]);
1476 set_seg(&sregs.ds, &env->segs[R_DS]);
1477 set_seg(&sregs.es, &env->segs[R_ES]);
1478 set_seg(&sregs.fs, &env->segs[R_FS]);
1479 set_seg(&sregs.gs, &env->segs[R_GS]);
1480 set_seg(&sregs.ss, &env->segs[R_SS]);
1481 }
1482
1483 set_seg(&sregs.tr, &env->tr);
1484 set_seg(&sregs.ldt, &env->ldt);
1485
1486 sregs.idt.limit = env->idt.limit;
1487 sregs.idt.base = env->idt.base;
1488 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1489 sregs.gdt.limit = env->gdt.limit;
1490 sregs.gdt.base = env->gdt.base;
1491 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1492
1493 sregs.cr0 = env->cr[0];
1494 sregs.cr2 = env->cr[2];
1495 sregs.cr3 = env->cr[3];
1496 sregs.cr4 = env->cr[4];
1497
1498 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1499 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1500
1501 sregs.efer = env->efer;
1502
1503 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1504 }
1505
1506 static void kvm_msr_buf_reset(X86CPU *cpu)
1507 {
1508 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1509 }
1510
1511 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1512 {
1513 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1514 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1515 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1516
1517 assert((void *)(entry + 1) <= limit);
1518
1519 entry->index = index;
1520 entry->reserved = 0;
1521 entry->data = value;
1522 msrs->nmsrs++;
1523 }
1524
1525 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1526 {
1527 CPUX86State *env = &cpu->env;
1528 int ret;
1529
1530 if (!has_msr_tsc_deadline) {
1531 return 0;
1532 }
1533
1534 kvm_msr_buf_reset(cpu);
1535 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1536
1537 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1538 if (ret < 0) {
1539 return ret;
1540 }
1541
1542 assert(ret == 1);
1543 return 0;
1544 }
1545
1546 /*
1547 * Provide a separate write service for the feature control MSR in order to
1548 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1549 * before writing any other state because forcibly leaving nested mode
1550 * invalidates the VCPU state.
1551 */
1552 static int kvm_put_msr_feature_control(X86CPU *cpu)
1553 {
1554 int ret;
1555
1556 if (!has_msr_feature_control) {
1557 return 0;
1558 }
1559
1560 kvm_msr_buf_reset(cpu);
1561 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL,
1562 cpu->env.msr_ia32_feature_control);
1563
1564 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1565 if (ret < 0) {
1566 return ret;
1567 }
1568
1569 assert(ret == 1);
1570 return 0;
1571 }
1572
1573 static int kvm_put_msrs(X86CPU *cpu, int level)
1574 {
1575 CPUX86State *env = &cpu->env;
1576 int i;
1577 int ret;
1578
1579 kvm_msr_buf_reset(cpu);
1580
1581 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1582 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1583 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1584 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1585 if (has_msr_star) {
1586 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1587 }
1588 if (has_msr_hsave_pa) {
1589 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1590 }
1591 if (has_msr_tsc_aux) {
1592 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1593 }
1594 if (has_msr_tsc_adjust) {
1595 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1596 }
1597 if (has_msr_misc_enable) {
1598 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1599 env->msr_ia32_misc_enable);
1600 }
1601 if (has_msr_smbase) {
1602 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1603 }
1604 if (has_msr_bndcfgs) {
1605 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1606 }
1607 if (has_msr_xss) {
1608 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1609 }
1610 #ifdef TARGET_X86_64
1611 if (lm_capable_kernel) {
1612 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1613 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1614 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1615 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1616 }
1617 #endif
1618 /*
1619 * The following MSRs have side effects on the guest or are too heavy
1620 * for normal writeback. Limit them to reset or full state updates.
1621 */
1622 if (level >= KVM_PUT_RESET_STATE) {
1623 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1624 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1625 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1626 if (has_msr_async_pf_en) {
1627 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1628 }
1629 if (has_msr_pv_eoi_en) {
1630 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1631 }
1632 if (has_msr_kvm_steal_time) {
1633 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1634 }
1635 if (has_msr_architectural_pmu) {
1636 /* Stop the counter. */
1637 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1638 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1639
1640 /* Set the counter values. */
1641 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1642 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1643 env->msr_fixed_counters[i]);
1644 }
1645 for (i = 0; i < num_architectural_pmu_counters; i++) {
1646 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1647 env->msr_gp_counters[i]);
1648 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1649 env->msr_gp_evtsel[i]);
1650 }
1651 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1652 env->msr_global_status);
1653 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1654 env->msr_global_ovf_ctrl);
1655
1656 /* Now start the PMU. */
1657 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1658 env->msr_fixed_ctr_ctrl);
1659 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1660 env->msr_global_ctrl);
1661 }
1662 if (has_msr_hv_hypercall) {
1663 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1664 env->msr_hv_guest_os_id);
1665 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1666 env->msr_hv_hypercall);
1667 }
1668 if (has_msr_hv_vapic) {
1669 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1670 env->msr_hv_vapic);
1671 }
1672 if (has_msr_hv_tsc) {
1673 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1674 }
1675 if (has_msr_hv_crash) {
1676 int j;
1677
1678 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1679 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1680 env->msr_hv_crash_params[j]);
1681
1682 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1683 HV_X64_MSR_CRASH_CTL_NOTIFY);
1684 }
1685 if (has_msr_hv_runtime) {
1686 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1687 }
1688 if (cpu->hyperv_synic) {
1689 int j;
1690
1691 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1692 env->msr_hv_synic_control);
1693 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1694 env->msr_hv_synic_version);
1695 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1696 env->msr_hv_synic_evt_page);
1697 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1698 env->msr_hv_synic_msg_page);
1699
1700 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1701 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1702 env->msr_hv_synic_sint[j]);
1703 }
1704 }
1705 if (has_msr_hv_stimer) {
1706 int j;
1707
1708 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1709 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1710 env->msr_hv_stimer_config[j]);
1711 }
1712
1713 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1714 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1715 env->msr_hv_stimer_count[j]);
1716 }
1717 }
1718 if (has_msr_mtrr) {
1719 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1720 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1721 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1722 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1723 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1724 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1725 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1726 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1727 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1728 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1729 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1730 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1731 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1732 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1733 env->mtrr_var[i].base);
1734 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i),
1735 env->mtrr_var[i].mask);
1736 }
1737 }
1738
1739 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1740 * kvm_put_msr_feature_control. */
1741 }
1742 if (env->mcg_cap) {
1743 int i;
1744
1745 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1746 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1747 if (has_msr_mcg_ext_ctl) {
1748 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1749 }
1750 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1751 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1752 }
1753 }
1754
1755 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1756 if (ret < 0) {
1757 return ret;
1758 }
1759
1760 assert(ret == cpu->kvm_msr_buf->nmsrs);
1761 return 0;
1762 }
1763
1764
1765 static int kvm_get_fpu(X86CPU *cpu)
1766 {
1767 CPUX86State *env = &cpu->env;
1768 struct kvm_fpu fpu;
1769 int i, ret;
1770
1771 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1772 if (ret < 0) {
1773 return ret;
1774 }
1775
1776 env->fpstt = (fpu.fsw >> 11) & 7;
1777 env->fpus = fpu.fsw;
1778 env->fpuc = fpu.fcw;
1779 env->fpop = fpu.last_opcode;
1780 env->fpip = fpu.last_ip;
1781 env->fpdp = fpu.last_dp;
1782 for (i = 0; i < 8; ++i) {
1783 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1784 }
1785 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1786 for (i = 0; i < CPU_NB_REGS; i++) {
1787 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1788 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1789 }
1790 env->mxcsr = fpu.mxcsr;
1791
1792 return 0;
1793 }
1794
1795 static int kvm_get_xsave(X86CPU *cpu)
1796 {
1797 CPUX86State *env = &cpu->env;
1798 X86XSaveArea *xsave = env->kvm_xsave_buf;
1799 int ret, i;
1800 uint16_t cwd, swd, twd;
1801
1802 if (!has_xsave) {
1803 return kvm_get_fpu(cpu);
1804 }
1805
1806 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1807 if (ret < 0) {
1808 return ret;
1809 }
1810
1811 cwd = xsave->legacy.fcw;
1812 swd = xsave->legacy.fsw;
1813 twd = xsave->legacy.ftw;
1814 env->fpop = xsave->legacy.fpop;
1815 env->fpstt = (swd >> 11) & 7;
1816 env->fpus = swd;
1817 env->fpuc = cwd;
1818 for (i = 0; i < 8; ++i) {
1819 env->fptags[i] = !((twd >> i) & 1);
1820 }
1821 env->fpip = xsave->legacy.fpip;
1822 env->fpdp = xsave->legacy.fpdp;
1823 env->mxcsr = xsave->legacy.mxcsr;
1824 memcpy(env->fpregs, &xsave->legacy.fpregs,
1825 sizeof env->fpregs);
1826 env->xstate_bv = xsave->header.xstate_bv;
1827 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1828 sizeof env->bnd_regs);
1829 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1830 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1831 sizeof env->opmask_regs);
1832
1833 for (i = 0; i < CPU_NB_REGS; i++) {
1834 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1835 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1836 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1837 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1838 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1839 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1840 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1841 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1842 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1843 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1844 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1845 }
1846
1847 #ifdef TARGET_X86_64
1848 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1849 16 * sizeof env->xmm_regs[16]);
1850 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1851 #endif
1852 return 0;
1853 }
1854
1855 static int kvm_get_xcrs(X86CPU *cpu)
1856 {
1857 CPUX86State *env = &cpu->env;
1858 int i, ret;
1859 struct kvm_xcrs xcrs;
1860
1861 if (!has_xcrs) {
1862 return 0;
1863 }
1864
1865 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1866 if (ret < 0) {
1867 return ret;
1868 }
1869
1870 for (i = 0; i < xcrs.nr_xcrs; i++) {
1871 /* Only support xcr0 now */
1872 if (xcrs.xcrs[i].xcr == 0) {
1873 env->xcr0 = xcrs.xcrs[i].value;
1874 break;
1875 }
1876 }
1877 return 0;
1878 }
1879
1880 static int kvm_get_sregs(X86CPU *cpu)
1881 {
1882 CPUX86State *env = &cpu->env;
1883 struct kvm_sregs sregs;
1884 uint32_t hflags;
1885 int bit, i, ret;
1886
1887 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1888 if (ret < 0) {
1889 return ret;
1890 }
1891
1892 /* There can only be one pending IRQ set in the bitmap at a time, so try
1893 to find it and save its number instead (-1 for none). */
1894 env->interrupt_injected = -1;
1895 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1896 if (sregs.interrupt_bitmap[i]) {
1897 bit = ctz64(sregs.interrupt_bitmap[i]);
1898 env->interrupt_injected = i * 64 + bit;
1899 break;
1900 }
1901 }
1902
1903 get_seg(&env->segs[R_CS], &sregs.cs);
1904 get_seg(&env->segs[R_DS], &sregs.ds);
1905 get_seg(&env->segs[R_ES], &sregs.es);
1906 get_seg(&env->segs[R_FS], &sregs.fs);
1907 get_seg(&env->segs[R_GS], &sregs.gs);
1908 get_seg(&env->segs[R_SS], &sregs.ss);
1909
1910 get_seg(&env->tr, &sregs.tr);
1911 get_seg(&env->ldt, &sregs.ldt);
1912
1913 env->idt.limit = sregs.idt.limit;
1914 env->idt.base = sregs.idt.base;
1915 env->gdt.limit = sregs.gdt.limit;
1916 env->gdt.base = sregs.gdt.base;
1917
1918 env->cr[0] = sregs.cr0;
1919 env->cr[2] = sregs.cr2;
1920 env->cr[3] = sregs.cr3;
1921 env->cr[4] = sregs.cr4;
1922
1923 env->efer = sregs.efer;
1924
1925 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1926
1927 #define HFLAG_COPY_MASK \
1928 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1929 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1930 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1931 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1932
1933 hflags = env->hflags & HFLAG_COPY_MASK;
1934 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1935 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1936 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1937 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1938 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1939
1940 if (env->cr[4] & CR4_OSFXSR_MASK) {
1941 hflags |= HF_OSFXSR_MASK;
1942 }
1943
1944 if (env->efer & MSR_EFER_LMA) {
1945 hflags |= HF_LMA_MASK;
1946 }
1947
1948 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1949 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1950 } else {
1951 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1952 (DESC_B_SHIFT - HF_CS32_SHIFT);
1953 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1954 (DESC_B_SHIFT - HF_SS32_SHIFT);
1955 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1956 !(hflags & HF_CS32_MASK)) {
1957 hflags |= HF_ADDSEG_MASK;
1958 } else {
1959 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1960 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1961 }
1962 }
1963 env->hflags = hflags;
1964
1965 return 0;
1966 }
1967
1968 static int kvm_get_msrs(X86CPU *cpu)
1969 {
1970 CPUX86State *env = &cpu->env;
1971 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1972 int ret, i;
1973
1974 kvm_msr_buf_reset(cpu);
1975
1976 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1977 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1978 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1979 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1980 if (has_msr_star) {
1981 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1982 }
1983 if (has_msr_hsave_pa) {
1984 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1985 }
1986 if (has_msr_tsc_aux) {
1987 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
1988 }
1989 if (has_msr_tsc_adjust) {
1990 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
1991 }
1992 if (has_msr_tsc_deadline) {
1993 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
1994 }
1995 if (has_msr_misc_enable) {
1996 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
1997 }
1998 if (has_msr_smbase) {
1999 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2000 }
2001 if (has_msr_feature_control) {
2002 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2003 }
2004 if (has_msr_bndcfgs) {
2005 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2006 }
2007 if (has_msr_xss) {
2008 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2009 }
2010
2011
2012 if (!env->tsc_valid) {
2013 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2014 env->tsc_valid = !runstate_is_running();
2015 }
2016
2017 #ifdef TARGET_X86_64
2018 if (lm_capable_kernel) {
2019 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2020 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2021 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2022 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2023 }
2024 #endif
2025 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2026 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2027 if (has_msr_async_pf_en) {
2028 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2029 }
2030 if (has_msr_pv_eoi_en) {
2031 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2032 }
2033 if (has_msr_kvm_steal_time) {
2034 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2035 }
2036 if (has_msr_architectural_pmu) {
2037 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2038 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2039 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2040 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2041 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2042 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2043 }
2044 for (i = 0; i < num_architectural_pmu_counters; i++) {
2045 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2046 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2047 }
2048 }
2049
2050 if (env->mcg_cap) {
2051 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2052 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2053 if (has_msr_mcg_ext_ctl) {
2054 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2055 }
2056 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2057 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2058 }
2059 }
2060
2061 if (has_msr_hv_hypercall) {
2062 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2063 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2064 }
2065 if (has_msr_hv_vapic) {
2066 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2067 }
2068 if (has_msr_hv_tsc) {
2069 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2070 }
2071 if (has_msr_hv_crash) {
2072 int j;
2073
2074 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2075 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2076 }
2077 }
2078 if (has_msr_hv_runtime) {
2079 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2080 }
2081 if (cpu->hyperv_synic) {
2082 uint32_t msr;
2083
2084 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2085 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2086 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2087 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2088 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2089 kvm_msr_entry_add(cpu, msr, 0);
2090 }
2091 }
2092 if (has_msr_hv_stimer) {
2093 uint32_t msr;
2094
2095 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2096 msr++) {
2097 kvm_msr_entry_add(cpu, msr, 0);
2098 }
2099 }
2100 if (has_msr_mtrr) {
2101 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2102 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2103 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2104 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2105 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2106 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2107 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2108 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2109 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2110 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2111 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2112 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2113 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2114 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2115 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2116 }
2117 }
2118
2119 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2120 if (ret < 0) {
2121 return ret;
2122 }
2123
2124 assert(ret == cpu->kvm_msr_buf->nmsrs);
2125 for (i = 0; i < ret; i++) {
2126 uint32_t index = msrs[i].index;
2127 switch (index) {
2128 case MSR_IA32_SYSENTER_CS:
2129 env->sysenter_cs = msrs[i].data;
2130 break;
2131 case MSR_IA32_SYSENTER_ESP:
2132 env->sysenter_esp = msrs[i].data;
2133 break;
2134 case MSR_IA32_SYSENTER_EIP:
2135 env->sysenter_eip = msrs[i].data;
2136 break;
2137 case MSR_PAT:
2138 env->pat = msrs[i].data;
2139 break;
2140 case MSR_STAR:
2141 env->star = msrs[i].data;
2142 break;
2143 #ifdef TARGET_X86_64
2144 case MSR_CSTAR:
2145 env->cstar = msrs[i].data;
2146 break;
2147 case MSR_KERNELGSBASE:
2148 env->kernelgsbase = msrs[i].data;
2149 break;
2150 case MSR_FMASK:
2151 env->fmask = msrs[i].data;
2152 break;
2153 case MSR_LSTAR:
2154 env->lstar = msrs[i].data;
2155 break;
2156 #endif
2157 case MSR_IA32_TSC:
2158 env->tsc = msrs[i].data;
2159 break;
2160 case MSR_TSC_AUX:
2161 env->tsc_aux = msrs[i].data;
2162 break;
2163 case MSR_TSC_ADJUST:
2164 env->tsc_adjust = msrs[i].data;
2165 break;
2166 case MSR_IA32_TSCDEADLINE:
2167 env->tsc_deadline = msrs[i].data;
2168 break;
2169 case MSR_VM_HSAVE_PA:
2170 env->vm_hsave = msrs[i].data;
2171 break;
2172 case MSR_KVM_SYSTEM_TIME:
2173 env->system_time_msr = msrs[i].data;
2174 break;
2175 case MSR_KVM_WALL_CLOCK:
2176 env->wall_clock_msr = msrs[i].data;
2177 break;
2178 case MSR_MCG_STATUS:
2179 env->mcg_status = msrs[i].data;
2180 break;
2181 case MSR_MCG_CTL:
2182 env->mcg_ctl = msrs[i].data;
2183 break;
2184 case MSR_MCG_EXT_CTL:
2185 env->mcg_ext_ctl = msrs[i].data;
2186 break;
2187 case MSR_IA32_MISC_ENABLE:
2188 env->msr_ia32_misc_enable = msrs[i].data;
2189 break;
2190 case MSR_IA32_SMBASE:
2191 env->smbase = msrs[i].data;
2192 break;
2193 case MSR_IA32_FEATURE_CONTROL:
2194 env->msr_ia32_feature_control = msrs[i].data;
2195 break;
2196 case MSR_IA32_BNDCFGS:
2197 env->msr_bndcfgs = msrs[i].data;
2198 break;
2199 case MSR_IA32_XSS:
2200 env->xss = msrs[i].data;
2201 break;
2202 default:
2203 if (msrs[i].index >= MSR_MC0_CTL &&
2204 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2205 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2206 }
2207 break;
2208 case MSR_KVM_ASYNC_PF_EN:
2209 env->async_pf_en_msr = msrs[i].data;
2210 break;
2211 case MSR_KVM_PV_EOI_EN:
2212 env->pv_eoi_en_msr = msrs[i].data;
2213 break;
2214 case MSR_KVM_STEAL_TIME:
2215 env->steal_time_msr = msrs[i].data;
2216 break;
2217 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2218 env->msr_fixed_ctr_ctrl = msrs[i].data;
2219 break;
2220 case MSR_CORE_PERF_GLOBAL_CTRL:
2221 env->msr_global_ctrl = msrs[i].data;
2222 break;
2223 case MSR_CORE_PERF_GLOBAL_STATUS:
2224 env->msr_global_status = msrs[i].data;
2225 break;
2226 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2227 env->msr_global_ovf_ctrl = msrs[i].data;
2228 break;
2229 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2230 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2231 break;
2232 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2233 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2234 break;
2235 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2236 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2237 break;
2238 case HV_X64_MSR_HYPERCALL:
2239 env->msr_hv_hypercall = msrs[i].data;
2240 break;
2241 case HV_X64_MSR_GUEST_OS_ID:
2242 env->msr_hv_guest_os_id = msrs[i].data;
2243 break;
2244 case HV_X64_MSR_APIC_ASSIST_PAGE:
2245 env->msr_hv_vapic = msrs[i].data;
2246 break;
2247 case HV_X64_MSR_REFERENCE_TSC:
2248 env->msr_hv_tsc = msrs[i].data;
2249 break;
2250 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2251 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2252 break;
2253 case HV_X64_MSR_VP_RUNTIME:
2254 env->msr_hv_runtime = msrs[i].data;
2255 break;
2256 case HV_X64_MSR_SCONTROL:
2257 env->msr_hv_synic_control = msrs[i].data;
2258 break;
2259 case HV_X64_MSR_SVERSION:
2260 env->msr_hv_synic_version = msrs[i].data;
2261 break;
2262 case HV_X64_MSR_SIEFP:
2263 env->msr_hv_synic_evt_page = msrs[i].data;
2264 break;
2265 case HV_X64_MSR_SIMP:
2266 env->msr_hv_synic_msg_page = msrs[i].data;
2267 break;
2268 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2269 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2270 break;
2271 case HV_X64_MSR_STIMER0_CONFIG:
2272 case HV_X64_MSR_STIMER1_CONFIG:
2273 case HV_X64_MSR_STIMER2_CONFIG:
2274 case HV_X64_MSR_STIMER3_CONFIG:
2275 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2276 msrs[i].data;
2277 break;
2278 case HV_X64_MSR_STIMER0_COUNT:
2279 case HV_X64_MSR_STIMER1_COUNT:
2280 case HV_X64_MSR_STIMER2_COUNT:
2281 case HV_X64_MSR_STIMER3_COUNT:
2282 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2283 msrs[i].data;
2284 break;
2285 case MSR_MTRRdefType:
2286 env->mtrr_deftype = msrs[i].data;
2287 break;
2288 case MSR_MTRRfix64K_00000:
2289 env->mtrr_fixed[0] = msrs[i].data;
2290 break;
2291 case MSR_MTRRfix16K_80000:
2292 env->mtrr_fixed[1] = msrs[i].data;
2293 break;
2294 case MSR_MTRRfix16K_A0000:
2295 env->mtrr_fixed[2] = msrs[i].data;
2296 break;
2297 case MSR_MTRRfix4K_C0000:
2298 env->mtrr_fixed[3] = msrs[i].data;
2299 break;
2300 case MSR_MTRRfix4K_C8000:
2301 env->mtrr_fixed[4] = msrs[i].data;
2302 break;
2303 case MSR_MTRRfix4K_D0000:
2304 env->mtrr_fixed[5] = msrs[i].data;
2305 break;
2306 case MSR_MTRRfix4K_D8000:
2307 env->mtrr_fixed[6] = msrs[i].data;
2308 break;
2309 case MSR_MTRRfix4K_E0000:
2310 env->mtrr_fixed[7] = msrs[i].data;
2311 break;
2312 case MSR_MTRRfix4K_E8000:
2313 env->mtrr_fixed[8] = msrs[i].data;
2314 break;
2315 case MSR_MTRRfix4K_F0000:
2316 env->mtrr_fixed[9] = msrs[i].data;
2317 break;
2318 case MSR_MTRRfix4K_F8000:
2319 env->mtrr_fixed[10] = msrs[i].data;
2320 break;
2321 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2322 if (index & 1) {
2323 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2324 } else {
2325 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2326 }
2327 break;
2328 }
2329 }
2330
2331 return 0;
2332 }
2333
2334 static int kvm_put_mp_state(X86CPU *cpu)
2335 {
2336 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2337
2338 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2339 }
2340
2341 static int kvm_get_mp_state(X86CPU *cpu)
2342 {
2343 CPUState *cs = CPU(cpu);
2344 CPUX86State *env = &cpu->env;
2345 struct kvm_mp_state mp_state;
2346 int ret;
2347
2348 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2349 if (ret < 0) {
2350 return ret;
2351 }
2352 env->mp_state = mp_state.mp_state;
2353 if (kvm_irqchip_in_kernel()) {
2354 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2355 }
2356 return 0;
2357 }
2358
2359 static int kvm_get_apic(X86CPU *cpu)
2360 {
2361 DeviceState *apic = cpu->apic_state;
2362 struct kvm_lapic_state kapic;
2363 int ret;
2364
2365 if (apic && kvm_irqchip_in_kernel()) {
2366 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2367 if (ret < 0) {
2368 return ret;
2369 }
2370
2371 kvm_get_apic_state(apic, &kapic);
2372 }
2373 return 0;
2374 }
2375
2376 static int kvm_put_apic(X86CPU *cpu)
2377 {
2378 DeviceState *apic = cpu->apic_state;
2379 struct kvm_lapic_state kapic;
2380
2381 if (apic && kvm_irqchip_in_kernel()) {
2382 kvm_put_apic_state(apic, &kapic);
2383
2384 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2385 }
2386 return 0;
2387 }
2388
2389 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2390 {
2391 CPUState *cs = CPU(cpu);
2392 CPUX86State *env = &cpu->env;
2393 struct kvm_vcpu_events events = {};
2394
2395 if (!kvm_has_vcpu_events()) {
2396 return 0;
2397 }
2398
2399 events.exception.injected = (env->exception_injected >= 0);
2400 events.exception.nr = env->exception_injected;
2401 events.exception.has_error_code = env->has_error_code;
2402 events.exception.error_code = env->error_code;
2403 events.exception.pad = 0;
2404
2405 events.interrupt.injected = (env->interrupt_injected >= 0);
2406 events.interrupt.nr = env->interrupt_injected;
2407 events.interrupt.soft = env->soft_interrupt;
2408
2409 events.nmi.injected = env->nmi_injected;
2410 events.nmi.pending = env->nmi_pending;
2411 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2412 events.nmi.pad = 0;
2413
2414 events.sipi_vector = env->sipi_vector;
2415
2416 if (has_msr_smbase) {
2417 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2418 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2419 if (kvm_irqchip_in_kernel()) {
2420 /* As soon as these are moved to the kernel, remove them
2421 * from cs->interrupt_request.
2422 */
2423 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2424 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2425 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2426 } else {
2427 /* Keep these in cs->interrupt_request. */
2428 events.smi.pending = 0;
2429 events.smi.latched_init = 0;
2430 }
2431 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2432 }
2433
2434 events.flags = 0;
2435 if (level >= KVM_PUT_RESET_STATE) {
2436 events.flags |=
2437 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2438 }
2439
2440 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2441 }
2442
2443 static int kvm_get_vcpu_events(X86CPU *cpu)
2444 {
2445 CPUX86State *env = &cpu->env;
2446 struct kvm_vcpu_events events;
2447 int ret;
2448
2449 if (!kvm_has_vcpu_events()) {
2450 return 0;
2451 }
2452
2453 memset(&events, 0, sizeof(events));
2454 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2455 if (ret < 0) {
2456 return ret;
2457 }
2458 env->exception_injected =
2459 events.exception.injected ? events.exception.nr : -1;
2460 env->has_error_code = events.exception.has_error_code;
2461 env->error_code = events.exception.error_code;
2462
2463 env->interrupt_injected =
2464 events.interrupt.injected ? events.interrupt.nr : -1;
2465 env->soft_interrupt = events.interrupt.soft;
2466
2467 env->nmi_injected = events.nmi.injected;
2468 env->nmi_pending = events.nmi.pending;
2469 if (events.nmi.masked) {
2470 env->hflags2 |= HF2_NMI_MASK;
2471 } else {
2472 env->hflags2 &= ~HF2_NMI_MASK;
2473 }
2474
2475 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2476 if (events.smi.smm) {
2477 env->hflags |= HF_SMM_MASK;
2478 } else {
2479 env->hflags &= ~HF_SMM_MASK;
2480 }
2481 if (events.smi.pending) {
2482 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2483 } else {
2484 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2485 }
2486 if (events.smi.smm_inside_nmi) {
2487 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2488 } else {
2489 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2490 }
2491 if (events.smi.latched_init) {
2492 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2493 } else {
2494 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2495 }
2496 }
2497
2498 env->sipi_vector = events.sipi_vector;
2499
2500 return 0;
2501 }
2502
2503 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2504 {
2505 CPUState *cs = CPU(cpu);
2506 CPUX86State *env = &cpu->env;
2507 int ret = 0;
2508 unsigned long reinject_trap = 0;
2509
2510 if (!kvm_has_vcpu_events()) {
2511 if (env->exception_injected == 1) {
2512 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2513 } else if (env->exception_injected == 3) {
2514 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2515 }
2516 env->exception_injected = -1;
2517 }
2518
2519 /*
2520 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2521 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2522 * by updating the debug state once again if single-stepping is on.
2523 * Another reason to call kvm_update_guest_debug here is a pending debug
2524 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2525 * reinject them via SET_GUEST_DEBUG.
2526 */
2527 if (reinject_trap ||
2528 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2529 ret = kvm_update_guest_debug(cs, reinject_trap);
2530 }
2531 return ret;
2532 }
2533
2534 static int kvm_put_debugregs(X86CPU *cpu)
2535 {
2536 CPUX86State *env = &cpu->env;
2537 struct kvm_debugregs dbgregs;
2538 int i;
2539
2540 if (!kvm_has_debugregs()) {
2541 return 0;
2542 }
2543
2544 for (i = 0; i < 4; i++) {
2545 dbgregs.db[i] = env->dr[i];
2546 }
2547 dbgregs.dr6 = env->dr[6];
2548 dbgregs.dr7 = env->dr[7];
2549 dbgregs.flags = 0;
2550
2551 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2552 }
2553
2554 static int kvm_get_debugregs(X86CPU *cpu)
2555 {
2556 CPUX86State *env = &cpu->env;
2557 struct kvm_debugregs dbgregs;
2558 int i, ret;
2559
2560 if (!kvm_has_debugregs()) {
2561 return 0;
2562 }
2563
2564 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2565 if (ret < 0) {
2566 return ret;
2567 }
2568 for (i = 0; i < 4; i++) {
2569 env->dr[i] = dbgregs.db[i];
2570 }
2571 env->dr[4] = env->dr[6] = dbgregs.dr6;
2572 env->dr[5] = env->dr[7] = dbgregs.dr7;
2573
2574 return 0;
2575 }
2576
2577 int kvm_arch_put_registers(CPUState *cpu, int level)
2578 {
2579 X86CPU *x86_cpu = X86_CPU(cpu);
2580 int ret;
2581
2582 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2583
2584 if (level >= KVM_PUT_RESET_STATE) {
2585 ret = kvm_put_msr_feature_control(x86_cpu);
2586 if (ret < 0) {
2587 return ret;
2588 }
2589 }
2590
2591 if (level == KVM_PUT_FULL_STATE) {
2592 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2593 * because TSC frequency mismatch shouldn't abort migration,
2594 * unless the user explicitly asked for a more strict TSC
2595 * setting (e.g. using an explicit "tsc-freq" option).
2596 */
2597 kvm_arch_set_tsc_khz(cpu);
2598 }
2599
2600 ret = kvm_getput_regs(x86_cpu, 1);
2601 if (ret < 0) {
2602 return ret;
2603 }
2604 ret = kvm_put_xsave(x86_cpu);
2605 if (ret < 0) {
2606 return ret;
2607 }
2608 ret = kvm_put_xcrs(x86_cpu);
2609 if (ret < 0) {
2610 return ret;
2611 }
2612 ret = kvm_put_sregs(x86_cpu);
2613 if (ret < 0) {
2614 return ret;
2615 }
2616 /* must be before kvm_put_msrs */
2617 ret = kvm_inject_mce_oldstyle(x86_cpu);
2618 if (ret < 0) {
2619 return ret;
2620 }
2621 ret = kvm_put_msrs(x86_cpu, level);
2622 if (ret < 0) {
2623 return ret;
2624 }
2625 if (level >= KVM_PUT_RESET_STATE) {
2626 ret = kvm_put_mp_state(x86_cpu);
2627 if (ret < 0) {
2628 return ret;
2629 }
2630 ret = kvm_put_apic(x86_cpu);
2631 if (ret < 0) {
2632 return ret;
2633 }
2634 }
2635
2636 ret = kvm_put_tscdeadline_msr(x86_cpu);
2637 if (ret < 0) {
2638 return ret;
2639 }
2640
2641 ret = kvm_put_vcpu_events(x86_cpu, level);
2642 if (ret < 0) {
2643 return ret;
2644 }
2645 ret = kvm_put_debugregs(x86_cpu);
2646 if (ret < 0) {
2647 return ret;
2648 }
2649 /* must be last */
2650 ret = kvm_guest_debug_workarounds(x86_cpu);
2651 if (ret < 0) {
2652 return ret;
2653 }
2654 return 0;
2655 }
2656
2657 int kvm_arch_get_registers(CPUState *cs)
2658 {
2659 X86CPU *cpu = X86_CPU(cs);
2660 int ret;
2661
2662 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2663
2664 ret = kvm_getput_regs(cpu, 0);
2665 if (ret < 0) {
2666 goto out;
2667 }
2668 ret = kvm_get_xsave(cpu);
2669 if (ret < 0) {
2670 goto out;
2671 }
2672 ret = kvm_get_xcrs(cpu);
2673 if (ret < 0) {
2674 goto out;
2675 }
2676 ret = kvm_get_sregs(cpu);
2677 if (ret < 0) {
2678 goto out;
2679 }
2680 ret = kvm_get_msrs(cpu);
2681 if (ret < 0) {
2682 goto out;
2683 }
2684 ret = kvm_get_mp_state(cpu);
2685 if (ret < 0) {
2686 goto out;
2687 }
2688 ret = kvm_get_apic(cpu);
2689 if (ret < 0) {
2690 goto out;
2691 }
2692 ret = kvm_get_vcpu_events(cpu);
2693 if (ret < 0) {
2694 goto out;
2695 }
2696 ret = kvm_get_debugregs(cpu);
2697 if (ret < 0) {
2698 goto out;
2699 }
2700 ret = 0;
2701 out:
2702 cpu_sync_bndcs_hflags(&cpu->env);
2703 return ret;
2704 }
2705
2706 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2707 {
2708 X86CPU *x86_cpu = X86_CPU(cpu);
2709 CPUX86State *env = &x86_cpu->env;
2710 int ret;
2711
2712 /* Inject NMI */
2713 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2714 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2715 qemu_mutex_lock_iothread();
2716 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2717 qemu_mutex_unlock_iothread();
2718 DPRINTF("injected NMI\n");
2719 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2720 if (ret < 0) {
2721 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2722 strerror(-ret));
2723 }
2724 }
2725 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2726 qemu_mutex_lock_iothread();
2727 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2728 qemu_mutex_unlock_iothread();
2729 DPRINTF("injected SMI\n");
2730 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2731 if (ret < 0) {
2732 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2733 strerror(-ret));
2734 }
2735 }
2736 }
2737
2738 if (!kvm_pic_in_kernel()) {
2739 qemu_mutex_lock_iothread();
2740 }
2741
2742 /* Force the VCPU out of its inner loop to process any INIT requests
2743 * or (for userspace APIC, but it is cheap to combine the checks here)
2744 * pending TPR access reports.
2745 */
2746 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2747 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2748 !(env->hflags & HF_SMM_MASK)) {
2749 cpu->exit_request = 1;
2750 }
2751 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2752 cpu->exit_request = 1;
2753 }
2754 }
2755
2756 if (!kvm_pic_in_kernel()) {
2757 /* Try to inject an interrupt if the guest can accept it */
2758 if (run->ready_for_interrupt_injection &&
2759 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2760 (env->eflags & IF_MASK)) {
2761 int irq;
2762
2763 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2764 irq = cpu_get_pic_interrupt(env);
2765 if (irq >= 0) {
2766 struct kvm_interrupt intr;
2767
2768 intr.irq = irq;
2769 DPRINTF("injected interrupt %d\n", irq);
2770 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2771 if (ret < 0) {
2772 fprintf(stderr,
2773 "KVM: injection failed, interrupt lost (%s)\n",
2774 strerror(-ret));
2775 }
2776 }
2777 }
2778
2779 /* If we have an interrupt but the guest is not ready to receive an
2780 * interrupt, request an interrupt window exit. This will
2781 * cause a return to userspace as soon as the guest is ready to
2782 * receive interrupts. */
2783 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2784 run->request_interrupt_window = 1;
2785 } else {
2786 run->request_interrupt_window = 0;
2787 }
2788
2789 DPRINTF("setting tpr\n");
2790 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2791
2792 qemu_mutex_unlock_iothread();
2793 }
2794 }
2795
2796 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2797 {
2798 X86CPU *x86_cpu = X86_CPU(cpu);
2799 CPUX86State *env = &x86_cpu->env;
2800
2801 if (run->flags & KVM_RUN_X86_SMM) {
2802 env->hflags |= HF_SMM_MASK;
2803 } else {
2804 env->hflags &= HF_SMM_MASK;
2805 }
2806 if (run->if_flag) {
2807 env->eflags |= IF_MASK;
2808 } else {
2809 env->eflags &= ~IF_MASK;
2810 }
2811
2812 /* We need to protect the apic state against concurrent accesses from
2813 * different threads in case the userspace irqchip is used. */
2814 if (!kvm_irqchip_in_kernel()) {
2815 qemu_mutex_lock_iothread();
2816 }
2817 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2818 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2819 if (!kvm_irqchip_in_kernel()) {
2820 qemu_mutex_unlock_iothread();
2821 }
2822 return cpu_get_mem_attrs(env);
2823 }
2824
2825 int kvm_arch_process_async_events(CPUState *cs)
2826 {
2827 X86CPU *cpu = X86_CPU(cs);
2828 CPUX86State *env = &cpu->env;
2829
2830 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2831 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2832 assert(env->mcg_cap);
2833
2834 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2835
2836 kvm_cpu_synchronize_state(cs);
2837
2838 if (env->exception_injected == EXCP08_DBLE) {
2839 /* this means triple fault */
2840 qemu_system_reset_request();
2841 cs->exit_request = 1;
2842 return 0;
2843 }
2844 env->exception_injected = EXCP12_MCHK;
2845 env->has_error_code = 0;
2846
2847 cs->halted = 0;
2848 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2849 env->mp_state = KVM_MP_STATE_RUNNABLE;
2850 }
2851 }
2852
2853 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2854 !(env->hflags & HF_SMM_MASK)) {
2855 kvm_cpu_synchronize_state(cs);
2856 do_cpu_init(cpu);
2857 }
2858
2859 if (kvm_irqchip_in_kernel()) {
2860 return 0;
2861 }
2862
2863 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2864 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2865 apic_poll_irq(cpu->apic_state);
2866 }
2867 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2868 (env->eflags & IF_MASK)) ||
2869 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2870 cs->halted = 0;
2871 }
2872 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2873 kvm_cpu_synchronize_state(cs);
2874 do_cpu_sipi(cpu);
2875 }
2876 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2877 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2878 kvm_cpu_synchronize_state(cs);
2879 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2880 env->tpr_access_type);
2881 }
2882
2883 return cs->halted;
2884 }
2885
2886 static int kvm_handle_halt(X86CPU *cpu)
2887 {
2888 CPUState *cs = CPU(cpu);
2889 CPUX86State *env = &cpu->env;
2890
2891 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2892 (env->eflags & IF_MASK)) &&
2893 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2894 cs->halted = 1;
2895 return EXCP_HLT;
2896 }
2897
2898 return 0;
2899 }
2900
2901 static int kvm_handle_tpr_access(X86CPU *cpu)
2902 {
2903 CPUState *cs = CPU(cpu);
2904 struct kvm_run *run = cs->kvm_run;
2905
2906 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2907 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2908 : TPR_ACCESS_READ);
2909 return 1;
2910 }
2911
2912 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2913 {
2914 static const uint8_t int3 = 0xcc;
2915
2916 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2917 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2918 return -EINVAL;
2919 }
2920 return 0;
2921 }
2922
2923 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2924 {
2925 uint8_t int3;
2926
2927 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2928 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2929 return -EINVAL;
2930 }
2931 return 0;
2932 }
2933
2934 static struct {
2935 target_ulong addr;
2936 int len;
2937 int type;
2938 } hw_breakpoint[4];
2939
2940 static int nb_hw_breakpoint;
2941
2942 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2943 {
2944 int n;
2945
2946 for (n = 0; n < nb_hw_breakpoint; n++) {
2947 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2948 (hw_breakpoint[n].len == len || len == -1)) {
2949 return n;
2950 }
2951 }
2952 return -1;
2953 }
2954
2955 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2956 target_ulong len, int type)
2957 {
2958 switch (type) {
2959 case GDB_BREAKPOINT_HW:
2960 len = 1;
2961 break;
2962 case GDB_WATCHPOINT_WRITE:
2963 case GDB_WATCHPOINT_ACCESS:
2964 switch (len) {
2965 case 1:
2966 break;
2967 case 2:
2968 case 4:
2969 case 8:
2970 if (addr & (len - 1)) {
2971 return -EINVAL;
2972 }
2973 break;
2974 default:
2975 return -EINVAL;
2976 }
2977 break;
2978 default:
2979 return -ENOSYS;
2980 }
2981
2982 if (nb_hw_breakpoint == 4) {
2983 return -ENOBUFS;
2984 }
2985 if (find_hw_breakpoint(addr, len, type) >= 0) {
2986 return -EEXIST;
2987 }
2988 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2989 hw_breakpoint[nb_hw_breakpoint].len = len;
2990 hw_breakpoint[nb_hw_breakpoint].type = type;
2991 nb_hw_breakpoint++;
2992
2993 return 0;
2994 }
2995
2996 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2997 target_ulong len, int type)
2998 {
2999 int n;
3000
3001 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3002 if (n < 0) {
3003 return -ENOENT;
3004 }
3005 nb_hw_breakpoint--;
3006 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3007
3008 return 0;
3009 }
3010
3011 void kvm_arch_remove_all_hw_breakpoints(void)
3012 {
3013 nb_hw_breakpoint = 0;
3014 }
3015
3016 static CPUWatchpoint hw_watchpoint;
3017
3018 static int kvm_handle_debug(X86CPU *cpu,
3019 struct kvm_debug_exit_arch *arch_info)
3020 {
3021 CPUState *cs = CPU(cpu);
3022 CPUX86State *env = &cpu->env;
3023 int ret = 0;
3024 int n;
3025
3026 if (arch_info->exception == 1) {
3027 if (arch_info->dr6 & (1 << 14)) {
3028 if (cs->singlestep_enabled) {
3029 ret = EXCP_DEBUG;
3030 }
3031 } else {
3032 for (n = 0; n < 4; n++) {
3033 if (arch_info->dr6 & (1 << n)) {
3034 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3035 case 0x0:
3036 ret = EXCP_DEBUG;
3037 break;
3038 case 0x1:
3039 ret = EXCP_DEBUG;
3040 cs->watchpoint_hit = &hw_watchpoint;
3041 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3042 hw_watchpoint.flags = BP_MEM_WRITE;
3043 break;
3044 case 0x3:
3045 ret = EXCP_DEBUG;
3046 cs->watchpoint_hit = &hw_watchpoint;
3047 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3048 hw_watchpoint.flags = BP_MEM_ACCESS;
3049 break;
3050 }
3051 }
3052 }
3053 }
3054 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3055 ret = EXCP_DEBUG;
3056 }
3057 if (ret == 0) {
3058 cpu_synchronize_state(cs);
3059 assert(env->exception_injected == -1);
3060
3061 /* pass to guest */
3062 env->exception_injected = arch_info->exception;
3063 env->has_error_code = 0;
3064 }
3065
3066 return ret;
3067 }
3068
3069 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3070 {
3071 const uint8_t type_code[] = {
3072 [GDB_BREAKPOINT_HW] = 0x0,
3073 [GDB_WATCHPOINT_WRITE] = 0x1,
3074 [GDB_WATCHPOINT_ACCESS] = 0x3
3075 };
3076 const uint8_t len_code[] = {
3077 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3078 };
3079 int n;
3080
3081 if (kvm_sw_breakpoints_active(cpu)) {
3082 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3083 }
3084 if (nb_hw_breakpoint > 0) {
3085 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3086 dbg->arch.debugreg[7] = 0x0600;
3087 for (n = 0; n < nb_hw_breakpoint; n++) {
3088 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3089 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3090 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3091 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3092 }
3093 }
3094 }
3095
3096 static bool host_supports_vmx(void)
3097 {
3098 uint32_t ecx, unused;
3099
3100 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3101 return ecx & CPUID_EXT_VMX;
3102 }
3103
3104 #define VMX_INVALID_GUEST_STATE 0x80000021
3105
3106 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3107 {
3108 X86CPU *cpu = X86_CPU(cs);
3109 uint64_t code;
3110 int ret;
3111
3112 switch (run->exit_reason) {
3113 case KVM_EXIT_HLT:
3114 DPRINTF("handle_hlt\n");
3115 qemu_mutex_lock_iothread();
3116 ret = kvm_handle_halt(cpu);
3117 qemu_mutex_unlock_iothread();
3118 break;
3119 case KVM_EXIT_SET_TPR:
3120 ret = 0;
3121 break;
3122 case KVM_EXIT_TPR_ACCESS:
3123 qemu_mutex_lock_iothread();
3124 ret = kvm_handle_tpr_access(cpu);
3125 qemu_mutex_unlock_iothread();
3126 break;
3127 case KVM_EXIT_FAIL_ENTRY:
3128 code = run->fail_entry.hardware_entry_failure_reason;
3129 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3130 code);
3131 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3132 fprintf(stderr,
3133 "\nIf you're running a guest on an Intel machine without "
3134 "unrestricted mode\n"
3135 "support, the failure can be most likely due to the guest "
3136 "entering an invalid\n"
3137 "state for Intel VT. For example, the guest maybe running "
3138 "in big real mode\n"
3139 "which is not supported on less recent Intel processors."
3140 "\n\n");
3141 }
3142 ret = -1;
3143 break;
3144 case KVM_EXIT_EXCEPTION:
3145 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3146 run->ex.exception, run->ex.error_code);
3147 ret = -1;
3148 break;
3149 case KVM_EXIT_DEBUG:
3150 DPRINTF("kvm_exit_debug\n");
3151 qemu_mutex_lock_iothread();
3152 ret = kvm_handle_debug(cpu, &run->debug.arch);
3153 qemu_mutex_unlock_iothread();
3154 break;
3155 case KVM_EXIT_HYPERV:
3156 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3157 break;
3158 case KVM_EXIT_IOAPIC_EOI:
3159 ioapic_eoi_broadcast(run->eoi.vector);
3160 ret = 0;
3161 break;
3162 default:
3163 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3164 ret = -1;
3165 break;
3166 }
3167
3168 return ret;
3169 }
3170
3171 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3172 {
3173 X86CPU *cpu = X86_CPU(cs);
3174 CPUX86State *env = &cpu->env;
3175
3176 kvm_cpu_synchronize_state(cs);
3177 return !(env->cr[0] & CR0_PE_MASK) ||
3178 ((env->segs[R_CS].selector & 3) != 3);
3179 }
3180
3181 void kvm_arch_init_irq_routing(KVMState *s)
3182 {
3183 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3184 /* If kernel can't do irq routing, interrupt source
3185 * override 0->2 cannot be set up as required by HPET.
3186 * So we have to disable it.
3187 */
3188 no_hpet = 1;
3189 }
3190 /* We know at this point that we're using the in-kernel
3191 * irqchip, so we can use irqfds, and on x86 we know
3192 * we can use msi via irqfd and GSI routing.
3193 */
3194 kvm_msi_via_irqfd_allowed = true;
3195 kvm_gsi_routing_allowed = true;
3196
3197 if (kvm_irqchip_is_split()) {
3198 int i;
3199
3200 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3201 MSI routes for signaling interrupts to the local apics. */
3202 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3203 struct MSIMessage msg = { 0x0, 0x0 };
3204 if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) {
3205 error_report("Could not enable split IRQ mode.");
3206 exit(1);
3207 }
3208 }
3209 }
3210 }
3211
3212 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3213 {
3214 int ret;
3215 if (machine_kernel_irqchip_split(ms)) {
3216 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3217 if (ret) {
3218 error_report("Could not enable split irqchip mode: %s\n",
3219 strerror(-ret));
3220 exit(1);
3221 } else {
3222 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3223 kvm_split_irqchip = true;
3224 return 1;
3225 }
3226 } else {
3227 return 0;
3228 }
3229 }
3230
3231 /* Classic KVM device assignment interface. Will remain x86 only. */
3232 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3233 uint32_t flags, uint32_t *dev_id)
3234 {
3235 struct kvm_assigned_pci_dev dev_data = {
3236 .segnr = dev_addr->domain,
3237 .busnr = dev_addr->bus,
3238 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3239 .flags = flags,
3240 };
3241 int ret;
3242
3243 dev_data.assigned_dev_id =
3244 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3245
3246 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3247 if (ret < 0) {
3248 return ret;
3249 }
3250
3251 *dev_id = dev_data.assigned_dev_id;
3252
3253 return 0;
3254 }
3255
3256 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3257 {
3258 struct kvm_assigned_pci_dev dev_data = {
3259 .assigned_dev_id = dev_id,
3260 };
3261
3262 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3263 }
3264
3265 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3266 uint32_t irq_type, uint32_t guest_irq)
3267 {
3268 struct kvm_assigned_irq assigned_irq = {
3269 .assigned_dev_id = dev_id,
3270 .guest_irq = guest_irq,
3271 .flags = irq_type,
3272 };
3273
3274 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3275 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3276 } else {
3277 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3278 }
3279 }
3280
3281 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3282 uint32_t guest_irq)
3283 {
3284 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3285 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3286
3287 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3288 }
3289
3290 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3291 {
3292 struct kvm_assigned_pci_dev dev_data = {
3293 .assigned_dev_id = dev_id,
3294 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3295 };
3296
3297 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3298 }
3299
3300 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3301 uint32_t type)
3302 {
3303 struct kvm_assigned_irq assigned_irq = {
3304 .assigned_dev_id = dev_id,
3305 .flags = type,
3306 };
3307
3308 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3309 }
3310
3311 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3312 {
3313 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3314 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3315 }
3316
3317 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3318 {
3319 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3320 KVM_DEV_IRQ_GUEST_MSI, virq);
3321 }
3322
3323 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3324 {
3325 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3326 KVM_DEV_IRQ_HOST_MSI);
3327 }
3328
3329 bool kvm_device_msix_supported(KVMState *s)
3330 {
3331 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3332 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3333 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3334 }
3335
3336 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3337 uint32_t nr_vectors)
3338 {
3339 struct kvm_assigned_msix_nr msix_nr = {
3340 .assigned_dev_id = dev_id,
3341 .entry_nr = nr_vectors,
3342 };
3343
3344 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3345 }
3346
3347 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3348 int virq)
3349 {
3350 struct kvm_assigned_msix_entry msix_entry = {
3351 .assigned_dev_id = dev_id,
3352 .gsi = virq,
3353 .entry = vector,
3354 };
3355
3356 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3357 }
3358
3359 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3360 {
3361 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3362 KVM_DEV_IRQ_GUEST_MSIX, 0);
3363 }
3364
3365 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3366 {
3367 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3368 KVM_DEV_IRQ_HOST_MSIX);
3369 }
3370
3371 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3372 uint64_t address, uint32_t data, PCIDevice *dev)
3373 {
3374 return 0;
3375 }
3376
3377 int kvm_arch_msi_data_to_gsi(uint32_t data)
3378 {
3379 abort();
3380 }
AR7 emulation for QEMU