2 * QEMU i8255x (PRO100) emulation
4 * Copyright (c) 2006-2007 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 * Tested features (i82559):
24 * PXE boot (i386) no valid link
25 * Linux networking (i386) ok
33 * Intel 8255x 10/100 Mbps Ethernet Controller Family
34 * Open Source Software Developer Manual
37 #if defined(TARGET_I386)
38 # warning "PXE boot still not working!"
41 #include <stddef.h> /* offsetof */
45 #include "eeprom93xx.h"
47 /* Common declarations for all PCI devices. */
49 #define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51 #define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53 #define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
58 /* debug EEPRO100 card */
59 //~ #define DEBUG_EEPRO100
62 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
64 #define logout(fmt, ...) ((void)0)
67 /* Set flags to 0 to disable debug output. */
70 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
72 #define missing(text) assert(!"feature is missing in this emulation: " text)
74 #define MAX_ETH_FRAME_SIZE 1514
76 /* This driver supports several different devices which are declared here. */
77 #define i82551 0x82551
78 #define i82557B 0x82557b
79 #define i82557C 0x82557c
80 #define i82558B 0x82558b
81 #define i82559C 0x82559c
82 #define i82559ER 0x82559e
83 #define i82562 0x82562
85 #define EEPROM_SIZE 64
87 #define PCI_MEM_SIZE (4 * KiB)
88 #define PCI_IO_SIZE 64
89 #define PCI_FLASH_SIZE (128 * KiB)
91 #define BIT(n) (1 << (n))
92 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
94 /* The SCB accepts the following controls for the Tx and Rx units: */
95 #define CU_NOP 0x0000 /* No operation. */
96 #define CU_START 0x0010 /* CU start. */
97 #define CU_RESUME 0x0020 /* CU resume. */
98 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
99 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
100 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
101 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
102 #define CU_SRESUME 0x00a0 /* CU static resume. */
104 #define RU_NOP 0x0000
105 #define RX_START 0x0001
106 #define RX_RESUME 0x0002
107 #define RX_ABORT 0x0004
108 #define RX_ADDR_LOAD 0x0006
109 #define RX_RESUMENR 0x0007
110 #define INT_MASK 0x0100
111 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
113 typedef unsigned char bool;
115 /* Offsets to the various registers.
116 All accesses need not be longword aligned. */
117 enum speedo_offsets
{
120 SCBCmd
= 2, /* Rx/Command Unit command and status. */
122 SCBPointer
= 4, /* General purpose pointer. */
123 SCBPort
= 8, /* Misc. commands and operands. */
124 SCBflash
= 12, SCBeeprom
= 14, /* EEPROM and flash memory control. */
125 SCBCtrlMDI
= 16, /* MDI interface control. */
126 SCBEarlyRx
= 20, /* Early receive byte count. */
130 /* A speedo3 transmit buffer descriptor with two buffers... */
134 uint32_t link
; /* void * */
135 uint32_t tx_desc_addr
; /* transmit buffer decsriptor array address. */
136 uint16_t tcb_bytes
; /* transmit command block byte count (in lower 14 bits */
137 uint8_t tx_threshold
; /* transmit threshold */
138 uint8_t tbd_count
; /* TBD number */
139 //~ /* This constitutes two "TBD" entries: hdr and data */
140 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
141 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
142 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
143 //~ int32_t tx_buf_size1; /* Length of Tx data. */
146 /* Receive frame descriptor. */
150 uint32_t link
; /* struct RxFD * */
151 uint32_t rx_buf_addr
; /* void * */
154 char packet
[MAX_ETH_FRAME_SIZE
+ 4];
158 uint32_t tx_good_frames
, tx_max_collisions
, tx_late_collisions
,
159 tx_underruns
, tx_lost_crs
, tx_deferred
, tx_single_collisions
,
160 tx_multiple_collisions
, tx_total_collisions
;
161 uint32_t rx_good_frames
, rx_crc_errors
, rx_alignment_errors
,
162 rx_resource_errors
, rx_overrun_errors
, rx_cdt_errors
,
163 rx_short_frame_errors
;
164 uint32_t fc_xmt_pause
, fc_rcv_pause
, fc_rcv_unsupported
;
165 uint16_t xmt_tco_frames
, rcv_tco_frames
;
200 uint8_t phys
[6]; /* mac address */
202 uint8_t mult
[8]; /* multicast mask array */
207 uint8_t scb_stat
; /* SCB stat/ack byte */
208 uint8_t int_stat
; /* PCI interrupt status */
209 uint32_t region
[3]; /* PCI region addresses */
211 uint32_t statcounter
[19];
214 uint32_t device
; /* device variant */
216 /* (cu_base + cu_offset) address the next command block in the command block list. */
217 uint32_t cu_base
; /* CU base address */
218 uint32_t cu_offset
; /* CU address offset */
219 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
220 uint32_t ru_base
; /* RU base address */
221 uint32_t ru_offset
; /* RU address offset */
222 uint32_t statsaddr
; /* pointer to eepro100_stats_t */
223 eepro100_stats_t statistics
; /* statistical counters */
228 /* Configuration bytes. */
229 uint8_t configuration
[22];
231 /* Data in mem is always in the byte order of the controller (le). */
232 uint8_t mem
[PCI_MEM_SIZE
];
235 /* Default values for MDI (PHY) registers */
236 static const uint16_t eepro100_mdi_default
[] = {
237 /* MDI Registers 0 - 6, 7 */
238 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
239 /* MDI Registers 8 - 15 */
240 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
241 /* MDI Registers 16 - 31 */
242 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
243 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
246 /* Readonly mask for MDI (PHY) registers */
247 static const uint16_t eepro100_mdi_mask
[] = {
248 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
249 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
250 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
251 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
254 #define POLYNOMIAL 0x04c11db6
258 static int compute_mcast_idx(const uint8_t * ep
)
265 for (i
= 0; i
< 6; i
++) {
267 for (j
= 0; j
< 8; j
++) {
268 carry
= ((crc
& 0x80000000L
) ? 1 : 0) ^ (b
& 0x01);
272 crc
= ((crc
^ POLYNOMIAL
) | carry
);
278 #if defined(DEBUG_EEPRO100)
279 static const char *nic_dump(const uint8_t * buf
, unsigned size
)
281 static char dump
[3 * 16 + 1];
286 p
+= sprintf(p
, " %02x", *buf
++);
290 #endif /* DEBUG_EEPRO100 */
293 stat_ack_not_ours
= 0x00,
294 stat_ack_sw_gen
= 0x04,
296 stat_ack_cu_idle
= 0x20,
297 stat_ack_frame_rx
= 0x40,
298 stat_ack_cu_cmd_done
= 0x80,
299 stat_ack_not_present
= 0xFF,
300 stat_ack_rx
= (stat_ack_sw_gen
| stat_ack_rnr
| stat_ack_frame_rx
),
301 stat_ack_tx
= (stat_ack_cu_idle
| stat_ack_cu_cmd_done
),
304 static void disable_interrupt(EEPRO100State
* s
)
307 logout("interrupt disabled\n");
308 qemu_irq_lower(s
->pci_dev
->irq
[0]);
313 static void enable_interrupt(EEPRO100State
* s
)
316 logout("interrupt enabled\n");
317 qemu_irq_raise(s
->pci_dev
->irq
[0]);
322 static void eepro100_acknowledge(EEPRO100State
* s
)
324 s
->scb_stat
&= ~s
->mem
[SCBAck
];
325 s
->mem
[SCBAck
] = s
->scb_stat
;
326 if (s
->scb_stat
== 0) {
327 disable_interrupt(s
);
331 static void eepro100_interrupt(EEPRO100State
* s
, uint8_t stat
)
333 uint8_t mask
= ~s
->mem
[SCBIntmask
];
334 s
->mem
[SCBAck
] |= stat
;
335 stat
= s
->scb_stat
= s
->mem
[SCBAck
];
336 stat
&= (mask
| 0x0f);
337 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
338 if (stat
&& (mask
& 0x01)) {
339 /* SCB mask and SCB Bit M do not disable interrupt. */
341 } else if (s
->int_stat
) {
342 disable_interrupt(s
);
346 static void eepro100_cx_interrupt(EEPRO100State
* s
)
348 /* CU completed action command. */
349 /* Transmit not ok (82557 only, not in emulation). */
350 eepro100_interrupt(s
, 0x80);
353 static void eepro100_cna_interrupt(EEPRO100State
* s
)
355 /* CU left the active state. */
356 eepro100_interrupt(s
, 0x20);
359 static void eepro100_fr_interrupt(EEPRO100State
* s
)
361 /* RU received a complete frame. */
362 eepro100_interrupt(s
, 0x40);
366 static void eepro100_rnr_interrupt(EEPRO100State
* s
)
368 /* RU is not ready. */
369 eepro100_interrupt(s
, 0x10);
373 static void eepro100_mdi_interrupt(EEPRO100State
* s
)
375 /* MDI completed read or write cycle. */
376 eepro100_interrupt(s
, 0x08);
379 static void eepro100_swi_interrupt(EEPRO100State
* s
)
381 /* Software has requested an interrupt. */
382 eepro100_interrupt(s
, 0x04);
386 static void eepro100_fcp_interrupt(EEPRO100State
* s
)
388 /* Flow control pause interrupt (82558 and later). */
389 eepro100_interrupt(s
, 0x01);
393 static void pci_reset(EEPRO100State
* s
)
395 uint32_t device
= s
->device
;
396 uint8_t *pci_conf
= s
->pci_dev
->config
;
401 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
403 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
405 PCI_CONFIG_16(PCI_COMMAND
, 0x0000);
407 PCI_CONFIG_16(PCI_STATUS
, 0x2800);
408 /* PCI Revision ID */
409 PCI_CONFIG_8(PCI_REVISION_ID
, 0x08);
411 PCI_CONFIG_8(0x09, 0x00);
412 pci_config_set_class(pci_conf
, PCI_CLASS_NETWORK_ETHERNET
);
413 /* PCI Cache Line Size */
414 /* check cache line size!!! */
415 //~ PCI_CONFIG_8(0x0c, 0x00);
416 /* PCI Latency Timer */
417 PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
418 /* PCI Header Type */
419 /* BIST (built-in self test) */
420 #if defined(TARGET_I386)
421 // !!! workaround for buggy bios
422 //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
425 /* PCI Base Address Registers */
426 /* CSR Memory Mapped Base Address */
427 PCI_CONFIG_32(PCI_BASE_ADDRESS_0
,
428 PCI_ADDRESS_SPACE_MEM
| PCI_ADDRESS_SPACE_MEM_PREFETCH
);
429 /* CSR I/O Mapped Base Address */
430 PCI_CONFIG_32(PCI_BASE_ADDRESS_1
, PCI_ADDRESS_SPACE_IO
);
432 /* Flash Memory Mapped Base Address */
433 PCI_CONFIG_32(PCI_BASE_ADDRESS_2
, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM
);
436 /* Expansion ROM Base Address (depends on boot disable!!!) */
437 PCI_CONFIG_32(0x30, 0x00000000);
438 /* Capability Pointer */
439 PCI_CONFIG_8(0x34, 0xdc);
441 PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
443 PCI_CONFIG_8(0x3e, 0x08);
444 /* Maximum Latency */
445 PCI_CONFIG_8(0x3f, 0x18);
446 /* Power Management Capabilities / Next Item Pointer / Capability ID */
447 PCI_CONFIG_32(0xdc, 0x7e210001);
451 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
452 PCI_CONFIG_8(PCI_REVISION_ID
, 0x0f);
455 PCI_CONFIG_16(PCI_DEVICE_ID
, 0x1229);
456 PCI_CONFIG_8(PCI_REVISION_ID
, 0x02);
459 PCI_CONFIG_16(PCI_DEVICE_ID
, 0x1229);
460 PCI_CONFIG_8(PCI_REVISION_ID
, 0x03);
463 PCI_CONFIG_16(PCI_DEVICE_ID
, 0x1229);
464 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
465 PCI_CONFIG_8(PCI_REVISION_ID
, 0x05);
468 PCI_CONFIG_16(PCI_DEVICE_ID
, 0x1229);
469 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
470 //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
473 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
474 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
475 PCI_CONFIG_8(PCI_REVISION_ID
, 0x09);
477 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
478 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
480 logout("Device %X is undefined!\n", device
);
483 if (device
== i82557C
|| device
== i82558B
|| device
== i82559C
) {
484 logout("Get device id and revision from EEPROM!!!\n");
488 static void nic_selective_reset(EEPRO100State
* s
)
491 uint16_t *eeprom_contents
= eeprom93xx_data(s
->eeprom
);
492 //~ eeprom93xx_reset(s->eeprom);
493 memcpy(eeprom_contents
, s
->macaddr
, 6);
494 eeprom_contents
[0xa] = 0x4000;
496 for (i
= 0; i
< EEPROM_SIZE
- 1; i
++) {
497 sum
+= eeprom_contents
[i
];
499 eeprom_contents
[EEPROM_SIZE
- 1] = 0xbaba - sum
;
501 memset(s
->mem
, 0, sizeof(s
->mem
));
502 uint32_t val
= BIT(21);
503 memcpy(&s
->mem
[SCBCtrlMDI
], &val
, sizeof(val
));
505 assert(sizeof(s
->mdimem
) == sizeof(eepro100_mdi_default
));
506 memcpy(&s
->mdimem
[0], &eepro100_mdi_default
[0], sizeof(s
->mdimem
));
509 static void nic_reset(void *opaque
)
511 EEPRO100State
*s
= (EEPRO100State
*) opaque
;
517 nic_selective_reset(s
);
520 #if defined(DEBUG_EEPRO100)
521 static const char *reg
[PCI_IO_SIZE
/ 4] = {
525 "EEPROM/Flash Control",
527 "Receive DMA Byte Count",
528 "Flow control register",
529 "General Status/Control"
532 static char *regname(uint32_t addr
)
535 if (addr
< PCI_IO_SIZE
) {
536 const char *r
= reg
[addr
/ 4];
538 sprintf(buf
, "%s+%u", r
, addr
% 4);
540 sprintf(buf
, "0x%02x", addr
);
543 sprintf(buf
, "??? 0x%08x", addr
);
547 #endif /* DEBUG_EEPRO100 */
550 static uint16_t eepro100_read_status(EEPRO100State
* s
)
552 uint16_t val
= s
->status
;
553 logout("val=0x%04x\n", val
);
557 static void eepro100_write_status(EEPRO100State
* s
, uint16_t val
)
559 logout("val=0x%04x\n", val
);
564 /*****************************************************************************
568 ****************************************************************************/
571 static uint16_t eepro100_read_command(EEPRO100State
* s
)
573 uint16_t val
= 0xffff;
574 //~ logout("val=0x%04x\n", val);
579 /* Commands that can be put in a command list entry. */
584 CmdMulticastList
= 3,
586 CmdTDR
= 5, /* load microcode */
590 /* And some extra flags: */
591 CmdSuspend
= 0x4000, /* Suspend after completion. */
592 CmdIntr
= 0x2000, /* Interrupt after completion. */
593 CmdTxFlex
= 0x0008, /* Use "Flexible mode" for CmdTx command. */
596 static cu_state_t
get_cu_state(EEPRO100State
* s
)
598 return ((s
->mem
[SCBStatus
] >> 6) & 0x03);
601 static void set_cu_state(EEPRO100State
* s
, cu_state_t state
)
603 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0x3f) + (state
<< 6);
606 static ru_state_t
get_ru_state(EEPRO100State
* s
)
608 return ((s
->mem
[SCBStatus
] >> 2) & 0x0f);
611 static void set_ru_state(EEPRO100State
* s
, ru_state_t state
)
613 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0xc3) + (state
<< 2);
616 static void dump_statistics(EEPRO100State
* s
)
618 /* Dump statistical data. Most data is never changed by the emulation
619 * and always 0, so we first just copy the whole block and then those
620 * values which really matter.
621 * Number of data should check configuration!!!
623 cpu_physical_memory_write(s
->statsaddr
, (uint8_t *) & s
->statistics
, 64);
624 stl_phys(s
->statsaddr
+ 0, s
->statistics
.tx_good_frames
);
625 stl_phys(s
->statsaddr
+ 36, s
->statistics
.rx_good_frames
);
626 stl_phys(s
->statsaddr
+ 48, s
->statistics
.rx_resource_errors
);
627 stl_phys(s
->statsaddr
+ 60, s
->statistics
.rx_short_frame_errors
);
628 //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
629 //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
630 //~ missing("CU dump statistical counters");
633 static void eepro100_cu_command(EEPRO100State
* s
, uint8_t val
)
642 if (get_cu_state(s
) != cu_idle
) {
643 /* Intel documentation says that CU must be idle for the CU
644 * start command. Intel driver for Linux also starts the CU
645 * from suspended state. */
646 logout("CU state is %u, should be %u\n", get_cu_state(s
), cu_idle
);
647 //~ assert(!"wrong CU state");
649 set_cu_state(s
, cu_active
);
650 s
->cu_offset
= s
->pointer
;
652 cb_address
= s
->cu_base
+ s
->cu_offset
;
653 cpu_physical_memory_read(cb_address
, (uint8_t *) & tx
, sizeof(tx
));
654 uint16_t status
= le16_to_cpu(tx
.status
);
655 uint16_t command
= le16_to_cpu(tx
.command
);
657 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
658 val
, status
, command
, tx
.link
);
659 bool bit_el
= ((command
& 0x8000) != 0);
660 bool bit_s
= ((command
& 0x4000) != 0);
661 bool bit_i
= ((command
& 0x2000) != 0);
662 bool bit_nc
= ((command
& 0x0010) != 0);
663 //~ bool bit_sf = ((command & 0x0008) != 0);
664 uint16_t cmd
= command
& 0x0007;
665 s
->cu_offset
= le32_to_cpu(tx
.link
);
671 cpu_physical_memory_read(cb_address
+ 8, &s
->macaddr
[0], 6);
672 logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6));
675 cpu_physical_memory_read(cb_address
+ 8, &s
->configuration
[0],
676 sizeof(s
->configuration
));
677 logout("configuration: %s\n", nic_dump(&s
->configuration
[0], 16));
679 case CmdMulticastList
:
680 //~ missing("multicast list");
684 uint32_t tbd_array
= le32_to_cpu(tx
.tx_desc_addr
);
685 uint16_t tcb_bytes
= (le16_to_cpu(tx
.tcb_bytes
) & 0x3fff);
687 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
688 tbd_array
, tcb_bytes
, tx
.tbd_count
);
691 assert(tcb_bytes
<= 2600);
692 /* Next assertion fails for local configuration. */
693 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
694 if (!((tcb_bytes
> 0) || (tbd_array
!= 0xffffffff))) {
696 ("illegal values of TBD array address and TCB byte count!\n");
698 uint8_t buf
[MAX_ETH_FRAME_SIZE
+ 4];
700 uint32_t tbd_address
= cb_address
+ 0x10;
701 assert(tcb_bytes
<= sizeof(buf
));
702 while (size
< tcb_bytes
) {
703 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
704 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
705 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
708 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
709 tx_buffer_address
, tx_buffer_size
);
710 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
712 size
+= tx_buffer_size
;
714 if (tbd_array
== 0xffffffff) {
715 /* Simplified mode. Was already handled by code above. */
718 uint8_t tbd_count
= 0;
719 if (!(s
->configuration
[6] & BIT(4))) {
721 assert(tcb_bytes
== 0);
722 for (; tbd_count
< 2; tbd_count
++) {
723 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
724 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
725 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
728 ("TBD (extended mode): buffer address 0x%08x, size 0x%04x\n",
729 tx_buffer_address
, tx_buffer_size
);
730 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
732 size
+= tx_buffer_size
;
733 if (tx_buffer_el
& 1) {
738 tbd_address
= tbd_array
;
739 for (; tbd_count
< tx
.tbd_count
; tbd_count
++) {
740 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
741 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
742 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
745 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
746 tx_buffer_address
, tx_buffer_size
);
747 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
749 size
+= tx_buffer_size
;
750 if (tx_buffer_el
& 1) {
755 qemu_send_packet(s
->vc
, buf
, size
);
756 s
->statistics
.tx_good_frames
++;
757 /* Transmit with bad status would raise an CX/TNO interrupt.
758 * (82557 only). Emulation never has bad status. */
759 //~ eepro100_cx_interrupt(s);
762 logout("load microcode\n");
763 /* Starting with offset 8, the command contains
764 * 64 dwords microcode which we just ignore here. */
767 missing("undefined command");
769 /* Write new status (success). */
770 stw_phys(cb_address
, status
| 0x8000 | 0x2000);
772 /* CU completed action. */
773 eepro100_cx_interrupt(s
);
776 /* CU becomes idle. */
777 set_cu_state(s
, cu_idle
);
778 eepro100_cna_interrupt(s
);
780 /* CU becomes suspended. */
781 set_cu_state(s
, cu_suspended
);
782 eepro100_cna_interrupt(s
);
784 /* More entries in list. */
785 logout("CU list with at least one more entry\n");
788 logout("CU list empty\n");
789 /* List is empty. Now CU is idle or suspended. */
792 if (get_cu_state(s
) != cu_suspended
) {
793 logout("bad CU resume from CU state %u\n", get_cu_state(s
));
794 /* Workaround for bad Linux eepro100 driver which resumes
795 * from idle state. */
796 //~ missing("cu resume");
797 set_cu_state(s
, cu_suspended
);
799 if (get_cu_state(s
) == cu_suspended
) {
800 logout("CU resuming\n");
801 set_cu_state(s
, cu_active
);
806 /* Load dump counters address. */
807 s
->statsaddr
= s
->pointer
;
808 logout("val=0x%02x (status address)\n", val
);
811 /* Dump statistical counters. */
816 logout("val=0x%02x (CU base address)\n", val
);
817 s
->cu_base
= s
->pointer
;
820 /* Dump and reset statistical counters. */
822 memset(&s
->statistics
, 0, sizeof(s
->statistics
));
825 /* CU static resume. */
826 missing("CU static resume");
829 missing("Undefined CU command");
833 static void eepro100_ru_command(EEPRO100State
* s
, uint8_t val
)
841 if (get_ru_state(s
) != ru_idle
) {
842 logout("RU state is %u, should be %u\n", get_ru_state(s
), ru_idle
);
843 //~ assert(!"wrong RU state");
845 set_ru_state(s
, ru_ready
);
846 s
->ru_offset
= s
->pointer
;
847 logout("val=0x%02x (rx start)\n", val
);
851 if (get_ru_state(s
) != ru_suspended
) {
852 logout("RU state is %u, should be %u\n", get_ru_state(s
),
854 //~ assert(!"wrong RU state");
856 set_ru_state(s
, ru_ready
);
860 logout("val=0x%02x (RU base address)\n", val
);
861 s
->ru_base
= s
->pointer
;
864 logout("val=0x%02x (undefined RU command)\n", val
);
865 missing("Undefined SU command");
869 static void eepro100_write_command(EEPRO100State
* s
, uint8_t val
)
871 eepro100_ru_command(s
, val
& 0x0f);
872 eepro100_cu_command(s
, val
& 0xf0);
874 logout("val=0x%02x\n", val
);
876 /* Clear command byte after command was accepted. */
880 /*****************************************************************************
884 ****************************************************************************/
886 #define EEPROM_CS 0x02
887 #define EEPROM_SK 0x01
888 #define EEPROM_DI 0x04
889 #define EEPROM_DO 0x08
891 static uint16_t eepro100_read_eeprom(EEPRO100State
* s
)
894 memcpy(&val
, &s
->mem
[SCBeeprom
], sizeof(val
));
895 if (eeprom93xx_read(s
->eeprom
)) {
903 static void eepro100_write_eeprom(eeprom_t
* eeprom
, uint8_t val
)
905 logout("write val=0x%02x\n", val
);
907 /* mask unwriteable bits */
908 //~ val = SET_MASKED(val, 0x31, eeprom->value);
910 int eecs
= ((val
& EEPROM_CS
) != 0);
911 int eesk
= ((val
& EEPROM_SK
) != 0);
912 int eedi
= ((val
& EEPROM_DI
) != 0);
913 eeprom93xx_write(eeprom
, eecs
, eesk
, eedi
);
916 static void eepro100_write_pointer(EEPRO100State
* s
, uint32_t val
)
918 s
->pointer
= le32_to_cpu(val
);
919 logout("val=0x%08x\n", val
);
922 /*****************************************************************************
926 ****************************************************************************/
928 #if defined(DEBUG_EEPRO100)
929 static const char *mdi_op_name
[] = {
936 static const char *mdi_reg_name
[] = {
939 "PHY Identification (Word 1)",
940 "PHY Identification (Word 2)",
941 "Auto-Negotiation Advertisement",
942 "Auto-Negotiation Link Partner Ability",
943 "Auto-Negotiation Expansion"
945 #endif /* DEBUG_EEPRO100 */
947 static uint32_t eepro100_read_mdi(EEPRO100State
* s
)
950 memcpy(&val
, &s
->mem
[0x10], sizeof(val
));
952 #ifdef DEBUG_EEPRO100
953 uint8_t raiseint
= (val
& BIT(29)) >> 29;
954 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
955 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
956 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
957 uint16_t data
= (val
& BITS(15, 0));
959 /* Emulation takes no time to finish MDI transaction. */
961 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
962 val
, raiseint
, mdi_op_name
[opcode
], phy
,
963 mdi_reg_name
[reg
], data
));
967 //~ #define BITS(val, upper, lower) (val & ???)
968 static void eepro100_write_mdi(EEPRO100State
* s
, uint32_t val
)
970 uint8_t raiseint
= (val
& BIT(29)) >> 29;
971 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
972 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
973 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
974 uint16_t data
= (val
& BITS(15, 0));
976 /* Unsupported PHY address. */
977 //~ logout("phy must be 1 but is %u\n", phy);
979 } else if (opcode
!= 1 && opcode
!= 2) {
980 /* Unsupported opcode. */
981 logout("opcode must be 1 or 2 but is %u\n", opcode
);
983 } else if (reg
> 6) {
984 /* Unsupported register. */
985 logout("register must be 0...6 but is %u\n", reg
);
988 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
989 val
, raiseint
, mdi_op_name
[opcode
], phy
,
990 mdi_reg_name
[reg
], data
));
994 case 0: /* Control Register */
996 /* Reset status and control registers to default. */
997 s
->mdimem
[0] = eepro100_mdi_default
[0];
998 s
->mdimem
[1] = eepro100_mdi_default
[1];
999 data
= s
->mdimem
[reg
];
1001 /* Restart Auto Configuration = Normal Operation */
1005 case 1: /* Status Register */
1006 missing("not writable");
1007 data
= s
->mdimem
[reg
];
1009 case 2: /* PHY Identification Register (Word 1) */
1010 case 3: /* PHY Identification Register (Word 2) */
1011 missing("not implemented");
1013 case 4: /* Auto-Negotiation Advertisement Register */
1014 case 5: /* Auto-Negotiation Link Partner Ability Register */
1016 case 6: /* Auto-Negotiation Expansion Register */
1018 missing("not implemented");
1020 s
->mdimem
[reg
] = data
;
1021 } else if (opcode
== 2) {
1024 case 0: /* Control Register */
1025 if (data
& 0x8000) {
1026 /* Reset status and control registers to default. */
1027 s
->mdimem
[0] = eepro100_mdi_default
[0];
1028 s
->mdimem
[1] = eepro100_mdi_default
[1];
1031 case 1: /* Status Register */
1032 s
->mdimem
[reg
] |= 0x0020;
1034 case 2: /* PHY Identification Register (Word 1) */
1035 case 3: /* PHY Identification Register (Word 2) */
1036 case 4: /* Auto-Negotiation Advertisement Register */
1038 case 5: /* Auto-Negotiation Link Partner Ability Register */
1039 s
->mdimem
[reg
] = 0x41fe;
1041 case 6: /* Auto-Negotiation Expansion Register */
1042 s
->mdimem
[reg
] = 0x0001;
1045 data
= s
->mdimem
[reg
];
1047 /* Emulation takes no time to finish MDI transaction.
1048 * Set MDI bit in SCB status register. */
1049 s
->mem
[SCBAck
] |= 0x08;
1052 eepro100_mdi_interrupt(s
);
1055 val
= (val
& 0xffff0000) + data
;
1056 memcpy(&s
->mem
[0x10], &val
, sizeof(val
));
1059 /*****************************************************************************
1063 ****************************************************************************/
1065 #define PORT_SOFTWARE_RESET 0
1066 #define PORT_SELFTEST 1
1067 #define PORT_SELECTIVE_RESET 2
1069 #define PORT_SELECTION_MASK 3
1072 uint32_t st_sign
; /* Self Test Signature */
1073 uint32_t st_result
; /* Self Test Results */
1074 } eepro100_selftest_t
;
1076 static uint32_t eepro100_read_port(EEPRO100State
* s
)
1081 static void eepro100_write_port(EEPRO100State
* s
, uint32_t val
)
1083 val
= le32_to_cpu(val
);
1084 uint32_t address
= (val
& ~PORT_SELECTION_MASK
);
1085 uint8_t selection
= (val
& PORT_SELECTION_MASK
);
1086 switch (selection
) {
1087 case PORT_SOFTWARE_RESET
:
1091 logout("selftest address=0x%08x\n", address
);
1092 eepro100_selftest_t data
;
1093 cpu_physical_memory_read(address
, (uint8_t *) & data
, sizeof(data
));
1094 data
.st_sign
= 0xffffffff;
1096 cpu_physical_memory_write(address
, (uint8_t *) & data
, sizeof(data
));
1098 case PORT_SELECTIVE_RESET
:
1099 logout("selective reset, selftest address=0x%08x\n", address
);
1100 nic_selective_reset(s
);
1103 logout("val=0x%08x\n", val
);
1104 missing("unknown port selection");
1108 /*****************************************************************************
1110 * General hardware emulation.
1112 ****************************************************************************/
1114 static uint8_t eepro100_read1(EEPRO100State
* s
, uint32_t addr
)
1117 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1118 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1123 //~ val = eepro100_read_status(s);
1124 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1127 //~ val = eepro100_read_status(s);
1128 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1131 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1132 //~ val = eepro100_read_command(s);
1135 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1138 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1141 val
= eepro100_read_eeprom(s
);
1143 case 0x1b: /* PMDR (power management driver register) */
1145 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1147 case 0x1d: /* general status register */
1148 /* 100 Mbps full duplex, valid link */
1150 logout("addr=General Status val=%02x\n", val
);
1153 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1154 missing("unknown byte read");
1159 static uint16_t eepro100_read2(EEPRO100State
* s
, uint32_t addr
)
1162 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1163 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1166 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1170 //~ val = eepro100_read_status(s);
1173 val
= eepro100_read_eeprom(s
);
1176 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1177 missing("unknown word read");
1182 static uint32_t eepro100_read4(EEPRO100State
* s
, uint32_t addr
)
1185 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1186 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1191 //~ val = eepro100_read_status(s);
1192 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1195 //~ val = eepro100_read_pointer(s);
1196 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1199 val
= eepro100_read_port(s
);
1200 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1203 val
= eepro100_read_mdi(s
);
1206 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1207 missing("unknown longword read");
1212 static void eepro100_write1(EEPRO100State
* s
, uint32_t addr
, uint8_t val
)
1214 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1215 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1218 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1222 //~ eepro100_write_status(s, val);
1225 eepro100_acknowledge(s
);
1228 eepro100_write_command(s
, val
);
1232 eepro100_swi_interrupt(s
);
1234 eepro100_interrupt(s
, 0);
1241 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1244 eepro100_write_eeprom(s
->eeprom
, val
);
1247 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1248 missing("unknown byte write");
1252 static void eepro100_write2(EEPRO100State
* s
, uint32_t addr
, uint16_t val
)
1254 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1255 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1258 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1262 //~ eepro100_write_status(s, val);
1263 eepro100_acknowledge(s
);
1266 eepro100_write_command(s
, val
);
1267 eepro100_write1(s
, SCBIntmask
, val
>> 8);
1270 eepro100_write_eeprom(s
->eeprom
, val
);
1273 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1274 missing("unknown word write");
1278 static void eepro100_write4(EEPRO100State
* s
, uint32_t addr
, uint32_t val
)
1280 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1281 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1286 eepro100_write_pointer(s
, val
);
1289 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1290 eepro100_write_port(s
, val
);
1293 eepro100_write_mdi(s
, val
);
1296 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1297 missing("unknown longword write");
1301 static uint32_t ioport_read1(void *opaque
, uint32_t addr
)
1303 EEPRO100State
*s
= opaque
;
1304 //~ logout("addr=%s\n", regname(addr));
1305 return eepro100_read1(s
, addr
- s
->region
[1]);
1308 static uint32_t ioport_read2(void *opaque
, uint32_t addr
)
1310 EEPRO100State
*s
= opaque
;
1311 return eepro100_read2(s
, addr
- s
->region
[1]);
1314 static uint32_t ioport_read4(void *opaque
, uint32_t addr
)
1316 EEPRO100State
*s
= opaque
;
1317 return eepro100_read4(s
, addr
- s
->region
[1]);
1320 static void ioport_write1(void *opaque
, uint32_t addr
, uint32_t val
)
1322 EEPRO100State
*s
= opaque
;
1323 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1324 eepro100_write1(s
, addr
- s
->region
[1], val
);
1327 static void ioport_write2(void *opaque
, uint32_t addr
, uint32_t val
)
1329 EEPRO100State
*s
= opaque
;
1330 eepro100_write2(s
, addr
- s
->region
[1], val
);
1333 static void ioport_write4(void *opaque
, uint32_t addr
, uint32_t val
)
1335 EEPRO100State
*s
= opaque
;
1336 eepro100_write4(s
, addr
- s
->region
[1], val
);
1339 /***********************************************************/
1340 /* PCI EEPRO100 definitions */
1342 typedef struct PCIEEPRO100State
{
1344 EEPRO100State eepro100
;
1347 static void pci_map(PCIDevice
* pci_dev
, int region_num
,
1348 uint32_t addr
, uint32_t size
, int type
)
1350 PCIEEPRO100State
*d
= (PCIEEPRO100State
*) pci_dev
;
1351 EEPRO100State
*s
= &d
->eepro100
;
1353 logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1354 region_num
, addr
, size
, type
);
1356 assert(region_num
== 1);
1357 register_ioport_write(addr
, size
, 1, ioport_write1
, s
);
1358 register_ioport_read(addr
, size
, 1, ioport_read1
, s
);
1359 register_ioport_write(addr
, size
, 2, ioport_write2
, s
);
1360 register_ioport_read(addr
, size
, 2, ioport_read2
, s
);
1361 register_ioport_write(addr
, size
, 4, ioport_write4
, s
);
1362 register_ioport_read(addr
, size
, 4, ioport_read4
, s
);
1364 s
->region
[region_num
] = addr
;
1367 static void pci_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1369 EEPRO100State
*s
= opaque
;
1370 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1371 eepro100_write1(s
, addr
, val
);
1374 static void pci_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1376 EEPRO100State
*s
= opaque
;
1377 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1378 eepro100_write2(s
, addr
, val
);
1381 static void pci_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1383 EEPRO100State
*s
= opaque
;
1384 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1385 eepro100_write4(s
, addr
, val
);
1388 static uint32_t pci_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1390 EEPRO100State
*s
= opaque
;
1391 //~ logout("addr=%s\n", regname(addr));
1392 return eepro100_read1(s
, addr
);
1395 static uint32_t pci_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1397 EEPRO100State
*s
= opaque
;
1398 //~ logout("addr=%s\n", regname(addr));
1399 return eepro100_read2(s
, addr
);
1402 static uint32_t pci_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1404 EEPRO100State
*s
= opaque
;
1405 //~ logout("addr=%s\n", regname(addr));
1406 return eepro100_read4(s
, addr
);
1409 static CPUWriteMemoryFunc
*pci_mmio_write
[] = {
1415 static CPUReadMemoryFunc
*pci_mmio_read
[] = {
1421 static void pci_mmio_map(PCIDevice
* pci_dev
, int region_num
,
1422 uint32_t addr
, uint32_t size
, int type
)
1424 PCIEEPRO100State
*d
= (PCIEEPRO100State
*) pci_dev
;
1426 logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1427 region_num
, addr
, size
, type
);
1429 if (region_num
== 0) {
1430 /* Map control / status registers. */
1431 cpu_register_physical_memory(addr
, size
, d
->eepro100
.mmio_index
);
1432 d
->eepro100
.region
[region_num
] = addr
;
1436 static int nic_can_receive(VLANClientState
*vc
)
1438 EEPRO100State
*s
= vc
->opaque
;
1440 return get_ru_state(s
) == ru_ready
;
1441 //~ return !eepro100_buffer_full(s);
1444 static ssize_t
nic_receive(VLANClientState
*vc
, const uint8_t * buf
, size_t size
)
1447 * - Magic packets should set bit 30 in power management driver register.
1448 * - Interesting packets should set bit 29 in power management driver register.
1450 EEPRO100State
*s
= vc
->opaque
;
1451 uint16_t rfd_status
= 0xa000;
1452 static const uint8_t broadcast_macaddr
[6] =
1453 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1455 /* TODO: check multiple IA bit. */
1456 assert(!(s
->configuration
[20] & BIT(6)));
1458 if (s
->configuration
[8] & 0x80) {
1459 /* CSMA is disabled. */
1460 logout("%p received while CSMA is disabled\n", s
);
1462 } else if (size
< 64 && (s
->configuration
[7] & 1)) {
1463 /* Short frame and configuration byte 7/0 (discard short receive) set:
1464 * Short frame is discarded */
1465 logout("%p received short frame (%d byte)\n", s
, size
);
1466 s
->statistics
.rx_short_frame_errors
++;
1468 } else if ((size
> MAX_ETH_FRAME_SIZE
+ 4) && !(s
->configuration
[18] & 8)) {
1469 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1470 * Long frames are discarded. */
1471 logout("%p received long frame (%d byte), ignored\n", s
, size
);
1473 } else if (memcmp(buf
, s
->macaddr
, 6) == 0) { // !!!
1474 /* Frame matches individual address. */
1475 /* TODO: check configuration byte 15/4 (ignore U/L). */
1476 logout("%p received frame for me, len=%d\n", s
, size
);
1477 } else if (memcmp(buf
, broadcast_macaddr
, 6) == 0) {
1478 /* Broadcast frame. */
1479 logout("%p received broadcast, len=%d\n", s
, size
);
1480 rfd_status
|= 0x0002;
1481 } else if (buf
[0] & 0x01) { // !!!
1482 /* Multicast frame. */
1483 logout("%p received multicast, len=%d\n", s
, size
);
1484 /* TODO: check multicast all bit. */
1485 assert(!(s
->configuration
[21] & BIT(3)));
1486 int mcast_idx
= compute_mcast_idx(buf
);
1487 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7)))) {
1490 rfd_status
|= 0x0002;
1491 } else if (s
->configuration
[15] & 1) {
1492 /* Promiscuous: receive all. */
1493 logout("%p received frame in promiscuous mode, len=%d\n", s
, size
);
1494 rfd_status
|= 0x0004;
1496 logout("%p received frame, ignored, len=%d,%s\n", s
, size
,
1497 nic_dump(buf
, size
));
1501 if (get_ru_state(s
) != ru_ready
) {
1502 /* No ressources available. */
1503 logout("no ressources, state=%u\n", get_ru_state(s
));
1504 s
->statistics
.rx_resource_errors
++;
1505 //~ assert(!"no ressources");
1509 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1511 cpu_physical_memory_read(s
->ru_base
+ s
->ru_offset
, (uint8_t *) & rx
,
1512 offsetof(eepro100_rx_t
, packet
));
1513 uint16_t rfd_command
= le16_to_cpu(rx
.command
);
1514 uint16_t rfd_size
= le16_to_cpu(rx
.size
);
1515 assert(size
<= rfd_size
);
1517 rfd_status
|= 0x0080;
1519 logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", rfd_command
,
1520 rx
.link
, rx
.rx_buf_addr
, rfd_size
);
1521 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, status
),
1523 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, count
), size
);
1524 /* Early receive interrupt not supported. */
1525 //~ eepro100_er_interrupt(s);
1526 /* Receive CRC Transfer not supported. */
1527 assert(!(s
->configuration
[18] & 4));
1528 /* TODO: check stripping enable bit. */
1529 //~ assert(!(s->configuration[17] & 1));
1530 cpu_physical_memory_write(s
->ru_base
+ s
->ru_offset
+
1531 offsetof(eepro100_rx_t
, packet
), buf
, size
);
1532 s
->statistics
.rx_good_frames
++;
1533 eepro100_fr_interrupt(s
);
1534 s
->ru_offset
= le32_to_cpu(rx
.link
);
1535 if (rfd_command
& 0x8000) {
1536 /* EL bit is set, so this was the last frame. */
1539 if (rfd_command
& 0x4000) {
1541 set_ru_state(s
, ru_suspended
);
1546 static int nic_load(QEMUFile
* f
, void *opaque
, int version_id
)
1548 EEPRO100State
*s
= (EEPRO100State
*) opaque
;
1555 if (s
->pci_dev
&& version_id
>= 3) {
1556 ret
= pci_device_load(s
->pci_dev
, f
);
1561 if (version_id
>= 2) {
1562 qemu_get_8s(f
, &s
->rxcr
);
1567 qemu_get_8s(f
, &s
->cmd
);
1568 qemu_get_be32s(f
, &s
->start
);
1569 qemu_get_be32s(f
, &s
->stop
);
1570 qemu_get_8s(f
, &s
->boundary
);
1571 qemu_get_8s(f
, &s
->tsr
);
1572 qemu_get_8s(f
, &s
->tpsr
);
1573 qemu_get_be16s(f
, &s
->tcnt
);
1574 qemu_get_be16s(f
, &s
->rcnt
);
1575 qemu_get_be32s(f
, &s
->rsar
);
1576 qemu_get_8s(f
, &s
->rsr
);
1577 qemu_get_8s(f
, &s
->isr
);
1578 qemu_get_8s(f
, &s
->dcfg
);
1579 qemu_get_8s(f
, &s
->imr
);
1580 qemu_get_buffer(f
, s
->phys
, 6);
1581 qemu_get_8s(f
, &s
->curpag
);
1582 qemu_get_buffer(f
, s
->mult
, 8);
1583 qemu_get_buffer(f
, s
->mem
, sizeof(s
->mem
));
1585 /* Restore all members of struct between scv_stat and mem */
1586 qemu_get_8s(f
, &s
->scb_stat
);
1587 qemu_get_8s(f
, &s
->int_stat
);
1588 for (i
= 0; i
< 3; i
++)
1589 qemu_get_be32s(f
, &s
->region
[i
]);
1590 qemu_get_buffer(f
, s
->macaddr
, 6);
1591 for (i
= 0; i
< 19; i
++)
1592 qemu_get_be32s(f
, &s
->statcounter
[i
]);
1593 for (i
= 0; i
< 32; i
++)
1594 qemu_get_be16s(f
, &s
->mdimem
[i
]);
1595 /* The eeprom should be saved and restored by its own routines */
1596 qemu_get_be32s(f
, &s
->device
);
1597 qemu_get_be32s(f
, &s
->pointer
);
1598 qemu_get_be32s(f
, &s
->cu_base
);
1599 qemu_get_be32s(f
, &s
->cu_offset
);
1600 qemu_get_be32s(f
, &s
->ru_base
);
1601 qemu_get_be32s(f
, &s
->ru_offset
);
1602 qemu_get_be32s(f
, &s
->statsaddr
);
1603 /* Restore epro100_stats_t statistics */
1604 qemu_get_be32s(f
, &s
->statistics
.tx_good_frames
);
1605 qemu_get_be32s(f
, &s
->statistics
.tx_max_collisions
);
1606 qemu_get_be32s(f
, &s
->statistics
.tx_late_collisions
);
1607 qemu_get_be32s(f
, &s
->statistics
.tx_underruns
);
1608 qemu_get_be32s(f
, &s
->statistics
.tx_lost_crs
);
1609 qemu_get_be32s(f
, &s
->statistics
.tx_deferred
);
1610 qemu_get_be32s(f
, &s
->statistics
.tx_single_collisions
);
1611 qemu_get_be32s(f
, &s
->statistics
.tx_multiple_collisions
);
1612 qemu_get_be32s(f
, &s
->statistics
.tx_total_collisions
);
1613 qemu_get_be32s(f
, &s
->statistics
.rx_good_frames
);
1614 qemu_get_be32s(f
, &s
->statistics
.rx_crc_errors
);
1615 qemu_get_be32s(f
, &s
->statistics
.rx_alignment_errors
);
1616 qemu_get_be32s(f
, &s
->statistics
.rx_resource_errors
);
1617 qemu_get_be32s(f
, &s
->statistics
.rx_overrun_errors
);
1618 qemu_get_be32s(f
, &s
->statistics
.rx_cdt_errors
);
1619 qemu_get_be32s(f
, &s
->statistics
.rx_short_frame_errors
);
1620 qemu_get_be32s(f
, &s
->statistics
.fc_xmt_pause
);
1621 qemu_get_be32s(f
, &s
->statistics
.fc_rcv_pause
);
1622 qemu_get_be32s(f
, &s
->statistics
.fc_rcv_unsupported
);
1623 qemu_get_be16s(f
, &s
->statistics
.xmt_tco_frames
);
1624 qemu_get_be16s(f
, &s
->statistics
.rcv_tco_frames
);
1625 qemu_get_be32s(f
, &s
->statistics
.complete
);
1627 qemu_get_be16s(f
, &s
->status
);
1630 /* Configuration bytes. */
1631 qemu_get_buffer(f
, s
->configuration
, sizeof(s
->configuration
));
1636 static void nic_save(QEMUFile
* f
, void *opaque
)
1638 EEPRO100State
*s
= (EEPRO100State
*) opaque
;
1642 pci_device_save(s
->pci_dev
, f
);
1644 qemu_put_8s(f
, &s
->rxcr
);
1646 qemu_put_8s(f
, &s
->cmd
);
1647 qemu_put_be32s(f
, &s
->start
);
1648 qemu_put_be32s(f
, &s
->stop
);
1649 qemu_put_8s(f
, &s
->boundary
);
1650 qemu_put_8s(f
, &s
->tsr
);
1651 qemu_put_8s(f
, &s
->tpsr
);
1652 qemu_put_be16s(f
, &s
->tcnt
);
1653 qemu_put_be16s(f
, &s
->rcnt
);
1654 qemu_put_be32s(f
, &s
->rsar
);
1655 qemu_put_8s(f
, &s
->rsr
);
1656 qemu_put_8s(f
, &s
->isr
);
1657 qemu_put_8s(f
, &s
->dcfg
);
1658 qemu_put_8s(f
, &s
->imr
);
1659 qemu_put_buffer(f
, s
->phys
, 6);
1660 qemu_put_8s(f
, &s
->curpag
);
1661 qemu_put_buffer(f
, s
->mult
, 8);
1662 qemu_put_buffer(f
, s
->mem
, sizeof(s
->mem
));
1664 /* Save all members of struct between scv_stat and mem */
1665 qemu_put_8s(f
, &s
->scb_stat
);
1666 qemu_put_8s(f
, &s
->int_stat
);
1667 for (i
= 0; i
< 3; i
++)
1668 qemu_put_be32s(f
, &s
->region
[i
]);
1669 qemu_put_buffer(f
, s
->macaddr
, 6);
1670 for (i
= 0; i
< 19; i
++)
1671 qemu_put_be32s(f
, &s
->statcounter
[i
]);
1672 for (i
= 0; i
< 32; i
++)
1673 qemu_put_be16s(f
, &s
->mdimem
[i
]);
1674 /* The eeprom should be saved and restored by its own routines */
1675 qemu_put_be32s(f
, &s
->device
);
1676 qemu_put_be32s(f
, &s
->pointer
);
1677 qemu_put_be32s(f
, &s
->cu_base
);
1678 qemu_put_be32s(f
, &s
->cu_offset
);
1679 qemu_put_be32s(f
, &s
->ru_base
);
1680 qemu_put_be32s(f
, &s
->ru_offset
);
1681 qemu_put_be32s(f
, &s
->statsaddr
);
1682 /* Save epro100_stats_t statistics */
1683 qemu_put_be32s(f
, &s
->statistics
.tx_good_frames
);
1684 qemu_put_be32s(f
, &s
->statistics
.tx_max_collisions
);
1685 qemu_put_be32s(f
, &s
->statistics
.tx_late_collisions
);
1686 qemu_put_be32s(f
, &s
->statistics
.tx_underruns
);
1687 qemu_put_be32s(f
, &s
->statistics
.tx_lost_crs
);
1688 qemu_put_be32s(f
, &s
->statistics
.tx_deferred
);
1689 qemu_put_be32s(f
, &s
->statistics
.tx_single_collisions
);
1690 qemu_put_be32s(f
, &s
->statistics
.tx_multiple_collisions
);
1691 qemu_put_be32s(f
, &s
->statistics
.tx_total_collisions
);
1692 qemu_put_be32s(f
, &s
->statistics
.rx_good_frames
);
1693 qemu_put_be32s(f
, &s
->statistics
.rx_crc_errors
);
1694 qemu_put_be32s(f
, &s
->statistics
.rx_alignment_errors
);
1695 qemu_put_be32s(f
, &s
->statistics
.rx_resource_errors
);
1696 qemu_put_be32s(f
, &s
->statistics
.rx_overrun_errors
);
1697 qemu_put_be32s(f
, &s
->statistics
.rx_cdt_errors
);
1698 qemu_put_be32s(f
, &s
->statistics
.rx_short_frame_errors
);
1699 qemu_put_be32s(f
, &s
->statistics
.fc_xmt_pause
);
1700 qemu_put_be32s(f
, &s
->statistics
.fc_rcv_pause
);
1701 qemu_put_be32s(f
, &s
->statistics
.fc_rcv_unsupported
);
1702 qemu_put_be16s(f
, &s
->statistics
.xmt_tco_frames
);
1703 qemu_put_be16s(f
, &s
->statistics
.rcv_tco_frames
);
1704 qemu_put_be32s(f
, &s
->statistics
.complete
);
1706 qemu_put_be16s(f
, &s
->status
);
1709 /* Configuration bytes. */
1710 qemu_put_buffer(f
, s
->configuration
, sizeof(s
->configuration
));
1713 static void nic_cleanup(VLANClientState
*vc
)
1715 EEPRO100State
*s
= vc
->opaque
;
1717 unregister_savevm(vc
->model
, s
);
1719 eeprom93xx_free(s
->eeprom
);
1722 static int pci_nic_uninit(PCIDevice
*dev
)
1724 PCIEEPRO100State
*d
= (PCIEEPRO100State
*) dev
;
1725 EEPRO100State
*s
= &d
->eepro100
;
1727 cpu_unregister_io_memory(s
->mmio_index
);
1732 static void nic_init(PCIDevice
*pci_dev
, uint32_t device
)
1734 PCIEEPRO100State
*d
= (PCIEEPRO100State
*)pci_dev
;
1739 d
->dev
.unregister
= pci_nic_uninit
;
1743 s
->pci_dev
= &d
->dev
;
1747 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1748 * i82559 and later support 64 or 256 word EEPROM. */
1749 s
->eeprom
= eeprom93xx_new(EEPROM_SIZE
);
1751 /* Handler for memory-mapped I/O */
1752 d
->eepro100
.mmio_index
=
1753 cpu_register_io_memory(pci_mmio_read
, pci_mmio_write
, s
);
1755 pci_register_bar(&d
->dev
, 0, PCI_MEM_SIZE
,
1756 PCI_ADDRESS_SPACE_MEM
|
1757 PCI_ADDRESS_SPACE_MEM_PREFETCH
, pci_mmio_map
);
1758 pci_register_bar(&d
->dev
, 1, PCI_IO_SIZE
, PCI_ADDRESS_SPACE_IO
,
1760 pci_register_bar(&d
->dev
, 2, PCI_FLASH_SIZE
, PCI_ADDRESS_SPACE_MEM
,
1763 qdev_get_macaddr(&d
->dev
.qdev
, s
->macaddr
);
1764 logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6));
1765 assert(s
->region
[1] == 0);
1769 s
->vc
= qdev_get_vlan_client(&d
->dev
.qdev
,
1770 nic_can_receive
, nic_receive
, NULL
,
1773 qemu_format_nic_info_str(s
->vc
, s
->macaddr
);
1775 qemu_register_reset(nic_reset
, s
);
1777 register_savevm(s
->vc
->model
, -1, 3, nic_save
, nic_load
, s
);
1780 static void pci_i82551_init(PCIDevice
*dev
)
1782 nic_init(dev
, i82551
);
1785 static void pci_i82557b_init(PCIDevice
*dev
)
1787 nic_init(dev
, i82557B
);
1790 static void pci_i82559er_init(PCIDevice
*dev
)
1792 nic_init(dev
, i82559ER
);
1795 static void eepro100_register_devices(void)
1797 pci_qdev_register("i82551", sizeof(PCIEEPRO100State
),
1799 pci_qdev_register("i82557b", sizeof(PCIEEPRO100State
),
1801 pci_qdev_register("i82559er", sizeof(PCIEEPRO100State
),
1805 device_init(eepro100_register_devices
)