hw/pxa2xx_lcd.c

   1 /*
   2  * Intel XScale PXA255/270 LCDC emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPLv2.
   8  */
   9
  10 #include "hw.h"
  11 #include "console.h"
  12 #include "pxa.h"
  13 #include "pixel_ops.h"
  14 /* FIXME: For graphic_rotate. Should probably be done in common code.  */
  15 #include "sysemu.h"
  16 #include "framebuffer.h"
  17
  18 struct DMAChannel {
  19     target_phys_addr_t branch;
  20     uint8_t up;
  21     uint8_t palette[1024];
  22     uint8_t pbuffer[1024];
  23     void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
  24                    int *miny, int *maxy);
  25
  26     target_phys_addr_t descriptor;
  27     target_phys_addr_t source;
  28     uint32_t id;
  29     uint32_t command;
  30 };
  31
  32 struct PXA2xxLCDState {
  33     qemu_irq irq;
  34     int irqlevel;
  35
  36     int invalidated;
  37     DisplayState *ds;
  38     drawfn *line_fn[2];
  39     int dest_width;
  40     int xres, yres;
  41     int pal_for;
  42     int transp;
  43     enum {
  44         pxa_lcdc_2bpp = 1,
  45         pxa_lcdc_4bpp = 2,
  46         pxa_lcdc_8bpp = 3,
  47         pxa_lcdc_16bpp = 4,
  48         pxa_lcdc_18bpp = 5,
  49         pxa_lcdc_18pbpp = 6,
  50         pxa_lcdc_19bpp = 7,
  51         pxa_lcdc_19pbpp = 8,
  52         pxa_lcdc_24bpp = 9,
  53         pxa_lcdc_25bpp = 10,
  54     } bpp;
  55
  56     uint32_t control[6];
  57     uint32_t status[2];
  58     uint32_t ovl1c[2];
  59     uint32_t ovl2c[2];
  60     uint32_t ccr;
  61     uint32_t cmdcr;
  62     uint32_t trgbr;
  63     uint32_t tcr;
  64     uint32_t liidr;
  65     uint8_t bscntr;
  66
  67     struct DMAChannel dma_ch[7];
  68
  69     qemu_irq vsync_cb;
  70     int orientation;
  71 };
  72
  73 typedef struct __attribute__ ((__packed__)) {
  74     uint32_t fdaddr;
  75     uint32_t fsaddr;
  76     uint32_t fidr;
  77     uint32_t ldcmd;
  78 } PXAFrameDescriptor;
  79
  80 #define LCCR0   0x000   /* LCD Controller Control register 0 */
  81 #define LCCR1   0x004   /* LCD Controller Control register 1 */
  82 #define LCCR2   0x008   /* LCD Controller Control register 2 */
  83 #define LCCR3   0x00c   /* LCD Controller Control register 3 */
  84 #define LCCR4   0x010   /* LCD Controller Control register 4 */
  85 #define LCCR5   0x014   /* LCD Controller Control register 5 */
  86
  87 #define FBR0    0x020   /* DMA Channel 0 Frame Branch register */
  88 #define FBR1    0x024   /* DMA Channel 1 Frame Branch register */
  89 #define FBR2    0x028   /* DMA Channel 2 Frame Branch register */
  90 #define FBR3    0x02c   /* DMA Channel 3 Frame Branch register */
  91 #define FBR4    0x030   /* DMA Channel 4 Frame Branch register */
  92 #define FBR5    0x110   /* DMA Channel 5 Frame Branch register */
  93 #define FBR6    0x114   /* DMA Channel 6 Frame Branch register */
  94
  95 #define LCSR1   0x034   /* LCD Controller Status register 1 */
  96 #define LCSR0   0x038   /* LCD Controller Status register 0 */
  97 #define LIIDR   0x03c   /* LCD Controller Interrupt ID register */
  98
  99 #define TRGBR   0x040   /* TMED RGB Seed register */
 100 #define TCR     0x044   /* TMED Control register */
 101
 102 #define OVL1C1  0x050   /* Overlay 1 Control register 1 */
 103 #define OVL1C2  0x060   /* Overlay 1 Control register 2 */
 104 #define OVL2C1  0x070   /* Overlay 2 Control register 1 */
 105 #define OVL2C2  0x080   /* Overlay 2 Control register 2 */
 106 #define CCR     0x090   /* Cursor Control register */
 107
 108 #define CMDCR   0x100   /* Command Control register */
 109 #define PRSR    0x104   /* Panel Read Status register */
 110
 111 #define PXA_LCDDMA_CHANS        7
 112 #define DMA_FDADR               0x00    /* Frame Descriptor Address register */
 113 #define DMA_FSADR               0x04    /* Frame Source Address register */
 114 #define DMA_FIDR                0x08    /* Frame ID register */
 115 #define DMA_LDCMD               0x0c    /* Command register */
 116
 117 /* LCD Buffer Strength Control register */
 118 #define BSCNTR  0x04000054
 119
 120 /* Bitfield masks */
 121 #define LCCR0_ENB       (1 << 0)
 122 #define LCCR0_CMS       (1 << 1)
 123 #define LCCR0_SDS       (1 << 2)
 124 #define LCCR0_LDM       (1 << 3)
 125 #define LCCR0_SOFM0     (1 << 4)
 126 #define LCCR0_IUM       (1 << 5)
 127 #define LCCR0_EOFM0     (1 << 6)
 128 #define LCCR0_PAS       (1 << 7)
 129 #define LCCR0_DPD       (1 << 9)
 130 #define LCCR0_DIS       (1 << 10)
 131 #define LCCR0_QDM       (1 << 11)
 132 #define LCCR0_PDD       (0xff << 12)
 133 #define LCCR0_BSM0      (1 << 20)
 134 #define LCCR0_OUM       (1 << 21)
 135 #define LCCR0_LCDT      (1 << 22)
 136 #define LCCR0_RDSTM     (1 << 23)
 137 #define LCCR0_CMDIM     (1 << 24)
 138 #define LCCR0_OUC       (1 << 25)
 139 #define LCCR0_LDDALT    (1 << 26)
 140 #define LCCR1_PPL(x)    ((x) & 0x3ff)
 141 #define LCCR2_LPP(x)    ((x) & 0x3ff)
 142 #define LCCR3_API       (15 << 16)
 143 #define LCCR3_BPP(x)    ((((x) >> 24) & 7) | (((x) >> 26) & 8))
 144 #define LCCR3_PDFOR(x)  (((x) >> 30) & 3)
 145 #define LCCR4_K1(x)     (((x) >> 0) & 7)
 146 #define LCCR4_K2(x)     (((x) >> 3) & 7)
 147 #define LCCR4_K3(x)     (((x) >> 6) & 7)
 148 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
 149 #define LCCR5_SOFM(ch)  (1 << (ch - 1))
 150 #define LCCR5_EOFM(ch)  (1 << (ch + 7))
 151 #define LCCR5_BSM(ch)   (1 << (ch + 15))
 152 #define LCCR5_IUM(ch)   (1 << (ch + 23))
 153 #define OVLC1_EN        (1 << 31)
 154 #define CCR_CEN         (1 << 31)
 155 #define FBR_BRA         (1 << 0)
 156 #define FBR_BINT        (1 << 1)
 157 #define FBR_SRCADDR     (0xfffffff << 4)
 158 #define LCSR0_LDD       (1 << 0)
 159 #define LCSR0_SOF0      (1 << 1)
 160 #define LCSR0_BER       (1 << 2)
 161 #define LCSR0_ABC       (1 << 3)
 162 #define LCSR0_IU0       (1 << 4)
 163 #define LCSR0_IU1       (1 << 5)
 164 #define LCSR0_OU        (1 << 6)
 165 #define LCSR0_QD        (1 << 7)
 166 #define LCSR0_EOF0      (1 << 8)
 167 #define LCSR0_BS0       (1 << 9)
 168 #define LCSR0_SINT      (1 << 10)
 169 #define LCSR0_RDST      (1 << 11)
 170 #define LCSR0_CMDINT    (1 << 12)
 171 #define LCSR0_BERCH(x)  (((x) & 7) << 28)
 172 #define LCSR1_SOF(ch)   (1 << (ch - 1))
 173 #define LCSR1_EOF(ch)   (1 << (ch + 7))
 174 #define LCSR1_BS(ch)    (1 << (ch + 15))
 175 #define LCSR1_IU(ch)    (1 << (ch + 23))
 176 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
 177 #define LDCMD_EOFINT    (1 << 21)
 178 #define LDCMD_SOFINT    (1 << 22)
 179 #define LDCMD_PAL       (1 << 26)
 180
 181 /* Route internal interrupt lines to the global IC */
 182 static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
 183 {
 184     int level = 0;
 185     level |= (s->status[0] & LCSR0_LDD)    && !(s->control[0] & LCCR0_LDM);
 186     level |= (s->status[0] & LCSR0_SOF0)   && !(s->control[0] & LCCR0_SOFM0);
 187     level |= (s->status[0] & LCSR0_IU0)    && !(s->control[0] & LCCR0_IUM);
 188     level |= (s->status[0] & LCSR0_IU1)    && !(s->control[5] & LCCR5_IUM(1));
 189     level |= (s->status[0] & LCSR0_OU)     && !(s->control[0] & LCCR0_OUM);
 190     level |= (s->status[0] & LCSR0_QD)     && !(s->control[0] & LCCR0_QDM);
 191     level |= (s->status[0] & LCSR0_EOF0)   && !(s->control[0] & LCCR0_EOFM0);
 192     level |= (s->status[0] & LCSR0_BS0)    && !(s->control[0] & LCCR0_BSM0);
 193     level |= (s->status[0] & LCSR0_RDST)   && !(s->control[0] & LCCR0_RDSTM);
 194     level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
 195     level |= (s->status[1] & ~s->control[5]);
 196
 197     qemu_set_irq(s->irq, !!level);
 198     s->irqlevel = level;
 199 }
 200
 201 /* Set Branch Status interrupt high and poke associated registers */
 202 static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
 203 {
 204     int unmasked;
 205     if (ch == 0) {
 206         s->status[0] |= LCSR0_BS0;
 207         unmasked = !(s->control[0] & LCCR0_BSM0);
 208     } else {
 209         s->status[1] |= LCSR1_BS(ch);
 210         unmasked = !(s->control[5] & LCCR5_BSM(ch));
 211     }
 212
 213     if (unmasked) {
 214         if (s->irqlevel)
 215             s->status[0] |= LCSR0_SINT;
 216         else
 217             s->liidr = s->dma_ch[ch].id;
 218     }
 219 }
 220
 221 /* Set Start Of Frame Status interrupt high and poke associated registers */
 222 static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
 223 {
 224     int unmasked;
 225     if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
 226         return;
 227
 228     if (ch == 0) {
 229         s->status[0] |= LCSR0_SOF0;
 230         unmasked = !(s->control[0] & LCCR0_SOFM0);
 231     } else {
 232         s->status[1] |= LCSR1_SOF(ch);
 233         unmasked = !(s->control[5] & LCCR5_SOFM(ch));
 234     }
 235
 236     if (unmasked) {
 237         if (s->irqlevel)
 238             s->status[0] |= LCSR0_SINT;
 239         else
 240             s->liidr = s->dma_ch[ch].id;
 241     }
 242 }
 243
 244 /* Set End Of Frame Status interrupt high and poke associated registers */
 245 static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
 246 {
 247     int unmasked;
 248     if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
 249         return;
 250
 251     if (ch == 0) {
 252         s->status[0] |= LCSR0_EOF0;
 253         unmasked = !(s->control[0] & LCCR0_EOFM0);
 254     } else {
 255         s->status[1] |= LCSR1_EOF(ch);
 256         unmasked = !(s->control[5] & LCCR5_EOFM(ch));
 257     }
 258
 259     if (unmasked) {
 260         if (s->irqlevel)
 261             s->status[0] |= LCSR0_SINT;
 262         else
 263             s->liidr = s->dma_ch[ch].id;
 264     }
 265 }
 266
 267 /* Set Bus Error Status interrupt high and poke associated registers */
 268 static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
 269 {
 270     s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
 271     if (s->irqlevel)
 272         s->status[0] |= LCSR0_SINT;
 273     else
 274         s->liidr = s->dma_ch[ch].id;
 275 }
 276
 277 /* Set Read Status interrupt high and poke associated registers */
 278 static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
 279 {
 280     s->status[0] |= LCSR0_RDST;
 281     if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
 282         s->status[0] |= LCSR0_SINT;
 283 }
 284
 285 /* Load new Frame Descriptors from DMA */
 286 static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
 287 {
 288     PXAFrameDescriptor desc;
 289     target_phys_addr_t descptr;
 290     int i;
 291
 292     for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
 293         s->dma_ch[i].source = 0;
 294
 295         if (!s->dma_ch[i].up)
 296             continue;
 297
 298         if (s->dma_ch[i].branch & FBR_BRA) {
 299             descptr = s->dma_ch[i].branch & FBR_SRCADDR;
 300             if (s->dma_ch[i].branch & FBR_BINT)
 301                 pxa2xx_dma_bs_set(s, i);
 302             s->dma_ch[i].branch &= ~FBR_BRA;
 303         } else
 304             descptr = s->dma_ch[i].descriptor;
 305
 306         if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
 307                     sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
 308             continue;
 309
 310         cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
 311         s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
 312         s->dma_ch[i].source = tswap32(desc.fsaddr);
 313         s->dma_ch[i].id = tswap32(desc.fidr);
 314         s->dma_ch[i].command = tswap32(desc.ldcmd);
 315     }
 316 }
 317
 318 static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
 319 {
 320     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 321     int ch;
 322
 323     switch (offset) {
 324     case LCCR0:
 325         return s->control[0];
 326     case LCCR1:
 327         return s->control[1];
 328     case LCCR2:
 329         return s->control[2];
 330     case LCCR3:
 331         return s->control[3];
 332     case LCCR4:
 333         return s->control[4];
 334     case LCCR5:
 335         return s->control[5];
 336
 337     case OVL1C1:
 338         return s->ovl1c[0];
 339     case OVL1C2:
 340         return s->ovl1c[1];
 341     case OVL2C1:
 342         return s->ovl2c[0];
 343     case OVL2C2:
 344         return s->ovl2c[1];
 345
 346     case CCR:
 347         return s->ccr;
 348
 349     case CMDCR:
 350         return s->cmdcr;
 351
 352     case TRGBR:
 353         return s->trgbr;
 354     case TCR:
 355         return s->tcr;
 356
 357     case 0x200 ... 0x1000:      /* DMA per-channel registers */
 358         ch = (offset - 0x200) >> 4;
 359         if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
 360             goto fail;
 361
 362         switch (offset & 0xf) {
 363         case DMA_FDADR:
 364             return s->dma_ch[ch].descriptor;
 365         case DMA_FSADR:
 366             return s->dma_ch[ch].source;
 367         case DMA_FIDR:
 368             return s->dma_ch[ch].id;
 369         case DMA_LDCMD:
 370             return s->dma_ch[ch].command;
 371         default:
 372             goto fail;
 373         }
 374
 375     case FBR0:
 376         return s->dma_ch[0].branch;
 377     case FBR1:
 378         return s->dma_ch[1].branch;
 379     case FBR2:
 380         return s->dma_ch[2].branch;
 381     case FBR3:
 382         return s->dma_ch[3].branch;
 383     case FBR4:
 384         return s->dma_ch[4].branch;
 385     case FBR5:
 386         return s->dma_ch[5].branch;
 387     case FBR6:
 388         return s->dma_ch[6].branch;
 389
 390     case BSCNTR:
 391         return s->bscntr;
 392
 393     case PRSR:
 394         return 0;
 395
 396     case LCSR0:
 397         return s->status[0];
 398     case LCSR1:
 399         return s->status[1];
 400     case LIIDR:
 401         return s->liidr;
 402
 403     default:
 404     fail:
 405         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 406     }
 407
 408     return 0;
 409 }
 410
 411 static void pxa2xx_lcdc_write(void *opaque,
 412                 target_phys_addr_t offset, uint32_t value)
 413 {
 414     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 415     int ch;
 416
 417     switch (offset) {
 418     case LCCR0:
 419         /* ACK Quick Disable done */
 420         if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
 421             s->status[0] |= LCSR0_QD;
 422
 423         if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
 424             printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
 425
 426         if ((s->control[3] & LCCR3_API) &&
 427                 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
 428             s->status[0] |= LCSR0_ABC;
 429
 430         s->control[0] = value & 0x07ffffff;
 431         pxa2xx_lcdc_int_update(s);
 432
 433         s->dma_ch[0].up = !!(value & LCCR0_ENB);
 434         s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
 435         break;
 436
 437     case LCCR1:
 438         s->control[1] = value;
 439         break;
 440
 441     case LCCR2:
 442         s->control[2] = value;
 443         break;
 444
 445     case LCCR3:
 446         s->control[3] = value & 0xefffffff;
 447         s->bpp = LCCR3_BPP(value);
 448         break;
 449
 450     case LCCR4:
 451         s->control[4] = value & 0x83ff81ff;
 452         break;
 453
 454     case LCCR5:
 455         s->control[5] = value & 0x3f3f3f3f;
 456         break;
 457
 458     case OVL1C1:
 459         if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
 460             printf("%s: Overlay 1 not supported\n", __FUNCTION__);
 461
 462         s->ovl1c[0] = value & 0x80ffffff;
 463         s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
 464         break;
 465
 466     case OVL1C2:
 467         s->ovl1c[1] = value & 0x000fffff;
 468         break;
 469
 470     case OVL2C1:
 471         if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
 472             printf("%s: Overlay 2 not supported\n", __FUNCTION__);
 473
 474         s->ovl2c[0] = value & 0x80ffffff;
 475         s->dma_ch[2].up = !!(value & OVLC1_EN);
 476         s->dma_ch[3].up = !!(value & OVLC1_EN);
 477         s->dma_ch[4].up = !!(value & OVLC1_EN);
 478         break;
 479
 480     case OVL2C2:
 481         s->ovl2c[1] = value & 0x007fffff;
 482         break;
 483
 484     case CCR:
 485         if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
 486             printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
 487
 488         s->ccr = value & 0x81ffffe7;
 489         s->dma_ch[5].up = !!(value & CCR_CEN);
 490         break;
 491
 492     case CMDCR:
 493         s->cmdcr = value & 0xff;
 494         break;
 495
 496     case TRGBR:
 497         s->trgbr = value & 0x00ffffff;
 498         break;
 499
 500     case TCR:
 501         s->tcr = value & 0x7fff;
 502         break;
 503
 504     case 0x200 ... 0x1000:      /* DMA per-channel registers */
 505         ch = (offset - 0x200) >> 4;
 506         if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
 507             goto fail;
 508
 509         switch (offset & 0xf) {
 510         case DMA_FDADR:
 511             s->dma_ch[ch].descriptor = value & 0xfffffff0;
 512             break;
 513
 514         default:
 515             goto fail;
 516         }
 517         break;
 518
 519     case FBR0:
 520         s->dma_ch[0].branch = value & 0xfffffff3;
 521         break;
 522     case FBR1:
 523         s->dma_ch[1].branch = value & 0xfffffff3;
 524         break;
 525     case FBR2:
 526         s->dma_ch[2].branch = value & 0xfffffff3;
 527         break;
 528     case FBR3:
 529         s->dma_ch[3].branch = value & 0xfffffff3;
 530         break;
 531     case FBR4:
 532         s->dma_ch[4].branch = value & 0xfffffff3;
 533         break;
 534     case FBR5:
 535         s->dma_ch[5].branch = value & 0xfffffff3;
 536         break;
 537     case FBR6:
 538         s->dma_ch[6].branch = value & 0xfffffff3;
 539         break;
 540
 541     case BSCNTR:
 542         s->bscntr = value & 0xf;
 543         break;
 544
 545     case PRSR:
 546         break;
 547
 548     case LCSR0:
 549         s->status[0] &= ~(value & 0xfff);
 550         if (value & LCSR0_BER)
 551             s->status[0] &= ~LCSR0_BERCH(7);
 552         break;
 553
 554     case LCSR1:
 555         s->status[1] &= ~(value & 0x3e3f3f);
 556         break;
 557
 558     default:
 559     fail:
 560         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 561     }
 562 }
 563
 564 static CPUReadMemoryFunc * const pxa2xx_lcdc_readfn[] = {
 565     pxa2xx_lcdc_read,
 566     pxa2xx_lcdc_read,
 567     pxa2xx_lcdc_read
 568 };
 569
 570 static CPUWriteMemoryFunc * const pxa2xx_lcdc_writefn[] = {
 571     pxa2xx_lcdc_write,
 572     pxa2xx_lcdc_write,
 573     pxa2xx_lcdc_write
 574 };
 575
 576 /* Load new palette for a given DMA channel, convert to internal format */
 577 static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
 578 {
 579     int i, n, format, r, g, b, alpha;
 580     uint32_t *dest, *src;
 581     s->pal_for = LCCR4_PALFOR(s->control[4]);
 582     format = s->pal_for;
 583
 584     switch (bpp) {
 585     case pxa_lcdc_2bpp:
 586         n = 4;
 587         break;
 588     case pxa_lcdc_4bpp:
 589         n = 16;
 590         break;
 591     case pxa_lcdc_8bpp:
 592         n = 256;
 593         break;
 594     default:
 595         format = 0;
 596         return;
 597     }
 598
 599     src = (uint32_t *) s->dma_ch[ch].pbuffer;
 600     dest = (uint32_t *) s->dma_ch[ch].palette;
 601     alpha = r = g = b = 0;
 602
 603     for (i = 0; i < n; i ++) {
 604         switch (format) {
 605         case 0: /* 16 bpp, no transparency */
 606             alpha = 0;
 607             if (s->control[0] & LCCR0_CMS)
 608                 r = g = b = *src & 0xff;
 609             else {
 610                 r = (*src & 0xf800) >> 8;
 611                 g = (*src & 0x07e0) >> 3;
 612                 b = (*src & 0x001f) << 3;
 613             }
 614             break;
 615         case 1: /* 16 bpp plus transparency */
 616             alpha = *src & (1 << 24);
 617             if (s->control[0] & LCCR0_CMS)
 618                 r = g = b = *src & 0xff;
 619             else {
 620                 r = (*src & 0xf800) >> 8;
 621                 g = (*src & 0x07e0) >> 3;
 622                 b = (*src & 0x001f) << 3;
 623             }
 624             break;
 625         case 2: /* 18 bpp plus transparency */
 626             alpha = *src & (1 << 24);
 627             if (s->control[0] & LCCR0_CMS)
 628                 r = g = b = *src & 0xff;
 629             else {
 630                 r = (*src & 0xf80000) >> 16;
 631                 g = (*src & 0x00fc00) >> 8;
 632                 b = (*src & 0x0000f8);
 633             }
 634             break;
 635         case 3: /* 24 bpp plus transparency */
 636             alpha = *src & (1 << 24);
 637             if (s->control[0] & LCCR0_CMS)
 638                 r = g = b = *src & 0xff;
 639             else {
 640                 r = (*src & 0xff0000) >> 16;
 641                 g = (*src & 0x00ff00) >> 8;
 642                 b = (*src & 0x0000ff);
 643             }
 644             break;
 645         }
 646         switch (ds_get_bits_per_pixel(s->ds)) {
 647         case 8:
 648             *dest = rgb_to_pixel8(r, g, b) | alpha;
 649             break;
 650         case 15:
 651             *dest = rgb_to_pixel15(r, g, b) | alpha;
 652             break;
 653         case 16:
 654             *dest = rgb_to_pixel16(r, g, b) | alpha;
 655             break;
 656         case 24:
 657             *dest = rgb_to_pixel24(r, g, b) | alpha;
 658             break;
 659         case 32:
 660             *dest = rgb_to_pixel32(r, g, b) | alpha;
 661             break;
 662         }
 663         src ++;
 664         dest ++;
 665     }
 666 }
 667
 668 static void pxa2xx_lcdc_dma0_redraw_horiz(PXA2xxLCDState *s,
 669                 target_phys_addr_t addr, int *miny, int *maxy)
 670 {
 671     int src_width, dest_width;
 672     drawfn fn = NULL;
 673     if (s->dest_width)
 674         fn = s->line_fn[s->transp][s->bpp];
 675     if (!fn)
 676         return;
 677
 678     src_width = (s->xres + 3) & ~3;     /* Pad to a 4 pixels multiple */
 679     if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
 680         src_width *= 3;
 681     else if (s->bpp > pxa_lcdc_16bpp)
 682         src_width *= 4;
 683     else if (s->bpp > pxa_lcdc_8bpp)
 684         src_width *= 2;
 685
 686     dest_width = s->xres * s->dest_width;
 687     *miny = 0;
 688     framebuffer_update_display(s->ds,
 689                                addr, s->xres, s->yres,
 690                                src_width, dest_width, s->dest_width,
 691                                s->invalidated,
 692                                fn, s->dma_ch[0].palette, miny, maxy);
 693 }
 694
 695 static void pxa2xx_lcdc_dma0_redraw_vert(PXA2xxLCDState *s,
 696                target_phys_addr_t addr, int *miny, int *maxy)
 697 {
 698     int src_width, dest_width;
 699     drawfn fn = NULL;
 700     if (s->dest_width)
 701         fn = s->line_fn[s->transp][s->bpp];
 702     if (!fn)
 703         return;
 704
 705     src_width = (s->xres + 3) & ~3;     /* Pad to a 4 pixels multiple */
 706     if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
 707         src_width *= 3;
 708     else if (s->bpp > pxa_lcdc_16bpp)
 709         src_width *= 4;
 710     else if (s->bpp > pxa_lcdc_8bpp)
 711         src_width *= 2;
 712
 713     dest_width = s->yres * s->dest_width;
 714     *miny = 0;
 715     framebuffer_update_display(s->ds,
 716                                addr, s->xres, s->yres,
 717                                src_width, s->dest_width, -dest_width,
 718                                s->invalidated,
 719                                fn, s->dma_ch[0].palette,
 720                                miny, maxy);
 721 }
 722
 723 static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
 724 {
 725     int width, height;
 726     if (!(s->control[0] & LCCR0_ENB))
 727         return;
 728
 729     width = LCCR1_PPL(s->control[1]) + 1;
 730     height = LCCR2_LPP(s->control[2]) + 1;
 731
 732     if (width != s->xres || height != s->yres) {
 733         if (s->orientation)
 734             qemu_console_resize(s->ds, height, width);
 735         else
 736             qemu_console_resize(s->ds, width, height);
 737         s->invalidated = 1;
 738         s->xres = width;
 739         s->yres = height;
 740     }
 741 }
 742
 743 static void pxa2xx_update_display(void *opaque)
 744 {
 745     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 746     target_phys_addr_t fbptr;
 747     int miny, maxy;
 748     int ch;
 749     if (!(s->control[0] & LCCR0_ENB))
 750         return;
 751
 752     pxa2xx_descriptor_load(s);
 753
 754     pxa2xx_lcdc_resize(s);
 755     miny = s->yres;
 756     maxy = 0;
 757     s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
 758     /* Note: With overlay planes the order depends on LCCR0 bit 25.  */
 759     for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
 760         if (s->dma_ch[ch].up) {
 761             if (!s->dma_ch[ch].source) {
 762                 pxa2xx_dma_ber_set(s, ch);
 763                 continue;
 764             }
 765             fbptr = s->dma_ch[ch].source;
 766             if (!(fbptr >= PXA2XX_SDRAM_BASE &&
 767                     fbptr <= PXA2XX_SDRAM_BASE + ram_size)) {
 768                 pxa2xx_dma_ber_set(s, ch);
 769                 continue;
 770             }
 771
 772             if (s->dma_ch[ch].command & LDCMD_PAL) {
 773                 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
 774                     MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
 775                         sizeof(s->dma_ch[ch].pbuffer)));
 776                 pxa2xx_palette_parse(s, ch, s->bpp);
 777             } else {
 778                 /* Do we need to reparse palette */
 779                 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
 780                     pxa2xx_palette_parse(s, ch, s->bpp);
 781
 782                 /* ACK frame start */
 783                 pxa2xx_dma_sof_set(s, ch);
 784
 785                 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
 786                 s->invalidated = 0;
 787
 788                 /* ACK frame completed */
 789                 pxa2xx_dma_eof_set(s, ch);
 790             }
 791         }
 792
 793     if (s->control[0] & LCCR0_DIS) {
 794         /* ACK last frame completed */
 795         s->control[0] &= ~LCCR0_ENB;
 796         s->status[0] |= LCSR0_LDD;
 797     }
 798
 799     if (miny >= 0) {
 800         if (s->orientation)
 801             dpy_update(s->ds, miny, 0, maxy - miny, s->xres);
 802         else
 803             dpy_update(s->ds, 0, miny, s->xres, maxy - miny);
 804     }
 805     pxa2xx_lcdc_int_update(s);
 806
 807     qemu_irq_raise(s->vsync_cb);
 808 }
 809
 810 static void pxa2xx_invalidate_display(void *opaque)
 811 {
 812     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 813     s->invalidated = 1;
 814 }
 815
 816 static void pxa2xx_screen_dump(void *opaque, const char *filename)
 817 {
 818     /* TODO */
 819 }
 820
 821 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
 822 {
 823     PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
 824
 825     if (angle) {
 826         s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
 827     } else {
 828         s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
 829     }
 830
 831     s->orientation = angle;
 832     s->xres = s->yres = -1;
 833     pxa2xx_lcdc_resize(s);
 834 }
 835
 836 static const VMStateDescription vmstate_dma_channel = {
 837     .name = "dma_channel",
 838     .version_id = 0,
 839     .minimum_version_id = 0,
 840     .minimum_version_id_old = 0,
 841     .fields      = (VMStateField[]) {
 842         VMSTATE_UINTTL(branch, struct DMAChannel),
 843         VMSTATE_UINT8(up, struct DMAChannel),
 844         VMSTATE_BUFFER(pbuffer, struct DMAChannel),
 845         VMSTATE_UINTTL(descriptor, struct DMAChannel),
 846         VMSTATE_UINTTL(source, struct DMAChannel),
 847         VMSTATE_UINT32(id, struct DMAChannel),
 848         VMSTATE_UINT32(command, struct DMAChannel),
 849         VMSTATE_END_OF_LIST()
 850     }
 851 };
 852
 853 static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
 854 {
 855     PXA2xxLCDState *s = opaque;
 856
 857     s->bpp = LCCR3_BPP(s->control[3]);
 858     s->xres = s->yres = s->pal_for = -1;
 859
 860     return 0;
 861 }
 862
 863 static const VMStateDescription vmstate_pxa2xx_lcdc = {
 864     .name = "pxa2xx_lcdc",
 865     .version_id = 0,
 866     .minimum_version_id = 0,
 867     .minimum_version_id_old = 0,
 868     .post_load = pxa2xx_lcdc_post_load,
 869     .fields      = (VMStateField[]) {
 870         VMSTATE_INT32(irqlevel, PXA2xxLCDState),
 871         VMSTATE_INT32(transp, PXA2xxLCDState),
 872         VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
 873         VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
 874         VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
 875         VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
 876         VMSTATE_UINT32(ccr, PXA2xxLCDState),
 877         VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
 878         VMSTATE_UINT32(trgbr, PXA2xxLCDState),
 879         VMSTATE_UINT32(tcr, PXA2xxLCDState),
 880         VMSTATE_UINT32(liidr, PXA2xxLCDState),
 881         VMSTATE_UINT8(bscntr, PXA2xxLCDState),
 882         VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
 883                              vmstate_dma_channel, struct DMAChannel),
 884         VMSTATE_END_OF_LIST()
 885     }
 886 };
 887
 888 #define BITS 8
 889 #include "pxa2xx_template.h"
 890 #define BITS 15
 891 #include "pxa2xx_template.h"
 892 #define BITS 16
 893 #include "pxa2xx_template.h"
 894 #define BITS 24
 895 #include "pxa2xx_template.h"
 896 #define BITS 32
 897 #include "pxa2xx_template.h"
 898
 899 PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
 900 {
 901     int iomemtype;
 902     PXA2xxLCDState *s;
 903
 904     s = (PXA2xxLCDState *) qemu_mallocz(sizeof(PXA2xxLCDState));
 905     s->invalidated = 1;
 906     s->irq = irq;
 907
 908     pxa2xx_lcdc_orientation(s, graphic_rotate);
 909
 910     iomemtype = cpu_register_io_memory(pxa2xx_lcdc_readfn,
 911                     pxa2xx_lcdc_writefn, s, DEVICE_NATIVE_ENDIAN);
 912     cpu_register_physical_memory(base, 0x00100000, iomemtype);
 913
 914     s->ds = graphic_console_init(pxa2xx_update_display,
 915                                  pxa2xx_invalidate_display,
 916                                  pxa2xx_screen_dump, NULL, s);
 917
 918     switch (ds_get_bits_per_pixel(s->ds)) {
 919     case 0:
 920         s->dest_width = 0;
 921         break;
 922     case 8:
 923         s->line_fn[0] = pxa2xx_draw_fn_8;
 924         s->line_fn[1] = pxa2xx_draw_fn_8t;
 925         s->dest_width = 1;
 926         break;
 927     case 15:
 928         s->line_fn[0] = pxa2xx_draw_fn_15;
 929         s->line_fn[1] = pxa2xx_draw_fn_15t;
 930         s->dest_width = 2;
 931         break;
 932     case 16:
 933         s->line_fn[0] = pxa2xx_draw_fn_16;
 934         s->line_fn[1] = pxa2xx_draw_fn_16t;
 935         s->dest_width = 2;
 936         break;
 937     case 24:
 938         s->line_fn[0] = pxa2xx_draw_fn_24;
 939         s->line_fn[1] = pxa2xx_draw_fn_24t;
 940         s->dest_width = 3;
 941         break;
 942     case 32:
 943         s->line_fn[0] = pxa2xx_draw_fn_32;
 944         s->line_fn[1] = pxa2xx_draw_fn_32t;
 945         s->dest_width = 4;
 946         break;
 947     default:
 948         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
 949         exit(1);
 950     }
 951
 952     vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
 953
 954     return s;
 955 }
 956
 957 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
 958 {
 959     s->vsync_cb = handler;
 960 }