target-arm/internals.h

   1 /*
   2  * QEMU ARM CPU -- internal functions and types
   3  *
   4  * Copyright (c) 2014 Linaro Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  *
  20  * This header defines functions, types, etc which need to be shared
  21  * between different source files within target-arm/ but which are
  22  * private to it and not required by the rest of QEMU.
  23  */
  24
  25 #ifndef TARGET_ARM_INTERNALS_H
  26 #define TARGET_ARM_INTERNALS_H
  27
  28 /* register banks for CPU modes */
  29 #define BANK_USRSYS 0
  30 #define BANK_SVC    1
  31 #define BANK_ABT    2
  32 #define BANK_UND    3
  33 #define BANK_IRQ    4
  34 #define BANK_FIQ    5
  35 #define BANK_HYP    6
  36 #define BANK_MON    7
  37
  38 static inline bool excp_is_internal(int excp)
  39 {
  40     /* Return true if this exception number represents a QEMU-internal
  41      * exception that will not be passed to the guest.
  42      */
  43     return excp == EXCP_INTERRUPT
  44         || excp == EXCP_HLT
  45         || excp == EXCP_DEBUG
  46         || excp == EXCP_HALTED
  47         || excp == EXCP_EXCEPTION_EXIT
  48         || excp == EXCP_KERNEL_TRAP
  49         || excp == EXCP_SEMIHOST
  50         || excp == EXCP_STREX;
  51 }
  52
  53 /* Exception names for debug logging; note that not all of these
  54  * precisely correspond to architectural exceptions.
  55  */
  56 static const char * const excnames[] = {
  57     [EXCP_UDEF] = "Undefined Instruction",
  58     [EXCP_SWI] = "SVC",
  59     [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
  60     [EXCP_DATA_ABORT] = "Data Abort",
  61     [EXCP_IRQ] = "IRQ",
  62     [EXCP_FIQ] = "FIQ",
  63     [EXCP_BKPT] = "Breakpoint",
  64     [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
  65     [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
  66     [EXCP_STREX] = "QEMU intercept of STREX",
  67     [EXCP_HVC] = "Hypervisor Call",
  68     [EXCP_HYP_TRAP] = "Hypervisor Trap",
  69     [EXCP_SMC] = "Secure Monitor Call",
  70     [EXCP_VIRQ] = "Virtual IRQ",
  71     [EXCP_VFIQ] = "Virtual FIQ",
  72     [EXCP_SEMIHOST] = "Semihosting call",
  73 };
  74
  75 static inline void arm_log_exception(int idx)
  76 {
  77     if (qemu_loglevel_mask(CPU_LOG_INT)) {
  78         const char *exc = NULL;
  79
  80         if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
  81             exc = excnames[idx];
  82         }
  83         if (!exc) {
  84             exc = "unknown";
  85         }
  86         qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
  87     }
  88 }
  89
  90 /* Scale factor for generic timers, ie number of ns per tick.
  91  * This gives a 62.5MHz timer.
  92  */
  93 #define GTIMER_SCALE 16
  94
  95 /*
  96  * For AArch64, map a given EL to an index in the banked_spsr array.
  97  * Note that this mapping and the AArch32 mapping defined in bank_number()
  98  * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
  99  * mandated mapping between each other.
 100  */
 101 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
 102 {
 103     static const unsigned int map[4] = {
 104         [1] = BANK_SVC, /* EL1.  */
 105         [2] = BANK_HYP, /* EL2.  */
 106         [3] = BANK_MON, /* EL3.  */
 107     };
 108     assert(el >= 1 && el <= 3);
 109     return map[el];
 110 }
 111
 112 /* Map CPU modes onto saved register banks.  */
 113 static inline int bank_number(int mode)
 114 {
 115     switch (mode) {
 116     case ARM_CPU_MODE_USR:
 117     case ARM_CPU_MODE_SYS:
 118         return BANK_USRSYS;
 119     case ARM_CPU_MODE_SVC:
 120         return BANK_SVC;
 121     case ARM_CPU_MODE_ABT:
 122         return BANK_ABT;
 123     case ARM_CPU_MODE_UND:
 124         return BANK_UND;
 125     case ARM_CPU_MODE_IRQ:
 126         return BANK_IRQ;
 127     case ARM_CPU_MODE_FIQ:
 128         return BANK_FIQ;
 129     case ARM_CPU_MODE_HYP:
 130         return BANK_HYP;
 131     case ARM_CPU_MODE_MON:
 132         return BANK_MON;
 133     }
 134     g_assert_not_reached();
 135 }
 136
 137 void switch_mode(CPUARMState *, int);
 138 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 139 void arm_translate_init(void);
 140
 141 enum arm_fprounding {
 142     FPROUNDING_TIEEVEN,
 143     FPROUNDING_POSINF,
 144     FPROUNDING_NEGINF,
 145     FPROUNDING_ZERO,
 146     FPROUNDING_TIEAWAY,
 147     FPROUNDING_ODD
 148 };
 149
 150 int arm_rmode_to_sf(int rmode);
 151
 152 static inline void aarch64_save_sp(CPUARMState *env, int el)
 153 {
 154     if (env->pstate & PSTATE_SP) {
 155         env->sp_el[el] = env->xregs[31];
 156     } else {
 157         env->sp_el[0] = env->xregs[31];
 158     }
 159 }
 160
 161 static inline void aarch64_restore_sp(CPUARMState *env, int el)
 162 {
 163     if (env->pstate & PSTATE_SP) {
 164         env->xregs[31] = env->sp_el[el];
 165     } else {
 166         env->xregs[31] = env->sp_el[0];
 167     }
 168 }
 169
 170 static inline void update_spsel(CPUARMState *env, uint32_t imm)
 171 {
 172     unsigned int cur_el = arm_current_el(env);
 173     /* Update PSTATE SPSel bit; this requires us to update the
 174      * working stack pointer in xregs[31].
 175      */
 176     if (!((imm ^ env->pstate) & PSTATE_SP)) {
 177         return;
 178     }
 179     aarch64_save_sp(env, cur_el);
 180     env->pstate = deposit32(env->pstate, 0, 1, imm);
 181
 182     /* We rely on illegal updates to SPsel from EL0 to get trapped
 183      * at translation time.
 184      */
 185     assert(cur_el >= 1 && cur_el <= 3);
 186     aarch64_restore_sp(env, cur_el);
 187 }
 188
 189 /*
 190  * arm_pamax
 191  * @cpu: ARMCPU
 192  *
 193  * Returns the implementation defined bit-width of physical addresses.
 194  * The ARMv8 reference manuals refer to this as PAMax().
 195  */
 196 static inline unsigned int arm_pamax(ARMCPU *cpu)
 197 {
 198     static const unsigned int pamax_map[] = {
 199         [0] = 32,
 200         [1] = 36,
 201         [2] = 40,
 202         [3] = 42,
 203         [4] = 44,
 204         [5] = 48,
 205     };
 206     unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
 207
 208     /* id_aa64mmfr0 is a read-only register so values outside of the
 209      * supported mappings can be considered an implementation error.  */
 210     assert(parange < ARRAY_SIZE(pamax_map));
 211     return pamax_map[parange];
 212 }
 213
 214 /* Return true if extended addresses are enabled.
 215  * This is always the case if our translation regime is 64 bit,
 216  * but depends on TTBCR.EAE for 32 bit.
 217  */
 218 static inline bool extended_addresses_enabled(CPUARMState *env)
 219 {
 220     TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
 221     return arm_el_is_aa64(env, 1) ||
 222            (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
 223 }
 224
 225 /* Valid Syndrome Register EC field values */
 226 enum arm_exception_class {
 227     EC_UNCATEGORIZED          = 0x00,
 228     EC_WFX_TRAP               = 0x01,
 229     EC_CP15RTTRAP             = 0x03,
 230     EC_CP15RRTTRAP            = 0x04,
 231     EC_CP14RTTRAP             = 0x05,
 232     EC_CP14DTTRAP             = 0x06,
 233     EC_ADVSIMDFPACCESSTRAP    = 0x07,
 234     EC_FPIDTRAP               = 0x08,
 235     EC_CP14RRTTRAP            = 0x0c,
 236     EC_ILLEGALSTATE           = 0x0e,
 237     EC_AA32_SVC               = 0x11,
 238     EC_AA32_HVC               = 0x12,
 239     EC_AA32_SMC               = 0x13,
 240     EC_AA64_SVC               = 0x15,
 241     EC_AA64_HVC               = 0x16,
 242     EC_AA64_SMC               = 0x17,
 243     EC_SYSTEMREGISTERTRAP     = 0x18,
 244     EC_INSNABORT              = 0x20,
 245     EC_INSNABORT_SAME_EL      = 0x21,
 246     EC_PCALIGNMENT            = 0x22,
 247     EC_DATAABORT              = 0x24,
 248     EC_DATAABORT_SAME_EL      = 0x25,
 249     EC_SPALIGNMENT            = 0x26,
 250     EC_AA32_FPTRAP            = 0x28,
 251     EC_AA64_FPTRAP            = 0x2c,
 252     EC_SERROR                 = 0x2f,
 253     EC_BREAKPOINT             = 0x30,
 254     EC_BREAKPOINT_SAME_EL     = 0x31,
 255     EC_SOFTWARESTEP           = 0x32,
 256     EC_SOFTWARESTEP_SAME_EL   = 0x33,
 257     EC_WATCHPOINT             = 0x34,
 258     EC_WATCHPOINT_SAME_EL     = 0x35,
 259     EC_AA32_BKPT              = 0x38,
 260     EC_VECTORCATCH            = 0x3a,
 261     EC_AA64_BKPT              = 0x3c,
 262 };
 263
 264 #define ARM_EL_EC_SHIFT 26
 265 #define ARM_EL_IL_SHIFT 25
 266 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
 267
 268 /* Utility functions for constructing various kinds of syndrome value.
 269  * Note that in general we follow the AArch64 syndrome values; in a
 270  * few cases the value in HSR for exceptions taken to AArch32 Hyp
 271  * mode differs slightly, so if we ever implemented Hyp mode then the
 272  * syndrome value would need some massaging on exception entry.
 273  * (One example of this is that AArch64 defaults to IL bit set for
 274  * exceptions which don't specifically indicate information about the
 275  * trapping instruction, whereas AArch32 defaults to IL bit clear.)
 276  */
 277 static inline uint32_t syn_uncategorized(void)
 278 {
 279     return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 280 }
 281
 282 static inline uint32_t syn_aa64_svc(uint32_t imm16)
 283 {
 284     return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 285 }
 286
 287 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
 288 {
 289     return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 290 }
 291
 292 static inline uint32_t syn_aa64_smc(uint32_t imm16)
 293 {
 294     return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 295 }
 296
 297 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
 298 {
 299     return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 300         | (is_16bit ? 0 : ARM_EL_IL);
 301 }
 302
 303 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
 304 {
 305     return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 306 }
 307
 308 static inline uint32_t syn_aa32_smc(void)
 309 {
 310     return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
 311 }
 312
 313 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
 314 {
 315     return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
 316 }
 317
 318 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
 319 {
 320     return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
 321         | (is_16bit ? 0 : ARM_EL_IL);
 322 }
 323
 324 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
 325                                            int crn, int crm, int rt,
 326                                            int isread)
 327 {
 328     return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
 329         | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
 330         | (crm << 1) | isread;
 331 }
 332
 333 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
 334                                         int crn, int crm, int rt, int isread,
 335                                         bool is_16bit)
 336 {
 337     return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
 338         | (is_16bit ? 0 : ARM_EL_IL)
 339         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 340         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 341 }
 342
 343 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
 344                                         int crn, int crm, int rt, int isread,
 345                                         bool is_16bit)
 346 {
 347     return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
 348         | (is_16bit ? 0 : ARM_EL_IL)
 349         | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
 350         | (crn << 10) | (rt << 5) | (crm << 1) | isread;
 351 }
 352
 353 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
 354                                          int rt, int rt2, int isread,
 355                                          bool is_16bit)
 356 {
 357     return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
 358         | (is_16bit ? 0 : ARM_EL_IL)
 359         | (cv << 24) | (cond << 20) | (opc1 << 16)
 360         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 361 }
 362
 363 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
 364                                          int rt, int rt2, int isread,
 365                                          bool is_16bit)
 366 {
 367     return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
 368         | (is_16bit ? 0 : ARM_EL_IL)
 369         | (cv << 24) | (cond << 20) | (opc1 << 16)
 370         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 371 }
 372
 373 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
 374 {
 375     return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
 376         | (is_16bit ? 0 : ARM_EL_IL)
 377         | (cv << 24) | (cond << 20);
 378 }
 379
 380 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
 381 {
 382     return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 383         | (ea << 9) | (s1ptw << 7) | fsc;
 384 }
 385
 386 static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
 387                                       int wnr, int fsc)
 388 {
 389     return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 390         | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
 391 }
 392
 393 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
 394 {
 395     return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 396         | (isv << 24) | (ex << 6) | 0x22;
 397 }
 398
 399 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
 400 {
 401     return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 402         | (cm << 8) | (wnr << 6) | 0x22;
 403 }
 404
 405 static inline uint32_t syn_breakpoint(int same_el)
 406 {
 407     return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
 408         | ARM_EL_IL | 0x22;
 409 }
 410
 411 static inline uint32_t syn_wfx(int cv, int cond, int ti)
 412 {
 413     return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
 414            (cv << 24) | (cond << 20) | ti;
 415 }
 416
 417 /* Update a QEMU watchpoint based on the information the guest has set in the
 418  * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
 419  */
 420 void hw_watchpoint_update(ARMCPU *cpu, int n);
 421 /* Update the QEMU watchpoints for every guest watchpoint. This does a
 422  * complete delete-and-reinstate of the QEMU watchpoint list and so is
 423  * suitable for use after migration or on reset.
 424  */
 425 void hw_watchpoint_update_all(ARMCPU *cpu);
 426 /* Update a QEMU breakpoint based on the information the guest has set in the
 427  * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
 428  */
 429 void hw_breakpoint_update(ARMCPU *cpu, int n);
 430 /* Update the QEMU breakpoints for every guest breakpoint. This does a
 431  * complete delete-and-reinstate of the QEMU breakpoint list and so is
 432  * suitable for use after migration or on reset.
 433  */
 434 void hw_breakpoint_update_all(ARMCPU *cpu);
 435
 436 /* Callback function for checking if a watchpoint should trigger. */
 437 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
 438
 439 /* Callback function for when a watchpoint or breakpoint triggers. */
 440 void arm_debug_excp_handler(CPUState *cs);
 441
 442 #ifdef CONFIG_USER_ONLY
 443 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
 444 {
 445     return false;
 446 }
 447 #else
 448 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
 449 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
 450 /* Actually handle a PSCI call */
 451 void arm_handle_psci_call(ARMCPU *cpu);
 452 #endif
 453
 454 /**
 455  * ARMMMUFaultInfo: Information describing an ARM MMU Fault
 456  * @s2addr: Address that caused a fault at stage 2
 457  * @stage2: True if we faulted at stage 2
 458  * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
 459  */
 460 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 461 struct ARMMMUFaultInfo {
 462     target_ulong s2addr;
 463     bool stage2;
 464     bool s1ptw;
 465 };
 466
 467 /* Do a page table walk and add page to TLB if possible */
 468 bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
 469                   uint32_t *fsr, ARMMMUFaultInfo *fi);
 470
 471 /* Return true if the stage 1 translation regime is using LPAE format page
 472  * tables */
 473 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
 474
 475 /* Raise a data fault alignment exception for the specified virtual address */
 476 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,
 477                                  int is_user, uintptr_t retaddr);
 478
 479 #endif