hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/pci/pci.h"
  27 #include "hw/pci-host/apb.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/char/serial.h"
  30 #include "hw/timer/m48t59.h"
  31 #include "hw/block/fdc.h"
  32 #include "net/net.h"
  33 #include "qemu/timer.h"
  34 #include "sysemu/sysemu.h"
  35 #include "hw/boards.h"
  36 #include "hw/nvram/openbios_firmware_abi.h"
  37 #include "hw/nvram/fw_cfg.h"
  38 #include "hw/sysbus.h"
  39 #include "hw/ide.h"
  40 #include "hw/loader.h"
  41 #include "elf.h"
  42 #include "sysemu/block-backend.h"
  43 #include "exec/address-spaces.h"
  44
  45 //#define DEBUG_IRQ
  46 //#define DEBUG_EBUS
  47 //#define DEBUG_TIMER
  48
  49 #ifdef DEBUG_IRQ
  50 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  51     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  52 #else
  53 #define CPUIRQ_DPRINTF(fmt, ...)
  54 #endif
  55
  56 #ifdef DEBUG_EBUS
  57 #define EBUS_DPRINTF(fmt, ...)                                  \
  58     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  59 #else
  60 #define EBUS_DPRINTF(fmt, ...)
  61 #endif
  62
  63 #ifdef DEBUG_TIMER
  64 #define TIMER_DPRINTF(fmt, ...)                                  \
  65     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  66 #else
  67 #define TIMER_DPRINTF(fmt, ...)
  68 #endif
  69
  70 #define KERNEL_LOAD_ADDR     0x00404000
  71 #define CMDLINE_ADDR         0x003ff000
  72 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  73 #define PROM_VADDR           0x000ffd00000ULL
  74 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  75 #define APB_MEM_BASE         0x1ff00000000ULL
  76 #define APB_PCI_IO_BASE      (APB_SPECIAL_BASE + 0x02000000ULL)
  77 #define PROM_FILENAME        "openbios-sparc64"
  78 #define NVRAM_SIZE           0x2000
  79 #define MAX_IDE_BUS          2
  80 #define BIOS_CFG_IOPORT      0x510
  81 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  82 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  83 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  84
  85 #define IVEC_MAX             0x40
  86
  87 #define TICK_MAX             0x7fffffffffffffffULL
  88
  89 struct hwdef {
  90     const char * const default_cpu_model;
  91     uint16_t machine_id;
  92     uint64_t prom_addr;
  93     uint64_t console_serial_base;
  94 };
  95
  96 typedef struct EbusState {
  97     PCIDevice pci_dev;
  98     MemoryRegion bar0;
  99     MemoryRegion bar1;
 100 } EbusState;
 101
 102 void DMA_init(ISABus *bus, int high_page_enable)
 103 {
 104 }
 105
 106 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 107                             Error **errp)
 108 {
 109     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 110 }
 111
 112 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 113                                   const char *arch, ram_addr_t RAM_size,
 114                                   const char *boot_devices,
 115                                   uint32_t kernel_image, uint32_t kernel_size,
 116                                   const char *cmdline,
 117                                   uint32_t initrd_image, uint32_t initrd_size,
 118                                   uint32_t NVRAM_image,
 119                                   int width, int height, int depth,
 120                                   const uint8_t *macaddr)
 121 {
 122     unsigned int i;
 123     uint32_t start, end;
 124     uint8_t image[0x1ff0];
 125     struct OpenBIOS_nvpart_v1 *part_header;
 126     NvramClass *k = NVRAM_GET_CLASS(nvram);
 127
 128     memset(image, '\0', sizeof(image));
 129
 130     start = 0;
 131
 132     // OpenBIOS nvram variables
 133     // Variable partition
 134     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 135     part_header->signature = OPENBIOS_PART_SYSTEM;
 136     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 137
 138     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 139     for (i = 0; i < nb_prom_envs; i++)
 140         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 141
 142     // End marker
 143     image[end++] = '\0';
 144
 145     end = start + ((end - start + 15) & ~15);
 146     OpenBIOS_finish_partition(part_header, end - start);
 147
 148     // free partition
 149     start = end;
 150     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 151     part_header->signature = OPENBIOS_PART_FREE;
 152     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 153
 154     end = 0x1fd0;
 155     OpenBIOS_finish_partition(part_header, end - start);
 156
 157     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 158
 159     for (i = 0; i < sizeof(image); i++) {
 160         (k->write)(nvram, i, image[i]);
 161     }
 162
 163     return 0;
 164 }
 165
 166 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 167                                   const char *initrd_filename,
 168                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 169                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 170                                   uint64_t *kernel_entry)
 171 {
 172     int linux_boot;
 173     unsigned int i;
 174     long kernel_size;
 175     uint8_t *ptr;
 176     uint64_t kernel_top;
 177
 178     linux_boot = (kernel_filename != NULL);
 179
 180     kernel_size = 0;
 181     if (linux_boot) {
 182         int bswap_needed;
 183
 184 #ifdef BSWAP_NEEDED
 185         bswap_needed = 1;
 186 #else
 187         bswap_needed = 0;
 188 #endif
 189         kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
 190                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0);
 191         if (kernel_size < 0) {
 192             *kernel_addr = KERNEL_LOAD_ADDR;
 193             *kernel_entry = KERNEL_LOAD_ADDR;
 194             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 195                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 196                                     TARGET_PAGE_SIZE);
 197         }
 198         if (kernel_size < 0) {
 199             kernel_size = load_image_targphys(kernel_filename,
 200                                               KERNEL_LOAD_ADDR,
 201                                               RAM_size - KERNEL_LOAD_ADDR);
 202         }
 203         if (kernel_size < 0) {
 204             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 205                     kernel_filename);
 206             exit(1);
 207         }
 208         /* load initrd above kernel */
 209         *initrd_size = 0;
 210         if (initrd_filename) {
 211             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 212
 213             *initrd_size = load_image_targphys(initrd_filename,
 214                                                *initrd_addr,
 215                                                RAM_size - *initrd_addr);
 216             if ((int)*initrd_size < 0) {
 217                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 218                         initrd_filename);
 219                 exit(1);
 220             }
 221         }
 222         if (*initrd_size > 0) {
 223             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 224                 ptr = rom_ptr(*kernel_addr + i);
 225                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 226                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 227                     stl_p(ptr + 28, *initrd_size);
 228                     break;
 229                 }
 230             }
 231         }
 232     }
 233     return kernel_size;
 234 }
 235
 236 void cpu_check_irqs(CPUSPARCState *env)
 237 {
 238     CPUState *cs;
 239     uint32_t pil = env->pil_in |
 240                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 241
 242     /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
 243     if (env->ivec_status & 0x20) {
 244         return;
 245     }
 246     cs = CPU(sparc_env_get_cpu(env));
 247     /* check if TM or SM in SOFTINT are set
 248        setting these also causes interrupt 14 */
 249     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
 250         pil |= 1 << 14;
 251     }
 252
 253     /* The bit corresponding to psrpil is (1<< psrpil), the next bit
 254        is (2 << psrpil). */
 255     if (pil < (2 << env->psrpil)){
 256         if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 257             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
 258                            env->interrupt_index);
 259             env->interrupt_index = 0;
 260             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 261         }
 262         return;
 263     }
 264
 265     if (cpu_interrupts_enabled(env)) {
 266
 267         unsigned int i;
 268
 269         for (i = 15; i > env->psrpil; i--) {
 270             if (pil & (1 << i)) {
 271                 int old_interrupt = env->interrupt_index;
 272                 int new_interrupt = TT_EXTINT | i;
 273
 274                 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
 275                   && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
 276                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
 277                                    "current %x >= pending %x\n",
 278                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
 279                 } else if (old_interrupt != new_interrupt) {
 280                     env->interrupt_index = new_interrupt;
 281                     CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
 282                                    old_interrupt, new_interrupt);
 283                     cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 284                 }
 285                 break;
 286             }
 287         }
 288     } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 289         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
 290                        "current interrupt %x\n",
 291                        pil, env->pil_in, env->softint, env->interrupt_index);
 292         env->interrupt_index = 0;
 293         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 294     }
 295 }
 296
 297 static void cpu_kick_irq(SPARCCPU *cpu)
 298 {
 299     CPUState *cs = CPU(cpu);
 300     CPUSPARCState *env = &cpu->env;
 301
 302     cs->halted = 0;
 303     cpu_check_irqs(env);
 304     qemu_cpu_kick(cs);
 305 }
 306
 307 static void cpu_set_ivec_irq(void *opaque, int irq, int level)
 308 {
 309     SPARCCPU *cpu = opaque;
 310     CPUSPARCState *env = &cpu->env;
 311     CPUState *cs;
 312
 313     if (level) {
 314         if (!(env->ivec_status & 0x20)) {
 315             CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
 316             cs = CPU(cpu);
 317             cs->halted = 0;
 318             env->interrupt_index = TT_IVEC;
 319             env->ivec_status |= 0x20;
 320             env->ivec_data[0] = (0x1f << 6) | irq;
 321             env->ivec_data[1] = 0;
 322             env->ivec_data[2] = 0;
 323             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 324         }
 325     } else {
 326         if (env->ivec_status & 0x20) {
 327             CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
 328             cs = CPU(cpu);
 329             env->ivec_status &= ~0x20;
 330             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 331         }
 332     }
 333 }
 334
 335 typedef struct ResetData {
 336     SPARCCPU *cpu;
 337     uint64_t prom_addr;
 338 } ResetData;
 339
 340 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
 341                                   QEMUBHFunc *cb, uint32_t frequency,
 342                                   uint64_t disabled_mask, uint64_t npt_mask)
 343 {
 344     CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
 345
 346     timer->name = name;
 347     timer->frequency = frequency;
 348     timer->disabled_mask = disabled_mask;
 349     timer->npt_mask = npt_mask;
 350
 351     timer->disabled = 1;
 352     timer->npt = 1;
 353     timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 354
 355     timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
 356
 357     return timer;
 358 }
 359
 360 static void cpu_timer_reset(CPUTimer *timer)
 361 {
 362     timer->disabled = 1;
 363     timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 364
 365     timer_del(timer->qtimer);
 366 }
 367
 368 static void main_cpu_reset(void *opaque)
 369 {
 370     ResetData *s = (ResetData *)opaque;
 371     CPUSPARCState *env = &s->cpu->env;
 372     static unsigned int nr_resets;
 373
 374     cpu_reset(CPU(s->cpu));
 375
 376     cpu_timer_reset(env->tick);
 377     cpu_timer_reset(env->stick);
 378     cpu_timer_reset(env->hstick);
 379
 380     env->gregs[1] = 0; // Memory start
 381     env->gregs[2] = ram_size; // Memory size
 382     env->gregs[3] = 0; // Machine description XXX
 383     if (nr_resets++ == 0) {
 384         /* Power on reset */
 385         env->pc = s->prom_addr + 0x20ULL;
 386     } else {
 387         env->pc = s->prom_addr + 0x40ULL;
 388     }
 389     env->npc = env->pc + 4;
 390 }
 391
 392 static void tick_irq(void *opaque)
 393 {
 394     SPARCCPU *cpu = opaque;
 395     CPUSPARCState *env = &cpu->env;
 396
 397     CPUTimer* timer = env->tick;
 398
 399     if (timer->disabled) {
 400         CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
 401         return;
 402     } else {
 403         CPUIRQ_DPRINTF("tick: fire\n");
 404     }
 405
 406     env->softint |= SOFTINT_TIMER;
 407     cpu_kick_irq(cpu);
 408 }
 409
 410 static void stick_irq(void *opaque)
 411 {
 412     SPARCCPU *cpu = opaque;
 413     CPUSPARCState *env = &cpu->env;
 414
 415     CPUTimer* timer = env->stick;
 416
 417     if (timer->disabled) {
 418         CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
 419         return;
 420     } else {
 421         CPUIRQ_DPRINTF("stick: fire\n");
 422     }
 423
 424     env->softint |= SOFTINT_STIMER;
 425     cpu_kick_irq(cpu);
 426 }
 427
 428 static void hstick_irq(void *opaque)
 429 {
 430     SPARCCPU *cpu = opaque;
 431     CPUSPARCState *env = &cpu->env;
 432
 433     CPUTimer* timer = env->hstick;
 434
 435     if (timer->disabled) {
 436         CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
 437         return;
 438     } else {
 439         CPUIRQ_DPRINTF("hstick: fire\n");
 440     }
 441
 442     env->softint |= SOFTINT_STIMER;
 443     cpu_kick_irq(cpu);
 444 }
 445
 446 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
 447 {
 448     return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
 449 }
 450
 451 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
 452 {
 453     return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
 454 }
 455
 456 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
 457 {
 458     uint64_t real_count = count & ~timer->npt_mask;
 459     uint64_t npt_bit = count & timer->npt_mask;
 460
 461     int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 462                     cpu_to_timer_ticks(real_count, timer->frequency);
 463
 464     TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
 465                   timer->name, real_count,
 466                   timer->npt ? "disabled" : "enabled", timer);
 467
 468     timer->npt = npt_bit ? 1 : 0;
 469     timer->clock_offset = vm_clock_offset;
 470 }
 471
 472 uint64_t cpu_tick_get_count(CPUTimer *timer)
 473 {
 474     uint64_t real_count = timer_to_cpu_ticks(
 475                     qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
 476                     timer->frequency);
 477
 478     TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
 479            timer->name, real_count,
 480            timer->npt ? "disabled" : "enabled", timer);
 481
 482     if (timer->npt) {
 483         real_count |= timer->npt_mask;
 484     }
 485
 486     return real_count;
 487 }
 488
 489 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 490 {
 491     int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 492
 493     uint64_t real_limit = limit & ~timer->disabled_mask;
 494     timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
 495
 496     int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
 497                     timer->clock_offset;
 498
 499     if (expires < now) {
 500         expires = now + 1;
 501     }
 502
 503     TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
 504                   "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
 505                   timer->name, real_limit,
 506                   timer->disabled?"disabled":"enabled",
 507                   timer, limit,
 508                   timer_to_cpu_ticks(now - timer->clock_offset,
 509                                      timer->frequency),
 510                   timer_to_cpu_ticks(expires - now, timer->frequency));
 511
 512     if (!real_limit) {
 513         TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
 514                 timer->name);
 515         timer_del(timer->qtimer);
 516     } else if (timer->disabled) {
 517         timer_del(timer->qtimer);
 518     } else {
 519         timer_mod(timer->qtimer, expires);
 520     }
 521 }
 522
 523 static void isa_irq_handler(void *opaque, int n, int level)
 524 {
 525     static const int isa_irq_to_ivec[16] = {
 526         [1] = 0x29, /* keyboard */
 527         [4] = 0x2b, /* serial */
 528         [6] = 0x27, /* floppy */
 529         [7] = 0x22, /* parallel */
 530         [12] = 0x2a, /* mouse */
 531     };
 532     qemu_irq *irqs = opaque;
 533     int ivec;
 534
 535     assert(n < 16);
 536     ivec = isa_irq_to_ivec[n];
 537     EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
 538     if (ivec) {
 539         qemu_set_irq(irqs[ivec], level);
 540     }
 541 }
 542
 543 /* EBUS (Eight bit bus) bridge */
 544 static ISABus *
 545 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
 546 {
 547     qemu_irq *isa_irq;
 548     PCIDevice *pci_dev;
 549     ISABus *isa_bus;
 550
 551     pci_dev = pci_create_simple(bus, devfn, "ebus");
 552     isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
 553     isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
 554     isa_bus_irqs(isa_bus, isa_irq);
 555     return isa_bus;
 556 }
 557
 558 static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp)
 559 {
 560     EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
 561
 562     if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 563                      pci_address_space_io(pci_dev), errp)) {
 564         return;
 565     }
 566
 567     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 568     pci_dev->config[0x05] = 0x00;
 569     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 570     pci_dev->config[0x07] = 0x03; // status = medium devsel
 571     pci_dev->config[0x09] = 0x00; // programming i/f
 572     pci_dev->config[0x0D] = 0x0a; // latency_timer
 573
 574     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 575                              0, 0x1000000);
 576     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 577     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 578                              0, 0x4000);
 579     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 580 }
 581
 582 static void ebus_class_init(ObjectClass *klass, void *data)
 583 {
 584     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 585
 586     k->realize = pci_ebus_realize;
 587     k->vendor_id = PCI_VENDOR_ID_SUN;
 588     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 589     k->revision = 0x01;
 590     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 591 }
 592
 593 static const TypeInfo ebus_info = {
 594     .name          = "ebus",
 595     .parent        = TYPE_PCI_DEVICE,
 596     .instance_size = sizeof(EbusState),
 597     .class_init    = ebus_class_init,
 598 };
 599
 600 #define TYPE_OPENPROM "openprom"
 601 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 602
 603 typedef struct PROMState {
 604     SysBusDevice parent_obj;
 605
 606     MemoryRegion prom;
 607 } PROMState;
 608
 609 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 610 {
 611     hwaddr *base_addr = (hwaddr *)opaque;
 612     return addr + *base_addr - PROM_VADDR;
 613 }
 614
 615 /* Boot PROM (OpenBIOS) */
 616 static void prom_init(hwaddr addr, const char *bios_name)
 617 {
 618     DeviceState *dev;
 619     SysBusDevice *s;
 620     char *filename;
 621     int ret;
 622
 623     dev = qdev_create(NULL, TYPE_OPENPROM);
 624     qdev_init_nofail(dev);
 625     s = SYS_BUS_DEVICE(dev);
 626
 627     sysbus_mmio_map(s, 0, addr);
 628
 629     /* load boot prom */
 630     if (bios_name == NULL) {
 631         bios_name = PROM_FILENAME;
 632     }
 633     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 634     if (filename) {
 635         ret = load_elf(filename, translate_prom_address, &addr,
 636                        NULL, NULL, NULL, 1, EM_SPARCV9, 0);
 637         if (ret < 0 || ret > PROM_SIZE_MAX) {
 638             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 639         }
 640         g_free(filename);
 641     } else {
 642         ret = -1;
 643     }
 644     if (ret < 0 || ret > PROM_SIZE_MAX) {
 645         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 646         exit(1);
 647     }
 648 }
 649
 650 static int prom_init1(SysBusDevice *dev)
 651 {
 652     PROMState *s = OPENPROM(dev);
 653
 654     memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX,
 655                            &error_fatal);
 656     vmstate_register_ram_global(&s->prom);
 657     memory_region_set_readonly(&s->prom, true);
 658     sysbus_init_mmio(dev, &s->prom);
 659     return 0;
 660 }
 661
 662 static Property prom_properties[] = {
 663     {/* end of property list */},
 664 };
 665
 666 static void prom_class_init(ObjectClass *klass, void *data)
 667 {
 668     DeviceClass *dc = DEVICE_CLASS(klass);
 669     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 670
 671     k->init = prom_init1;
 672     dc->props = prom_properties;
 673 }
 674
 675 static const TypeInfo prom_info = {
 676     .name          = TYPE_OPENPROM,
 677     .parent        = TYPE_SYS_BUS_DEVICE,
 678     .instance_size = sizeof(PROMState),
 679     .class_init    = prom_class_init,
 680 };
 681
 682
 683 #define TYPE_SUN4U_MEMORY "memory"
 684 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
 685
 686 typedef struct RamDevice {
 687     SysBusDevice parent_obj;
 688
 689     MemoryRegion ram;
 690     uint64_t size;
 691 } RamDevice;
 692
 693 /* System RAM */
 694 static int ram_init1(SysBusDevice *dev)
 695 {
 696     RamDevice *d = SUN4U_RAM(dev);
 697
 698     memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 699                            &error_fatal);
 700     vmstate_register_ram_global(&d->ram);
 701     sysbus_init_mmio(dev, &d->ram);
 702     return 0;
 703 }
 704
 705 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 706 {
 707     DeviceState *dev;
 708     SysBusDevice *s;
 709     RamDevice *d;
 710
 711     /* allocate RAM */
 712     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
 713     s = SYS_BUS_DEVICE(dev);
 714
 715     d = SUN4U_RAM(dev);
 716     d->size = RAM_size;
 717     qdev_init_nofail(dev);
 718
 719     sysbus_mmio_map(s, 0, addr);
 720 }
 721
 722 static Property ram_properties[] = {
 723     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 724     DEFINE_PROP_END_OF_LIST(),
 725 };
 726
 727 static void ram_class_init(ObjectClass *klass, void *data)
 728 {
 729     DeviceClass *dc = DEVICE_CLASS(klass);
 730     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 731
 732     k->init = ram_init1;
 733     dc->props = ram_properties;
 734 }
 735
 736 static const TypeInfo ram_info = {
 737     .name          = TYPE_SUN4U_MEMORY,
 738     .parent        = TYPE_SYS_BUS_DEVICE,
 739     .instance_size = sizeof(RamDevice),
 740     .class_init    = ram_class_init,
 741 };
 742
 743 static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 744 {
 745     SPARCCPU *cpu;
 746     CPUSPARCState *env;
 747     ResetData *reset_info;
 748
 749     uint32_t   tick_frequency = 100*1000000;
 750     uint32_t  stick_frequency = 100*1000000;
 751     uint32_t hstick_frequency = 100*1000000;
 752
 753     if (cpu_model == NULL) {
 754         cpu_model = hwdef->default_cpu_model;
 755     }
 756     cpu = cpu_sparc_init(cpu_model);
 757     if (cpu == NULL) {
 758         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 759         exit(1);
 760     }
 761     env = &cpu->env;
 762
 763     env->tick = cpu_timer_create("tick", cpu, tick_irq,
 764                                   tick_frequency, TICK_INT_DIS,
 765                                   TICK_NPT_MASK);
 766
 767     env->stick = cpu_timer_create("stick", cpu, stick_irq,
 768                                    stick_frequency, TICK_INT_DIS,
 769                                    TICK_NPT_MASK);
 770
 771     env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
 772                                     hstick_frequency, TICK_INT_DIS,
 773                                     TICK_NPT_MASK);
 774
 775     reset_info = g_malloc0(sizeof(ResetData));
 776     reset_info->cpu = cpu;
 777     reset_info->prom_addr = hwdef->prom_addr;
 778     qemu_register_reset(main_cpu_reset, reset_info);
 779
 780     return cpu;
 781 }
 782
 783 static void sun4uv_init(MemoryRegion *address_space_mem,
 784                         MachineState *machine,
 785                         const struct hwdef *hwdef)
 786 {
 787     SPARCCPU *cpu;
 788     Nvram *nvram;
 789     unsigned int i;
 790     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 791     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 792     ISABus *isa_bus;
 793     SysBusDevice *s;
 794     qemu_irq *ivec_irqs, *pbm_irqs;
 795     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 796     DriveInfo *fd[MAX_FD];
 797     DeviceState *dev;
 798     FWCfgState *fw_cfg;
 799
 800     /* init CPUs */
 801     cpu = cpu_devinit(machine->cpu_model, hwdef);
 802
 803     /* set up devices */
 804     ram_init(0, machine->ram_size);
 805
 806     prom_init(hwdef->prom_addr, bios_name);
 807
 808     ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX);
 809     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
 810                            &pci_bus3, &pbm_irqs);
 811     pci_vga_init(pci_bus);
 812
 813     // XXX Should be pci_bus3
 814     isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
 815
 816     i = 0;
 817     if (hwdef->console_serial_base) {
 818         serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
 819                        NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 820         i++;
 821     }
 822
 823     serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS);
 824     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
 825
 826     for(i = 0; i < nb_nics; i++)
 827         pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 828
 829     ide_drive_get(hd, ARRAY_SIZE(hd));
 830
 831     pci_cmd646_ide_init(pci_bus, hd, 1);
 832
 833     isa_create_simple(isa_bus, "i8042");
 834
 835     /* Floppy */
 836     for(i = 0; i < MAX_FD; i++) {
 837         fd[i] = drive_get(IF_FLOPPY, 0, i);
 838     }
 839     dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC));
 840     if (fd[0]) {
 841         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
 842                             &error_abort);
 843     }
 844     if (fd[1]) {
 845         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
 846                             &error_abort);
 847     }
 848     qdev_prop_set_uint32(dev, "dma", -1);
 849     qdev_init_nofail(dev);
 850
 851     /* Map NVRAM into I/O (ebus) space */
 852     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 853     s = SYS_BUS_DEVICE(nvram);
 854     memory_region_add_subregion(get_system_io(), 0x2000,
 855                                 sysbus_mmio_get_region(s, 0));
 856
 857     initrd_size = 0;
 858     initrd_addr = 0;
 859     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 860                                     machine->initrd_filename,
 861                                     ram_size, &initrd_size, &initrd_addr,
 862                                     &kernel_addr, &kernel_entry);
 863
 864     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 865                            machine->boot_order,
 866                            kernel_addr, kernel_size,
 867                            machine->kernel_cmdline,
 868                            initrd_addr, initrd_size,
 869                            /* XXX: need an option to load a NVRAM image */
 870                            0,
 871                            graphic_width, graphic_height, graphic_depth,
 872                            (uint8_t *)&nd_table[0].macaddr);
 873
 874     fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
 875     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 876     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 877     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 878     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 879     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 880     if (machine->kernel_cmdline) {
 881         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 882                        strlen(machine->kernel_cmdline) + 1);
 883         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 884     } else {
 885         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 886     }
 887     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 888     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 889     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 890
 891     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 892     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 893     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 894
 895     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 896 }
 897
 898 enum {
 899     sun4u_id = 0,
 900     sun4v_id = 64,
 901     niagara_id,
 902 };
 903
 904 static const struct hwdef hwdefs[] = {
 905     /* Sun4u generic PC-like machine */
 906     {
 907         .default_cpu_model = "TI UltraSparc IIi",
 908         .machine_id = sun4u_id,
 909         .prom_addr = 0x1fff0000000ULL,
 910         .console_serial_base = 0,
 911     },
 912     /* Sun4v generic PC-like machine */
 913     {
 914         .default_cpu_model = "Sun UltraSparc T1",
 915         .machine_id = sun4v_id,
 916         .prom_addr = 0x1fff0000000ULL,
 917         .console_serial_base = 0,
 918     },
 919     /* Sun4v generic Niagara machine */
 920     {
 921         .default_cpu_model = "Sun UltraSparc T1",
 922         .machine_id = niagara_id,
 923         .prom_addr = 0xfff0000000ULL,
 924         .console_serial_base = 0xfff0c2c000ULL,
 925     },
 926 };
 927
 928 /* Sun4u hardware initialisation */
 929 static void sun4u_init(MachineState *machine)
 930 {
 931     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 932 }
 933
 934 /* Sun4v hardware initialisation */
 935 static void sun4v_init(MachineState *machine)
 936 {
 937     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 938 }
 939
 940 /* Niagara hardware initialisation */
 941 static void niagara_init(MachineState *machine)
 942 {
 943     sun4uv_init(get_system_memory(), machine, &hwdefs[2]);
 944 }
 945
 946 static void sun4u_class_init(ObjectClass *oc, void *data)
 947 {
 948     MachineClass *mc = MACHINE_CLASS(oc);
 949
 950     mc->desc = "Sun4u platform";
 951     mc->init = sun4u_init;
 952     mc->max_cpus = 1; /* XXX for now */
 953     mc->is_default = 1;
 954     mc->default_boot_order = "c";
 955 }
 956
 957 static const TypeInfo sun4u_type = {
 958     .name = MACHINE_TYPE_NAME("sun4u"),
 959     .parent = TYPE_MACHINE,
 960     .class_init = sun4u_class_init,
 961 };
 962
 963 static void sun4v_class_init(ObjectClass *oc, void *data)
 964 {
 965     MachineClass *mc = MACHINE_CLASS(oc);
 966
 967     mc->desc = "Sun4v platform";
 968     mc->init = sun4v_init;
 969     mc->max_cpus = 1; /* XXX for now */
 970     mc->default_boot_order = "c";
 971 }
 972
 973 static const TypeInfo sun4v_type = {
 974     .name = MACHINE_TYPE_NAME("sun4v"),
 975     .parent = TYPE_MACHINE,
 976     .class_init = sun4v_class_init,
 977 };
 978
 979 static void niagara_class_init(ObjectClass *oc, void *data)
 980 {
 981     MachineClass *mc = MACHINE_CLASS(oc);
 982
 983     mc->desc = "Sun4v platform, Niagara";
 984     mc->init = niagara_init;
 985     mc->max_cpus = 1; /* XXX for now */
 986     mc->default_boot_order = "c";
 987 }
 988
 989 static const TypeInfo niagara_type = {
 990     .name = MACHINE_TYPE_NAME("Niagara"),
 991     .parent = TYPE_MACHINE,
 992     .class_init = niagara_class_init,
 993 };
 994
 995 static void sun4u_register_types(void)
 996 {
 997     type_register_static(&ebus_info);
 998     type_register_static(&prom_info);
 999     type_register_static(&ram_info);
1000 }
1001
1002 static void sun4u_machine_init(void)
1003 {
1004     type_register_static(&sun4u_type);
1005     type_register_static(&sun4v_type);
1006     type_register_static(&niagara_type);
1007 }
1008
1009 type_init(sun4u_register_types)
1010 machine_init(sun4u_machine_init)