2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "sysemu/sysemu.h"
28 #include "sysemu/numa.h"
30 #include "hw/fw-path-provider.h"
33 #include "sysemu/device_tree.h"
34 #include "sysemu/block-backend.h"
35 #include "sysemu/cpus.h"
36 #include "sysemu/kvm.h"
38 #include "migration/migration.h"
39 #include "mmu-hash64.h"
42 #include "hw/boards.h"
43 #include "hw/ppc/ppc.h"
44 #include "hw/loader.h"
46 #include "hw/ppc/spapr.h"
47 #include "hw/ppc/spapr_vio.h"
48 #include "hw/pci-host/spapr.h"
49 #include "hw/ppc/xics.h"
50 #include "hw/pci/msi.h"
52 #include "hw/pci/pci.h"
53 #include "hw/scsi/scsi.h"
54 #include "hw/virtio/virtio-scsi.h"
56 #include "exec/address-spaces.h"
58 #include "qemu/config-file.h"
59 #include "qemu/error-report.h"
63 #include "hw/compat.h"
64 #include "qemu-common.h"
68 /* SLOF memory layout:
70 * SLOF raw image loaded at 0, copies its romfs right below the flat
71 * device-tree, then position SLOF itself 31M below that
73 * So we set FW_OVERHEAD to 40MB which should account for all of that
76 * We load our kernel at 4M, leaving space for SLOF initial image
78 #define FDT_MAX_SIZE 0x100000
79 #define RTAS_MAX_SIZE 0x10000
80 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
81 #define FW_MAX_SIZE 0x400000
82 #define FW_FILE_NAME "slof.bin"
83 #define FW_OVERHEAD 0x2800000
84 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
86 #define MIN_RMA_SLOF 128UL
88 #define TIMEBASE_FREQ 512000000ULL
90 #define PHANDLE_XICP 0x00001111
92 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
94 static XICSState
*try_create_xics(const char *type
, int nr_servers
,
95 int nr_irqs
, Error
**errp
)
100 dev
= qdev_create(NULL
, type
);
101 qdev_prop_set_uint32(dev
, "nr_servers", nr_servers
);
102 qdev_prop_set_uint32(dev
, "nr_irqs", nr_irqs
);
103 object_property_set_bool(OBJECT(dev
), true, "realized", &err
);
105 error_propagate(errp
, err
);
106 object_unparent(OBJECT(dev
));
109 return XICS_COMMON(dev
);
112 static XICSState
*xics_system_init(MachineState
*machine
,
113 int nr_servers
, int nr_irqs
)
115 XICSState
*icp
= NULL
;
120 if (machine_kernel_irqchip_allowed(machine
)) {
121 icp
= try_create_xics(TYPE_KVM_XICS
, nr_servers
, nr_irqs
, &err
);
123 if (machine_kernel_irqchip_required(machine
) && !icp
) {
124 error_report("kernel_irqchip requested but unavailable: %s",
125 error_get_pretty(err
));
130 icp
= try_create_xics(TYPE_XICS
, nr_servers
, nr_irqs
, &error_abort
);
136 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
140 uint32_t servers_prop
[smt_threads
];
141 uint32_t gservers_prop
[smt_threads
* 2];
142 int index
= ppc_get_vcpu_dt_id(cpu
);
144 if (cpu
->cpu_version
) {
145 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->cpu_version
);
151 /* Build interrupt servers and gservers properties */
152 for (i
= 0; i
< smt_threads
; i
++) {
153 servers_prop
[i
] = cpu_to_be32(index
+ i
);
154 /* Hack, direct the group queues back to cpu 0 */
155 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
156 gservers_prop
[i
*2 + 1] = 0;
158 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
159 servers_prop
, sizeof(servers_prop
));
163 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
164 gservers_prop
, sizeof(gservers_prop
));
169 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, CPUState
*cs
)
172 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
173 int index
= ppc_get_vcpu_dt_id(cpu
);
174 uint32_t associativity
[] = {cpu_to_be32(0x5),
178 cpu_to_be32(cs
->numa_node
),
181 /* Advertise NUMA via ibm,associativity */
182 if (nb_numa_nodes
> 1) {
183 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
184 sizeof(associativity
));
190 static int spapr_fixup_cpu_dt(void *fdt
, sPAPRMachineState
*spapr
)
192 int ret
= 0, offset
, cpus_offset
;
195 int smt
= kvmppc_smt_threads();
196 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
199 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
200 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
201 int index
= ppc_get_vcpu_dt_id(cpu
);
203 if ((index
% smt
) != 0) {
207 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
209 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
210 if (cpus_offset
< 0) {
211 cpus_offset
= fdt_add_subnode(fdt
, fdt_path_offset(fdt
, "/"),
213 if (cpus_offset
< 0) {
217 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
219 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
225 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
226 pft_size_prop
, sizeof(pft_size_prop
));
231 ret
= spapr_fixup_cpu_numa_dt(fdt
, offset
, cs
);
236 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
,
237 ppc_get_compat_smt_threads(cpu
));
246 static size_t create_page_sizes_prop(CPUPPCState
*env
, uint32_t *prop
,
249 size_t maxcells
= maxsize
/ sizeof(uint32_t);
253 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
254 struct ppc_one_seg_page_size
*sps
= &env
->sps
.sps
[i
];
256 if (!sps
->page_shift
) {
259 for (count
= 0; count
< PPC_PAGE_SIZES_MAX_SZ
; count
++) {
260 if (sps
->enc
[count
].page_shift
== 0) {
264 if ((p
- prop
) >= (maxcells
- 3 - count
* 2)) {
267 *(p
++) = cpu_to_be32(sps
->page_shift
);
268 *(p
++) = cpu_to_be32(sps
->slb_enc
);
269 *(p
++) = cpu_to_be32(count
);
270 for (j
= 0; j
< count
; j
++) {
271 *(p
++) = cpu_to_be32(sps
->enc
[j
].page_shift
);
272 *(p
++) = cpu_to_be32(sps
->enc
[j
].pte_enc
);
276 return (p
- prop
) * sizeof(uint32_t);
279 static hwaddr
spapr_node0_size(void)
281 MachineState
*machine
= MACHINE(qdev_get_machine());
285 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
286 if (numa_info
[i
].node_mem
) {
287 return MIN(pow2floor(numa_info
[i
].node_mem
),
292 return machine
->ram_size
;
299 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
300 #exp, fdt_strerror(ret)); \
305 static void add_str(GString
*s
, const gchar
*s1
)
307 g_string_append_len(s
, s1
, strlen(s1
) + 1);
310 static void *spapr_create_fdt_skel(hwaddr initrd_base
,
314 const char *kernel_cmdline
,
318 uint32_t start_prop
= cpu_to_be32(initrd_base
);
319 uint32_t end_prop
= cpu_to_be32(initrd_base
+ initrd_size
);
320 GString
*hypertas
= g_string_sized_new(256);
321 GString
*qemu_hypertas
= g_string_sized_new(256);
322 uint32_t refpoints
[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
323 uint32_t interrupt_server_ranges_prop
[] = {0, cpu_to_be32(max_cpus
)};
324 unsigned char vec5
[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
327 add_str(hypertas
, "hcall-pft");
328 add_str(hypertas
, "hcall-term");
329 add_str(hypertas
, "hcall-dabr");
330 add_str(hypertas
, "hcall-interrupt");
331 add_str(hypertas
, "hcall-tce");
332 add_str(hypertas
, "hcall-vio");
333 add_str(hypertas
, "hcall-splpar");
334 add_str(hypertas
, "hcall-bulk");
335 add_str(hypertas
, "hcall-set-mode");
336 add_str(qemu_hypertas
, "hcall-memop1");
338 fdt
= g_malloc0(FDT_MAX_SIZE
);
339 _FDT((fdt_create(fdt
, FDT_MAX_SIZE
)));
342 _FDT((fdt_add_reservemap_entry(fdt
, KERNEL_LOAD_ADDR
, kernel_size
)));
345 _FDT((fdt_add_reservemap_entry(fdt
, initrd_base
, initrd_size
)));
347 _FDT((fdt_finish_reservemap(fdt
)));
350 _FDT((fdt_begin_node(fdt
, "")));
351 _FDT((fdt_property_string(fdt
, "device_type", "chrp")));
352 _FDT((fdt_property_string(fdt
, "model", "IBM pSeries (emulated by qemu)")));
353 _FDT((fdt_property_string(fdt
, "compatible", "qemu,pseries")));
356 * Add info to guest to indentify which host is it being run on
357 * and what is the uuid of the guest
359 if (kvmppc_get_host_model(&buf
)) {
360 _FDT((fdt_property_string(fdt
, "host-model", buf
)));
363 if (kvmppc_get_host_serial(&buf
)) {
364 _FDT((fdt_property_string(fdt
, "host-serial", buf
)));
368 buf
= g_strdup_printf(UUID_FMT
, qemu_uuid
[0], qemu_uuid
[1],
369 qemu_uuid
[2], qemu_uuid
[3], qemu_uuid
[4],
370 qemu_uuid
[5], qemu_uuid
[6], qemu_uuid
[7],
371 qemu_uuid
[8], qemu_uuid
[9], qemu_uuid
[10],
372 qemu_uuid
[11], qemu_uuid
[12], qemu_uuid
[13],
373 qemu_uuid
[14], qemu_uuid
[15]);
375 _FDT((fdt_property_string(fdt
, "vm,uuid", buf
)));
378 if (qemu_get_vm_name()) {
379 _FDT((fdt_property_string(fdt
, "ibm,partition-name",
380 qemu_get_vm_name())));
383 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x2)));
384 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x2)));
387 _FDT((fdt_begin_node(fdt
, "chosen")));
389 /* Set Form1_affinity */
390 _FDT((fdt_property(fdt
, "ibm,architecture-vec-5", vec5
, sizeof(vec5
))));
392 _FDT((fdt_property_string(fdt
, "bootargs", kernel_cmdline
)));
393 _FDT((fdt_property(fdt
, "linux,initrd-start",
394 &start_prop
, sizeof(start_prop
))));
395 _FDT((fdt_property(fdt
, "linux,initrd-end",
396 &end_prop
, sizeof(end_prop
))));
398 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
399 cpu_to_be64(kernel_size
) };
401 _FDT((fdt_property(fdt
, "qemu,boot-kernel", &kprop
, sizeof(kprop
))));
403 _FDT((fdt_property(fdt
, "qemu,boot-kernel-le", NULL
, 0)));
407 _FDT((fdt_property_cell(fdt
, "qemu,boot-menu", boot_menu
)));
409 _FDT((fdt_property_cell(fdt
, "qemu,graphic-width", graphic_width
)));
410 _FDT((fdt_property_cell(fdt
, "qemu,graphic-height", graphic_height
)));
411 _FDT((fdt_property_cell(fdt
, "qemu,graphic-depth", graphic_depth
)));
413 _FDT((fdt_end_node(fdt
)));
416 _FDT((fdt_begin_node(fdt
, "rtas")));
418 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
419 add_str(hypertas
, "hcall-multi-tce");
421 _FDT((fdt_property(fdt
, "ibm,hypertas-functions", hypertas
->str
,
423 g_string_free(hypertas
, TRUE
);
424 _FDT((fdt_property(fdt
, "qemu,hypertas-functions", qemu_hypertas
->str
,
425 qemu_hypertas
->len
)));
426 g_string_free(qemu_hypertas
, TRUE
);
428 _FDT((fdt_property(fdt
, "ibm,associativity-reference-points",
429 refpoints
, sizeof(refpoints
))));
431 _FDT((fdt_property_cell(fdt
, "rtas-error-log-max", RTAS_ERROR_LOG_MAX
)));
432 _FDT((fdt_property_cell(fdt
, "rtas-event-scan-rate",
433 RTAS_EVENT_SCAN_RATE
)));
436 _FDT((fdt_property(fdt
, "ibm,change-msix-capable", NULL
, 0)));
440 * According to PAPR, rtas ibm,os-term does not guarantee a return
441 * back to the guest cpu.
443 * While an additional ibm,extended-os-term property indicates that
444 * rtas call return will always occur. Set this property.
446 _FDT((fdt_property(fdt
, "ibm,extended-os-term", NULL
, 0)));
448 _FDT((fdt_end_node(fdt
)));
450 /* interrupt controller */
451 _FDT((fdt_begin_node(fdt
, "interrupt-controller")));
453 _FDT((fdt_property_string(fdt
, "device_type",
454 "PowerPC-External-Interrupt-Presentation")));
455 _FDT((fdt_property_string(fdt
, "compatible", "IBM,ppc-xicp")));
456 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
457 _FDT((fdt_property(fdt
, "ibm,interrupt-server-ranges",
458 interrupt_server_ranges_prop
,
459 sizeof(interrupt_server_ranges_prop
))));
460 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 2)));
461 _FDT((fdt_property_cell(fdt
, "linux,phandle", PHANDLE_XICP
)));
462 _FDT((fdt_property_cell(fdt
, "phandle", PHANDLE_XICP
)));
464 _FDT((fdt_end_node(fdt
)));
467 _FDT((fdt_begin_node(fdt
, "vdevice")));
469 _FDT((fdt_property_string(fdt
, "device_type", "vdevice")));
470 _FDT((fdt_property_string(fdt
, "compatible", "IBM,vdevice")));
471 _FDT((fdt_property_cell(fdt
, "#address-cells", 0x1)));
472 _FDT((fdt_property_cell(fdt
, "#size-cells", 0x0)));
473 _FDT((fdt_property_cell(fdt
, "#interrupt-cells", 0x2)));
474 _FDT((fdt_property(fdt
, "interrupt-controller", NULL
, 0)));
476 _FDT((fdt_end_node(fdt
)));
479 spapr_events_fdt_skel(fdt
, epow_irq
);
481 /* /hypervisor node */
483 uint8_t hypercall
[16];
485 /* indicate KVM hypercall interface */
486 _FDT((fdt_begin_node(fdt
, "hypervisor")));
487 _FDT((fdt_property_string(fdt
, "compatible", "linux,kvm")));
488 if (kvmppc_has_cap_fixup_hcalls()) {
490 * Older KVM versions with older guest kernels were broken with the
491 * magic page, don't allow the guest to map it.
493 kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
495 _FDT((fdt_property(fdt
, "hcall-instructions", hypercall
,
496 sizeof(hypercall
))));
498 _FDT((fdt_end_node(fdt
)));
501 _FDT((fdt_end_node(fdt
))); /* close root node */
502 _FDT((fdt_finish(fdt
)));
507 int spapr_h_cas_compose_response(sPAPRMachineState
*spapr
,
508 target_ulong addr
, target_ulong size
)
510 void *fdt
, *fdt_skel
;
511 sPAPRDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
515 /* Create sceleton */
516 fdt_skel
= g_malloc0(size
);
517 _FDT((fdt_create(fdt_skel
, size
)));
518 _FDT((fdt_begin_node(fdt_skel
, "")));
519 _FDT((fdt_end_node(fdt_skel
)));
520 _FDT((fdt_finish(fdt_skel
)));
521 fdt
= g_malloc0(size
);
522 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
525 /* Fix skeleton up */
526 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
528 /* Pack resulting tree */
529 _FDT((fdt_pack(fdt
)));
531 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
532 trace_spapr_cas_failed(size
);
536 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
537 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
538 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
544 static void spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
547 uint32_t associativity
[] = {
548 cpu_to_be32(0x4), /* length */
549 cpu_to_be32(0x0), cpu_to_be32(0x0),
550 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
553 uint64_t mem_reg_property
[2];
556 mem_reg_property
[0] = cpu_to_be64(start
);
557 mem_reg_property
[1] = cpu_to_be64(size
);
559 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, start
);
560 off
= fdt_add_subnode(fdt
, 0, mem_name
);
562 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
563 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
564 sizeof(mem_reg_property
))));
565 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
566 sizeof(associativity
))));
569 static int spapr_populate_memory(sPAPRMachineState
*spapr
, void *fdt
)
571 MachineState
*machine
= MACHINE(spapr
);
572 hwaddr mem_start
, node_size
;
573 int i
, nb_nodes
= nb_numa_nodes
;
574 NodeInfo
*nodes
= numa_info
;
577 /* No NUMA nodes, assume there is just one node with whole RAM */
578 if (!nb_numa_nodes
) {
580 ramnode
.node_mem
= machine
->ram_size
;
584 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
585 if (!nodes
[i
].node_mem
) {
588 if (mem_start
>= machine
->ram_size
) {
591 node_size
= nodes
[i
].node_mem
;
592 if (node_size
> machine
->ram_size
- mem_start
) {
593 node_size
= machine
->ram_size
- mem_start
;
597 /* ppc_spapr_init() checks for rma_size <= node0_size already */
598 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
599 mem_start
+= spapr
->rma_size
;
600 node_size
-= spapr
->rma_size
;
602 for ( ; node_size
; ) {
603 hwaddr sizetmp
= pow2floor(node_size
);
605 /* mem_start != 0 here */
606 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
607 sizetmp
= 1ULL << ctzl(mem_start
);
610 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
611 node_size
-= sizetmp
;
612 mem_start
+= sizetmp
;
619 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
620 sPAPRMachineState
*spapr
)
622 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
623 CPUPPCState
*env
= &cpu
->env
;
624 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
625 int index
= ppc_get_vcpu_dt_id(cpu
);
626 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
627 0xffffffff, 0xffffffff};
628 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ
;
629 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
630 uint32_t page_sizes_prop
[64];
631 size_t page_sizes_prop_size
;
632 uint32_t vcpus_per_socket
= smp_threads
* smp_cores
;
633 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
635 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
636 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
638 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
639 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
640 env
->dcache_line_size
)));
641 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
642 env
->dcache_line_size
)));
643 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
644 env
->icache_line_size
)));
645 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
646 env
->icache_line_size
)));
648 if (pcc
->l1_dcache_size
) {
649 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
650 pcc
->l1_dcache_size
)));
652 fprintf(stderr
, "Warning: Unknown L1 dcache size for cpu\n");
654 if (pcc
->l1_icache_size
) {
655 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
656 pcc
->l1_icache_size
)));
658 fprintf(stderr
, "Warning: Unknown L1 icache size for cpu\n");
661 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
662 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
663 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", env
->slb_nr
)));
664 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
665 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
667 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
668 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
671 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
672 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
673 segs
, sizeof(segs
))));
676 /* Advertise VMX/VSX (vector extensions) if available
677 * 0 / no property == no vector extensions
678 * 1 == VMX / Altivec available
679 * 2 == VSX available */
680 if (env
->insns_flags
& PPC_ALTIVEC
) {
681 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
683 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
686 /* Advertise DFP (Decimal Floating Point) if available
687 * 0 / no property == no DFP
688 * 1 == DFP available */
689 if (env
->insns_flags2
& PPC2_DFP
) {
690 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
693 page_sizes_prop_size
= create_page_sizes_prop(env
, page_sizes_prop
,
694 sizeof(page_sizes_prop
));
695 if (page_sizes_prop_size
) {
696 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
697 page_sizes_prop
, page_sizes_prop_size
)));
700 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
701 cs
->cpu_index
/ vcpus_per_socket
)));
703 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
704 pft_size_prop
, sizeof(pft_size_prop
))));
706 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cs
));
708 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
,
709 ppc_get_compat_smt_threads(cpu
)));
712 static void spapr_populate_cpus_dt_node(void *fdt
, sPAPRMachineState
*spapr
)
717 int smt
= kvmppc_smt_threads();
719 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
721 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
722 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
725 * We walk the CPUs in reverse order to ensure that CPU DT nodes
726 * created by fdt_add_subnode() end up in the right order in FDT
727 * for the guest kernel the enumerate the CPUs correctly.
729 CPU_FOREACH_REVERSE(cs
) {
730 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
731 int index
= ppc_get_vcpu_dt_id(cpu
);
732 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
735 if ((index
% smt
) != 0) {
739 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
740 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
743 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
748 static void spapr_finalize_fdt(sPAPRMachineState
*spapr
,
753 MachineState
*machine
= MACHINE(qdev_get_machine());
754 const char *boot_device
= machine
->boot_order
;
761 fdt
= g_malloc(FDT_MAX_SIZE
);
763 /* open out the base tree into a temp buffer for the final tweaks */
764 _FDT((fdt_open_into(spapr
->fdt_skel
, fdt
, FDT_MAX_SIZE
)));
766 ret
= spapr_populate_memory(spapr
, fdt
);
768 fprintf(stderr
, "couldn't setup memory nodes in fdt\n");
772 ret
= spapr_populate_vdevice(spapr
->vio_bus
, fdt
);
774 fprintf(stderr
, "couldn't setup vio devices in fdt\n");
778 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
779 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
783 fprintf(stderr
, "couldn't setup PCI devices in fdt\n");
788 ret
= spapr_rtas_device_tree_setup(fdt
, rtas_addr
, rtas_size
);
790 fprintf(stderr
, "Couldn't set up RTAS device tree properties\n");
794 spapr_populate_cpus_dt_node(fdt
, spapr
);
796 bootlist
= get_boot_devices_list(&cb
, true);
797 if (cb
&& bootlist
) {
798 int offset
= fdt_path_offset(fdt
, "/chosen");
802 for (i
= 0; i
< cb
; i
++) {
803 if (bootlist
[i
] == '\n') {
808 ret
= fdt_setprop_string(fdt
, offset
, "qemu,boot-list", bootlist
);
811 if (boot_device
&& strlen(boot_device
)) {
812 int offset
= fdt_path_offset(fdt
, "/chosen");
817 fdt_setprop_string(fdt
, offset
, "qemu,boot-device", boot_device
);
820 if (!spapr
->has_graphics
) {
821 spapr_populate_chosen_stdout(fdt
, spapr
->vio_bus
);
824 _FDT((fdt_pack(fdt
)));
826 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
827 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
828 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
832 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
833 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
839 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
841 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
844 static void emulate_spapr_hypercall(PowerPCCPU
*cpu
)
846 CPUPPCState
*env
= &cpu
->env
;
849 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
850 env
->gpr
[3] = H_PRIVILEGE
;
852 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
856 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
857 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
858 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
859 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
860 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
862 static void spapr_reset_htab(sPAPRMachineState
*spapr
)
867 /* allocate hash page table. For now we always make this 16mb,
868 * later we should probably make it scale to the size of guest
871 shift
= kvmppc_reset_htab(spapr
->htab_shift
);
874 /* Kernel handles htab, we don't need to allocate one */
875 spapr
->htab_shift
= shift
;
876 kvmppc_kern_htab
= true;
878 /* Tell readers to update their file descriptor */
879 if (spapr
->htab_fd
>= 0) {
880 spapr
->htab_fd_stale
= true;
884 /* Allocate an htab if we don't yet have one */
885 spapr
->htab
= qemu_memalign(HTAB_SIZE(spapr
), HTAB_SIZE(spapr
));
889 memset(spapr
->htab
, 0, HTAB_SIZE(spapr
));
891 for (index
= 0; index
< HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
; index
++) {
892 DIRTY_HPTE(HPTE(spapr
->htab
, index
));
896 /* Update the RMA size if necessary */
897 if (spapr
->vrma_adjust
) {
898 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(),
903 static int find_unknown_sysbus_device(SysBusDevice
*sbdev
, void *opaque
)
905 bool matched
= false;
907 if (object_dynamic_cast(OBJECT(sbdev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
912 error_report("Device %s is not supported by this machine yet.",
913 qdev_fw_name(DEVICE(sbdev
)));
921 * A guest reset will cause spapr->htab_fd to become stale if being used.
922 * Reopen the file descriptor to make sure the whole HTAB is properly read.
924 static int spapr_check_htab_fd(sPAPRMachineState
*spapr
)
928 if (spapr
->htab_fd_stale
) {
929 close(spapr
->htab_fd
);
930 spapr
->htab_fd
= kvmppc_get_htab_fd(false);
931 if (spapr
->htab_fd
< 0) {
932 error_report("Unable to open fd for reading hash table from KVM: "
933 "%s", strerror(errno
));
936 spapr
->htab_fd_stale
= false;
942 static void ppc_spapr_reset(void)
944 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
945 PowerPCCPU
*first_ppc_cpu
;
948 /* Check for unknown sysbus devices */
949 foreach_dynamic_sysbus_device(find_unknown_sysbus_device
, NULL
);
951 /* Reset the hash table & recalc the RMA */
952 spapr_reset_htab(spapr
);
954 qemu_devices_reset();
957 * We place the device tree and RTAS just below either the top of the RMA,
958 * or just below 2GB, whichever is lowere, so that it can be
959 * processed with 32-bit real mode code if necessary
961 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
962 spapr
->rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
963 spapr
->fdt_addr
= spapr
->rtas_addr
- FDT_MAX_SIZE
;
966 spapr_finalize_fdt(spapr
, spapr
->fdt_addr
, spapr
->rtas_addr
,
970 cpu_physical_memory_write(spapr
->rtas_addr
, spapr
->rtas_blob
,
973 /* Set up the entry state */
974 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
975 first_ppc_cpu
->env
.gpr
[3] = spapr
->fdt_addr
;
976 first_ppc_cpu
->env
.gpr
[5] = 0;
977 first_cpu
->halted
= 0;
978 first_ppc_cpu
->env
.nip
= SPAPR_ENTRY_POINT
;
982 static void spapr_cpu_reset(void *opaque
)
984 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
985 PowerPCCPU
*cpu
= opaque
;
986 CPUState
*cs
= CPU(cpu
);
987 CPUPPCState
*env
= &cpu
->env
;
991 /* All CPUs start halted. CPU0 is unhalted from the machine level
992 * reset code and the rest are explicitly started up by the guest
993 * using an RTAS call */
996 env
->spr
[SPR_HIOR
] = 0;
998 env
->external_htab
= (uint8_t *)spapr
->htab
;
999 if (kvm_enabled() && !env
->external_htab
) {
1001 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte*
1002 * functions do the right thing.
1004 env
->external_htab
= (void *)1;
1006 env
->htab_base
= -1;
1008 * htab_mask is the mask used to normalize hash value to PTEG index.
1009 * htab_shift is log2 of hash table size.
1010 * We have 8 hpte per group, and each hpte is 16 bytes.
1011 * ie have 128 bytes per hpte entry.
1013 env
->htab_mask
= (1ULL << (spapr
->htab_shift
- 7)) - 1;
1014 env
->spr
[SPR_SDR1
] = (target_ulong
)(uintptr_t)spapr
->htab
|
1015 (spapr
->htab_shift
- 18);
1018 static void spapr_create_nvram(sPAPRMachineState
*spapr
)
1020 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1021 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1024 qdev_prop_set_drive_nofail(dev
, "drive", blk_by_legacy_dinfo(dinfo
));
1027 qdev_init_nofail(dev
);
1029 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
1032 static void spapr_rtc_create(sPAPRMachineState
*spapr
)
1034 DeviceState
*dev
= qdev_create(NULL
, TYPE_SPAPR_RTC
);
1036 qdev_init_nofail(dev
);
1039 object_property_add_alias(qdev_get_machine(), "rtc-time",
1040 OBJECT(spapr
->rtc
), "date", NULL
);
1043 /* Returns whether we want to use VGA or not */
1044 static int spapr_vga_init(PCIBus
*pci_bus
)
1046 switch (vga_interface_type
) {
1052 return pci_vga_init(pci_bus
) != NULL
;
1054 fprintf(stderr
, "This vga model is not supported,"
1055 "currently it only supports -vga std\n");
1060 static int spapr_post_load(void *opaque
, int version_id
)
1062 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1065 /* In earlier versions, there was no separate qdev for the PAPR
1066 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1067 * So when migrating from those versions, poke the incoming offset
1068 * value into the RTC device */
1069 if (version_id
< 3) {
1070 err
= spapr_rtc_import_offset(spapr
->rtc
, spapr
->rtc_offset
);
1076 static bool version_before_3(void *opaque
, int version_id
)
1078 return version_id
< 3;
1081 static const VMStateDescription vmstate_spapr
= {
1084 .minimum_version_id
= 1,
1085 .post_load
= spapr_post_load
,
1086 .fields
= (VMStateField
[]) {
1087 /* used to be @next_irq */
1088 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
1091 VMSTATE_UINT64_TEST(rtc_offset
, sPAPRMachineState
, version_before_3
),
1093 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPRMachineState
, 2),
1094 VMSTATE_END_OF_LIST()
1098 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
1100 sPAPRMachineState
*spapr
= opaque
;
1102 /* "Iteration" header */
1103 qemu_put_be32(f
, spapr
->htab_shift
);
1106 spapr
->htab_save_index
= 0;
1107 spapr
->htab_first_pass
= true;
1109 assert(kvm_enabled());
1111 spapr
->htab_fd
= kvmppc_get_htab_fd(false);
1112 spapr
->htab_fd_stale
= false;
1113 if (spapr
->htab_fd
< 0) {
1114 fprintf(stderr
, "Unable to open fd for reading hash table from KVM: %s\n",
1124 static void htab_save_first_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
1127 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
1128 int index
= spapr
->htab_save_index
;
1129 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1131 assert(spapr
->htab_first_pass
);
1136 /* Consume invalid HPTEs */
1137 while ((index
< htabslots
)
1138 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1140 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1143 /* Consume valid HPTEs */
1145 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
1146 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1148 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1151 if (index
> chunkstart
) {
1152 int n_valid
= index
- chunkstart
;
1154 qemu_put_be32(f
, chunkstart
);
1155 qemu_put_be16(f
, n_valid
);
1156 qemu_put_be16(f
, 0);
1157 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1158 HASH_PTE_SIZE_64
* n_valid
);
1160 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1164 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
1166 if (index
>= htabslots
) {
1167 assert(index
== htabslots
);
1169 spapr
->htab_first_pass
= false;
1171 spapr
->htab_save_index
= index
;
1174 static int htab_save_later_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
1177 bool final
= max_ns
< 0;
1178 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
1179 int examined
= 0, sent
= 0;
1180 int index
= spapr
->htab_save_index
;
1181 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1183 assert(!spapr
->htab_first_pass
);
1186 int chunkstart
, invalidstart
;
1188 /* Consume non-dirty HPTEs */
1189 while ((index
< htabslots
)
1190 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
1196 /* Consume valid dirty HPTEs */
1197 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
1198 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1199 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1200 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1205 invalidstart
= index
;
1206 /* Consume invalid dirty HPTEs */
1207 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
1208 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1209 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1210 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1215 if (index
> chunkstart
) {
1216 int n_valid
= invalidstart
- chunkstart
;
1217 int n_invalid
= index
- invalidstart
;
1219 qemu_put_be32(f
, chunkstart
);
1220 qemu_put_be16(f
, n_valid
);
1221 qemu_put_be16(f
, n_invalid
);
1222 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1223 HASH_PTE_SIZE_64
* n_valid
);
1224 sent
+= index
- chunkstart
;
1226 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1231 if (examined
>= htabslots
) {
1235 if (index
>= htabslots
) {
1236 assert(index
== htabslots
);
1239 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
1241 if (index
>= htabslots
) {
1242 assert(index
== htabslots
);
1246 spapr
->htab_save_index
= index
;
1248 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
1251 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1252 #define MAX_KVM_BUF_SIZE 2048
1254 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
1256 sPAPRMachineState
*spapr
= opaque
;
1259 /* Iteration header */
1260 qemu_put_be32(f
, 0);
1263 assert(kvm_enabled());
1265 rc
= spapr_check_htab_fd(spapr
);
1270 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
,
1271 MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
1275 } else if (spapr
->htab_first_pass
) {
1276 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
1278 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
1282 qemu_put_be32(f
, 0);
1283 qemu_put_be16(f
, 0);
1284 qemu_put_be16(f
, 0);
1289 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
1291 sPAPRMachineState
*spapr
= opaque
;
1293 /* Iteration header */
1294 qemu_put_be32(f
, 0);
1299 assert(kvm_enabled());
1301 rc
= spapr_check_htab_fd(spapr
);
1306 rc
= kvmppc_save_htab(f
, spapr
->htab_fd
, MAX_KVM_BUF_SIZE
, -1);
1310 close(spapr
->htab_fd
);
1311 spapr
->htab_fd
= -1;
1313 htab_save_later_pass(f
, spapr
, -1);
1317 qemu_put_be32(f
, 0);
1318 qemu_put_be16(f
, 0);
1319 qemu_put_be16(f
, 0);
1324 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
1326 sPAPRMachineState
*spapr
= opaque
;
1327 uint32_t section_hdr
;
1330 if (version_id
< 1 || version_id
> 1) {
1331 fprintf(stderr
, "htab_load() bad version\n");
1335 section_hdr
= qemu_get_be32(f
);
1338 /* First section, just the hash shift */
1339 if (spapr
->htab_shift
!= section_hdr
) {
1340 error_report("htab_shift mismatch: source %d target %d",
1341 section_hdr
, spapr
->htab_shift
);
1348 assert(kvm_enabled());
1350 fd
= kvmppc_get_htab_fd(true);
1352 fprintf(stderr
, "Unable to open fd to restore KVM hash table: %s\n",
1359 uint16_t n_valid
, n_invalid
;
1361 index
= qemu_get_be32(f
);
1362 n_valid
= qemu_get_be16(f
);
1363 n_invalid
= qemu_get_be16(f
);
1365 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
1370 if ((index
+ n_valid
+ n_invalid
) >
1371 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
1372 /* Bad index in stream */
1373 fprintf(stderr
, "htab_load() bad index %d (%hd+%hd entries) "
1374 "in htab stream (htab_shift=%d)\n", index
, n_valid
, n_invalid
,
1381 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
1382 HASH_PTE_SIZE_64
* n_valid
);
1385 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
1386 HASH_PTE_SIZE_64
* n_invalid
);
1393 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
1408 static SaveVMHandlers savevm_htab_handlers
= {
1409 .save_live_setup
= htab_save_setup
,
1410 .save_live_iterate
= htab_save_iterate
,
1411 .save_live_complete
= htab_save_complete
,
1412 .load_state
= htab_load
,
1415 static void spapr_boot_set(void *opaque
, const char *boot_device
,
1418 MachineState
*machine
= MACHINE(qdev_get_machine());
1419 machine
->boot_order
= g_strdup(boot_device
);
1422 static void spapr_cpu_init(sPAPRMachineState
*spapr
, PowerPCCPU
*cpu
)
1424 CPUPPCState
*env
= &cpu
->env
;
1426 /* Set time-base frequency to 512 MHz */
1427 cpu_ppc_tb_init(env
, TIMEBASE_FREQ
);
1429 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
1430 * MSR[IP] should never be set.
1432 env
->msr_mask
&= ~(1 << 6);
1434 /* Tell KVM that we're in PAPR mode */
1435 if (kvm_enabled()) {
1436 kvmppc_set_papr(cpu
);
1439 if (cpu
->max_compat
) {
1440 if (ppc_set_compat(cpu
, cpu
->max_compat
) < 0) {
1445 xics_cpu_setup(spapr
->icp
, cpu
);
1447 qemu_register_reset(spapr_cpu_reset
, cpu
);
1451 * Reset routine for LMB DR devices.
1453 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1454 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1455 * when it walks all its children devices. LMB devices reset occurs
1456 * as part of spapr_ppc_reset().
1458 static void spapr_drc_reset(void *opaque
)
1460 sPAPRDRConnector
*drc
= opaque
;
1461 DeviceState
*d
= DEVICE(drc
);
1468 static void spapr_create_lmb_dr_connectors(sPAPRMachineState
*spapr
)
1470 MachineState
*machine
= MACHINE(spapr
);
1471 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
1472 uint32_t nr_rma_lmbs
= spapr
->rma_size
/lmb_size
;
1473 uint32_t nr_lmbs
= machine
->maxram_size
/lmb_size
- nr_rma_lmbs
;
1474 uint32_t nr_assigned_lmbs
= machine
->ram_size
/lmb_size
- nr_rma_lmbs
;
1477 for (i
= 0; i
< nr_lmbs
; i
++) {
1478 sPAPRDRConnector
*drc
;
1481 if (i
< nr_assigned_lmbs
) {
1482 addr
= (i
+ nr_rma_lmbs
) * lmb_size
;
1484 addr
= (i
- nr_assigned_lmbs
) * lmb_size
+
1485 spapr
->hotplug_memory
.base
;
1487 drc
= spapr_dr_connector_new(OBJECT(spapr
), SPAPR_DR_CONNECTOR_TYPE_LMB
,
1489 qemu_register_reset(spapr_drc_reset
, drc
);
1494 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1495 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1496 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1498 static void spapr_validate_node_memory(MachineState
*machine
)
1502 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
||
1503 machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
1504 error_report("Can't support memory configuration where RAM size "
1505 "0x" RAM_ADDR_FMT
" or maxmem size "
1506 "0x" RAM_ADDR_FMT
" isn't aligned to %llu MB",
1507 machine
->ram_size
, machine
->maxram_size
,
1508 SPAPR_MEMORY_BLOCK_SIZE
/M_BYTE
);
1512 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1513 if (numa_info
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
1514 error_report("Can't support memory configuration where memory size"
1515 " %" PRIx64
" of node %d isn't aligned to %llu MB",
1516 numa_info
[i
].node_mem
, i
,
1517 SPAPR_MEMORY_BLOCK_SIZE
/M_BYTE
);
1523 /* pSeries LPAR / sPAPR hardware init */
1524 static void ppc_spapr_init(MachineState
*machine
)
1526 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
1527 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1528 const char *kernel_filename
= machine
->kernel_filename
;
1529 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1530 const char *initrd_filename
= machine
->initrd_filename
;
1534 MemoryRegion
*sysmem
= get_system_memory();
1535 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1536 MemoryRegion
*rma_region
;
1538 hwaddr rma_alloc_size
;
1539 hwaddr node0_size
= spapr_node0_size();
1540 uint32_t initrd_base
= 0;
1541 long kernel_size
= 0, initrd_size
= 0;
1542 long load_limit
, fw_size
;
1543 bool kernel_le
= false;
1546 msi_supported
= true;
1548 QLIST_INIT(&spapr
->phbs
);
1550 cpu_ppc_hypercall
= emulate_spapr_hypercall
;
1552 /* Allocate RMA if necessary */
1553 rma_alloc_size
= kvmppc_alloc_rma(&rma
);
1555 if (rma_alloc_size
== -1) {
1556 error_report("Unable to create RMA");
1560 if (rma_alloc_size
&& (rma_alloc_size
< node0_size
)) {
1561 spapr
->rma_size
= rma_alloc_size
;
1563 spapr
->rma_size
= node0_size
;
1565 /* With KVM, we don't actually know whether KVM supports an
1566 * unbounded RMA (PR KVM) or is limited by the hash table size
1567 * (HV KVM using VRMA), so we always assume the latter
1569 * In that case, we also limit the initial allocations for RTAS
1570 * etc... to 256M since we have no way to know what the VRMA size
1571 * is going to be as it depends on the size of the hash table
1572 * isn't determined yet.
1574 if (kvm_enabled()) {
1575 spapr
->vrma_adjust
= 1;
1576 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
1580 if (spapr
->rma_size
> node0_size
) {
1581 fprintf(stderr
, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")\n",
1586 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1587 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
1589 /* We aim for a hash table of size 1/128 the size of RAM. The
1590 * normal rule of thumb is 1/64 the size of RAM, but that's much
1591 * more than needed for the Linux guests we support. */
1592 spapr
->htab_shift
= 18; /* Minimum architected size */
1593 while (spapr
->htab_shift
<= 46) {
1594 if ((1ULL << (spapr
->htab_shift
+ 7)) >= machine
->ram_size
) {
1597 spapr
->htab_shift
++;
1600 /* Set up Interrupt Controller before we create the VCPUs */
1601 spapr
->icp
= xics_system_init(machine
,
1602 DIV_ROUND_UP(max_cpus
* kvmppc_smt_threads(),
1606 if (smc
->dr_lmb_enabled
) {
1607 spapr_validate_node_memory(machine
);
1611 if (machine
->cpu_model
== NULL
) {
1612 machine
->cpu_model
= kvm_enabled() ? "host" : "POWER7";
1614 for (i
= 0; i
< smp_cpus
; i
++) {
1615 cpu
= cpu_ppc_init(machine
->cpu_model
);
1617 fprintf(stderr
, "Unable to find PowerPC CPU definition\n");
1620 spapr_cpu_init(spapr
, cpu
);
1623 if (kvm_enabled()) {
1624 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1625 kvmppc_enable_logical_ci_hcalls();
1626 kvmppc_enable_set_mode_hcall();
1630 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
1632 memory_region_add_subregion(sysmem
, 0, ram
);
1634 if (rma_alloc_size
&& rma
) {
1635 rma_region
= g_new(MemoryRegion
, 1);
1636 memory_region_init_ram_ptr(rma_region
, NULL
, "ppc_spapr.rma",
1637 rma_alloc_size
, rma
);
1638 vmstate_register_ram_global(rma_region
);
1639 memory_region_add_subregion(sysmem
, 0, rma_region
);
1642 /* initialize hotplug memory address space */
1643 if (machine
->ram_size
< machine
->maxram_size
) {
1644 ram_addr_t hotplug_mem_size
= machine
->maxram_size
- machine
->ram_size
;
1646 if (machine
->ram_slots
> SPAPR_MAX_RAM_SLOTS
) {
1647 error_report("unsupported amount of memory slots: %"PRIu64
,
1648 machine
->ram_slots
);
1652 spapr
->hotplug_memory
.base
= ROUND_UP(machine
->ram_size
,
1653 SPAPR_HOTPLUG_MEM_ALIGN
);
1654 memory_region_init(&spapr
->hotplug_memory
.mr
, OBJECT(spapr
),
1655 "hotplug-memory", hotplug_mem_size
);
1656 memory_region_add_subregion(sysmem
, spapr
->hotplug_memory
.base
,
1657 &spapr
->hotplug_memory
.mr
);
1660 if (smc
->dr_lmb_enabled
) {
1661 spapr_create_lmb_dr_connectors(spapr
);
1664 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
1666 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1669 spapr
->rtas_size
= get_image_size(filename
);
1670 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
1671 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
1672 error_report("Could not load LPAR rtas '%s'", filename
);
1675 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
1676 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1677 (size_t)spapr
->rtas_size
, RTAS_MAX_SIZE
);
1682 /* Set up EPOW events infrastructure */
1683 spapr_events_init(spapr
);
1685 /* Set up the RTC RTAS interfaces */
1686 spapr_rtc_create(spapr
);
1688 /* Set up VIO bus */
1689 spapr
->vio_bus
= spapr_vio_bus_init();
1691 for (i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1692 if (serial_hds
[i
]) {
1693 spapr_vty_create(spapr
->vio_bus
, serial_hds
[i
]);
1697 /* We always have at least the nvram device on VIO */
1698 spapr_create_nvram(spapr
);
1701 spapr_pci_rtas_init();
1703 phb
= spapr_create_phb(spapr
, 0);
1705 for (i
= 0; i
< nb_nics
; i
++) {
1706 NICInfo
*nd
= &nd_table
[i
];
1709 nd
->model
= g_strdup("ibmveth");
1712 if (strcmp(nd
->model
, "ibmveth") == 0) {
1713 spapr_vlan_create(spapr
->vio_bus
, nd
);
1715 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
1719 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
1720 spapr_vscsi_create(spapr
->vio_bus
);
1724 if (spapr_vga_init(phb
->bus
)) {
1725 spapr
->has_graphics
= true;
1726 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
1730 pci_create_simple(phb
->bus
, -1, "pci-ohci");
1732 if (spapr
->has_graphics
) {
1733 USBBus
*usb_bus
= usb_bus_find(-1);
1735 usb_create_simple(usb_bus
, "usb-kbd");
1736 usb_create_simple(usb_bus
, "usb-mouse");
1740 if (spapr
->rma_size
< (MIN_RMA_SLOF
<< 20)) {
1741 fprintf(stderr
, "qemu: pSeries SLOF firmware requires >= "
1742 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF
);
1746 if (kernel_filename
) {
1747 uint64_t lowaddr
= 0;
1749 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
1750 NULL
, &lowaddr
, NULL
, 1, ELF_MACHINE
, 0);
1751 if (kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
1752 kernel_size
= load_elf(kernel_filename
,
1753 translate_kernel_address
, NULL
,
1754 NULL
, &lowaddr
, NULL
, 0, ELF_MACHINE
, 0);
1755 kernel_le
= kernel_size
> 0;
1757 if (kernel_size
< 0) {
1758 fprintf(stderr
, "qemu: error loading %s: %s\n",
1759 kernel_filename
, load_elf_strerror(kernel_size
));
1764 if (initrd_filename
) {
1765 /* Try to locate the initrd in the gap between the kernel
1766 * and the firmware. Add a bit of space just in case
1768 initrd_base
= (KERNEL_LOAD_ADDR
+ kernel_size
+ 0x1ffff) & ~0xffff;
1769 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
1770 load_limit
- initrd_base
);
1771 if (initrd_size
< 0) {
1772 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
1782 if (bios_name
== NULL
) {
1783 bios_name
= FW_FILE_NAME
;
1785 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1787 error_report("Could not find LPAR firmware '%s'", bios_name
);
1790 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
1792 error_report("Could not load LPAR firmware '%s'", filename
);
1797 /* FIXME: Should register things through the MachineState's qdev
1798 * interface, this is a legacy from the sPAPREnvironment structure
1799 * which predated MachineState but had a similar function */
1800 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
1801 register_savevm_live(NULL
, "spapr/htab", -1, 1,
1802 &savevm_htab_handlers
, spapr
);
1804 /* Prepare the device tree */
1805 spapr
->fdt_skel
= spapr_create_fdt_skel(initrd_base
, initrd_size
,
1806 kernel_size
, kernel_le
,
1808 spapr
->check_exception_irq
);
1809 assert(spapr
->fdt_skel
!= NULL
);
1812 QTAILQ_INIT(&spapr
->ccs_list
);
1813 qemu_register_reset(spapr_ccs_reset_hook
, spapr
);
1815 qemu_register_boot_set(spapr_boot_set
, spapr
);
1818 static int spapr_kvm_type(const char *vm_type
)
1824 if (!strcmp(vm_type
, "HV")) {
1828 if (!strcmp(vm_type
, "PR")) {
1832 error_report("Unknown kvm-type specified '%s'", vm_type
);
1837 * Implementation of an interface to adjust firmware path
1838 * for the bootindex property handling.
1840 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
1843 #define CAST(type, obj, name) \
1844 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
1845 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
1846 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
1849 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
1850 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
1851 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
1855 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
1856 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
1857 * in the top 16 bits of the 64-bit LUN
1859 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
1860 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1861 (uint64_t)id
<< 48);
1862 } else if (virtio
) {
1864 * We use SRP luns of the form 01000000 | (target << 8) | lun
1865 * in the top 32 bits of the 64-bit LUN
1866 * Note: the quote above is from SLOF and it is wrong,
1867 * the actual binding is:
1868 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
1870 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
1871 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1872 (uint64_t)id
<< 32);
1875 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
1876 * in the top 32 bits of the 64-bit LUN
1878 unsigned usb_port
= atoi(usb
->port
->path
);
1879 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
1880 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
1881 (uint64_t)id
<< 32);
1886 /* Replace "pci" with "pci@800000020000000" */
1887 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
1893 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
1895 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
1897 return g_strdup(spapr
->kvm_type
);
1900 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
1902 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
1904 g_free(spapr
->kvm_type
);
1905 spapr
->kvm_type
= g_strdup(value
);
1908 static void spapr_machine_initfn(Object
*obj
)
1910 object_property_add_str(obj
, "kvm-type",
1911 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
1912 object_property_set_description(obj
, "kvm-type",
1913 "Specifies the KVM virtualization mode (HV, PR)",
1917 static void ppc_cpu_do_nmi_on_cpu(void *arg
)
1921 cpu_synchronize_state(cs
);
1922 ppc_cpu_do_system_reset(cs
);
1925 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
1930 async_run_on_cpu(cs
, ppc_cpu_do_nmi_on_cpu
, cs
);
1934 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
1936 MachineClass
*mc
= MACHINE_CLASS(oc
);
1937 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
1938 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
1939 NMIClass
*nc
= NMI_CLASS(oc
);
1941 mc
->init
= ppc_spapr_init
;
1942 mc
->reset
= ppc_spapr_reset
;
1943 mc
->block_default_type
= IF_SCSI
;
1944 mc
->max_cpus
= MAX_CPUMASK_BITS
;
1945 mc
->no_parallel
= 1;
1946 mc
->default_boot_order
= "";
1947 mc
->default_ram_size
= 512 * M_BYTE
;
1948 mc
->kvm_type
= spapr_kvm_type
;
1949 mc
->has_dynamic_sysbus
= true;
1950 mc
->pci_allow_0_address
= true;
1952 smc
->dr_lmb_enabled
= false;
1953 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
1954 nc
->nmi_monitor_handler
= spapr_nmi
;
1957 static const TypeInfo spapr_machine_info
= {
1958 .name
= TYPE_SPAPR_MACHINE
,
1959 .parent
= TYPE_MACHINE
,
1961 .instance_size
= sizeof(sPAPRMachineState
),
1962 .instance_init
= spapr_machine_initfn
,
1963 .class_size
= sizeof(sPAPRMachineClass
),
1964 .class_init
= spapr_machine_class_init
,
1965 .interfaces
= (InterfaceInfo
[]) {
1966 { TYPE_FW_PATH_PROVIDER
},
1972 #define SPAPR_COMPAT_2_3 \
1975 .driver = "spapr-pci-host-bridge",\
1976 .property = "dynamic-reconfiguration",\
1980 #define SPAPR_COMPAT_2_2 \
1984 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
1985 .property = "mem_win_size",\
1986 .value = "0x20000000",\
1989 #define SPAPR_COMPAT_2_1 \
1993 static void spapr_compat_2_3(Object
*obj
)
1995 savevm_skip_section_footers();
1996 global_state_set_optional();
1999 static void spapr_compat_2_2(Object
*obj
)
2001 spapr_compat_2_3(obj
);
2004 static void spapr_compat_2_1(Object
*obj
)
2006 spapr_compat_2_2(obj
);
2009 static void spapr_machine_2_3_instance_init(Object
*obj
)
2011 spapr_compat_2_3(obj
);
2012 spapr_machine_initfn(obj
);
2015 static void spapr_machine_2_2_instance_init(Object
*obj
)
2017 spapr_compat_2_2(obj
);
2018 spapr_machine_initfn(obj
);
2021 static void spapr_machine_2_1_instance_init(Object
*obj
)
2023 spapr_compat_2_1(obj
);
2024 spapr_machine_initfn(obj
);
2027 static void spapr_machine_2_1_class_init(ObjectClass
*oc
, void *data
)
2029 MachineClass
*mc
= MACHINE_CLASS(oc
);
2030 static GlobalProperty compat_props
[] = {
2032 { /* end of list */ }
2035 mc
->desc
= "pSeries Logical Partition (PAPR compliant) v2.1";
2036 mc
->compat_props
= compat_props
;
2039 static const TypeInfo spapr_machine_2_1_info
= {
2040 .name
= MACHINE_TYPE_NAME("pseries-2.1"),
2041 .parent
= TYPE_SPAPR_MACHINE
,
2042 .class_init
= spapr_machine_2_1_class_init
,
2043 .instance_init
= spapr_machine_2_1_instance_init
,
2046 static void spapr_machine_2_2_class_init(ObjectClass
*oc
, void *data
)
2048 static GlobalProperty compat_props
[] = {
2050 { /* end of list */ }
2052 MachineClass
*mc
= MACHINE_CLASS(oc
);
2054 mc
->desc
= "pSeries Logical Partition (PAPR compliant) v2.2";
2055 mc
->compat_props
= compat_props
;
2058 static const TypeInfo spapr_machine_2_2_info
= {
2059 .name
= MACHINE_TYPE_NAME("pseries-2.2"),
2060 .parent
= TYPE_SPAPR_MACHINE
,
2061 .class_init
= spapr_machine_2_2_class_init
,
2062 .instance_init
= spapr_machine_2_2_instance_init
,
2065 static void spapr_machine_2_3_class_init(ObjectClass
*oc
, void *data
)
2067 static GlobalProperty compat_props
[] = {
2069 { /* end of list */ }
2071 MachineClass
*mc
= MACHINE_CLASS(oc
);
2073 mc
->desc
= "pSeries Logical Partition (PAPR compliant) v2.3";
2074 mc
->compat_props
= compat_props
;
2077 static const TypeInfo spapr_machine_2_3_info
= {
2078 .name
= MACHINE_TYPE_NAME("pseries-2.3"),
2079 .parent
= TYPE_SPAPR_MACHINE
,
2080 .class_init
= spapr_machine_2_3_class_init
,
2081 .instance_init
= spapr_machine_2_3_instance_init
,
2084 static void spapr_machine_2_4_class_init(ObjectClass
*oc
, void *data
)
2086 MachineClass
*mc
= MACHINE_CLASS(oc
);
2088 mc
->desc
= "pSeries Logical Partition (PAPR compliant) v2.4";
2089 mc
->alias
= "pseries";
2093 static const TypeInfo spapr_machine_2_4_info
= {
2094 .name
= MACHINE_TYPE_NAME("pseries-2.4"),
2095 .parent
= TYPE_SPAPR_MACHINE
,
2096 .class_init
= spapr_machine_2_4_class_init
,
2099 static void spapr_machine_2_5_class_init(ObjectClass
*oc
, void *data
)
2101 MachineClass
*mc
= MACHINE_CLASS(oc
);
2102 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
2104 mc
->name
= "pseries-2.5";
2105 mc
->desc
= "pSeries Logical Partition (PAPR compliant) v2.5";
2106 mc
->alias
= "pseries";
2108 smc
->dr_lmb_enabled
= true;
2111 static const TypeInfo spapr_machine_2_5_info
= {
2112 .name
= MACHINE_TYPE_NAME("pseries-2.5"),
2113 .parent
= TYPE_SPAPR_MACHINE
,
2114 .class_init
= spapr_machine_2_5_class_init
,
2117 static void spapr_machine_register_types(void)
2119 type_register_static(&spapr_machine_info
);
2120 type_register_static(&spapr_machine_2_1_info
);
2121 type_register_static(&spapr_machine_2_2_info
);
2122 type_register_static(&spapr_machine_2_3_info
);
2123 type_register_static(&spapr_machine_2_4_info
);
2124 type_register_static(&spapr_machine_2_5_info
);
2127 type_init(spapr_machine_register_types
)