target-cris/cpu.c

   1 /*
   2  * QEMU CRIS CPU
   3  *
   4  * Copyright (c) 2008 AXIS Communications AB
   5  * Written by Edgar E. Iglesias.
   6  *
   7  * Copyright (c) 2012 SUSE LINUX Products GmbH
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "cpu.h"
  25 #include "qemu-common.h"
  26 #include "mmu.h"
  27
  28
  29 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     CRISCPU *cpu = CRIS_CPU(cs);
  32
  33     cpu->env.pc = value;
  34 }
  35
  36 /* CPUClass::reset() */
  37 static void cris_cpu_reset(CPUState *s)
  38 {
  39     CRISCPU *cpu = CRIS_CPU(s);
  40     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
  41     CPUCRISState *env = &cpu->env;
  42     uint32_t vr;
  43
  44     ccc->parent_reset(s);
  45
  46     vr = env->pregs[PR_VR];
  47     memset(env, 0, offsetof(CPUCRISState, breakpoints));
  48     env->pregs[PR_VR] = vr;
  49     tlb_flush(env, 1);
  50
  51 #if defined(CONFIG_USER_ONLY)
  52     /* start in user mode with interrupts enabled.  */
  53     env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
  54 #else
  55     cris_mmu_init(env);
  56     env->pregs[PR_CCS] = 0;
  57 #endif
  58 }
  59
  60 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
  61 {
  62     ObjectClass *oc;
  63     char *typename;
  64
  65     if (cpu_model == NULL) {
  66         return NULL;
  67     }
  68
  69 #if defined(CONFIG_USER_ONLY)
  70     if (strcasecmp(cpu_model, "any") == 0) {
  71         return object_class_by_name("crisv32-" TYPE_CRIS_CPU);
  72     }
  73 #endif
  74
  75     typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model);
  76     oc = object_class_by_name(typename);
  77     g_free(typename);
  78     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
  79                        object_class_is_abstract(oc))) {
  80         oc = NULL;
  81     }
  82     return oc;
  83 }
  84
  85 CRISCPU *cpu_cris_init(const char *cpu_model)
  86 {
  87     CRISCPU *cpu;
  88     ObjectClass *oc;
  89
  90     oc = cris_cpu_class_by_name(cpu_model);
  91     if (oc == NULL) {
  92         return NULL;
  93     }
  94     cpu = CRIS_CPU(object_new(object_class_get_name(oc)));
  95
  96     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
  97
  98     return cpu;
  99 }
 100
 101 /* Sort alphabetically by VR. */
 102 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
 103 {
 104     CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
 105     CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
 106
 107     /*  */
 108     if (ccc_a->vr > ccc_b->vr) {
 109         return 1;
 110     } else if (ccc_a->vr < ccc_b->vr) {
 111         return -1;
 112     } else {
 113         return 0;
 114     }
 115 }
 116
 117 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
 118 {
 119     ObjectClass *oc = data;
 120     CPUListState *s = user_data;
 121     const char *typename = object_class_get_name(oc);
 122     char *name;
 123
 124     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU));
 125     (*s->cpu_fprintf)(s->file, "  %s\n", name);
 126     g_free(name);
 127 }
 128
 129 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 130 {
 131     CPUListState s = {
 132         .file = f,
 133         .cpu_fprintf = cpu_fprintf,
 134     };
 135     GSList *list;
 136
 137     list = object_class_get_list(TYPE_CRIS_CPU, false);
 138     list = g_slist_sort(list, cris_cpu_list_compare);
 139     (*cpu_fprintf)(f, "Available CPUs:\n");
 140     g_slist_foreach(list, cris_cpu_list_entry, &s);
 141     g_slist_free(list);
 142 }
 143
 144 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
 145 {
 146     CPUState *cs = CPU(dev);
 147     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
 148
 149     cpu_reset(cs);
 150     qemu_init_vcpu(cs);
 151
 152     ccc->parent_realize(dev, errp);
 153 }
 154
 155 #ifndef CONFIG_USER_ONLY
 156 static void cris_cpu_set_irq(void *opaque, int irq, int level)
 157 {
 158     CRISCPU *cpu = opaque;
 159     CPUState *cs = CPU(cpu);
 160     int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
 161
 162     if (level) {
 163         cpu_interrupt(cs, type);
 164     } else {
 165         cpu_reset_interrupt(cs, type);
 166     }
 167 }
 168 #endif
 169
 170 static void cris_cpu_initfn(Object *obj)
 171 {
 172     CPUState *cs = CPU(obj);
 173     CRISCPU *cpu = CRIS_CPU(obj);
 174     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
 175     CPUCRISState *env = &cpu->env;
 176     static bool tcg_initialized;
 177
 178     cs->env_ptr = env;
 179     cpu_exec_init(env);
 180
 181     env->pregs[PR_VR] = ccc->vr;
 182
 183 #ifndef CONFIG_USER_ONLY
 184     /* IRQ and NMI lines.  */
 185     qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
 186 #endif
 187
 188     if (tcg_enabled() && !tcg_initialized) {
 189         tcg_initialized = true;
 190         if (env->pregs[PR_VR] < 32) {
 191             cris_initialize_crisv10_tcg();
 192         } else {
 193             cris_initialize_tcg();
 194         }
 195     }
 196 }
 197
 198 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
 199 {
 200     CPUClass *cc = CPU_CLASS(oc);
 201     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 202
 203     ccc->vr = 8;
 204     cc->do_interrupt = crisv10_cpu_do_interrupt;
 205     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 206 }
 207
 208 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
 209 {
 210     CPUClass *cc = CPU_CLASS(oc);
 211     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 212
 213     ccc->vr = 9;
 214     cc->do_interrupt = crisv10_cpu_do_interrupt;
 215     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 216 }
 217
 218 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
 219 {
 220     CPUClass *cc = CPU_CLASS(oc);
 221     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 222
 223     ccc->vr = 10;
 224     cc->do_interrupt = crisv10_cpu_do_interrupt;
 225     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 226 }
 227
 228 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
 229 {
 230     CPUClass *cc = CPU_CLASS(oc);
 231     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 232
 233     ccc->vr = 11;
 234     cc->do_interrupt = crisv10_cpu_do_interrupt;
 235     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 236 }
 237
 238 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
 239 {
 240     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 241
 242     ccc->vr = 32;
 243 }
 244
 245 #define TYPE(model) model "-" TYPE_CRIS_CPU
 246
 247 static const TypeInfo cris_cpu_model_type_infos[] = {
 248     {
 249         .name = TYPE("crisv8"),
 250         .parent = TYPE_CRIS_CPU,
 251         .class_init = crisv8_cpu_class_init,
 252     }, {
 253         .name = TYPE("crisv9"),
 254         .parent = TYPE_CRIS_CPU,
 255         .class_init = crisv9_cpu_class_init,
 256     }, {
 257         .name = TYPE("crisv10"),
 258         .parent = TYPE_CRIS_CPU,
 259         .class_init = crisv10_cpu_class_init,
 260     }, {
 261         .name = TYPE("crisv11"),
 262         .parent = TYPE_CRIS_CPU,
 263         .class_init = crisv11_cpu_class_init,
 264     }, {
 265         .name = TYPE("crisv32"),
 266         .parent = TYPE_CRIS_CPU,
 267         .class_init = crisv32_cpu_class_init,
 268     }
 269 };
 270
 271 #undef TYPE
 272
 273 static void cris_cpu_class_init(ObjectClass *oc, void *data)
 274 {
 275     DeviceClass *dc = DEVICE_CLASS(oc);
 276     CPUClass *cc = CPU_CLASS(oc);
 277     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 278
 279     ccc->parent_realize = dc->realize;
 280     dc->realize = cris_cpu_realizefn;
 281
 282     ccc->parent_reset = cc->reset;
 283     cc->reset = cris_cpu_reset;
 284
 285     cc->class_by_name = cris_cpu_class_by_name;
 286     cc->do_interrupt = cris_cpu_do_interrupt;
 287     cc->dump_state = cris_cpu_dump_state;
 288     cc->set_pc = cris_cpu_set_pc;
 289     cc->gdb_read_register = cris_cpu_gdb_read_register;
 290     cc->gdb_write_register = cris_cpu_gdb_write_register;
 291 #ifndef CONFIG_USER_ONLY
 292     cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
 293 #endif
 294
 295     cc->gdb_num_core_regs = 49;
 296 }
 297
 298 static const TypeInfo cris_cpu_type_info = {
 299     .name = TYPE_CRIS_CPU,
 300     .parent = TYPE_CPU,
 301     .instance_size = sizeof(CRISCPU),
 302     .instance_init = cris_cpu_initfn,
 303     .abstract = true,
 304     .class_size = sizeof(CRISCPUClass),
 305     .class_init = cris_cpu_class_init,
 306 };
 307
 308 static void cris_cpu_register_types(void)
 309 {
 310     int i;
 311
 312     type_register_static(&cris_cpu_type_info);
 313     for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) {
 314         type_register_static(&cris_cpu_model_type_infos[i]);
 315     }
 316 }
 317
 318 type_init(cris_cpu_register_types)