2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
24 #include "qemu/timer.h"
25 #include "qemu/module.h"
26 #include "qemu/queue.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/msi.h"
30 #include "hw/pci/msix.h"
32 #include "qapi/error.h"
40 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
42 #define DPRINTF(...) do {} while (0)
44 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
45 __func__, __LINE__, _msg); abort(); } while (0)
47 #define TRB_LINK_LIMIT 32
48 #define COMMAND_LIMIT 256
49 #define TRANSFER_LIMIT 256
52 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
53 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
54 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
56 #define OFF_OPER LEN_CAP
57 #define OFF_RUNTIME 0x1000
58 #define OFF_DOORBELL 0x2000
59 #define OFF_MSIX_TABLE 0x3000
60 #define OFF_MSIX_PBA 0x3800
61 /* must be power of 2 */
62 #define LEN_REGS 0x4000
64 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
65 #error Increase OFF_RUNTIME
67 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
68 #error Increase OFF_DOORBELL
70 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
71 # error Increase LEN_REGS
75 #define USBCMD_RS (1<<0)
76 #define USBCMD_HCRST (1<<1)
77 #define USBCMD_INTE (1<<2)
78 #define USBCMD_HSEE (1<<3)
79 #define USBCMD_LHCRST (1<<7)
80 #define USBCMD_CSS (1<<8)
81 #define USBCMD_CRS (1<<9)
82 #define USBCMD_EWE (1<<10)
83 #define USBCMD_EU3S (1<<11)
85 #define USBSTS_HCH (1<<0)
86 #define USBSTS_HSE (1<<2)
87 #define USBSTS_EINT (1<<3)
88 #define USBSTS_PCD (1<<4)
89 #define USBSTS_SSS (1<<8)
90 #define USBSTS_RSS (1<<9)
91 #define USBSTS_SRE (1<<10)
92 #define USBSTS_CNR (1<<11)
93 #define USBSTS_HCE (1<<12)
96 #define PORTSC_CCS (1<<0)
97 #define PORTSC_PED (1<<1)
98 #define PORTSC_OCA (1<<3)
99 #define PORTSC_PR (1<<4)
100 #define PORTSC_PLS_SHIFT 5
101 #define PORTSC_PLS_MASK 0xf
102 #define PORTSC_PP (1<<9)
103 #define PORTSC_SPEED_SHIFT 10
104 #define PORTSC_SPEED_MASK 0xf
105 #define PORTSC_SPEED_FULL (1<<10)
106 #define PORTSC_SPEED_LOW (2<<10)
107 #define PORTSC_SPEED_HIGH (3<<10)
108 #define PORTSC_SPEED_SUPER (4<<10)
109 #define PORTSC_PIC_SHIFT 14
110 #define PORTSC_PIC_MASK 0x3
111 #define PORTSC_LWS (1<<16)
112 #define PORTSC_CSC (1<<17)
113 #define PORTSC_PEC (1<<18)
114 #define PORTSC_WRC (1<<19)
115 #define PORTSC_OCC (1<<20)
116 #define PORTSC_PRC (1<<21)
117 #define PORTSC_PLC (1<<22)
118 #define PORTSC_CEC (1<<23)
119 #define PORTSC_CAS (1<<24)
120 #define PORTSC_WCE (1<<25)
121 #define PORTSC_WDE (1<<26)
122 #define PORTSC_WOE (1<<27)
123 #define PORTSC_DR (1<<30)
124 #define PORTSC_WPR (1<<31)
126 #define CRCR_RCS (1<<0)
127 #define CRCR_CS (1<<1)
128 #define CRCR_CA (1<<2)
129 #define CRCR_CRR (1<<3)
131 #define IMAN_IP (1<<0)
132 #define IMAN_IE (1<<1)
134 #define ERDP_EHB (1<<3)
137 typedef struct XHCITRB
{
156 PLS_COMPILANCE_MODE
= 10,
161 #define CR_LINK TR_LINK
164 #define TRB_TYPE_SHIFT 10
165 #define TRB_TYPE_MASK 0x3f
166 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
168 #define TRB_EV_ED (1<<2)
170 #define TRB_TR_ENT (1<<1)
171 #define TRB_TR_ISP (1<<2)
172 #define TRB_TR_NS (1<<3)
173 #define TRB_TR_CH (1<<4)
174 #define TRB_TR_IOC (1<<5)
175 #define TRB_TR_IDT (1<<6)
176 #define TRB_TR_TBC_SHIFT 7
177 #define TRB_TR_TBC_MASK 0x3
178 #define TRB_TR_BEI (1<<9)
179 #define TRB_TR_TLBPC_SHIFT 16
180 #define TRB_TR_TLBPC_MASK 0xf
181 #define TRB_TR_FRAMEID_SHIFT 20
182 #define TRB_TR_FRAMEID_MASK 0x7ff
183 #define TRB_TR_SIA (1<<31)
185 #define TRB_TR_DIR (1<<16)
187 #define TRB_CR_SLOTID_SHIFT 24
188 #define TRB_CR_SLOTID_MASK 0xff
189 #define TRB_CR_EPID_SHIFT 16
190 #define TRB_CR_EPID_MASK 0x1f
192 #define TRB_CR_BSR (1<<9)
193 #define TRB_CR_DC (1<<9)
195 #define TRB_LK_TC (1<<1)
197 #define TRB_INTR_SHIFT 22
198 #define TRB_INTR_MASK 0x3ff
199 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
201 #define EP_TYPE_MASK 0x7
202 #define EP_TYPE_SHIFT 3
204 #define EP_STATE_MASK 0x7
205 #define EP_DISABLED (0<<0)
206 #define EP_RUNNING (1<<0)
207 #define EP_HALTED (2<<0)
208 #define EP_STOPPED (3<<0)
209 #define EP_ERROR (4<<0)
211 #define SLOT_STATE_MASK 0x1f
212 #define SLOT_STATE_SHIFT 27
213 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
214 #define SLOT_ENABLED 0
215 #define SLOT_DEFAULT 1
216 #define SLOT_ADDRESSED 2
217 #define SLOT_CONFIGURED 3
219 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
220 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
222 #define get_field(data, field) \
223 (((data) >> field##_SHIFT) & field##_MASK)
225 #define set_field(data, newval, field) do { \
226 uint32_t val = *data; \
227 val &= ~(field##_MASK << field##_SHIFT); \
228 val |= ((newval) & field##_MASK) << field##_SHIFT; \
232 typedef enum EPType
{
243 typedef struct XHCITransfer
{
244 XHCIEPContext
*epctx
;
251 unsigned int iso_pkts
;
252 unsigned int streamid
;
257 unsigned int trb_count
;
263 unsigned int pktsize
;
264 unsigned int cur_pkt
;
266 uint64_t mfindex_kick
;
268 QTAILQ_ENTRY(XHCITransfer
) next
;
271 struct XHCIStreamContext
{
277 struct XHCIEPContext
{
284 QTAILQ_HEAD(, XHCITransfer
) transfers
;
288 unsigned int max_psize
;
290 uint32_t kick_active
;
293 unsigned int max_pstreams
;
295 unsigned int nr_pstreams
;
296 XHCIStreamContext
*pstreams
;
298 /* iso xfer scheduling */
299 unsigned int interval
;
300 int64_t mfindex_last
;
301 QEMUTimer
*kick_timer
;
304 typedef struct XHCIEvRingSeg
{
311 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
312 unsigned int epid
, unsigned int streamid
);
313 static void xhci_kick_epctx(XHCIEPContext
*epctx
, unsigned int streamid
);
314 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
316 static void xhci_xfer_report(XHCITransfer
*xfer
);
317 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
318 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
319 static USBEndpoint
*xhci_epid_to_usbep(XHCIEPContext
*epctx
);
321 static const char *TRBType_names
[] = {
322 [TRB_RESERVED
] = "TRB_RESERVED",
323 [TR_NORMAL
] = "TR_NORMAL",
324 [TR_SETUP
] = "TR_SETUP",
325 [TR_DATA
] = "TR_DATA",
326 [TR_STATUS
] = "TR_STATUS",
327 [TR_ISOCH
] = "TR_ISOCH",
328 [TR_LINK
] = "TR_LINK",
329 [TR_EVDATA
] = "TR_EVDATA",
330 [TR_NOOP
] = "TR_NOOP",
331 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
332 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
333 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
334 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
335 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
336 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
337 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
338 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
339 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
340 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
341 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
342 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
343 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
344 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
345 [CR_NOOP
] = "CR_NOOP",
346 [ER_TRANSFER
] = "ER_TRANSFER",
347 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
348 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
349 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
350 [ER_DOORBELL
] = "ER_DOORBELL",
351 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
352 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
353 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
354 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
355 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
358 static const char *TRBCCode_names
[] = {
359 [CC_INVALID
] = "CC_INVALID",
360 [CC_SUCCESS
] = "CC_SUCCESS",
361 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
362 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
363 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
364 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
365 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
366 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
367 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
368 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
369 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
370 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
371 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
372 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
373 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
374 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
375 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
376 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
377 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
378 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
379 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
380 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
381 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
382 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
383 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
384 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
385 [CC_STOPPED
] = "CC_STOPPED",
386 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
387 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
388 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
389 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
390 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
391 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
392 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
393 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
394 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
397 static const char *ep_state_names
[] = {
398 [EP_DISABLED
] = "disabled",
399 [EP_RUNNING
] = "running",
400 [EP_HALTED
] = "halted",
401 [EP_STOPPED
] = "stopped",
402 [EP_ERROR
] = "error",
405 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
407 if (index
>= llen
|| list
[index
] == NULL
) {
413 static const char *trb_name(XHCITRB
*trb
)
415 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
416 ARRAY_SIZE(TRBType_names
));
419 static const char *event_name(XHCIEvent
*event
)
421 return lookup_name(event
->ccode
, TRBCCode_names
,
422 ARRAY_SIZE(TRBCCode_names
));
425 static const char *ep_state_name(uint32_t state
)
427 return lookup_name(state
, ep_state_names
,
428 ARRAY_SIZE(ep_state_names
));
431 static bool xhci_get_flag(XHCIState
*xhci
, enum xhci_flags bit
)
433 return xhci
->flags
& (1 << bit
);
436 static void xhci_set_flag(XHCIState
*xhci
, enum xhci_flags bit
)
438 xhci
->flags
|= (1 << bit
);
441 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
443 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
444 return (now
- xhci
->mfindex_start
) / 125000;
447 static void xhci_mfwrap_update(XHCIState
*xhci
)
449 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
450 uint32_t mfindex
, left
;
453 if ((xhci
->usbcmd
& bits
) == bits
) {
454 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
455 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
456 left
= 0x4000 - mfindex
;
457 timer_mod(xhci
->mfwrap_timer
, now
+ left
* 125000);
459 timer_del(xhci
->mfwrap_timer
);
463 static void xhci_mfwrap_timer(void *opaque
)
465 XHCIState
*xhci
= opaque
;
466 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
468 xhci_event(xhci
, &wrap
, 0);
469 xhci_mfwrap_update(xhci
);
472 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
474 if (sizeof(dma_addr_t
) == 4) {
477 return low
| (((dma_addr_t
)high
<< 16) << 16);
481 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
483 if (sizeof(dma_addr_t
) == 4) {
484 return addr
& 0xffffffff;
490 static inline void xhci_dma_read_u32s(XHCIState
*xhci
, dma_addr_t addr
,
491 uint32_t *buf
, size_t len
)
495 assert((len
% sizeof(uint32_t)) == 0);
497 pci_dma_read(PCI_DEVICE(xhci
), addr
, buf
, len
);
499 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
500 buf
[i
] = le32_to_cpu(buf
[i
]);
504 static inline void xhci_dma_write_u32s(XHCIState
*xhci
, dma_addr_t addr
,
505 uint32_t *buf
, size_t len
)
509 uint32_t n
= len
/ sizeof(uint32_t);
511 assert((len
% sizeof(uint32_t)) == 0);
512 assert(n
<= ARRAY_SIZE(tmp
));
514 for (i
= 0; i
< n
; i
++) {
515 tmp
[i
] = cpu_to_le32(buf
[i
]);
517 pci_dma_write(PCI_DEVICE(xhci
), addr
, tmp
, len
);
520 static XHCIPort
*xhci_lookup_port(XHCIState
*xhci
, struct USBPort
*uport
)
527 switch (uport
->dev
->speed
) {
531 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
532 index
= uport
->index
+ xhci
->numports_3
;
534 index
= uport
->index
;
537 case USB_SPEED_SUPER
:
538 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
539 index
= uport
->index
;
541 index
= uport
->index
+ xhci
->numports_2
;
547 return &xhci
->ports
[index
];
550 static void xhci_intx_update(XHCIState
*xhci
)
552 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
555 if (msix_enabled(pci_dev
) ||
556 msi_enabled(pci_dev
)) {
560 if (xhci
->intr
[0].iman
& IMAN_IP
&&
561 xhci
->intr
[0].iman
& IMAN_IE
&&
562 xhci
->usbcmd
& USBCMD_INTE
) {
566 trace_usb_xhci_irq_intx(level
);
567 pci_set_irq(pci_dev
, level
);
570 static void xhci_msix_update(XHCIState
*xhci
, int v
)
572 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
575 if (!msix_enabled(pci_dev
)) {
579 enabled
= xhci
->intr
[v
].iman
& IMAN_IE
;
580 if (enabled
== xhci
->intr
[v
].msix_used
) {
585 trace_usb_xhci_irq_msix_use(v
);
586 msix_vector_use(pci_dev
, v
);
587 xhci
->intr
[v
].msix_used
= true;
589 trace_usb_xhci_irq_msix_unuse(v
);
590 msix_vector_unuse(pci_dev
, v
);
591 xhci
->intr
[v
].msix_used
= false;
595 static void xhci_intr_raise(XHCIState
*xhci
, int v
)
597 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
598 bool pending
= (xhci
->intr
[v
].erdp_low
& ERDP_EHB
);
600 xhci
->intr
[v
].erdp_low
|= ERDP_EHB
;
601 xhci
->intr
[v
].iman
|= IMAN_IP
;
602 xhci
->usbsts
|= USBSTS_EINT
;
607 if (!(xhci
->intr
[v
].iman
& IMAN_IE
)) {
611 if (!(xhci
->usbcmd
& USBCMD_INTE
)) {
615 if (msix_enabled(pci_dev
)) {
616 trace_usb_xhci_irq_msix(v
);
617 msix_notify(pci_dev
, v
);
621 if (msi_enabled(pci_dev
)) {
622 trace_usb_xhci_irq_msi(v
);
623 msi_notify(pci_dev
, v
);
628 trace_usb_xhci_irq_intx(1);
629 pci_irq_assert(pci_dev
);
633 static inline int xhci_running(XHCIState
*xhci
)
635 return !(xhci
->usbsts
& USBSTS_HCH
);
638 static void xhci_die(XHCIState
*xhci
)
640 xhci
->usbsts
|= USBSTS_HCE
;
641 DPRINTF("xhci: asserted controller error\n");
644 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
646 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
647 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
651 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
652 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
653 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
654 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
656 ev_trb
.control
|= TRB_C
;
658 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
660 trace_usb_xhci_queue_event(v
, intr
->er_ep_idx
, trb_name(&ev_trb
),
661 event_name(event
), ev_trb
.parameter
,
662 ev_trb
.status
, ev_trb
.control
);
664 addr
= intr
->er_start
+ TRB_SIZE
*intr
->er_ep_idx
;
665 pci_dma_write(pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
668 if (intr
->er_ep_idx
>= intr
->er_size
) {
670 intr
->er_pcs
= !intr
->er_pcs
;
674 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
676 XHCIInterrupter
*intr
;
680 if (v
>= xhci
->numintrs
) {
681 DPRINTF("intr nr out of range (%d >= %d)\n", v
, xhci
->numintrs
);
684 intr
= &xhci
->intr
[v
];
686 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
687 if (erdp
< intr
->er_start
||
688 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
689 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
690 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
691 v
, intr
->er_start
, intr
->er_size
);
696 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
697 assert(dp_idx
< intr
->er_size
);
699 if ((intr
->er_ep_idx
+ 2) % intr
->er_size
== dp_idx
) {
700 DPRINTF("xhci: ER %d full, send ring full error\n", v
);
701 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
702 xhci_write_event(xhci
, &full
, v
);
703 } else if ((intr
->er_ep_idx
+ 1) % intr
->er_size
== dp_idx
) {
704 DPRINTF("xhci: ER %d full, drop event\n", v
);
706 xhci_write_event(xhci
, event
, v
);
709 xhci_intr_raise(xhci
, v
);
712 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
715 ring
->dequeue
= base
;
719 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
722 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
723 uint32_t link_cnt
= 0;
727 pci_dma_read(pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
728 trb
->addr
= ring
->dequeue
;
729 trb
->ccs
= ring
->ccs
;
730 le64_to_cpus(&trb
->parameter
);
731 le32_to_cpus(&trb
->status
);
732 le32_to_cpus(&trb
->control
);
734 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
735 trb
->parameter
, trb
->status
, trb
->control
);
737 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
741 type
= TRB_TYPE(*trb
);
743 if (type
!= TR_LINK
) {
745 *addr
= ring
->dequeue
;
747 ring
->dequeue
+= TRB_SIZE
;
750 if (++link_cnt
> TRB_LINK_LIMIT
) {
751 trace_usb_xhci_enforced_limit("trb-link");
754 ring
->dequeue
= xhci_mask64(trb
->parameter
);
755 if (trb
->control
& TRB_LK_TC
) {
756 ring
->ccs
= !ring
->ccs
;
762 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
764 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
767 dma_addr_t dequeue
= ring
->dequeue
;
768 bool ccs
= ring
->ccs
;
769 /* hack to bundle together the two/three TDs that make a setup transfer */
770 bool control_td_set
= 0;
771 uint32_t link_cnt
= 0;
775 pci_dma_read(pci_dev
, dequeue
, &trb
, TRB_SIZE
);
776 le64_to_cpus(&trb
.parameter
);
777 le32_to_cpus(&trb
.status
);
778 le32_to_cpus(&trb
.control
);
780 if ((trb
.control
& TRB_C
) != ccs
) {
784 type
= TRB_TYPE(trb
);
786 if (type
== TR_LINK
) {
787 if (++link_cnt
> TRB_LINK_LIMIT
) {
790 dequeue
= xhci_mask64(trb
.parameter
);
791 if (trb
.control
& TRB_LK_TC
) {
800 if (type
== TR_SETUP
) {
802 } else if (type
== TR_STATUS
) {
806 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
812 static void xhci_er_reset(XHCIState
*xhci
, int v
)
814 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
816 dma_addr_t erstba
= xhci_addr64(intr
->erstba_low
, intr
->erstba_high
);
818 if (intr
->erstsz
== 0 || erstba
== 0) {
824 /* cache the (sole) event ring segment location */
825 if (intr
->erstsz
!= 1) {
826 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr
->erstsz
);
830 pci_dma_read(PCI_DEVICE(xhci
), erstba
, &seg
, sizeof(seg
));
831 le32_to_cpus(&seg
.addr_low
);
832 le32_to_cpus(&seg
.addr_high
);
833 le32_to_cpus(&seg
.size
);
834 if (seg
.size
< 16 || seg
.size
> 4096) {
835 DPRINTF("xhci: invalid value for segment size: %d\n", seg
.size
);
839 intr
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
840 intr
->er_size
= seg
.size
;
845 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT
" [%d]\n",
846 v
, intr
->er_start
, intr
->er_size
);
849 static void xhci_run(XHCIState
*xhci
)
851 trace_usb_xhci_run();
852 xhci
->usbsts
&= ~USBSTS_HCH
;
853 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
856 static void xhci_stop(XHCIState
*xhci
)
858 trace_usb_xhci_stop();
859 xhci
->usbsts
|= USBSTS_HCH
;
860 xhci
->crcr_low
&= ~CRCR_CRR
;
863 static XHCIStreamContext
*xhci_alloc_stream_contexts(unsigned count
,
866 XHCIStreamContext
*stctx
;
869 stctx
= g_new0(XHCIStreamContext
, count
);
870 for (i
= 0; i
< count
; i
++) {
871 stctx
[i
].pctx
= base
+ i
* 16;
877 static void xhci_reset_streams(XHCIEPContext
*epctx
)
881 for (i
= 0; i
< epctx
->nr_pstreams
; i
++) {
882 epctx
->pstreams
[i
].sct
= -1;
886 static void xhci_alloc_streams(XHCIEPContext
*epctx
, dma_addr_t base
)
888 assert(epctx
->pstreams
== NULL
);
889 epctx
->nr_pstreams
= 2 << epctx
->max_pstreams
;
890 epctx
->pstreams
= xhci_alloc_stream_contexts(epctx
->nr_pstreams
, base
);
893 static void xhci_free_streams(XHCIEPContext
*epctx
)
895 assert(epctx
->pstreams
!= NULL
);
897 g_free(epctx
->pstreams
);
898 epctx
->pstreams
= NULL
;
899 epctx
->nr_pstreams
= 0;
902 static int xhci_epmask_to_eps_with_streams(XHCIState
*xhci
,
905 XHCIEPContext
**epctxs
,
909 XHCIEPContext
*epctx
;
913 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
915 slot
= &xhci
->slots
[slotid
- 1];
917 for (i
= 2, j
= 0; i
<= 31; i
++) {
918 if (!(epmask
& (1u << i
))) {
922 epctx
= slot
->eps
[i
- 1];
923 ep
= xhci_epid_to_usbep(epctx
);
924 if (!epctx
|| !epctx
->nr_pstreams
|| !ep
) {
936 static void xhci_free_device_streams(XHCIState
*xhci
, unsigned int slotid
,
939 USBEndpoint
*eps
[30];
942 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, NULL
, eps
);
944 usb_device_free_streams(eps
[0]->dev
, eps
, nr_eps
);
948 static TRBCCode
xhci_alloc_device_streams(XHCIState
*xhci
, unsigned int slotid
,
951 XHCIEPContext
*epctxs
[30];
952 USBEndpoint
*eps
[30];
953 int i
, r
, nr_eps
, req_nr_streams
, dev_max_streams
;
955 nr_eps
= xhci_epmask_to_eps_with_streams(xhci
, slotid
, epmask
, epctxs
,
961 req_nr_streams
= epctxs
[0]->nr_pstreams
;
962 dev_max_streams
= eps
[0]->max_streams
;
964 for (i
= 1; i
< nr_eps
; i
++) {
966 * HdG: I don't expect these to ever trigger, but if they do we need
967 * to come up with another solution, ie group identical endpoints
968 * together and make an usb_device_alloc_streams call per group.
970 if (epctxs
[i
]->nr_pstreams
!= req_nr_streams
) {
971 FIXME("guest streams config not identical for all eps");
972 return CC_RESOURCE_ERROR
;
974 if (eps
[i
]->max_streams
!= dev_max_streams
) {
975 FIXME("device streams config not identical for all eps");
976 return CC_RESOURCE_ERROR
;
981 * max-streams in both the device descriptor and in the controller is a
982 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
983 * streams the guest will ask for 5 rounded up to the next power of 2 which
984 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
986 * For redirected devices however this is an issue, as there we must ask
987 * the real xhci controller to alloc streams, and the host driver for the
988 * real xhci controller will likely disallow allocating more streams then
989 * the device can handle.
991 * So we limit the requested nr_streams to the maximum number the device
994 if (req_nr_streams
> dev_max_streams
) {
995 req_nr_streams
= dev_max_streams
;
998 r
= usb_device_alloc_streams(eps
[0]->dev
, eps
, nr_eps
, req_nr_streams
);
1000 DPRINTF("xhci: alloc streams failed\n");
1001 return CC_RESOURCE_ERROR
;
1007 static XHCIStreamContext
*xhci_find_stream(XHCIEPContext
*epctx
,
1008 unsigned int streamid
,
1011 XHCIStreamContext
*sctx
;
1013 uint32_t ctx
[2], sct
;
1015 assert(streamid
!= 0);
1017 if (streamid
>= epctx
->nr_pstreams
) {
1018 *cc_error
= CC_INVALID_STREAM_ID_ERROR
;
1021 sctx
= epctx
->pstreams
+ streamid
;
1023 FIXME("secondary streams not implemented yet");
1026 if (sctx
->sct
== -1) {
1027 xhci_dma_read_u32s(epctx
->xhci
, sctx
->pctx
, ctx
, sizeof(ctx
));
1028 sct
= (ctx
[0] >> 1) & 0x07;
1029 if (epctx
->lsa
&& sct
!= 1) {
1030 *cc_error
= CC_INVALID_STREAM_TYPE_ERROR
;
1034 base
= xhci_addr64(ctx
[0] & ~0xf, ctx
[1]);
1035 xhci_ring_init(epctx
->xhci
, &sctx
->ring
, base
);
1040 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
1041 XHCIStreamContext
*sctx
, uint32_t state
)
1043 XHCIRing
*ring
= NULL
;
1047 xhci_dma_read_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1048 ctx
[0] &= ~EP_STATE_MASK
;
1051 /* update ring dequeue ptr */
1052 if (epctx
->nr_pstreams
) {
1055 xhci_dma_read_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1057 ctx2
[0] |= sctx
->ring
.dequeue
| sctx
->ring
.ccs
;
1058 ctx2
[1] = (sctx
->ring
.dequeue
>> 16) >> 16;
1059 xhci_dma_write_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1062 ring
= &epctx
->ring
;
1065 ctx
[2] = ring
->dequeue
| ring
->ccs
;
1066 ctx
[3] = (ring
->dequeue
>> 16) >> 16;
1068 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
1069 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
1072 xhci_dma_write_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1073 if (epctx
->state
!= state
) {
1074 trace_usb_xhci_ep_state(epctx
->slotid
, epctx
->epid
,
1075 ep_state_name(epctx
->state
),
1076 ep_state_name(state
));
1078 epctx
->state
= state
;
1081 static void xhci_ep_kick_timer(void *opaque
)
1083 XHCIEPContext
*epctx
= opaque
;
1084 xhci_kick_epctx(epctx
, 0);
1087 static XHCIEPContext
*xhci_alloc_epctx(XHCIState
*xhci
,
1088 unsigned int slotid
,
1091 XHCIEPContext
*epctx
;
1093 epctx
= g_new0(XHCIEPContext
, 1);
1095 epctx
->slotid
= slotid
;
1098 QTAILQ_INIT(&epctx
->transfers
);
1099 epctx
->kick_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_ep_kick_timer
, epctx
);
1104 static void xhci_init_epctx(XHCIEPContext
*epctx
,
1105 dma_addr_t pctx
, uint32_t *ctx
)
1109 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
1111 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
1113 epctx
->max_psize
= ctx
[1]>>16;
1114 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
1115 epctx
->max_pstreams
= (ctx
[0] >> 10) & epctx
->xhci
->max_pstreams_mask
;
1116 epctx
->lsa
= (ctx
[0] >> 15) & 1;
1117 if (epctx
->max_pstreams
) {
1118 xhci_alloc_streams(epctx
, dequeue
);
1120 xhci_ring_init(epctx
->xhci
, &epctx
->ring
, dequeue
);
1121 epctx
->ring
.ccs
= ctx
[2] & 1;
1124 epctx
->interval
= 1 << ((ctx
[0] >> 16) & 0xff);
1127 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
1128 unsigned int epid
, dma_addr_t pctx
,
1132 XHCIEPContext
*epctx
;
1134 trace_usb_xhci_ep_enable(slotid
, epid
);
1135 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1136 assert(epid
>= 1 && epid
<= 31);
1138 slot
= &xhci
->slots
[slotid
-1];
1139 if (slot
->eps
[epid
-1]) {
1140 xhci_disable_ep(xhci
, slotid
, epid
);
1143 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
1144 slot
->eps
[epid
-1] = epctx
;
1145 xhci_init_epctx(epctx
, pctx
, ctx
);
1147 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1148 "size is %d\n", epid
/2, epid
%2, epctx
->type
, epctx
->max_psize
);
1150 epctx
->mfindex_last
= 0;
1152 epctx
->state
= EP_RUNNING
;
1153 ctx
[0] &= ~EP_STATE_MASK
;
1154 ctx
[0] |= EP_RUNNING
;
1159 static XHCITransfer
*xhci_ep_alloc_xfer(XHCIEPContext
*epctx
,
1162 uint32_t limit
= epctx
->nr_pstreams
+ 16;
1165 if (epctx
->xfer_count
>= limit
) {
1169 xfer
= g_new0(XHCITransfer
, 1);
1170 xfer
->epctx
= epctx
;
1171 xfer
->trbs
= g_new(XHCITRB
, length
);
1172 xfer
->trb_count
= length
;
1173 usb_packet_init(&xfer
->packet
);
1175 QTAILQ_INSERT_TAIL(&epctx
->transfers
, xfer
, next
);
1176 epctx
->xfer_count
++;
1181 static void xhci_ep_free_xfer(XHCITransfer
*xfer
)
1183 QTAILQ_REMOVE(&xfer
->epctx
->transfers
, xfer
, next
);
1184 xfer
->epctx
->xfer_count
--;
1186 usb_packet_cleanup(&xfer
->packet
);
1191 static int xhci_ep_nuke_one_xfer(XHCITransfer
*t
, TRBCCode report
)
1195 if (report
&& (t
->running_async
|| t
->running_retry
)) {
1197 xhci_xfer_report(t
);
1200 if (t
->running_async
) {
1201 usb_cancel_packet(&t
->packet
);
1202 t
->running_async
= 0;
1205 if (t
->running_retry
) {
1207 t
->epctx
->retry
= NULL
;
1208 timer_del(t
->epctx
->kick_timer
);
1210 t
->running_retry
= 0;
1221 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
1222 unsigned int epid
, TRBCCode report
)
1225 XHCIEPContext
*epctx
;
1228 USBEndpoint
*ep
= NULL
;
1229 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1230 assert(epid
>= 1 && epid
<= 31);
1232 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
1234 slot
= &xhci
->slots
[slotid
-1];
1236 if (!slot
->eps
[epid
-1]) {
1240 epctx
= slot
->eps
[epid
-1];
1243 xfer
= QTAILQ_FIRST(&epctx
->transfers
);
1247 killed
+= xhci_ep_nuke_one_xfer(xfer
, report
);
1249 report
= 0; /* Only report once */
1251 xhci_ep_free_xfer(xfer
);
1254 ep
= xhci_epid_to_usbep(epctx
);
1256 usb_device_ep_stopped(ep
->dev
, ep
);
1261 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1265 XHCIEPContext
*epctx
;
1267 trace_usb_xhci_ep_disable(slotid
, epid
);
1268 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1269 assert(epid
>= 1 && epid
<= 31);
1271 slot
= &xhci
->slots
[slotid
-1];
1273 if (!slot
->eps
[epid
-1]) {
1274 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1278 xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0);
1280 epctx
= slot
->eps
[epid
-1];
1282 if (epctx
->nr_pstreams
) {
1283 xhci_free_streams(epctx
);
1286 /* only touch guest RAM if we're not resetting the HC */
1287 if (xhci
->dcbaap_low
|| xhci
->dcbaap_high
) {
1288 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_DISABLED
);
1291 timer_free(epctx
->kick_timer
);
1293 slot
->eps
[epid
-1] = NULL
;
1298 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1302 XHCIEPContext
*epctx
;
1304 trace_usb_xhci_ep_stop(slotid
, epid
);
1305 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1307 if (epid
< 1 || epid
> 31) {
1308 DPRINTF("xhci: bad ep %d\n", epid
);
1309 return CC_TRB_ERROR
;
1312 slot
= &xhci
->slots
[slotid
-1];
1314 if (!slot
->eps
[epid
-1]) {
1315 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1316 return CC_EP_NOT_ENABLED_ERROR
;
1319 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, CC_STOPPED
) > 0) {
1320 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1321 "data might be lost\n");
1324 epctx
= slot
->eps
[epid
-1];
1326 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1328 if (epctx
->nr_pstreams
) {
1329 xhci_reset_streams(epctx
);
1335 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1339 XHCIEPContext
*epctx
;
1341 trace_usb_xhci_ep_reset(slotid
, epid
);
1342 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1344 if (epid
< 1 || epid
> 31) {
1345 DPRINTF("xhci: bad ep %d\n", epid
);
1346 return CC_TRB_ERROR
;
1349 slot
= &xhci
->slots
[slotid
-1];
1351 if (!slot
->eps
[epid
-1]) {
1352 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1353 return CC_EP_NOT_ENABLED_ERROR
;
1356 epctx
= slot
->eps
[epid
-1];
1358 if (epctx
->state
!= EP_HALTED
) {
1359 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1360 epid
, epctx
->state
);
1361 return CC_CONTEXT_STATE_ERROR
;
1364 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0) > 0) {
1365 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1366 "data might be lost\n");
1369 if (!xhci
->slots
[slotid
-1].uport
||
1370 !xhci
->slots
[slotid
-1].uport
->dev
||
1371 !xhci
->slots
[slotid
-1].uport
->dev
->attached
) {
1372 return CC_USB_TRANSACTION_ERROR
;
1375 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1377 if (epctx
->nr_pstreams
) {
1378 xhci_reset_streams(epctx
);
1384 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1385 unsigned int epid
, unsigned int streamid
,
1389 XHCIEPContext
*epctx
;
1390 XHCIStreamContext
*sctx
;
1393 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1395 if (epid
< 1 || epid
> 31) {
1396 DPRINTF("xhci: bad ep %d\n", epid
);
1397 return CC_TRB_ERROR
;
1400 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, streamid
, pdequeue
);
1401 dequeue
= xhci_mask64(pdequeue
);
1403 slot
= &xhci
->slots
[slotid
-1];
1405 if (!slot
->eps
[epid
-1]) {
1406 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1407 return CC_EP_NOT_ENABLED_ERROR
;
1410 epctx
= slot
->eps
[epid
-1];
1412 if (epctx
->state
!= EP_STOPPED
) {
1413 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1414 return CC_CONTEXT_STATE_ERROR
;
1417 if (epctx
->nr_pstreams
) {
1419 sctx
= xhci_find_stream(epctx
, streamid
, &err
);
1423 xhci_ring_init(xhci
, &sctx
->ring
, dequeue
& ~0xf);
1424 sctx
->ring
.ccs
= dequeue
& 1;
1427 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1428 epctx
->ring
.ccs
= dequeue
& 1;
1431 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_STOPPED
);
1436 static int xhci_xfer_create_sgl(XHCITransfer
*xfer
, int in_xfer
)
1438 XHCIState
*xhci
= xfer
->epctx
->xhci
;
1441 xfer
->int_req
= false;
1442 pci_dma_sglist_init(&xfer
->sgl
, PCI_DEVICE(xhci
), xfer
->trb_count
);
1443 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1444 XHCITRB
*trb
= &xfer
->trbs
[i
];
1446 unsigned int chunk
= 0;
1448 if (trb
->control
& TRB_TR_IOC
) {
1449 xfer
->int_req
= true;
1452 switch (TRB_TYPE(*trb
)) {
1454 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1455 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1461 addr
= xhci_mask64(trb
->parameter
);
1462 chunk
= trb
->status
& 0x1ffff;
1463 if (trb
->control
& TRB_TR_IDT
) {
1464 if (chunk
> 8 || in_xfer
) {
1465 DPRINTF("xhci: invalid immediate data TRB\n");
1468 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1470 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1479 qemu_sglist_destroy(&xfer
->sgl
);
1484 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1486 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1487 qemu_sglist_destroy(&xfer
->sgl
);
1490 static void xhci_xfer_report(XHCITransfer
*xfer
)
1496 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1497 XHCIState
*xhci
= xfer
->epctx
->xhci
;
1500 left
= xfer
->packet
.actual_length
;
1502 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1503 XHCITRB
*trb
= &xfer
->trbs
[i
];
1504 unsigned int chunk
= 0;
1506 switch (TRB_TYPE(*trb
)) {
1508 chunk
= trb
->status
& 0x1ffff;
1516 chunk
= trb
->status
& 0x1ffff;
1519 if (xfer
->status
== CC_SUCCESS
) {
1532 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1533 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1534 (xfer
->status
!= CC_SUCCESS
&& left
== 0))) {
1535 event
.slotid
= xfer
->epctx
->slotid
;
1536 event
.epid
= xfer
->epctx
->epid
;
1537 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1539 event
.ptr
= trb
->addr
;
1540 if (xfer
->status
== CC_SUCCESS
) {
1541 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1543 event
.ccode
= xfer
->status
;
1545 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1546 event
.ptr
= trb
->parameter
;
1547 event
.flags
|= TRB_EV_ED
;
1548 event
.length
= edtla
& 0xffffff;
1549 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1552 xhci_event(xhci
, &event
, TRB_INTR(*trb
));
1554 if (xfer
->status
!= CC_SUCCESS
) {
1559 switch (TRB_TYPE(*trb
)) {
1569 static void xhci_stall_ep(XHCITransfer
*xfer
)
1571 XHCIEPContext
*epctx
= xfer
->epctx
;
1572 XHCIState
*xhci
= epctx
->xhci
;
1574 XHCIStreamContext
*sctx
;
1576 if (epctx
->type
== ET_ISO_IN
|| epctx
->type
== ET_ISO_OUT
) {
1577 /* never halt isoch endpoints, 4.10.2 */
1581 if (epctx
->nr_pstreams
) {
1582 sctx
= xhci_find_stream(epctx
, xfer
->streamid
, &err
);
1586 sctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1587 sctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1588 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_HALTED
);
1590 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1591 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1592 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_HALTED
);
1596 static int xhci_setup_packet(XHCITransfer
*xfer
)
1601 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1603 if (xfer
->packet
.ep
) {
1604 ep
= xfer
->packet
.ep
;
1606 ep
= xhci_epid_to_usbep(xfer
->epctx
);
1608 DPRINTF("xhci: slot %d has no device\n",
1609 xfer
->epctx
->slotid
);
1614 xhci_xfer_create_sgl(xfer
, dir
== USB_TOKEN_IN
); /* Also sets int_req */
1615 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->streamid
,
1616 xfer
->trbs
[0].addr
, false, xfer
->int_req
);
1617 usb_packet_map(&xfer
->packet
, &xfer
->sgl
);
1618 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1619 xfer
->packet
.pid
, ep
->dev
->addr
, ep
->nr
);
1623 static int xhci_try_complete_packet(XHCITransfer
*xfer
)
1625 if (xfer
->packet
.status
== USB_RET_ASYNC
) {
1626 trace_usb_xhci_xfer_async(xfer
);
1627 xfer
->running_async
= 1;
1628 xfer
->running_retry
= 0;
1631 } else if (xfer
->packet
.status
== USB_RET_NAK
) {
1632 trace_usb_xhci_xfer_nak(xfer
);
1633 xfer
->running_async
= 0;
1634 xfer
->running_retry
= 1;
1638 xfer
->running_async
= 0;
1639 xfer
->running_retry
= 0;
1641 xhci_xfer_unmap(xfer
);
1644 if (xfer
->packet
.status
== USB_RET_SUCCESS
) {
1645 trace_usb_xhci_xfer_success(xfer
, xfer
->packet
.actual_length
);
1646 xfer
->status
= CC_SUCCESS
;
1647 xhci_xfer_report(xfer
);
1652 trace_usb_xhci_xfer_error(xfer
, xfer
->packet
.status
);
1653 switch (xfer
->packet
.status
) {
1655 case USB_RET_IOERROR
:
1656 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1657 xhci_xfer_report(xfer
);
1658 xhci_stall_ep(xfer
);
1661 xfer
->status
= CC_STALL_ERROR
;
1662 xhci_xfer_report(xfer
);
1663 xhci_stall_ep(xfer
);
1665 case USB_RET_BABBLE
:
1666 xfer
->status
= CC_BABBLE_DETECTED
;
1667 xhci_xfer_report(xfer
);
1668 xhci_stall_ep(xfer
);
1671 DPRINTF("%s: FIXME: status = %d\n", __func__
,
1672 xfer
->packet
.status
);
1673 FIXME("unhandled USB_RET_*");
1678 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1680 XHCITRB
*trb_setup
, *trb_status
;
1681 uint8_t bmRequestType
;
1683 trb_setup
= &xfer
->trbs
[0];
1684 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1686 trace_usb_xhci_xfer_start(xfer
, xfer
->epctx
->slotid
,
1687 xfer
->epctx
->epid
, xfer
->streamid
);
1689 /* at most one Event Data TRB allowed after STATUS */
1690 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1694 /* do some sanity checks */
1695 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1696 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1697 TRB_TYPE(*trb_setup
));
1700 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1701 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1702 TRB_TYPE(*trb_status
));
1705 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1706 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1709 if ((trb_setup
->status
& 0x1ffff) != 8) {
1710 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1711 (trb_setup
->status
& 0x1ffff));
1715 bmRequestType
= trb_setup
->parameter
;
1717 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1718 xfer
->iso_xfer
= false;
1719 xfer
->timed_xfer
= false;
1721 if (xhci_setup_packet(xfer
) < 0) {
1724 xfer
->packet
.parameter
= trb_setup
->parameter
;
1726 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1727 xhci_try_complete_packet(xfer
);
1731 static void xhci_calc_intr_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1732 XHCIEPContext
*epctx
, uint64_t mfindex
)
1734 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1735 ~(epctx
->interval
-1));
1736 uint64_t kick
= epctx
->mfindex_last
+ epctx
->interval
;
1738 assert(epctx
->interval
!= 0);
1739 xfer
->mfindex_kick
= MAX(asap
, kick
);
1742 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1743 XHCIEPContext
*epctx
, uint64_t mfindex
)
1745 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1746 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1747 ~(epctx
->interval
-1));
1748 if (asap
>= epctx
->mfindex_last
&&
1749 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1750 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1752 xfer
->mfindex_kick
= asap
;
1755 xfer
->mfindex_kick
= ((xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1756 & TRB_TR_FRAMEID_MASK
) << 3;
1757 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1758 if (xfer
->mfindex_kick
+ 0x100 < mfindex
) {
1759 xfer
->mfindex_kick
+= 0x4000;
1764 static void xhci_check_intr_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1765 XHCIEPContext
*epctx
, uint64_t mfindex
)
1767 if (xfer
->mfindex_kick
> mfindex
) {
1768 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1769 (xfer
->mfindex_kick
- mfindex
) * 125000);
1770 xfer
->running_retry
= 1;
1772 epctx
->mfindex_last
= xfer
->mfindex_kick
;
1773 timer_del(epctx
->kick_timer
);
1774 xfer
->running_retry
= 0;
1779 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1783 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx
->slotid
, epctx
->epid
);
1785 xfer
->in_xfer
= epctx
->type
>>2;
1787 switch(epctx
->type
) {
1791 xfer
->iso_xfer
= false;
1792 xfer
->timed_xfer
= true;
1793 mfindex
= xhci_mfindex_get(xhci
);
1794 xhci_calc_intr_kick(xhci
, xfer
, epctx
, mfindex
);
1795 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1796 if (xfer
->running_retry
) {
1803 xfer
->iso_xfer
= false;
1804 xfer
->timed_xfer
= false;
1809 xfer
->iso_xfer
= true;
1810 xfer
->timed_xfer
= true;
1811 mfindex
= xhci_mfindex_get(xhci
);
1812 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1813 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1814 if (xfer
->running_retry
) {
1819 trace_usb_xhci_unimplemented("endpoint type", epctx
->type
);
1823 if (xhci_setup_packet(xfer
) < 0) {
1826 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1827 xhci_try_complete_packet(xfer
);
1831 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1833 trace_usb_xhci_xfer_start(xfer
, xfer
->epctx
->slotid
,
1834 xfer
->epctx
->epid
, xfer
->streamid
);
1835 return xhci_submit(xhci
, xfer
, epctx
);
1838 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
1839 unsigned int epid
, unsigned int streamid
)
1841 XHCIEPContext
*epctx
;
1843 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1844 assert(epid
>= 1 && epid
<= 31);
1846 if (!xhci
->slots
[slotid
-1].enabled
) {
1847 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1850 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1852 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1857 if (epctx
->kick_active
) {
1860 xhci_kick_epctx(epctx
, streamid
);
1863 static void xhci_kick_epctx(XHCIEPContext
*epctx
, unsigned int streamid
)
1865 XHCIState
*xhci
= epctx
->xhci
;
1866 XHCIStreamContext
*stctx
= NULL
;
1869 USBEndpoint
*ep
= NULL
;
1871 unsigned int count
= 0;
1875 trace_usb_xhci_ep_kick(epctx
->slotid
, epctx
->epid
, streamid
);
1876 assert(!epctx
->kick_active
);
1878 /* If the device has been detached, but the guest has not noticed this
1879 yet the 2 above checks will succeed, but we must NOT continue */
1880 if (!xhci
->slots
[epctx
->slotid
- 1].uport
||
1881 !xhci
->slots
[epctx
->slotid
- 1].uport
->dev
||
1882 !xhci
->slots
[epctx
->slotid
- 1].uport
->dev
->attached
) {
1887 XHCITransfer
*xfer
= epctx
->retry
;
1889 trace_usb_xhci_xfer_retry(xfer
);
1890 assert(xfer
->running_retry
);
1891 if (xfer
->timed_xfer
) {
1892 /* time to kick the transfer? */
1893 mfindex
= xhci_mfindex_get(xhci
);
1894 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1895 if (xfer
->running_retry
) {
1898 xfer
->timed_xfer
= 0;
1899 xfer
->running_retry
= 1;
1901 if (xfer
->iso_xfer
) {
1902 /* retry iso transfer */
1903 if (xhci_setup_packet(xfer
) < 0) {
1906 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1907 assert(xfer
->packet
.status
!= USB_RET_NAK
);
1908 xhci_try_complete_packet(xfer
);
1910 /* retry nak'ed transfer */
1911 if (xhci_setup_packet(xfer
) < 0) {
1914 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1915 if (xfer
->packet
.status
== USB_RET_NAK
) {
1918 xhci_try_complete_packet(xfer
);
1920 assert(!xfer
->running_retry
);
1921 if (xfer
->complete
) {
1922 /* update ring dequeue ptr */
1923 xhci_set_ep_state(xhci
, epctx
, stctx
, epctx
->state
);
1924 xhci_ep_free_xfer(epctx
->retry
);
1926 epctx
->retry
= NULL
;
1929 if (epctx
->state
== EP_HALTED
) {
1930 DPRINTF("xhci: ep halted, not running schedule\n");
1935 if (epctx
->nr_pstreams
) {
1937 stctx
= xhci_find_stream(epctx
, streamid
, &err
);
1938 if (stctx
== NULL
) {
1941 ring
= &stctx
->ring
;
1942 xhci_set_ep_state(xhci
, epctx
, stctx
, EP_RUNNING
);
1944 ring
= &epctx
->ring
;
1946 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_RUNNING
);
1948 assert(ring
->dequeue
!= 0);
1950 epctx
->kick_active
++;
1952 length
= xhci_ring_chain_length(xhci
, ring
);
1954 if (epctx
->type
== ET_ISO_OUT
|| epctx
->type
== ET_ISO_IN
) {
1956 XHCIEvent ev
= { ER_TRANSFER
};
1957 ev
.ccode
= epctx
->type
== ET_ISO_IN
?
1958 CC_RING_OVERRUN
: CC_RING_UNDERRUN
;
1959 ev
.slotid
= epctx
->slotid
;
1960 ev
.epid
= epctx
->epid
;
1961 ev
.ptr
= epctx
->ring
.dequeue
;
1962 xhci_event(xhci
, &ev
, xhci
->slots
[epctx
->slotid
-1].intr
);
1966 xfer
= xhci_ep_alloc_xfer(epctx
, length
);
1971 for (i
= 0; i
< length
; i
++) {
1973 type
= xhci_ring_fetch(xhci
, ring
, &xfer
->trbs
[i
], NULL
);
1976 xhci_ep_free_xfer(xfer
);
1977 epctx
->kick_active
--;
1981 xfer
->streamid
= streamid
;
1983 if (epctx
->epid
== 1) {
1984 xhci_fire_ctl_transfer(xhci
, xfer
);
1986 xhci_fire_transfer(xhci
, xfer
, epctx
);
1988 if (xfer
->complete
) {
1989 /* update ring dequeue ptr */
1990 xhci_set_ep_state(xhci
, epctx
, stctx
, epctx
->state
);
1991 xhci_ep_free_xfer(xfer
);
1995 if (epctx
->state
== EP_HALTED
) {
1998 if (xfer
!= NULL
&& xfer
->running_retry
) {
1999 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2000 epctx
->retry
= xfer
;
2003 if (count
++ > TRANSFER_LIMIT
) {
2004 trace_usb_xhci_enforced_limit("transfers");
2008 epctx
->kick_active
--;
2010 ep
= xhci_epid_to_usbep(epctx
);
2012 usb_device_flush_ep_queue(ep
->dev
, ep
);
2016 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
2018 trace_usb_xhci_slot_enable(slotid
);
2019 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2020 xhci
->slots
[slotid
-1].enabled
= 1;
2021 xhci
->slots
[slotid
-1].uport
= NULL
;
2022 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
2027 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
2031 trace_usb_xhci_slot_disable(slotid
);
2032 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2034 for (i
= 1; i
<= 31; i
++) {
2035 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2036 xhci_disable_ep(xhci
, slotid
, i
);
2040 xhci
->slots
[slotid
-1].enabled
= 0;
2041 xhci
->slots
[slotid
-1].addressed
= 0;
2042 xhci
->slots
[slotid
-1].uport
= NULL
;
2043 xhci
->slots
[slotid
-1].intr
= 0;
2047 static USBPort
*xhci_lookup_uport(XHCIState
*xhci
, uint32_t *slot_ctx
)
2053 port
= (slot_ctx
[1]>>16) & 0xFF;
2054 if (port
< 1 || port
> xhci
->numports
) {
2057 port
= xhci
->ports
[port
-1].uport
->index
+1;
2058 pos
= snprintf(path
, sizeof(path
), "%d", port
);
2059 for (i
= 0; i
< 5; i
++) {
2060 port
= (slot_ctx
[0] >> 4*i
) & 0x0f;
2064 pos
+= snprintf(path
+ pos
, sizeof(path
) - pos
, ".%d", port
);
2067 QTAILQ_FOREACH(uport
, &xhci
->bus
.used
, next
) {
2068 if (strcmp(uport
->path
, path
) == 0) {
2075 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
2076 uint64_t pictx
, bool bsr
)
2081 dma_addr_t ictx
, octx
, dcbaap
;
2083 uint32_t ictl_ctx
[2];
2084 uint32_t slot_ctx
[4];
2085 uint32_t ep0_ctx
[5];
2089 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2091 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
2092 poctx
= ldq_le_pci_dma(PCI_DEVICE(xhci
), dcbaap
+ 8 * slotid
);
2093 ictx
= xhci_mask64(pictx
);
2094 octx
= xhci_mask64(poctx
);
2096 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2097 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2099 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2101 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
2102 DPRINTF("xhci: invalid input context control %08x %08x\n",
2103 ictl_ctx
[0], ictl_ctx
[1]);
2104 return CC_TRB_ERROR
;
2107 xhci_dma_read_u32s(xhci
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
2108 xhci_dma_read_u32s(xhci
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
2110 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2111 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2113 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2114 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2116 uport
= xhci_lookup_uport(xhci
, slot_ctx
);
2117 if (uport
== NULL
) {
2118 DPRINTF("xhci: port not found\n");
2119 return CC_TRB_ERROR
;
2121 trace_usb_xhci_slot_address(slotid
, uport
->path
);
2124 if (!dev
|| !dev
->attached
) {
2125 DPRINTF("xhci: port %s not connected\n", uport
->path
);
2126 return CC_USB_TRANSACTION_ERROR
;
2129 for (i
= 0; i
< xhci
->numslots
; i
++) {
2130 if (i
== slotid
-1) {
2133 if (xhci
->slots
[i
].uport
== uport
) {
2134 DPRINTF("xhci: port %s already assigned to slot %d\n",
2136 return CC_TRB_ERROR
;
2140 slot
= &xhci
->slots
[slotid
-1];
2141 slot
->uport
= uport
;
2143 slot
->intr
= get_field(slot_ctx
[2], TRB_INTR
);
2145 /* Make sure device is in USB_STATE_DEFAULT state */
2146 usb_device_reset(dev
);
2148 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2153 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slotid
;
2154 memset(&p
, 0, sizeof(p
));
2155 usb_packet_addbuf(&p
, buf
, sizeof(buf
));
2156 usb_packet_setup(&p
, USB_TOKEN_OUT
,
2157 usb_ep_get(dev
, USB_TOKEN_OUT
, 0), 0,
2159 usb_device_handle_control(dev
, &p
,
2160 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
2161 slotid
, 0, 0, NULL
);
2162 assert(p
.status
!= USB_RET_ASYNC
);
2165 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
2167 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2168 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2169 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2170 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2172 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2173 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2175 xhci
->slots
[slotid
-1].addressed
= 1;
2180 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
2181 uint64_t pictx
, bool dc
)
2183 dma_addr_t ictx
, octx
;
2184 uint32_t ictl_ctx
[2];
2185 uint32_t slot_ctx
[4];
2186 uint32_t islot_ctx
[4];
2191 trace_usb_xhci_slot_configure(slotid
);
2192 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2194 ictx
= xhci_mask64(pictx
);
2195 octx
= xhci
->slots
[slotid
-1].ctx
;
2197 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2198 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2201 for (i
= 2; i
<= 31; i
++) {
2202 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2203 xhci_disable_ep(xhci
, slotid
, i
);
2207 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2208 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2209 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
2210 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2211 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2212 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2217 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2219 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
2220 DPRINTF("xhci: invalid input context control %08x %08x\n",
2221 ictl_ctx
[0], ictl_ctx
[1]);
2222 return CC_TRB_ERROR
;
2225 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2226 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2228 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
2229 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx
[3]);
2230 return CC_CONTEXT_STATE_ERROR
;
2233 xhci_free_device_streams(xhci
, slotid
, ictl_ctx
[0] | ictl_ctx
[1]);
2235 for (i
= 2; i
<= 31; i
++) {
2236 if (ictl_ctx
[0] & (1<<i
)) {
2237 xhci_disable_ep(xhci
, slotid
, i
);
2239 if (ictl_ctx
[1] & (1<<i
)) {
2240 xhci_dma_read_u32s(xhci
, ictx
+32+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2241 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2242 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2243 ep_ctx
[3], ep_ctx
[4]);
2244 xhci_disable_ep(xhci
, slotid
, i
);
2245 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
2246 if (res
!= CC_SUCCESS
) {
2249 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2250 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2251 ep_ctx
[3], ep_ctx
[4]);
2252 xhci_dma_write_u32s(xhci
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2256 res
= xhci_alloc_device_streams(xhci
, slotid
, ictl_ctx
[1]);
2257 if (res
!= CC_SUCCESS
) {
2258 for (i
= 2; i
<= 31; i
++) {
2259 if (ictl_ctx
[1] & (1u << i
)) {
2260 xhci_disable_ep(xhci
, slotid
, i
);
2266 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2267 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
2268 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
2269 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
2270 SLOT_CONTEXT_ENTRIES_SHIFT
);
2271 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2272 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2274 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2280 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
2283 dma_addr_t ictx
, octx
;
2284 uint32_t ictl_ctx
[2];
2285 uint32_t iep0_ctx
[5];
2286 uint32_t ep0_ctx
[5];
2287 uint32_t islot_ctx
[4];
2288 uint32_t slot_ctx
[4];
2290 trace_usb_xhci_slot_evaluate(slotid
);
2291 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2293 ictx
= xhci_mask64(pictx
);
2294 octx
= xhci
->slots
[slotid
-1].ctx
;
2296 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2297 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2299 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2301 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2302 DPRINTF("xhci: invalid input context control %08x %08x\n",
2303 ictl_ctx
[0], ictl_ctx
[1]);
2304 return CC_TRB_ERROR
;
2307 if (ictl_ctx
[1] & 0x1) {
2308 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2310 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2311 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2313 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2315 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2316 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2317 /* update interrupter target field */
2318 xhci
->slots
[slotid
-1].intr
= get_field(islot_ctx
[2], TRB_INTR
);
2319 set_field(&slot_ctx
[2], xhci
->slots
[slotid
-1].intr
, TRB_INTR
);
2321 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2322 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2324 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2327 if (ictl_ctx
[1] & 0x2) {
2328 xhci_dma_read_u32s(xhci
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2330 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2331 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2332 iep0_ctx
[3], iep0_ctx
[4]);
2334 xhci_dma_read_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2336 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2337 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2339 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2340 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2342 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2348 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2350 uint32_t slot_ctx
[4];
2354 trace_usb_xhci_slot_reset(slotid
);
2355 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2357 octx
= xhci
->slots
[slotid
-1].ctx
;
2359 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2361 for (i
= 2; i
<= 31; i
++) {
2362 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2363 xhci_disable_ep(xhci
, slotid
, i
);
2367 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2368 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2369 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2370 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2371 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2372 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2377 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2379 unsigned int slotid
;
2380 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2381 if (slotid
< 1 || slotid
> xhci
->numslots
) {
2382 DPRINTF("xhci: bad slot id %d\n", slotid
);
2383 event
->ccode
= CC_TRB_ERROR
;
2385 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2386 DPRINTF("xhci: slot id %d not enabled\n", slotid
);
2387 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2393 /* cleanup slot state on usb device detach */
2394 static void xhci_detach_slot(XHCIState
*xhci
, USBPort
*uport
)
2398 for (slot
= 0; slot
< xhci
->numslots
; slot
++) {
2399 if (xhci
->slots
[slot
].uport
== uport
) {
2403 if (slot
== xhci
->numslots
) {
2407 for (ep
= 0; ep
< 31; ep
++) {
2408 if (xhci
->slots
[slot
].eps
[ep
]) {
2409 xhci_ep_nuke_xfers(xhci
, slot
+ 1, ep
+ 1, 0);
2412 xhci
->slots
[slot
].uport
= NULL
;
2415 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2418 uint8_t bw_ctx
[xhci
->numports
+1];
2420 DPRINTF("xhci_get_port_bandwidth()\n");
2422 ctx
= xhci_mask64(pctx
);
2424 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2426 /* TODO: actually implement real values here */
2428 memset(&bw_ctx
[1], 80, xhci
->numports
); /* 80% */
2429 pci_dma_write(PCI_DEVICE(xhci
), ctx
, bw_ctx
, sizeof(bw_ctx
));
2434 static uint32_t rotl(uint32_t v
, unsigned count
)
2437 return (v
<< count
) | (v
>> (32 - count
));
2441 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2444 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2445 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2446 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2450 static void xhci_process_commands(XHCIState
*xhci
)
2454 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2456 unsigned int i
, slotid
= 0, count
= 0;
2458 DPRINTF("xhci_process_commands()\n");
2459 if (!xhci_running(xhci
)) {
2460 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2464 xhci
->crcr_low
|= CRCR_CRR
;
2466 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2469 case CR_ENABLE_SLOT
:
2470 for (i
= 0; i
< xhci
->numslots
; i
++) {
2471 if (!xhci
->slots
[i
].enabled
) {
2475 if (i
>= xhci
->numslots
) {
2476 DPRINTF("xhci: no device slots available\n");
2477 event
.ccode
= CC_NO_SLOTS_ERROR
;
2480 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2483 case CR_DISABLE_SLOT
:
2484 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2486 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2489 case CR_ADDRESS_DEVICE
:
2490 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2492 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2493 trb
.control
& TRB_CR_BSR
);
2496 case CR_CONFIGURE_ENDPOINT
:
2497 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2499 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2500 trb
.control
& TRB_CR_DC
);
2503 case CR_EVALUATE_CONTEXT
:
2504 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2506 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2509 case CR_STOP_ENDPOINT
:
2510 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2512 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2514 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2517 case CR_RESET_ENDPOINT
:
2518 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2520 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2522 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2525 case CR_SET_TR_DEQUEUE
:
2526 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2528 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2530 unsigned int streamid
= (trb
.status
>> 16) & 0xffff;
2531 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
,
2536 case CR_RESET_DEVICE
:
2537 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2539 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2542 case CR_GET_PORT_BANDWIDTH
:
2543 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2545 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2546 if (xhci
->nec_quirks
) {
2547 event
.type
= 48; /* NEC reply */
2548 event
.length
= 0x3025;
2550 event
.ccode
= CC_TRB_ERROR
;
2553 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2554 if (xhci
->nec_quirks
) {
2555 uint32_t chi
= trb
.parameter
>> 32;
2556 uint32_t clo
= trb
.parameter
;
2557 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2558 event
.length
= val
& 0xFFFF;
2559 event
.epid
= val
>> 16;
2561 event
.type
= 48; /* NEC reply */
2563 event
.ccode
= CC_TRB_ERROR
;
2567 trace_usb_xhci_unimplemented("command", type
);
2568 event
.ccode
= CC_TRB_ERROR
;
2571 event
.slotid
= slotid
;
2572 xhci_event(xhci
, &event
, 0);
2574 if (count
++ > COMMAND_LIMIT
) {
2575 trace_usb_xhci_enforced_limit("commands");
2581 static bool xhci_port_have_device(XHCIPort
*port
)
2583 if (!port
->uport
->dev
|| !port
->uport
->dev
->attached
) {
2584 return false; /* no device present */
2586 if (!((1 << port
->uport
->dev
->speed
) & port
->speedmask
)) {
2587 return false; /* speed mismatch */
2592 static void xhci_port_notify(XHCIPort
*port
, uint32_t bits
)
2594 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
,
2595 port
->portnr
<< 24 };
2597 if ((port
->portsc
& bits
) == bits
) {
2600 trace_usb_xhci_port_notify(port
->portnr
, bits
);
2601 port
->portsc
|= bits
;
2602 if (!xhci_running(port
->xhci
)) {
2605 xhci_event(port
->xhci
, &ev
, 0);
2608 static void xhci_port_update(XHCIPort
*port
, int is_detach
)
2610 uint32_t pls
= PLS_RX_DETECT
;
2613 port
->portsc
= PORTSC_PP
;
2614 if (!is_detach
&& xhci_port_have_device(port
)) {
2615 port
->portsc
|= PORTSC_CCS
;
2616 switch (port
->uport
->dev
->speed
) {
2618 port
->portsc
|= PORTSC_SPEED_LOW
;
2621 case USB_SPEED_FULL
:
2622 port
->portsc
|= PORTSC_SPEED_FULL
;
2625 case USB_SPEED_HIGH
:
2626 port
->portsc
|= PORTSC_SPEED_HIGH
;
2629 case USB_SPEED_SUPER
:
2630 port
->portsc
|= PORTSC_SPEED_SUPER
;
2631 port
->portsc
|= PORTSC_PED
;
2636 set_field(&port
->portsc
, pls
, PORTSC_PLS
);
2637 trace_usb_xhci_port_link(port
->portnr
, pls
);
2638 xhci_port_notify(port
, PORTSC_CSC
);
2641 static void xhci_port_reset(XHCIPort
*port
, bool warm_reset
)
2643 trace_usb_xhci_port_reset(port
->portnr
, warm_reset
);
2645 if (!xhci_port_have_device(port
)) {
2649 usb_device_reset(port
->uport
->dev
);
2651 switch (port
->uport
->dev
->speed
) {
2652 case USB_SPEED_SUPER
:
2654 port
->portsc
|= PORTSC_WRC
;
2658 case USB_SPEED_FULL
:
2659 case USB_SPEED_HIGH
:
2660 set_field(&port
->portsc
, PLS_U0
, PORTSC_PLS
);
2661 trace_usb_xhci_port_link(port
->portnr
, PLS_U0
);
2662 port
->portsc
|= PORTSC_PED
;
2666 port
->portsc
&= ~PORTSC_PR
;
2667 xhci_port_notify(port
, PORTSC_PRC
);
2670 static void xhci_reset(DeviceState
*dev
)
2672 XHCIState
*xhci
= XHCI(dev
);
2675 trace_usb_xhci_reset();
2676 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2677 DPRINTF("xhci: reset while running!\n");
2681 xhci
->usbsts
= USBSTS_HCH
;
2684 xhci
->crcr_high
= 0;
2685 xhci
->dcbaap_low
= 0;
2686 xhci
->dcbaap_high
= 0;
2689 for (i
= 0; i
< xhci
->numslots
; i
++) {
2690 xhci_disable_slot(xhci
, i
+1);
2693 for (i
= 0; i
< xhci
->numports
; i
++) {
2694 xhci_port_update(xhci
->ports
+ i
, 0);
2697 for (i
= 0; i
< xhci
->numintrs
; i
++) {
2698 xhci
->intr
[i
].iman
= 0;
2699 xhci
->intr
[i
].imod
= 0;
2700 xhci
->intr
[i
].erstsz
= 0;
2701 xhci
->intr
[i
].erstba_low
= 0;
2702 xhci
->intr
[i
].erstba_high
= 0;
2703 xhci
->intr
[i
].erdp_low
= 0;
2704 xhci
->intr
[i
].erdp_high
= 0;
2705 xhci
->intr
[i
].msix_used
= 0;
2707 xhci
->intr
[i
].er_ep_idx
= 0;
2708 xhci
->intr
[i
].er_pcs
= 1;
2709 xhci
->intr
[i
].ev_buffer_put
= 0;
2710 xhci
->intr
[i
].ev_buffer_get
= 0;
2713 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
2714 xhci_mfwrap_update(xhci
);
2717 static uint64_t xhci_cap_read(void *ptr
, hwaddr reg
, unsigned size
)
2719 XHCIState
*xhci
= ptr
;
2723 case 0x00: /* HCIVERSION, CAPLENGTH */
2724 ret
= 0x01000000 | LEN_CAP
;
2726 case 0x04: /* HCSPARAMS 1 */
2727 ret
= ((xhci
->numports_2
+xhci
->numports_3
)<<24)
2728 | (xhci
->numintrs
<<8) | xhci
->numslots
;
2730 case 0x08: /* HCSPARAMS 2 */
2733 case 0x0c: /* HCSPARAMS 3 */
2736 case 0x10: /* HCCPARAMS */
2737 if (sizeof(dma_addr_t
) == 4) {
2738 ret
= 0x00080000 | (xhci
->max_pstreams_mask
<< 12);
2740 ret
= 0x00080001 | (xhci
->max_pstreams_mask
<< 12);
2743 case 0x14: /* DBOFF */
2746 case 0x18: /* RTSOFF */
2750 /* extended capabilities */
2751 case 0x20: /* Supported Protocol:00 */
2752 ret
= 0x02000402; /* USB 2.0 */
2754 case 0x24: /* Supported Protocol:04 */
2755 ret
= 0x20425355; /* "USB " */
2757 case 0x28: /* Supported Protocol:08 */
2758 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2759 ret
= (xhci
->numports_2
<<8) | (xhci
->numports_3
+1);
2761 ret
= (xhci
->numports_2
<<8) | 1;
2764 case 0x2c: /* Supported Protocol:0c */
2765 ret
= 0x00000000; /* reserved */
2767 case 0x30: /* Supported Protocol:00 */
2768 ret
= 0x03000002; /* USB 3.0 */
2770 case 0x34: /* Supported Protocol:04 */
2771 ret
= 0x20425355; /* "USB " */
2773 case 0x38: /* Supported Protocol:08 */
2774 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
2775 ret
= (xhci
->numports_3
<<8) | 1;
2777 ret
= (xhci
->numports_3
<<8) | (xhci
->numports_2
+1);
2780 case 0x3c: /* Supported Protocol:0c */
2781 ret
= 0x00000000; /* reserved */
2784 trace_usb_xhci_unimplemented("cap read", reg
);
2788 trace_usb_xhci_cap_read(reg
, ret
);
2792 static uint64_t xhci_port_read(void *ptr
, hwaddr reg
, unsigned size
)
2794 XHCIPort
*port
= ptr
;
2798 case 0x00: /* PORTSC */
2801 case 0x04: /* PORTPMSC */
2802 case 0x08: /* PORTLI */
2805 case 0x0c: /* reserved */
2807 trace_usb_xhci_unimplemented("port read", reg
);
2811 trace_usb_xhci_port_read(port
->portnr
, reg
, ret
);
2815 static void xhci_port_write(void *ptr
, hwaddr reg
,
2816 uint64_t val
, unsigned size
)
2818 XHCIPort
*port
= ptr
;
2819 uint32_t portsc
, notify
;
2821 trace_usb_xhci_port_write(port
->portnr
, reg
, val
);
2824 case 0x00: /* PORTSC */
2825 /* write-1-to-start bits */
2826 if (val
& PORTSC_WPR
) {
2827 xhci_port_reset(port
, true);
2830 if (val
& PORTSC_PR
) {
2831 xhci_port_reset(port
, false);
2835 portsc
= port
->portsc
;
2837 /* write-1-to-clear bits*/
2838 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2839 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2840 if (val
& PORTSC_LWS
) {
2841 /* overwrite PLS only when LWS=1 */
2842 uint32_t old_pls
= get_field(port
->portsc
, PORTSC_PLS
);
2843 uint32_t new_pls
= get_field(val
, PORTSC_PLS
);
2846 if (old_pls
!= PLS_U0
) {
2847 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2848 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2849 notify
= PORTSC_PLC
;
2853 if (old_pls
< PLS_U3
) {
2854 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2855 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2859 /* windows does this for some reason, don't spam stderr */
2862 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
2863 __func__
, old_pls
, new_pls
);
2867 /* read/write bits */
2868 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2869 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2870 port
->portsc
= portsc
;
2872 xhci_port_notify(port
, notify
);
2875 case 0x04: /* PORTPMSC */
2876 case 0x08: /* PORTLI */
2878 trace_usb_xhci_unimplemented("port write", reg
);
2882 static uint64_t xhci_oper_read(void *ptr
, hwaddr reg
, unsigned size
)
2884 XHCIState
*xhci
= ptr
;
2888 case 0x00: /* USBCMD */
2891 case 0x04: /* USBSTS */
2894 case 0x08: /* PAGESIZE */
2897 case 0x14: /* DNCTRL */
2900 case 0x18: /* CRCR low */
2901 ret
= xhci
->crcr_low
& ~0xe;
2903 case 0x1c: /* CRCR high */
2904 ret
= xhci
->crcr_high
;
2906 case 0x30: /* DCBAAP low */
2907 ret
= xhci
->dcbaap_low
;
2909 case 0x34: /* DCBAAP high */
2910 ret
= xhci
->dcbaap_high
;
2912 case 0x38: /* CONFIG */
2916 trace_usb_xhci_unimplemented("oper read", reg
);
2920 trace_usb_xhci_oper_read(reg
, ret
);
2924 static void xhci_oper_write(void *ptr
, hwaddr reg
,
2925 uint64_t val
, unsigned size
)
2927 XHCIState
*xhci
= ptr
;
2928 DeviceState
*d
= DEVICE(ptr
);
2930 trace_usb_xhci_oper_write(reg
, val
);
2933 case 0x00: /* USBCMD */
2934 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
2936 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
2939 if (val
& USBCMD_CSS
) {
2941 xhci
->usbsts
&= ~USBSTS_SRE
;
2943 if (val
& USBCMD_CRS
) {
2945 xhci
->usbsts
|= USBSTS_SRE
;
2947 xhci
->usbcmd
= val
& 0xc0f;
2948 xhci_mfwrap_update(xhci
);
2949 if (val
& USBCMD_HCRST
) {
2952 xhci_intx_update(xhci
);
2955 case 0x04: /* USBSTS */
2956 /* these bits are write-1-to-clear */
2957 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
2958 xhci_intx_update(xhci
);
2961 case 0x14: /* DNCTRL */
2962 xhci
->dnctrl
= val
& 0xffff;
2964 case 0x18: /* CRCR low */
2965 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
2967 case 0x1c: /* CRCR high */
2968 xhci
->crcr_high
= val
;
2969 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
2970 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
2971 xhci
->crcr_low
&= ~CRCR_CRR
;
2972 xhci_event(xhci
, &event
, 0);
2973 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
2975 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
2976 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
2978 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
2980 case 0x30: /* DCBAAP low */
2981 xhci
->dcbaap_low
= val
& 0xffffffc0;
2983 case 0x34: /* DCBAAP high */
2984 xhci
->dcbaap_high
= val
;
2986 case 0x38: /* CONFIG */
2987 xhci
->config
= val
& 0xff;
2990 trace_usb_xhci_unimplemented("oper write", reg
);
2994 static uint64_t xhci_runtime_read(void *ptr
, hwaddr reg
,
2997 XHCIState
*xhci
= ptr
;
3002 case 0x00: /* MFINDEX */
3003 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
3006 trace_usb_xhci_unimplemented("runtime read", reg
);
3010 int v
= (reg
- 0x20) / 0x20;
3011 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3012 switch (reg
& 0x1f) {
3013 case 0x00: /* IMAN */
3016 case 0x04: /* IMOD */
3019 case 0x08: /* ERSTSZ */
3022 case 0x10: /* ERSTBA low */
3023 ret
= intr
->erstba_low
;
3025 case 0x14: /* ERSTBA high */
3026 ret
= intr
->erstba_high
;
3028 case 0x18: /* ERDP low */
3029 ret
= intr
->erdp_low
;
3031 case 0x1c: /* ERDP high */
3032 ret
= intr
->erdp_high
;
3037 trace_usb_xhci_runtime_read(reg
, ret
);
3041 static void xhci_runtime_write(void *ptr
, hwaddr reg
,
3042 uint64_t val
, unsigned size
)
3044 XHCIState
*xhci
= ptr
;
3045 int v
= (reg
- 0x20) / 0x20;
3046 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3047 trace_usb_xhci_runtime_write(reg
, val
);
3050 trace_usb_xhci_unimplemented("runtime write", reg
);
3054 switch (reg
& 0x1f) {
3055 case 0x00: /* IMAN */
3056 if (val
& IMAN_IP
) {
3057 intr
->iman
&= ~IMAN_IP
;
3059 intr
->iman
&= ~IMAN_IE
;
3060 intr
->iman
|= val
& IMAN_IE
;
3062 xhci_intx_update(xhci
);
3064 xhci_msix_update(xhci
, v
);
3066 case 0x04: /* IMOD */
3069 case 0x08: /* ERSTSZ */
3070 intr
->erstsz
= val
& 0xffff;
3072 case 0x10: /* ERSTBA low */
3073 if (xhci
->nec_quirks
) {
3074 /* NEC driver bug: it doesn't align this to 64 bytes */
3075 intr
->erstba_low
= val
& 0xfffffff0;
3077 intr
->erstba_low
= val
& 0xffffffc0;
3080 case 0x14: /* ERSTBA high */
3081 intr
->erstba_high
= val
;
3082 xhci_er_reset(xhci
, v
);
3084 case 0x18: /* ERDP low */
3085 if (val
& ERDP_EHB
) {
3086 intr
->erdp_low
&= ~ERDP_EHB
;
3088 intr
->erdp_low
= (val
& ~ERDP_EHB
) | (intr
->erdp_low
& ERDP_EHB
);
3089 if (val
& ERDP_EHB
) {
3090 dma_addr_t erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
3091 unsigned int dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
3092 if (erdp
>= intr
->er_start
&&
3093 erdp
< (intr
->er_start
+ TRB_SIZE
* intr
->er_size
) &&
3094 dp_idx
!= intr
->er_ep_idx
) {
3095 xhci_intr_raise(xhci
, v
);
3099 case 0x1c: /* ERDP high */
3100 intr
->erdp_high
= val
;
3103 trace_usb_xhci_unimplemented("oper write", reg
);
3107 static uint64_t xhci_doorbell_read(void *ptr
, hwaddr reg
,
3110 /* doorbells always read as 0 */
3111 trace_usb_xhci_doorbell_read(reg
, 0);
3115 static void xhci_doorbell_write(void *ptr
, hwaddr reg
,
3116 uint64_t val
, unsigned size
)
3118 XHCIState
*xhci
= ptr
;
3119 unsigned int epid
, streamid
;
3121 trace_usb_xhci_doorbell_write(reg
, val
);
3123 if (!xhci_running(xhci
)) {
3124 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3132 xhci_process_commands(xhci
);
3134 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3139 streamid
= (val
>> 16) & 0xffff;
3140 if (reg
> xhci
->numslots
) {
3141 DPRINTF("xhci: bad doorbell %d\n", (int)reg
);
3142 } else if (epid
== 0 || epid
> 31) {
3143 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3144 (int)reg
, (uint32_t)val
);
3146 xhci_kick_ep(xhci
, reg
, epid
, streamid
);
3151 static void xhci_cap_write(void *opaque
, hwaddr addr
, uint64_t val
,
3157 static const MemoryRegionOps xhci_cap_ops
= {
3158 .read
= xhci_cap_read
,
3159 .write
= xhci_cap_write
,
3160 .valid
.min_access_size
= 1,
3161 .valid
.max_access_size
= 4,
3162 .impl
.min_access_size
= 4,
3163 .impl
.max_access_size
= 4,
3164 .endianness
= DEVICE_LITTLE_ENDIAN
,
3167 static const MemoryRegionOps xhci_oper_ops
= {
3168 .read
= xhci_oper_read
,
3169 .write
= xhci_oper_write
,
3170 .valid
.min_access_size
= 4,
3171 .valid
.max_access_size
= 4,
3172 .endianness
= DEVICE_LITTLE_ENDIAN
,
3175 static const MemoryRegionOps xhci_port_ops
= {
3176 .read
= xhci_port_read
,
3177 .write
= xhci_port_write
,
3178 .valid
.min_access_size
= 4,
3179 .valid
.max_access_size
= 4,
3180 .endianness
= DEVICE_LITTLE_ENDIAN
,
3183 static const MemoryRegionOps xhci_runtime_ops
= {
3184 .read
= xhci_runtime_read
,
3185 .write
= xhci_runtime_write
,
3186 .valid
.min_access_size
= 4,
3187 .valid
.max_access_size
= 4,
3188 .endianness
= DEVICE_LITTLE_ENDIAN
,
3191 static const MemoryRegionOps xhci_doorbell_ops
= {
3192 .read
= xhci_doorbell_read
,
3193 .write
= xhci_doorbell_write
,
3194 .valid
.min_access_size
= 4,
3195 .valid
.max_access_size
= 4,
3196 .endianness
= DEVICE_LITTLE_ENDIAN
,
3199 static void xhci_attach(USBPort
*usbport
)
3201 XHCIState
*xhci
= usbport
->opaque
;
3202 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3204 xhci_port_update(port
, 0);
3207 static void xhci_detach(USBPort
*usbport
)
3209 XHCIState
*xhci
= usbport
->opaque
;
3210 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3212 xhci_detach_slot(xhci
, usbport
);
3213 xhci_port_update(port
, 1);
3216 static void xhci_wakeup(USBPort
*usbport
)
3218 XHCIState
*xhci
= usbport
->opaque
;
3219 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3222 if (get_field(port
->portsc
, PORTSC_PLS
) != PLS_U3
) {
3225 set_field(&port
->portsc
, PLS_RESUME
, PORTSC_PLS
);
3226 xhci_port_notify(port
, PORTSC_PLC
);
3229 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
3231 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
3233 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
3234 xhci_ep_nuke_one_xfer(xfer
, 0);
3237 xhci_try_complete_packet(xfer
);
3238 xhci_kick_epctx(xfer
->epctx
, xfer
->streamid
);
3239 if (xfer
->complete
) {
3240 xhci_ep_free_xfer(xfer
);
3244 static void xhci_child_detach(USBPort
*uport
, USBDevice
*child
)
3246 USBBus
*bus
= usb_bus_from_device(child
);
3247 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3249 xhci_detach_slot(xhci
, child
->port
);
3252 static USBPortOps xhci_uport_ops
= {
3253 .attach
= xhci_attach
,
3254 .detach
= xhci_detach
,
3255 .wakeup
= xhci_wakeup
,
3256 .complete
= xhci_complete
,
3257 .child_detach
= xhci_child_detach
,
3260 static int xhci_find_epid(USBEndpoint
*ep
)
3265 if (ep
->pid
== USB_TOKEN_IN
) {
3266 return ep
->nr
* 2 + 1;
3272 static USBEndpoint
*xhci_epid_to_usbep(XHCIEPContext
*epctx
)
3280 uport
= epctx
->xhci
->slots
[epctx
->slotid
- 1].uport
;
3281 if (!uport
|| !uport
->dev
) {
3284 token
= (epctx
->epid
& 1) ? USB_TOKEN_IN
: USB_TOKEN_OUT
;
3285 return usb_ep_get(uport
->dev
, token
, epctx
->epid
>> 1);
3288 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
,
3289 unsigned int stream
)
3291 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3294 DPRINTF("%s\n", __func__
);
3295 slotid
= ep
->dev
->addr
;
3296 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
3297 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
3300 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
), stream
);
3303 static USBBusOps xhci_bus_ops
= {
3304 .wakeup_endpoint
= xhci_wakeup_endpoint
,
3307 static void usb_xhci_init(XHCIState
*xhci
)
3309 DeviceState
*dev
= DEVICE(xhci
);
3311 unsigned int i
, usbports
, speedmask
;
3313 xhci
->usbsts
= USBSTS_HCH
;
3315 if (xhci
->numports_2
> MAXPORTS_2
) {
3316 xhci
->numports_2
= MAXPORTS_2
;
3318 if (xhci
->numports_3
> MAXPORTS_3
) {
3319 xhci
->numports_3
= MAXPORTS_3
;
3321 usbports
= MAX(xhci
->numports_2
, xhci
->numports_3
);
3322 xhci
->numports
= xhci
->numports_2
+ xhci
->numports_3
;
3324 usb_bus_new(&xhci
->bus
, sizeof(xhci
->bus
), &xhci_bus_ops
, dev
);
3326 for (i
= 0; i
< usbports
; i
++) {
3328 if (i
< xhci
->numports_2
) {
3329 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3330 port
= &xhci
->ports
[i
+ xhci
->numports_3
];
3331 port
->portnr
= i
+ 1 + xhci
->numports_3
;
3333 port
= &xhci
->ports
[i
];
3334 port
->portnr
= i
+ 1;
3336 port
->uport
= &xhci
->uports
[i
];
3338 USB_SPEED_MASK_LOW
|
3339 USB_SPEED_MASK_FULL
|
3340 USB_SPEED_MASK_HIGH
;
3341 assert(i
< MAXPORTS
);
3342 snprintf(port
->name
, sizeof(port
->name
), "usb2 port #%d", i
+1);
3343 speedmask
|= port
->speedmask
;
3345 if (i
< xhci
->numports_3
) {
3346 if (xhci_get_flag(xhci
, XHCI_FLAG_SS_FIRST
)) {
3347 port
= &xhci
->ports
[i
];
3348 port
->portnr
= i
+ 1;
3350 port
= &xhci
->ports
[i
+ xhci
->numports_2
];
3351 port
->portnr
= i
+ 1 + xhci
->numports_2
;
3353 port
->uport
= &xhci
->uports
[i
];
3354 port
->speedmask
= USB_SPEED_MASK_SUPER
;
3355 assert(i
< MAXPORTS
);
3356 snprintf(port
->name
, sizeof(port
->name
), "usb3 port #%d", i
+1);
3357 speedmask
|= port
->speedmask
;
3359 usb_register_port(&xhci
->bus
, &xhci
->uports
[i
], xhci
, i
,
3360 &xhci_uport_ops
, speedmask
);
3364 static void usb_xhci_realize(struct PCIDevice
*dev
, Error
**errp
)
3369 XHCIState
*xhci
= XHCI(dev
);
3371 dev
->config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
3372 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
3373 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x10;
3374 dev
->config
[0x60] = 0x30; /* release number */
3376 if (strcmp(object_get_typename(OBJECT(dev
)), TYPE_NEC_XHCI
) == 0) {
3377 xhci
->nec_quirks
= true;
3379 if (xhci
->numintrs
> MAXINTRS
) {
3380 xhci
->numintrs
= MAXINTRS
;
3382 while (xhci
->numintrs
& (xhci
->numintrs
- 1)) { /* ! power of 2 */
3385 if (xhci
->numintrs
< 1) {
3388 if (xhci
->numslots
> MAXSLOTS
) {
3389 xhci
->numslots
= MAXSLOTS
;
3391 if (xhci
->numslots
< 1) {
3394 if (xhci_get_flag(xhci
, XHCI_FLAG_ENABLE_STREAMS
)) {
3395 xhci
->max_pstreams_mask
= 7; /* == 256 primary streams */
3397 xhci
->max_pstreams_mask
= 0;
3400 if (xhci
->msi
!= ON_OFF_AUTO_OFF
) {
3401 ret
= msi_init(dev
, 0x70, xhci
->numintrs
, true, false, &err
);
3402 /* Any error other than -ENOTSUP(board's MSI support is broken)
3403 * is a programming error */
3404 assert(!ret
|| ret
== -ENOTSUP
);
3405 if (ret
&& xhci
->msi
== ON_OFF_AUTO_ON
) {
3406 /* Can't satisfy user's explicit msi=on request, fail */
3407 error_append_hint(&err
, "You have to use msi=auto (default) or "
3408 "msi=off with this machine type.\n");
3409 error_propagate(errp
, err
);
3412 assert(!err
|| xhci
->msi
== ON_OFF_AUTO_AUTO
);
3413 /* With msi=auto, we fall back to MSI off silently */
3417 usb_xhci_init(xhci
);
3418 xhci
->mfwrap_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_mfwrap_timer
, xhci
);
3420 memory_region_init(&xhci
->mem
, OBJECT(xhci
), "xhci", LEN_REGS
);
3421 memory_region_init_io(&xhci
->mem_cap
, OBJECT(xhci
), &xhci_cap_ops
, xhci
,
3422 "capabilities", LEN_CAP
);
3423 memory_region_init_io(&xhci
->mem_oper
, OBJECT(xhci
), &xhci_oper_ops
, xhci
,
3424 "operational", 0x400);
3425 memory_region_init_io(&xhci
->mem_runtime
, OBJECT(xhci
), &xhci_runtime_ops
, xhci
,
3426 "runtime", LEN_RUNTIME
);
3427 memory_region_init_io(&xhci
->mem_doorbell
, OBJECT(xhci
), &xhci_doorbell_ops
, xhci
,
3428 "doorbell", LEN_DOORBELL
);
3430 memory_region_add_subregion(&xhci
->mem
, 0, &xhci
->mem_cap
);
3431 memory_region_add_subregion(&xhci
->mem
, OFF_OPER
, &xhci
->mem_oper
);
3432 memory_region_add_subregion(&xhci
->mem
, OFF_RUNTIME
, &xhci
->mem_runtime
);
3433 memory_region_add_subregion(&xhci
->mem
, OFF_DOORBELL
, &xhci
->mem_doorbell
);
3435 for (i
= 0; i
< xhci
->numports
; i
++) {
3436 XHCIPort
*port
= &xhci
->ports
[i
];
3437 uint32_t offset
= OFF_OPER
+ 0x400 + 0x10 * i
;
3439 memory_region_init_io(&port
->mem
, OBJECT(xhci
), &xhci_port_ops
, port
,
3441 memory_region_add_subregion(&xhci
->mem
, offset
, &port
->mem
);
3444 pci_register_bar(dev
, 0,
3445 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
3448 if (pci_bus_is_express(pci_get_bus(dev
)) ||
3449 xhci_get_flag(xhci
, XHCI_FLAG_FORCE_PCIE_ENDCAP
)) {
3450 ret
= pcie_endpoint_cap_init(dev
, 0xa0);
3454 if (xhci
->msix
!= ON_OFF_AUTO_OFF
) {
3455 /* TODO check for errors, and should fail when msix=on */
3456 msix_init(dev
, xhci
->numintrs
,
3457 &xhci
->mem
, 0, OFF_MSIX_TABLE
,
3458 &xhci
->mem
, 0, OFF_MSIX_PBA
,
3463 static void usb_xhci_exit(PCIDevice
*dev
)
3466 XHCIState
*xhci
= XHCI(dev
);
3468 trace_usb_xhci_exit();
3470 for (i
= 0; i
< xhci
->numslots
; i
++) {
3471 xhci_disable_slot(xhci
, i
+ 1);
3474 if (xhci
->mfwrap_timer
) {
3475 timer_del(xhci
->mfwrap_timer
);
3476 timer_free(xhci
->mfwrap_timer
);
3477 xhci
->mfwrap_timer
= NULL
;
3480 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_cap
);
3481 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_oper
);
3482 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_runtime
);
3483 memory_region_del_subregion(&xhci
->mem
, &xhci
->mem_doorbell
);
3485 for (i
= 0; i
< xhci
->numports
; i
++) {
3486 XHCIPort
*port
= &xhci
->ports
[i
];
3487 memory_region_del_subregion(&xhci
->mem
, &port
->mem
);
3490 /* destroy msix memory region */
3491 if (dev
->msix_table
&& dev
->msix_pba
3492 && dev
->msix_entry_used
) {
3493 msix_uninit(dev
, &xhci
->mem
, &xhci
->mem
);
3496 usb_bus_release(&xhci
->bus
);
3499 static int usb_xhci_post_load(void *opaque
, int version_id
)
3501 XHCIState
*xhci
= opaque
;
3502 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
3504 XHCIEPContext
*epctx
;
3505 dma_addr_t dcbaap
, pctx
;
3506 uint32_t slot_ctx
[4];
3508 int slotid
, epid
, state
, intr
;
3510 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
3512 for (slotid
= 1; slotid
<= xhci
->numslots
; slotid
++) {
3513 slot
= &xhci
->slots
[slotid
-1];
3514 if (!slot
->addressed
) {
3518 xhci_mask64(ldq_le_pci_dma(pci_dev
, dcbaap
+ 8 * slotid
));
3519 xhci_dma_read_u32s(xhci
, slot
->ctx
, slot_ctx
, sizeof(slot_ctx
));
3520 slot
->uport
= xhci_lookup_uport(xhci
, slot_ctx
);
3522 /* should not happen, but may trigger on guest bugs */
3524 slot
->addressed
= 0;
3527 assert(slot
->uport
&& slot
->uport
->dev
);
3529 for (epid
= 1; epid
<= 31; epid
++) {
3530 pctx
= slot
->ctx
+ 32 * epid
;
3531 xhci_dma_read_u32s(xhci
, pctx
, ep_ctx
, sizeof(ep_ctx
));
3532 state
= ep_ctx
[0] & EP_STATE_MASK
;
3533 if (state
== EP_DISABLED
) {
3536 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
3537 slot
->eps
[epid
-1] = epctx
;
3538 xhci_init_epctx(epctx
, pctx
, ep_ctx
);
3539 epctx
->state
= state
;
3540 if (state
== EP_RUNNING
) {
3541 /* kick endpoint after vmload is finished */
3542 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
3547 for (intr
= 0; intr
< xhci
->numintrs
; intr
++) {
3548 if (xhci
->intr
[intr
].msix_used
) {
3549 msix_vector_use(pci_dev
, intr
);
3551 msix_vector_unuse(pci_dev
, intr
);
3558 static const VMStateDescription vmstate_xhci_ring
= {
3559 .name
= "xhci-ring",
3561 .fields
= (VMStateField
[]) {
3562 VMSTATE_UINT64(dequeue
, XHCIRing
),
3563 VMSTATE_BOOL(ccs
, XHCIRing
),
3564 VMSTATE_END_OF_LIST()
3568 static const VMStateDescription vmstate_xhci_port
= {
3569 .name
= "xhci-port",
3571 .fields
= (VMStateField
[]) {
3572 VMSTATE_UINT32(portsc
, XHCIPort
),
3573 VMSTATE_END_OF_LIST()
3577 static const VMStateDescription vmstate_xhci_slot
= {
3578 .name
= "xhci-slot",
3580 .fields
= (VMStateField
[]) {
3581 VMSTATE_BOOL(enabled
, XHCISlot
),
3582 VMSTATE_BOOL(addressed
, XHCISlot
),
3583 VMSTATE_END_OF_LIST()
3587 static const VMStateDescription vmstate_xhci_event
= {
3588 .name
= "xhci-event",
3590 .fields
= (VMStateField
[]) {
3591 VMSTATE_UINT32(type
, XHCIEvent
),
3592 VMSTATE_UINT32(ccode
, XHCIEvent
),
3593 VMSTATE_UINT64(ptr
, XHCIEvent
),
3594 VMSTATE_UINT32(length
, XHCIEvent
),
3595 VMSTATE_UINT32(flags
, XHCIEvent
),
3596 VMSTATE_UINT8(slotid
, XHCIEvent
),
3597 VMSTATE_UINT8(epid
, XHCIEvent
),
3598 VMSTATE_END_OF_LIST()
3602 static bool xhci_er_full(void *opaque
, int version_id
)
3607 static const VMStateDescription vmstate_xhci_intr
= {
3608 .name
= "xhci-intr",
3610 .fields
= (VMStateField
[]) {
3612 VMSTATE_UINT32(iman
, XHCIInterrupter
),
3613 VMSTATE_UINT32(imod
, XHCIInterrupter
),
3614 VMSTATE_UINT32(erstsz
, XHCIInterrupter
),
3615 VMSTATE_UINT32(erstba_low
, XHCIInterrupter
),
3616 VMSTATE_UINT32(erstba_high
, XHCIInterrupter
),
3617 VMSTATE_UINT32(erdp_low
, XHCIInterrupter
),
3618 VMSTATE_UINT32(erdp_high
, XHCIInterrupter
),
3621 VMSTATE_BOOL(msix_used
, XHCIInterrupter
),
3622 VMSTATE_BOOL(er_pcs
, XHCIInterrupter
),
3623 VMSTATE_UINT64(er_start
, XHCIInterrupter
),
3624 VMSTATE_UINT32(er_size
, XHCIInterrupter
),
3625 VMSTATE_UINT32(er_ep_idx
, XHCIInterrupter
),
3627 /* event queue (used if ring is full) */
3628 VMSTATE_BOOL(er_full_unused
, XHCIInterrupter
),
3629 VMSTATE_UINT32_TEST(ev_buffer_put
, XHCIInterrupter
, xhci_er_full
),
3630 VMSTATE_UINT32_TEST(ev_buffer_get
, XHCIInterrupter
, xhci_er_full
),
3631 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer
, XHCIInterrupter
, EV_QUEUE
,
3633 vmstate_xhci_event
, XHCIEvent
),
3635 VMSTATE_END_OF_LIST()
3639 static const VMStateDescription vmstate_xhci
= {
3642 .post_load
= usb_xhci_post_load
,
3643 .fields
= (VMStateField
[]) {
3644 VMSTATE_PCI_DEVICE(parent_obj
, XHCIState
),
3645 VMSTATE_MSIX(parent_obj
, XHCIState
),
3647 VMSTATE_STRUCT_VARRAY_UINT32(ports
, XHCIState
, numports
, 1,
3648 vmstate_xhci_port
, XHCIPort
),
3649 VMSTATE_STRUCT_VARRAY_UINT32(slots
, XHCIState
, numslots
, 1,
3650 vmstate_xhci_slot
, XHCISlot
),
3651 VMSTATE_STRUCT_VARRAY_UINT32(intr
, XHCIState
, numintrs
, 1,
3652 vmstate_xhci_intr
, XHCIInterrupter
),
3654 /* Operational Registers */
3655 VMSTATE_UINT32(usbcmd
, XHCIState
),
3656 VMSTATE_UINT32(usbsts
, XHCIState
),
3657 VMSTATE_UINT32(dnctrl
, XHCIState
),
3658 VMSTATE_UINT32(crcr_low
, XHCIState
),
3659 VMSTATE_UINT32(crcr_high
, XHCIState
),
3660 VMSTATE_UINT32(dcbaap_low
, XHCIState
),
3661 VMSTATE_UINT32(dcbaap_high
, XHCIState
),
3662 VMSTATE_UINT32(config
, XHCIState
),
3664 /* Runtime Registers & state */
3665 VMSTATE_INT64(mfindex_start
, XHCIState
),
3666 VMSTATE_TIMER_PTR(mfwrap_timer
, XHCIState
),
3667 VMSTATE_STRUCT(cmd_ring
, XHCIState
, 1, vmstate_xhci_ring
, XHCIRing
),
3669 VMSTATE_END_OF_LIST()
3673 static Property xhci_properties
[] = {
3674 DEFINE_PROP_BIT("streams", XHCIState
, flags
,
3675 XHCI_FLAG_ENABLE_STREAMS
, true),
3676 DEFINE_PROP_UINT32("p2", XHCIState
, numports_2
, 4),
3677 DEFINE_PROP_UINT32("p3", XHCIState
, numports_3
, 4),
3678 DEFINE_PROP_END_OF_LIST(),
3681 static void xhci_instance_init(Object
*obj
)
3683 /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
3684 * line, therefore, no need to wait to realize like other devices */
3685 PCI_DEVICE(obj
)->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
3688 static void xhci_class_init(ObjectClass
*klass
, void *data
)
3690 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3691 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3693 dc
->vmsd
= &vmstate_xhci
;
3694 dc
->props
= xhci_properties
;
3695 dc
->reset
= xhci_reset
;
3696 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
3697 k
->realize
= usb_xhci_realize
;
3698 k
->exit
= usb_xhci_exit
;
3699 k
->class_id
= PCI_CLASS_SERIAL_USB
;
3702 static const TypeInfo xhci_info
= {
3704 .parent
= TYPE_PCI_DEVICE
,
3705 .instance_size
= sizeof(XHCIState
),
3706 .class_init
= xhci_class_init
,
3707 .instance_init
= xhci_instance_init
,
3709 .interfaces
= (InterfaceInfo
[]) {
3710 { INTERFACE_PCIE_DEVICE
},
3711 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
3716 static void qemu_xhci_class_init(ObjectClass
*klass
, void *data
)
3718 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3720 k
->vendor_id
= PCI_VENDOR_ID_REDHAT
;
3721 k
->device_id
= PCI_DEVICE_ID_REDHAT_XHCI
;
3725 static void qemu_xhci_instance_init(Object
*obj
)
3727 XHCIState
*xhci
= XHCI(obj
);
3729 xhci
->msi
= ON_OFF_AUTO_OFF
;
3730 xhci
->msix
= ON_OFF_AUTO_AUTO
;
3731 xhci
->numintrs
= MAXINTRS
;
3732 xhci
->numslots
= MAXSLOTS
;
3733 xhci_set_flag(xhci
, XHCI_FLAG_SS_FIRST
);
3736 static const TypeInfo qemu_xhci_info
= {
3737 .name
= TYPE_QEMU_XHCI
,
3738 .parent
= TYPE_XHCI
,
3739 .class_init
= qemu_xhci_class_init
,
3740 .instance_init
= qemu_xhci_instance_init
,
3743 static void xhci_register_types(void)
3745 type_register_static(&xhci_info
);
3746 type_register_static(&qemu_xhci_info
);
3749 type_init(xhci_register_types
)