2 * USB UHCI controller emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "qemu/osdep.h"
32 #include "hw/usb/uhci-regs.h"
33 #include "hw/pci/pci.h"
34 #include "qapi/error.h"
35 #include "qemu/timer.h"
37 #include "sysemu/dma.h"
39 #include "qemu/main-loop.h"
40 #include "qemu/module.h"
42 #define FRAME_TIMER_FREQ 1000
44 #define FRAME_MAX_LOOPS 256
46 /* Must be large enough to handle 10 frame delay for initial isoc requests */
49 #define MAX_FRAMES_PER_TICK (QH_VALID / 2)
54 TD_RESULT_STOP_FRAME
= 10,
57 TD_RESULT_ASYNC_START
,
61 typedef struct UHCIState UHCIState
;
62 typedef struct UHCIAsync UHCIAsync
;
63 typedef struct UHCIQueue UHCIQueue
;
64 typedef struct UHCIInfo UHCIInfo
;
65 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass
;
73 void (*realize
)(PCIDevice
*dev
, Error
**errp
);
77 struct UHCIPCIDeviceClass
{
78 PCIDeviceClass parent_class
;
83 * Pending async transaction.
84 * 'packet' must be the first field because completion
85 * handler does "(UHCIAsync *) pkt" cast.
90 uint8_t static_buf
[64]; /* 64 bytes is enough, except for isoc packets */
93 QTAILQ_ENTRY(UHCIAsync
) next
;
103 QTAILQ_ENTRY(UHCIQueue
) next
;
104 QTAILQ_HEAD(, UHCIAsync
) asyncs
;
108 typedef struct UHCIPort
{
116 USBBus bus
; /* Note unused when we're a companion controller */
117 uint16_t cmd
; /* cmd register */
119 uint16_t intr
; /* interrupt enable register */
120 uint16_t frnum
; /* frame number */
121 uint32_t fl_base_addr
; /* frame list base address */
123 uint8_t status2
; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
125 QEMUTimer
*frame_timer
;
127 uint32_t frame_bytes
;
128 uint32_t frame_bandwidth
;
129 bool completions_only
;
130 UHCIPort ports
[NB_PORTS
];
132 /* Interrupts that should be raised at the end of the current frame. */
133 uint32_t pending_int_mask
;
136 QTAILQ_HEAD(, UHCIQueue
) queues
;
137 uint8_t num_ports_vmstate
;
145 typedef struct UHCI_TD
{
147 uint32_t ctrl
; /* see TD_CTRL_xxx */
152 typedef struct UHCI_QH
{
157 static void uhci_async_cancel(UHCIAsync
*async
);
158 static void uhci_queue_fill(UHCIQueue
*q
, UHCI_TD
*td
);
159 static void uhci_resume(void *opaque
);
161 #define TYPE_UHCI "pci-uhci-usb"
162 #define UHCI(obj) OBJECT_CHECK(UHCIState, (obj), TYPE_UHCI)
164 static inline int32_t uhci_queue_token(UHCI_TD
*td
)
166 if ((td
->token
& (0xf << 15)) == 0) {
167 /* ctrl ep, cover ep and dev, not pid! */
168 return td
->token
& 0x7ff00;
170 /* covers ep, dev, pid -> identifies the endpoint */
171 return td
->token
& 0x7ffff;
175 static UHCIQueue
*uhci_queue_new(UHCIState
*s
, uint32_t qh_addr
, UHCI_TD
*td
,
180 queue
= g_new0(UHCIQueue
, 1);
182 queue
->qh_addr
= qh_addr
;
183 queue
->token
= uhci_queue_token(td
);
185 QTAILQ_INIT(&queue
->asyncs
);
186 QTAILQ_INSERT_HEAD(&s
->queues
, queue
, next
);
187 queue
->valid
= QH_VALID
;
188 trace_usb_uhci_queue_add(queue
->token
);
192 static void uhci_queue_free(UHCIQueue
*queue
, const char *reason
)
194 UHCIState
*s
= queue
->uhci
;
197 while (!QTAILQ_EMPTY(&queue
->asyncs
)) {
198 async
= QTAILQ_FIRST(&queue
->asyncs
);
199 uhci_async_cancel(async
);
201 usb_device_ep_stopped(queue
->ep
->dev
, queue
->ep
);
203 trace_usb_uhci_queue_del(queue
->token
, reason
);
204 QTAILQ_REMOVE(&s
->queues
, queue
, next
);
208 static UHCIQueue
*uhci_queue_find(UHCIState
*s
, UHCI_TD
*td
)
210 uint32_t token
= uhci_queue_token(td
);
213 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
214 if (queue
->token
== token
) {
221 static bool uhci_queue_verify(UHCIQueue
*queue
, uint32_t qh_addr
, UHCI_TD
*td
,
222 uint32_t td_addr
, bool queuing
)
224 UHCIAsync
*first
= QTAILQ_FIRST(&queue
->asyncs
);
225 uint32_t queue_token_addr
= (queue
->token
>> 8) & 0x7f;
227 return queue
->qh_addr
== qh_addr
&&
228 queue
->token
== uhci_queue_token(td
) &&
229 queue_token_addr
== queue
->ep
->dev
->addr
&&
230 (queuing
|| !(td
->ctrl
& TD_CTRL_ACTIVE
) || first
== NULL
||
231 first
->td_addr
== td_addr
);
234 static UHCIAsync
*uhci_async_alloc(UHCIQueue
*queue
, uint32_t td_addr
)
236 UHCIAsync
*async
= g_new0(UHCIAsync
, 1);
238 async
->queue
= queue
;
239 async
->td_addr
= td_addr
;
240 usb_packet_init(&async
->packet
);
241 trace_usb_uhci_packet_add(async
->queue
->token
, async
->td_addr
);
246 static void uhci_async_free(UHCIAsync
*async
)
248 trace_usb_uhci_packet_del(async
->queue
->token
, async
->td_addr
);
249 usb_packet_cleanup(&async
->packet
);
250 if (async
->buf
!= async
->static_buf
) {
256 static void uhci_async_link(UHCIAsync
*async
)
258 UHCIQueue
*queue
= async
->queue
;
259 QTAILQ_INSERT_TAIL(&queue
->asyncs
, async
, next
);
260 trace_usb_uhci_packet_link_async(async
->queue
->token
, async
->td_addr
);
263 static void uhci_async_unlink(UHCIAsync
*async
)
265 UHCIQueue
*queue
= async
->queue
;
266 QTAILQ_REMOVE(&queue
->asyncs
, async
, next
);
267 trace_usb_uhci_packet_unlink_async(async
->queue
->token
, async
->td_addr
);
270 static void uhci_async_cancel(UHCIAsync
*async
)
272 uhci_async_unlink(async
);
273 trace_usb_uhci_packet_cancel(async
->queue
->token
, async
->td_addr
,
276 usb_cancel_packet(&async
->packet
);
277 uhci_async_free(async
);
281 * Mark all outstanding async packets as invalid.
282 * This is used for canceling them when TDs are removed by the HCD.
284 static void uhci_async_validate_begin(UHCIState
*s
)
288 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
294 * Cancel async packets that are no longer valid
296 static void uhci_async_validate_end(UHCIState
*s
)
298 UHCIQueue
*queue
, *n
;
300 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
302 uhci_queue_free(queue
, "validate-end");
307 static void uhci_async_cancel_device(UHCIState
*s
, USBDevice
*dev
)
309 UHCIQueue
*queue
, *n
;
311 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
312 if (queue
->ep
->dev
== dev
) {
313 uhci_queue_free(queue
, "cancel-device");
318 static void uhci_async_cancel_all(UHCIState
*s
)
320 UHCIQueue
*queue
, *nq
;
322 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, nq
) {
323 uhci_queue_free(queue
, "cancel-all");
327 static UHCIAsync
*uhci_async_find_td(UHCIState
*s
, uint32_t td_addr
)
332 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
333 QTAILQ_FOREACH(async
, &queue
->asyncs
, next
) {
334 if (async
->td_addr
== td_addr
) {
342 static void uhci_update_irq(UHCIState
*s
)
345 if (((s
->status2
& 1) && (s
->intr
& (1 << 2))) ||
346 ((s
->status2
& 2) && (s
->intr
& (1 << 3))) ||
347 ((s
->status
& UHCI_STS_USBERR
) && (s
->intr
& (1 << 0))) ||
348 ((s
->status
& UHCI_STS_RD
) && (s
->intr
& (1 << 1))) ||
349 (s
->status
& UHCI_STS_HSERR
) ||
350 (s
->status
& UHCI_STS_HCPERR
)) {
355 pci_set_irq(&s
->dev
, level
);
358 static void uhci_reset(DeviceState
*dev
)
360 PCIDevice
*d
= PCI_DEVICE(dev
);
361 UHCIState
*s
= UHCI(d
);
366 trace_usb_uhci_reset();
368 pci_conf
= s
->dev
.config
;
370 pci_conf
[0x6a] = 0x01; /* usb clock */
371 pci_conf
[0x6b] = 0x00;
373 s
->status
= UHCI_STS_HCHALTED
;
379 for(i
= 0; i
< NB_PORTS
; i
++) {
382 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
383 usb_port_reset(&port
->port
);
387 uhci_async_cancel_all(s
);
388 qemu_bh_cancel(s
->bh
);
392 static const VMStateDescription vmstate_uhci_port
= {
395 .minimum_version_id
= 1,
396 .fields
= (VMStateField
[]) {
397 VMSTATE_UINT16(ctrl
, UHCIPort
),
398 VMSTATE_END_OF_LIST()
402 static int uhci_post_load(void *opaque
, int version_id
)
404 UHCIState
*s
= opaque
;
406 if (version_id
< 2) {
407 s
->expire_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
408 (NANOSECONDS_PER_SECOND
/ FRAME_TIMER_FREQ
);
413 static const VMStateDescription vmstate_uhci
= {
416 .minimum_version_id
= 1,
417 .post_load
= uhci_post_load
,
418 .fields
= (VMStateField
[]) {
419 VMSTATE_PCI_DEVICE(dev
, UHCIState
),
420 VMSTATE_UINT8_EQUAL(num_ports_vmstate
, UHCIState
, NULL
),
421 VMSTATE_STRUCT_ARRAY(ports
, UHCIState
, NB_PORTS
, 1,
422 vmstate_uhci_port
, UHCIPort
),
423 VMSTATE_UINT16(cmd
, UHCIState
),
424 VMSTATE_UINT16(status
, UHCIState
),
425 VMSTATE_UINT16(intr
, UHCIState
),
426 VMSTATE_UINT16(frnum
, UHCIState
),
427 VMSTATE_UINT32(fl_base_addr
, UHCIState
),
428 VMSTATE_UINT8(sof_timing
, UHCIState
),
429 VMSTATE_UINT8(status2
, UHCIState
),
430 VMSTATE_TIMER_PTR(frame_timer
, UHCIState
),
431 VMSTATE_INT64_V(expire_time
, UHCIState
, 2),
432 VMSTATE_UINT32_V(pending_int_mask
, UHCIState
, 3),
433 VMSTATE_END_OF_LIST()
437 static void uhci_port_write(void *opaque
, hwaddr addr
,
438 uint64_t val
, unsigned size
)
440 UHCIState
*s
= opaque
;
442 trace_usb_uhci_mmio_writew(addr
, val
);
446 if ((val
& UHCI_CMD_RS
) && !(s
->cmd
& UHCI_CMD_RS
)) {
447 /* start frame processing */
448 trace_usb_uhci_schedule_start();
449 s
->expire_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
450 (NANOSECONDS_PER_SECOND
/ FRAME_TIMER_FREQ
);
451 timer_mod(s
->frame_timer
, s
->expire_time
);
452 s
->status
&= ~UHCI_STS_HCHALTED
;
453 } else if (!(val
& UHCI_CMD_RS
)) {
454 s
->status
|= UHCI_STS_HCHALTED
;
456 if (val
& UHCI_CMD_GRESET
) {
460 /* send reset on the USB bus */
461 for(i
= 0; i
< NB_PORTS
; i
++) {
463 usb_device_reset(port
->port
.dev
);
465 uhci_reset(DEVICE(s
));
468 if (val
& UHCI_CMD_HCRESET
) {
469 uhci_reset(DEVICE(s
));
473 if (val
& UHCI_CMD_EGSM
) {
474 if ((s
->ports
[0].ctrl
& UHCI_PORT_RD
) ||
475 (s
->ports
[1].ctrl
& UHCI_PORT_RD
)) {
482 /* XXX: the chip spec is not coherent, so we add a hidden
483 register to distinguish between IOC and SPD */
484 if (val
& UHCI_STS_USBINT
)
493 if (s
->status
& UHCI_STS_HCHALTED
)
494 s
->frnum
= val
& 0x7ff;
497 s
->fl_base_addr
&= 0xffff0000;
498 s
->fl_base_addr
|= val
& ~0xfff;
501 s
->fl_base_addr
&= 0x0000ffff;
502 s
->fl_base_addr
|= (val
<< 16);
505 s
->sof_timing
= val
& 0xff;
517 dev
= port
->port
.dev
;
518 if (dev
&& dev
->attached
) {
520 if ( (val
& UHCI_PORT_RESET
) &&
521 !(port
->ctrl
& UHCI_PORT_RESET
) ) {
522 usb_device_reset(dev
);
525 port
->ctrl
&= UHCI_PORT_READ_ONLY
;
526 /* enabled may only be set if a device is connected */
527 if (!(port
->ctrl
& UHCI_PORT_CCS
)) {
528 val
&= ~UHCI_PORT_EN
;
530 port
->ctrl
|= (val
& ~UHCI_PORT_READ_ONLY
);
531 /* some bits are reset when a '1' is written to them */
532 port
->ctrl
&= ~(val
& UHCI_PORT_WRITE_CLEAR
);
538 static uint64_t uhci_port_read(void *opaque
, hwaddr addr
, unsigned size
)
540 UHCIState
*s
= opaque
;
557 val
= s
->fl_base_addr
& 0xffff;
560 val
= (s
->fl_base_addr
>> 16) & 0xffff;
578 val
= 0xff7f; /* disabled port */
582 trace_usb_uhci_mmio_readw(addr
, val
);
587 /* signal resume if controller suspended */
588 static void uhci_resume (void *opaque
)
590 UHCIState
*s
= (UHCIState
*)opaque
;
595 if (s
->cmd
& UHCI_CMD_EGSM
) {
596 s
->cmd
|= UHCI_CMD_FGR
;
597 s
->status
|= UHCI_STS_RD
;
602 static void uhci_attach(USBPort
*port1
)
604 UHCIState
*s
= port1
->opaque
;
605 UHCIPort
*port
= &s
->ports
[port1
->index
];
607 /* set connect status */
608 port
->ctrl
|= UHCI_PORT_CCS
| UHCI_PORT_CSC
;
611 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
612 port
->ctrl
|= UHCI_PORT_LSDA
;
614 port
->ctrl
&= ~UHCI_PORT_LSDA
;
620 static void uhci_detach(USBPort
*port1
)
622 UHCIState
*s
= port1
->opaque
;
623 UHCIPort
*port
= &s
->ports
[port1
->index
];
625 uhci_async_cancel_device(s
, port1
->dev
);
627 /* set connect status */
628 if (port
->ctrl
& UHCI_PORT_CCS
) {
629 port
->ctrl
&= ~UHCI_PORT_CCS
;
630 port
->ctrl
|= UHCI_PORT_CSC
;
633 if (port
->ctrl
& UHCI_PORT_EN
) {
634 port
->ctrl
&= ~UHCI_PORT_EN
;
635 port
->ctrl
|= UHCI_PORT_ENC
;
641 static void uhci_child_detach(USBPort
*port1
, USBDevice
*child
)
643 UHCIState
*s
= port1
->opaque
;
645 uhci_async_cancel_device(s
, child
);
648 static void uhci_wakeup(USBPort
*port1
)
650 UHCIState
*s
= port1
->opaque
;
651 UHCIPort
*port
= &s
->ports
[port1
->index
];
653 if (port
->ctrl
& UHCI_PORT_SUSPEND
&& !(port
->ctrl
& UHCI_PORT_RD
)) {
654 port
->ctrl
|= UHCI_PORT_RD
;
659 static USBDevice
*uhci_find_device(UHCIState
*s
, uint8_t addr
)
664 for (i
= 0; i
< NB_PORTS
; i
++) {
665 UHCIPort
*port
= &s
->ports
[i
];
666 if (!(port
->ctrl
& UHCI_PORT_EN
)) {
669 dev
= usb_find_device(&port
->port
, addr
);
677 static void uhci_read_td(UHCIState
*s
, UHCI_TD
*td
, uint32_t link
)
679 pci_dma_read(&s
->dev
, link
& ~0xf, td
, sizeof(*td
));
680 le32_to_cpus(&td
->link
);
681 le32_to_cpus(&td
->ctrl
);
682 le32_to_cpus(&td
->token
);
683 le32_to_cpus(&td
->buffer
);
686 static int uhci_handle_td_error(UHCIState
*s
, UHCI_TD
*td
, uint32_t td_addr
,
687 int status
, uint32_t *int_mask
)
689 uint32_t queue_token
= uhci_queue_token(td
);
694 td
->ctrl
|= TD_CTRL_NAK
;
695 return TD_RESULT_NEXT_QH
;
698 td
->ctrl
|= TD_CTRL_STALL
;
699 trace_usb_uhci_packet_complete_stall(queue_token
, td_addr
);
700 ret
= TD_RESULT_NEXT_QH
;
704 td
->ctrl
|= TD_CTRL_BABBLE
| TD_CTRL_STALL
;
705 /* frame interrupted */
706 trace_usb_uhci_packet_complete_babble(queue_token
, td_addr
);
707 ret
= TD_RESULT_STOP_FRAME
;
710 case USB_RET_IOERROR
:
713 td
->ctrl
|= TD_CTRL_TIMEOUT
;
714 td
->ctrl
&= ~(3 << TD_CTRL_ERROR_SHIFT
);
715 trace_usb_uhci_packet_complete_error(queue_token
, td_addr
);
716 ret
= TD_RESULT_NEXT_QH
;
720 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
721 s
->status
|= UHCI_STS_USBERR
;
722 if (td
->ctrl
& TD_CTRL_IOC
) {
729 static int uhci_complete_td(UHCIState
*s
, UHCI_TD
*td
, UHCIAsync
*async
, uint32_t *int_mask
)
731 int len
= 0, max_len
;
734 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
735 pid
= td
->token
& 0xff;
737 if (td
->ctrl
& TD_CTRL_IOS
)
738 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
740 if (async
->packet
.status
!= USB_RET_SUCCESS
) {
741 return uhci_handle_td_error(s
, td
, async
->td_addr
,
742 async
->packet
.status
, int_mask
);
745 len
= async
->packet
.actual_length
;
746 td
->ctrl
= (td
->ctrl
& ~0x7ff) | ((len
- 1) & 0x7ff);
748 /* The NAK bit may have been set by a previous frame, so clear it
749 here. The docs are somewhat unclear, but win2k relies on this
751 td
->ctrl
&= ~(TD_CTRL_ACTIVE
| TD_CTRL_NAK
);
752 if (td
->ctrl
& TD_CTRL_IOC
)
755 if (pid
== USB_TOKEN_IN
) {
756 pci_dma_write(&s
->dev
, td
->buffer
, async
->buf
, len
);
757 if ((td
->ctrl
& TD_CTRL_SPD
) && len
< max_len
) {
759 /* short packet: do not update QH */
760 trace_usb_uhci_packet_complete_shortxfer(async
->queue
->token
,
762 return TD_RESULT_NEXT_QH
;
767 trace_usb_uhci_packet_complete_success(async
->queue
->token
,
769 return TD_RESULT_COMPLETE
;
772 static int uhci_handle_td(UHCIState
*s
, UHCIQueue
*q
, uint32_t qh_addr
,
773 UHCI_TD
*td
, uint32_t td_addr
, uint32_t *int_mask
)
777 bool queuing
= (q
!= NULL
);
778 uint8_t pid
= td
->token
& 0xff;
781 async
= uhci_async_find_td(s
, td_addr
);
783 if (uhci_queue_verify(async
->queue
, qh_addr
, td
, td_addr
, queuing
)) {
784 assert(q
== NULL
|| q
== async
->queue
);
787 uhci_queue_free(async
->queue
, "guest re-used pending td");
793 q
= uhci_queue_find(s
, td
);
794 if (q
&& !uhci_queue_verify(q
, qh_addr
, td
, td_addr
, queuing
)) {
795 uhci_queue_free(q
, "guest re-used qh");
805 if (!(td
->ctrl
& TD_CTRL_ACTIVE
)) {
807 /* Guest marked a pending td non-active, cancel the queue */
808 uhci_queue_free(async
->queue
, "pending td non-active");
811 * ehci11d spec page 22: "Even if the Active bit in the TD is already
812 * cleared when the TD is fetched ... an IOC interrupt is generated"
814 if (td
->ctrl
& TD_CTRL_IOC
) {
817 return TD_RESULT_NEXT_QH
;
822 case USB_TOKEN_SETUP
:
826 /* invalid pid : frame interrupted */
827 s
->status
|= UHCI_STS_HCPERR
;
828 s
->cmd
&= ~UHCI_CMD_RS
;
830 return TD_RESULT_STOP_FRAME
;
835 /* we are busy filling the queue, we are not prepared
836 to consume completed packages then, just leave them
838 return TD_RESULT_ASYNC_CONT
;
842 UHCIAsync
*last
= QTAILQ_LAST(&async
->queue
->asyncs
);
844 * While we are waiting for the current td to complete, the guest
845 * may have added more tds to the queue. Note we re-read the td
846 * rather then caching it, as we want to see guest made changes!
848 uhci_read_td(s
, &last_td
, last
->td_addr
);
849 uhci_queue_fill(async
->queue
, &last_td
);
851 return TD_RESULT_ASYNC_CONT
;
853 uhci_async_unlink(async
);
857 if (s
->completions_only
) {
858 return TD_RESULT_ASYNC_CONT
;
861 /* Allocate new packet */
866 dev
= uhci_find_device(s
, (td
->token
>> 8) & 0x7f);
868 return uhci_handle_td_error(s
, td
, td_addr
, USB_RET_NODEV
,
871 ep
= usb_ep_get(dev
, pid
, (td
->token
>> 15) & 0xf);
872 q
= uhci_queue_new(s
, qh_addr
, td
, ep
);
874 async
= uhci_async_alloc(q
, td_addr
);
876 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
877 spd
= (pid
== USB_TOKEN_IN
&& (td
->ctrl
& TD_CTRL_SPD
) != 0);
878 usb_packet_setup(&async
->packet
, pid
, q
->ep
, 0, td_addr
, spd
,
879 (td
->ctrl
& TD_CTRL_IOC
) != 0);
880 if (max_len
<= sizeof(async
->static_buf
)) {
881 async
->buf
= async
->static_buf
;
883 async
->buf
= g_malloc(max_len
);
885 usb_packet_addbuf(&async
->packet
, async
->buf
, max_len
);
889 case USB_TOKEN_SETUP
:
890 pci_dma_read(&s
->dev
, td
->buffer
, async
->buf
, max_len
);
891 usb_handle_packet(q
->ep
->dev
, &async
->packet
);
892 if (async
->packet
.status
== USB_RET_SUCCESS
) {
893 async
->packet
.actual_length
= max_len
;
898 usb_handle_packet(q
->ep
->dev
, &async
->packet
);
902 abort(); /* Never to execute */
905 if (async
->packet
.status
== USB_RET_ASYNC
) {
906 uhci_async_link(async
);
908 uhci_queue_fill(q
, td
);
910 return TD_RESULT_ASYNC_START
;
914 ret
= uhci_complete_td(s
, td
, async
, int_mask
);
915 uhci_async_free(async
);
919 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
)
921 UHCIAsync
*async
= container_of(packet
, UHCIAsync
, packet
);
922 UHCIState
*s
= async
->queue
->uhci
;
924 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
925 uhci_async_cancel(async
);
930 /* Force processing of this packet *now*, needed for migration */
931 s
->completions_only
= true;
932 qemu_bh_schedule(s
->bh
);
935 static int is_valid(uint32_t link
)
937 return (link
& 1) == 0;
940 static int is_qh(uint32_t link
)
942 return (link
& 2) != 0;
945 static int depth_first(uint32_t link
)
947 return (link
& 4) != 0;
950 /* QH DB used for detecting QH loops */
951 #define UHCI_MAX_QUEUES 128
953 uint32_t addr
[UHCI_MAX_QUEUES
];
957 static void qhdb_reset(QhDb
*db
)
962 /* Add QH to DB. Returns 1 if already present or DB is full. */
963 static int qhdb_insert(QhDb
*db
, uint32_t addr
)
966 for (i
= 0; i
< db
->count
; i
++)
967 if (db
->addr
[i
] == addr
)
970 if (db
->count
>= UHCI_MAX_QUEUES
)
973 db
->addr
[db
->count
++] = addr
;
977 static void uhci_queue_fill(UHCIQueue
*q
, UHCI_TD
*td
)
979 uint32_t int_mask
= 0;
980 uint32_t plink
= td
->link
;
984 while (is_valid(plink
)) {
985 uhci_read_td(q
->uhci
, &ptd
, plink
);
986 if (!(ptd
.ctrl
& TD_CTRL_ACTIVE
)) {
989 if (uhci_queue_token(&ptd
) != q
->token
) {
992 trace_usb_uhci_td_queue(plink
& ~0xf, ptd
.ctrl
, ptd
.token
);
993 ret
= uhci_handle_td(q
->uhci
, q
, q
->qh_addr
, &ptd
, plink
, &int_mask
);
994 if (ret
== TD_RESULT_ASYNC_CONT
) {
997 assert(ret
== TD_RESULT_ASYNC_START
);
998 assert(int_mask
== 0);
1001 usb_device_flush_ep_queue(q
->ep
->dev
, q
->ep
);
1004 static void uhci_process_frame(UHCIState
*s
)
1006 uint32_t frame_addr
, link
, old_td_ctrl
, val
, int_mask
;
1007 uint32_t curr_qh
, td_count
= 0;
1013 frame_addr
= s
->fl_base_addr
+ ((s
->frnum
& 0x3ff) << 2);
1015 pci_dma_read(&s
->dev
, frame_addr
, &link
, 4);
1016 le32_to_cpus(&link
);
1023 for (cnt
= FRAME_MAX_LOOPS
; is_valid(link
) && cnt
; cnt
--) {
1024 if (!s
->completions_only
&& s
->frame_bytes
>= s
->frame_bandwidth
) {
1025 /* We've reached the usb 1.1 bandwidth, which is
1026 1280 bytes/frame, stop processing */
1027 trace_usb_uhci_frame_stop_bandwidth();
1032 trace_usb_uhci_qh_load(link
& ~0xf);
1034 if (qhdb_insert(&qhdb
, link
)) {
1036 * We're going in circles. Which is not a bug because
1037 * HCD is allowed to do that as part of the BW management.
1039 * Stop processing here if no transaction has been done
1040 * since we've been here last time.
1042 if (td_count
== 0) {
1043 trace_usb_uhci_frame_loop_stop_idle();
1046 trace_usb_uhci_frame_loop_continue();
1049 qhdb_insert(&qhdb
, link
);
1053 pci_dma_read(&s
->dev
, link
& ~0xf, &qh
, sizeof(qh
));
1054 le32_to_cpus(&qh
.link
);
1055 le32_to_cpus(&qh
.el_link
);
1057 if (!is_valid(qh
.el_link
)) {
1058 /* QH w/o elements */
1062 /* QH with elements */
1070 uhci_read_td(s
, &td
, link
);
1071 trace_usb_uhci_td_load(curr_qh
& ~0xf, link
& ~0xf, td
.ctrl
, td
.token
);
1073 old_td_ctrl
= td
.ctrl
;
1074 ret
= uhci_handle_td(s
, NULL
, curr_qh
, &td
, link
, &int_mask
);
1075 if (old_td_ctrl
!= td
.ctrl
) {
1076 /* update the status bits of the TD */
1077 val
= cpu_to_le32(td
.ctrl
);
1078 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
1082 case TD_RESULT_STOP_FRAME
: /* interrupted frame */
1085 case TD_RESULT_NEXT_QH
:
1086 case TD_RESULT_ASYNC_CONT
:
1087 trace_usb_uhci_td_nextqh(curr_qh
& ~0xf, link
& ~0xf);
1088 link
= curr_qh
? qh
.link
: td
.link
;
1091 case TD_RESULT_ASYNC_START
:
1092 trace_usb_uhci_td_async(curr_qh
& ~0xf, link
& ~0xf);
1093 link
= curr_qh
? qh
.link
: td
.link
;
1096 case TD_RESULT_COMPLETE
:
1097 trace_usb_uhci_td_complete(curr_qh
& ~0xf, link
& ~0xf);
1100 s
->frame_bytes
+= (td
.ctrl
& 0x7ff) + 1;
1103 /* update QH element link */
1105 val
= cpu_to_le32(qh
.el_link
);
1106 pci_dma_write(&s
->dev
, (curr_qh
& ~0xf) + 4, &val
, sizeof(val
));
1108 if (!depth_first(link
)) {
1109 /* done with this QH */
1117 assert(!"unknown return code");
1120 /* go to the next entry */
1124 s
->pending_int_mask
|= int_mask
;
1127 static void uhci_bh(void *opaque
)
1129 UHCIState
*s
= opaque
;
1130 uhci_process_frame(s
);
1133 static void uhci_frame_timer(void *opaque
)
1135 UHCIState
*s
= opaque
;
1136 uint64_t t_now
, t_last_run
;
1138 const uint64_t frame_t
= NANOSECONDS_PER_SECOND
/ FRAME_TIMER_FREQ
;
1140 s
->completions_only
= false;
1141 qemu_bh_cancel(s
->bh
);
1143 if (!(s
->cmd
& UHCI_CMD_RS
)) {
1145 trace_usb_uhci_schedule_stop();
1146 timer_del(s
->frame_timer
);
1147 uhci_async_cancel_all(s
);
1148 /* set hchalted bit in status - UHCI11D 2.1.2 */
1149 s
->status
|= UHCI_STS_HCHALTED
;
1153 /* We still store expire_time in our state, for migration */
1154 t_last_run
= s
->expire_time
- frame_t
;
1155 t_now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1157 /* Process up to MAX_FRAMES_PER_TICK frames */
1158 frames
= (t_now
- t_last_run
) / frame_t
;
1159 if (frames
> s
->maxframes
) {
1160 int skipped
= frames
- s
->maxframes
;
1161 s
->expire_time
+= skipped
* frame_t
;
1162 s
->frnum
= (s
->frnum
+ skipped
) & 0x7ff;
1165 if (frames
> MAX_FRAMES_PER_TICK
) {
1166 frames
= MAX_FRAMES_PER_TICK
;
1169 for (i
= 0; i
< frames
; i
++) {
1171 trace_usb_uhci_frame_start(s
->frnum
);
1172 uhci_async_validate_begin(s
);
1173 uhci_process_frame(s
);
1174 uhci_async_validate_end(s
);
1175 /* The spec says frnum is the frame currently being processed, and
1176 * the guest must look at frnum - 1 on interrupt, so inc frnum now */
1177 s
->frnum
= (s
->frnum
+ 1) & 0x7ff;
1178 s
->expire_time
+= frame_t
;
1181 /* Complete the previous frame(s) */
1182 if (s
->pending_int_mask
) {
1183 s
->status2
|= s
->pending_int_mask
;
1184 s
->status
|= UHCI_STS_USBINT
;
1187 s
->pending_int_mask
= 0;
1189 timer_mod(s
->frame_timer
, t_now
+ frame_t
);
1192 static const MemoryRegionOps uhci_ioport_ops
= {
1193 .read
= uhci_port_read
,
1194 .write
= uhci_port_write
,
1195 .valid
.min_access_size
= 1,
1196 .valid
.max_access_size
= 4,
1197 .impl
.min_access_size
= 2,
1198 .impl
.max_access_size
= 2,
1199 .endianness
= DEVICE_LITTLE_ENDIAN
,
1202 static USBPortOps uhci_port_ops
= {
1203 .attach
= uhci_attach
,
1204 .detach
= uhci_detach
,
1205 .child_detach
= uhci_child_detach
,
1206 .wakeup
= uhci_wakeup
,
1207 .complete
= uhci_async_complete
,
1210 static USBBusOps uhci_bus_ops
= {
1213 static void usb_uhci_common_realize(PCIDevice
*dev
, Error
**errp
)
1216 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1217 UHCIPCIDeviceClass
*u
= container_of(pc
, UHCIPCIDeviceClass
, parent_class
);
1218 UHCIState
*s
= UHCI(dev
);
1219 uint8_t *pci_conf
= s
->dev
.config
;
1222 pci_conf
[PCI_CLASS_PROG
] = 0x00;
1223 /* TODO: reset value should be 0. */
1224 pci_conf
[USB_SBRN
] = USB_RELEASE_1
; // release number
1226 pci_config_set_interrupt_pin(pci_conf
, u
->info
.irq_pin
+ 1);
1229 USBPort
*ports
[NB_PORTS
];
1230 for(i
= 0; i
< NB_PORTS
; i
++) {
1231 ports
[i
] = &s
->ports
[i
].port
;
1233 usb_register_companion(s
->masterbus
, ports
, NB_PORTS
,
1234 s
->firstport
, s
, &uhci_port_ops
,
1235 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
,
1238 error_propagate(errp
, err
);
1242 usb_bus_new(&s
->bus
, sizeof(s
->bus
), &uhci_bus_ops
, DEVICE(dev
));
1243 for (i
= 0; i
< NB_PORTS
; i
++) {
1244 usb_register_port(&s
->bus
, &s
->ports
[i
].port
, s
, i
, &uhci_port_ops
,
1245 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1248 s
->bh
= qemu_bh_new(uhci_bh
, s
);
1249 s
->frame_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, uhci_frame_timer
, s
);
1250 s
->num_ports_vmstate
= NB_PORTS
;
1251 QTAILQ_INIT(&s
->queues
);
1253 memory_region_init_io(&s
->io_bar
, OBJECT(s
), &uhci_ioport_ops
, s
,
1256 /* Use region 4 for consistency with real hardware. BSD guests seem
1258 pci_register_bar(&s
->dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1261 static void usb_uhci_vt82c686b_realize(PCIDevice
*dev
, Error
**errp
)
1263 UHCIState
*s
= UHCI(dev
);
1264 uint8_t *pci_conf
= s
->dev
.config
;
1266 /* USB misc control 1/2 */
1267 pci_set_long(pci_conf
+ 0x40,0x00001000);
1269 pci_set_long(pci_conf
+ 0x80,0x00020001);
1270 /* USB legacy support */
1271 pci_set_long(pci_conf
+ 0xc0,0x00002000);
1273 usb_uhci_common_realize(dev
, errp
);
1276 static void usb_uhci_exit(PCIDevice
*dev
)
1278 UHCIState
*s
= UHCI(dev
);
1280 trace_usb_uhci_exit();
1282 if (s
->frame_timer
) {
1283 timer_del(s
->frame_timer
);
1284 timer_free(s
->frame_timer
);
1285 s
->frame_timer
= NULL
;
1289 qemu_bh_delete(s
->bh
);
1292 uhci_async_cancel_all(s
);
1294 if (!s
->masterbus
) {
1295 usb_bus_release(&s
->bus
);
1299 static Property uhci_properties_companion
[] = {
1300 DEFINE_PROP_STRING("masterbus", UHCIState
, masterbus
),
1301 DEFINE_PROP_UINT32("firstport", UHCIState
, firstport
, 0),
1302 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1303 DEFINE_PROP_UINT32("maxframes", UHCIState
, maxframes
, 128),
1304 DEFINE_PROP_END_OF_LIST(),
1306 static Property uhci_properties_standalone
[] = {
1307 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1308 DEFINE_PROP_UINT32("maxframes", UHCIState
, maxframes
, 128),
1309 DEFINE_PROP_END_OF_LIST(),
1312 static void uhci_class_init(ObjectClass
*klass
, void *data
)
1314 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1315 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1317 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1318 dc
->vmsd
= &vmstate_uhci
;
1319 dc
->reset
= uhci_reset
;
1320 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
1323 static const TypeInfo uhci_pci_type_info
= {
1325 .parent
= TYPE_PCI_DEVICE
,
1326 .instance_size
= sizeof(UHCIState
),
1327 .class_size
= sizeof(UHCIPCIDeviceClass
),
1329 .class_init
= uhci_class_init
,
1330 .interfaces
= (InterfaceInfo
[]) {
1331 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
1336 static void uhci_data_class_init(ObjectClass
*klass
, void *data
)
1338 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1339 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1340 UHCIPCIDeviceClass
*u
= container_of(k
, UHCIPCIDeviceClass
, parent_class
);
1341 UHCIInfo
*info
= data
;
1343 k
->realize
= info
->realize
? info
->realize
: usb_uhci_common_realize
;
1344 k
->exit
= info
->unplug
? usb_uhci_exit
: NULL
;
1345 k
->vendor_id
= info
->vendor_id
;
1346 k
->device_id
= info
->device_id
;
1347 k
->revision
= info
->revision
;
1348 if (!info
->unplug
) {
1349 /* uhci controllers in companion setups can't be hotplugged */
1350 dc
->hotpluggable
= false;
1351 dc
->props
= uhci_properties_companion
;
1353 dc
->props
= uhci_properties_standalone
;
1358 static UHCIInfo uhci_info
[] = {
1360 .name
= "piix3-usb-uhci",
1361 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1362 .device_id
= PCI_DEVICE_ID_INTEL_82371SB_2
,
1367 .name
= "piix4-usb-uhci",
1368 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1369 .device_id
= PCI_DEVICE_ID_INTEL_82371AB_2
,
1374 .name
= "vt82c686b-usb-uhci",
1375 .vendor_id
= PCI_VENDOR_ID_VIA
,
1376 .device_id
= PCI_DEVICE_ID_VIA_UHCI
,
1379 .realize
= usb_uhci_vt82c686b_realize
,
1382 .name
= "ich9-usb-uhci1", /* 00:1d.0 */
1383 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1384 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI1
,
1389 .name
= "ich9-usb-uhci2", /* 00:1d.1 */
1390 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1391 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI2
,
1396 .name
= "ich9-usb-uhci3", /* 00:1d.2 */
1397 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1398 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI3
,
1403 .name
= "ich9-usb-uhci4", /* 00:1a.0 */
1404 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1405 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI4
,
1410 .name
= "ich9-usb-uhci5", /* 00:1a.1 */
1411 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1412 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI5
,
1417 .name
= "ich9-usb-uhci6", /* 00:1a.2 */
1418 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1419 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI6
,
1426 static void uhci_register_types(void)
1428 TypeInfo uhci_type_info
= {
1429 .parent
= TYPE_UHCI
,
1430 .class_init
= uhci_data_class_init
,
1434 type_register_static(&uhci_pci_type_info
);
1436 for (i
= 0; i
< ARRAY_SIZE(uhci_info
); i
++) {
1437 uhci_type_info
.name
= uhci_info
[i
].name
;
1438 uhci_type_info
.class_data
= uhci_info
+ i
;
1439 type_register(&uhci_type_info
);
1443 type_init(uhci_register_types
)