2 * QEMU RISC-V Spike Board
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This provides a RISC-V Board with the following devices:
9 * 0) HTIF Console and Poweroff
10 * 1) CLINT (Timer and IPI)
11 * 2) PLIC (Platform Level Interrupt Controller)
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2 or later, as published by the Free Software Foundation.
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * You should have received a copy of the GNU General Public License along with
23 * this program. If not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/osdep.h"
28 #include "qemu/error-report.h"
29 #include "qapi/error.h"
30 #include "hw/boards.h"
31 #include "hw/loader.h"
32 #include "hw/sysbus.h"
33 #include "target/riscv/cpu.h"
34 #include "hw/riscv/riscv_htif.h"
35 #include "hw/riscv/riscv_hart.h"
36 #include "hw/riscv/sifive_clint.h"
37 #include "hw/riscv/spike.h"
38 #include "hw/riscv/boot.h"
39 #include "chardev/char.h"
40 #include "sysemu/arch_init.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/qtest.h"
43 #include "sysemu/sysemu.h"
44 #include "exec/address-spaces.h"
48 static const struct MemmapEntry
{
52 [SPIKE_MROM
] = { 0x1000, 0x11000 },
53 [SPIKE_CLINT
] = { 0x2000000, 0x10000 },
54 [SPIKE_DRAM
] = { 0x80000000, 0x0 },
57 static void create_fdt(SpikeState
*s
, const struct MemmapEntry
*memmap
,
58 uint64_t mem_size
, const char *cmdline
)
65 fdt
= s
->fdt
= create_device_tree(&s
->fdt_size
);
67 error_report("create_device_tree() failed");
71 qemu_fdt_setprop_string(fdt
, "/", "model", "ucbbar,spike-bare,qemu");
72 qemu_fdt_setprop_string(fdt
, "/", "compatible", "ucbbar,spike-bare-dev");
73 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
74 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
76 qemu_fdt_add_subnode(fdt
, "/htif");
77 qemu_fdt_setprop_string(fdt
, "/htif", "compatible", "ucb,htif0");
79 qemu_fdt_add_subnode(fdt
, "/soc");
80 qemu_fdt_setprop(fdt
, "/soc", "ranges", NULL
, 0);
81 qemu_fdt_setprop_string(fdt
, "/soc", "compatible", "simple-bus");
82 qemu_fdt_setprop_cell(fdt
, "/soc", "#size-cells", 0x2);
83 qemu_fdt_setprop_cell(fdt
, "/soc", "#address-cells", 0x2);
85 nodename
= g_strdup_printf("/memory@%lx",
86 (long)memmap
[SPIKE_DRAM
].base
);
87 qemu_fdt_add_subnode(fdt
, nodename
);
88 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
89 memmap
[SPIKE_DRAM
].base
>> 32, memmap
[SPIKE_DRAM
].base
,
90 mem_size
>> 32, mem_size
);
91 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "memory");
94 qemu_fdt_add_subnode(fdt
, "/cpus");
95 qemu_fdt_setprop_cell(fdt
, "/cpus", "timebase-frequency",
96 SIFIVE_CLINT_TIMEBASE_FREQ
);
97 qemu_fdt_setprop_cell(fdt
, "/cpus", "#size-cells", 0x0);
98 qemu_fdt_setprop_cell(fdt
, "/cpus", "#address-cells", 0x1);
100 for (cpu
= s
->soc
.num_harts
- 1; cpu
>= 0; cpu
--) {
101 nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
102 char *intc
= g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
103 char *isa
= riscv_isa_string(&s
->soc
.harts
[cpu
]);
104 qemu_fdt_add_subnode(fdt
, nodename
);
105 qemu_fdt_setprop_string(fdt
, nodename
, "mmu-type", "riscv,sv48");
106 qemu_fdt_setprop_string(fdt
, nodename
, "riscv,isa", isa
);
107 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv");
108 qemu_fdt_setprop_string(fdt
, nodename
, "status", "okay");
109 qemu_fdt_setprop_cell(fdt
, nodename
, "reg", cpu
);
110 qemu_fdt_setprop_string(fdt
, nodename
, "device_type", "cpu");
111 qemu_fdt_add_subnode(fdt
, intc
);
112 qemu_fdt_setprop_cell(fdt
, intc
, "phandle", 1);
113 qemu_fdt_setprop_string(fdt
, intc
, "compatible", "riscv,cpu-intc");
114 qemu_fdt_setprop(fdt
, intc
, "interrupt-controller", NULL
, 0);
115 qemu_fdt_setprop_cell(fdt
, intc
, "#interrupt-cells", 1);
121 cells
= g_new0(uint32_t, s
->soc
.num_harts
* 4);
122 for (cpu
= 0; cpu
< s
->soc
.num_harts
; cpu
++) {
124 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu
);
125 uint32_t intc_phandle
= qemu_fdt_get_phandle(fdt
, nodename
);
126 cells
[cpu
* 4 + 0] = cpu_to_be32(intc_phandle
);
127 cells
[cpu
* 4 + 1] = cpu_to_be32(IRQ_M_SOFT
);
128 cells
[cpu
* 4 + 2] = cpu_to_be32(intc_phandle
);
129 cells
[cpu
* 4 + 3] = cpu_to_be32(IRQ_M_TIMER
);
132 nodename
= g_strdup_printf("/soc/clint@%lx",
133 (long)memmap
[SPIKE_CLINT
].base
);
134 qemu_fdt_add_subnode(fdt
, nodename
);
135 qemu_fdt_setprop_string(fdt
, nodename
, "compatible", "riscv,clint0");
136 qemu_fdt_setprop_cells(fdt
, nodename
, "reg",
137 0x0, memmap
[SPIKE_CLINT
].base
,
138 0x0, memmap
[SPIKE_CLINT
].size
);
139 qemu_fdt_setprop(fdt
, nodename
, "interrupts-extended",
140 cells
, s
->soc
.num_harts
* sizeof(uint32_t) * 4);
145 qemu_fdt_add_subnode(fdt
, "/chosen");
146 qemu_fdt_setprop_string(fdt
, "/chosen", "bootargs", cmdline
);
150 static void spike_board_init(MachineState
*machine
)
152 const struct MemmapEntry
*memmap
= spike_memmap
;
154 SpikeState
*s
= g_new0(SpikeState
, 1);
155 MemoryRegion
*system_memory
= get_system_memory();
156 MemoryRegion
*main_mem
= g_new(MemoryRegion
, 1);
157 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
159 unsigned int smp_cpus
= machine
->smp
.cpus
;
162 object_initialize_child(OBJECT(machine
), "soc", &s
->soc
, sizeof(s
->soc
),
163 TYPE_RISCV_HART_ARRAY
, &error_abort
, NULL
);
164 object_property_set_str(OBJECT(&s
->soc
), machine
->cpu_type
, "cpu-type",
166 object_property_set_int(OBJECT(&s
->soc
), smp_cpus
, "num-harts",
168 object_property_set_bool(OBJECT(&s
->soc
), true, "realized",
171 /* register system main memory (actual RAM) */
172 memory_region_init_ram(main_mem
, NULL
, "riscv.spike.ram",
173 machine
->ram_size
, &error_fatal
);
174 memory_region_add_subregion(system_memory
, memmap
[SPIKE_DRAM
].base
,
177 /* create device tree */
178 create_fdt(s
, memmap
, machine
->ram_size
, machine
->kernel_cmdline
);
181 memory_region_init_rom(mask_rom
, NULL
, "riscv.spike.mrom",
182 memmap
[SPIKE_MROM
].size
, &error_fatal
);
183 memory_region_add_subregion(system_memory
, memmap
[SPIKE_MROM
].base
,
186 if (machine
->kernel_filename
) {
187 riscv_load_kernel(machine
->kernel_filename
, htif_symbol_callback
);
191 uint32_t reset_vec
[8] = {
192 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
193 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
194 0xf1402573, /* csrr a0, mhartid */
195 #if defined(TARGET_RISCV32)
196 0x0182a283, /* lw t0, 24(t0) */
197 #elif defined(TARGET_RISCV64)
198 0x0182b283, /* ld t0, 24(t0) */
200 0x00028067, /* jr t0 */
202 memmap
[SPIKE_DRAM
].base
, /* start: .dword DRAM_BASE */
207 /* copy in the reset vector in little_endian byte order */
208 for (i
= 0; i
< sizeof(reset_vec
) >> 2; i
++) {
209 reset_vec
[i
] = cpu_to_le32(reset_vec
[i
]);
211 rom_add_blob_fixed_as("mrom.reset", reset_vec
, sizeof(reset_vec
),
212 memmap
[SPIKE_MROM
].base
, &address_space_memory
);
214 /* copy in the device tree */
215 if (fdt_pack(s
->fdt
) || fdt_totalsize(s
->fdt
) >
216 memmap
[SPIKE_MROM
].size
- sizeof(reset_vec
)) {
217 error_report("not enough space to store device-tree");
220 qemu_fdt_dumpdtb(s
->fdt
, fdt_totalsize(s
->fdt
));
221 rom_add_blob_fixed_as("mrom.fdt", s
->fdt
, fdt_totalsize(s
->fdt
),
222 memmap
[SPIKE_MROM
].base
+ sizeof(reset_vec
),
223 &address_space_memory
);
225 /* initialize HTIF using symbols found in load_kernel */
226 htif_mm_init(system_memory
, mask_rom
, &s
->soc
.harts
[0].env
, serial_hd(0));
228 /* Core Local Interruptor (timer and IPI) */
229 sifive_clint_create(memmap
[SPIKE_CLINT
].base
, memmap
[SPIKE_CLINT
].size
,
230 smp_cpus
, SIFIVE_SIP_BASE
, SIFIVE_TIMECMP_BASE
, SIFIVE_TIME_BASE
,
234 static void spike_v1_10_0_board_init(MachineState
*machine
)
236 const struct MemmapEntry
*memmap
= spike_memmap
;
238 SpikeState
*s
= g_new0(SpikeState
, 1);
239 MemoryRegion
*system_memory
= get_system_memory();
240 MemoryRegion
*main_mem
= g_new(MemoryRegion
, 1);
241 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
243 unsigned int smp_cpus
= machine
->smp
.cpus
;
245 if (!qtest_enabled()) {
246 info_report("The Spike v1.10.0 machine has been deprecated. "
247 "Please use the generic spike machine and specify the ISA "
248 "versions using -cpu.");
252 object_initialize_child(OBJECT(machine
), "soc", &s
->soc
, sizeof(s
->soc
),
253 TYPE_RISCV_HART_ARRAY
, &error_abort
, NULL
);
254 object_property_set_str(OBJECT(&s
->soc
), SPIKE_V1_10_0_CPU
, "cpu-type",
256 object_property_set_int(OBJECT(&s
->soc
), smp_cpus
, "num-harts",
258 object_property_set_bool(OBJECT(&s
->soc
), true, "realized",
261 /* register system main memory (actual RAM) */
262 memory_region_init_ram(main_mem
, NULL
, "riscv.spike.ram",
263 machine
->ram_size
, &error_fatal
);
264 memory_region_add_subregion(system_memory
, memmap
[SPIKE_DRAM
].base
,
267 /* create device tree */
268 create_fdt(s
, memmap
, machine
->ram_size
, machine
->kernel_cmdline
);
271 memory_region_init_rom(mask_rom
, NULL
, "riscv.spike.mrom",
272 memmap
[SPIKE_MROM
].size
, &error_fatal
);
273 memory_region_add_subregion(system_memory
, memmap
[SPIKE_MROM
].base
,
276 if (machine
->kernel_filename
) {
277 riscv_load_kernel(machine
->kernel_filename
, htif_symbol_callback
);
281 uint32_t reset_vec
[8] = {
282 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
283 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
284 0xf1402573, /* csrr a0, mhartid */
285 #if defined(TARGET_RISCV32)
286 0x0182a283, /* lw t0, 24(t0) */
287 #elif defined(TARGET_RISCV64)
288 0x0182b283, /* ld t0, 24(t0) */
290 0x00028067, /* jr t0 */
292 memmap
[SPIKE_DRAM
].base
, /* start: .dword DRAM_BASE */
297 /* copy in the reset vector in little_endian byte order */
298 for (i
= 0; i
< sizeof(reset_vec
) >> 2; i
++) {
299 reset_vec
[i
] = cpu_to_le32(reset_vec
[i
]);
301 rom_add_blob_fixed_as("mrom.reset", reset_vec
, sizeof(reset_vec
),
302 memmap
[SPIKE_MROM
].base
, &address_space_memory
);
304 /* copy in the device tree */
305 if (fdt_pack(s
->fdt
) || fdt_totalsize(s
->fdt
) >
306 memmap
[SPIKE_MROM
].size
- sizeof(reset_vec
)) {
307 error_report("not enough space to store device-tree");
310 qemu_fdt_dumpdtb(s
->fdt
, fdt_totalsize(s
->fdt
));
311 rom_add_blob_fixed_as("mrom.fdt", s
->fdt
, fdt_totalsize(s
->fdt
),
312 memmap
[SPIKE_MROM
].base
+ sizeof(reset_vec
),
313 &address_space_memory
);
315 /* initialize HTIF using symbols found in load_kernel */
316 htif_mm_init(system_memory
, mask_rom
, &s
->soc
.harts
[0].env
, serial_hd(0));
318 /* Core Local Interruptor (timer and IPI) */
319 sifive_clint_create(memmap
[SPIKE_CLINT
].base
, memmap
[SPIKE_CLINT
].size
,
320 smp_cpus
, SIFIVE_SIP_BASE
, SIFIVE_TIMECMP_BASE
, SIFIVE_TIME_BASE
,
324 static void spike_v1_09_1_board_init(MachineState
*machine
)
326 const struct MemmapEntry
*memmap
= spike_memmap
;
328 SpikeState
*s
= g_new0(SpikeState
, 1);
329 MemoryRegion
*system_memory
= get_system_memory();
330 MemoryRegion
*main_mem
= g_new(MemoryRegion
, 1);
331 MemoryRegion
*mask_rom
= g_new(MemoryRegion
, 1);
333 unsigned int smp_cpus
= machine
->smp
.cpus
;
335 if (!qtest_enabled()) {
336 info_report("The Spike v1.09.1 machine has been deprecated. "
337 "Please use the generic spike machine and specify the ISA "
338 "versions using -cpu.");
342 object_initialize_child(OBJECT(machine
), "soc", &s
->soc
, sizeof(s
->soc
),
343 TYPE_RISCV_HART_ARRAY
, &error_abort
, NULL
);
344 object_property_set_str(OBJECT(&s
->soc
), SPIKE_V1_09_1_CPU
, "cpu-type",
346 object_property_set_int(OBJECT(&s
->soc
), smp_cpus
, "num-harts",
348 object_property_set_bool(OBJECT(&s
->soc
), true, "realized",
351 /* register system main memory (actual RAM) */
352 memory_region_init_ram(main_mem
, NULL
, "riscv.spike.ram",
353 machine
->ram_size
, &error_fatal
);
354 memory_region_add_subregion(system_memory
, memmap
[SPIKE_DRAM
].base
,
358 memory_region_init_rom(mask_rom
, NULL
, "riscv.spike.mrom",
359 memmap
[SPIKE_MROM
].size
, &error_fatal
);
360 memory_region_add_subregion(system_memory
, memmap
[SPIKE_MROM
].base
,
363 if (machine
->kernel_filename
) {
364 riscv_load_kernel(machine
->kernel_filename
, htif_symbol_callback
);
368 uint32_t reset_vec
[8] = {
369 0x297 + memmap
[SPIKE_DRAM
].base
- memmap
[SPIKE_MROM
].base
, /* lui */
370 0x00028067, /* jump to DRAM_BASE */
371 0x00000000, /* reserved */
372 memmap
[SPIKE_MROM
].base
+ sizeof(reset_vec
), /* config string pointer */
373 0, 0, 0, 0 /* trap vector */
376 /* part one of config string - before memory size specified */
377 const char *config_string_tmpl
=
383 " addr 0x%" PRIx64
"x;\n"
387 " addr 0x%" PRIx64
"x;\n"
388 " size 0x%" PRIx64
"x;\n"
395 " timecmp 0x%" PRIx64
"x;\n"
396 " ipi 0x%" PRIx64
"x;\n"
401 /* build config string with supplied memory size */
402 char *isa
= riscv_isa_string(&s
->soc
.harts
[0]);
403 char *config_string
= g_strdup_printf(config_string_tmpl
,
404 (uint64_t)memmap
[SPIKE_CLINT
].base
+ SIFIVE_TIME_BASE
,
405 (uint64_t)memmap
[SPIKE_DRAM
].base
,
406 (uint64_t)ram_size
, isa
,
407 (uint64_t)memmap
[SPIKE_CLINT
].base
+ SIFIVE_TIMECMP_BASE
,
408 (uint64_t)memmap
[SPIKE_CLINT
].base
+ SIFIVE_SIP_BASE
);
410 size_t config_string_len
= strlen(config_string
);
412 /* copy in the reset vector in little_endian byte order */
413 for (i
= 0; i
< sizeof(reset_vec
) >> 2; i
++) {
414 reset_vec
[i
] = cpu_to_le32(reset_vec
[i
]);
416 rom_add_blob_fixed_as("mrom.reset", reset_vec
, sizeof(reset_vec
),
417 memmap
[SPIKE_MROM
].base
, &address_space_memory
);
419 /* copy in the config string */
420 rom_add_blob_fixed_as("mrom.reset", config_string
, config_string_len
,
421 memmap
[SPIKE_MROM
].base
+ sizeof(reset_vec
),
422 &address_space_memory
);
424 /* initialize HTIF using symbols found in load_kernel */
425 htif_mm_init(system_memory
, mask_rom
, &s
->soc
.harts
[0].env
, serial_hd(0));
427 /* Core Local Interruptor (timer and IPI) */
428 sifive_clint_create(memmap
[SPIKE_CLINT
].base
, memmap
[SPIKE_CLINT
].size
,
429 smp_cpus
, SIFIVE_SIP_BASE
, SIFIVE_TIMECMP_BASE
, SIFIVE_TIME_BASE
,
432 g_free(config_string
);
435 static void spike_v1_09_1_machine_init(MachineClass
*mc
)
437 mc
->desc
= "RISC-V Spike Board (Privileged ISA v1.9.1)";
438 mc
->init
= spike_v1_09_1_board_init
;
442 static void spike_v1_10_0_machine_init(MachineClass
*mc
)
444 mc
->desc
= "RISC-V Spike Board (Privileged ISA v1.10)";
445 mc
->init
= spike_v1_10_0_board_init
;
449 static void spike_machine_init(MachineClass
*mc
)
451 mc
->desc
= "RISC-V Spike Board";
452 mc
->init
= spike_board_init
;
454 mc
->is_default
= true;
455 mc
->default_cpu_type
= SPIKE_V1_10_0_CPU
;
458 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init
)
459 DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init
)
460 DEFINE_MACHINE("spike", spike_machine_init
)