2 * bonito north bridge support
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
14 * fulong 2e mini pc has a bonito north bridge.
18 * what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
20 * devfn pci_slot<<3 + funno
21 * one pci bus can have 32 devices and each device can have 8 functions.
23 * In bonito north bridge, pci slot = IDSEL bit - 12.
24 * For example, PCI_IDSEL_VIA686B = 17,
28 * VT686B_FUN0's devfn = (5<<3)+0
29 * VT686B_FUN1's devfn = (5<<3)+1
31 * qemu also uses pci address for north bridge to access pci config register.
37 * so function bonito_sbridge_pciaddr for the translation from
38 * north bridge address to pci address.
41 #include "qemu/osdep.h"
42 #include "qemu/error-report.h"
43 #include "hw/pci/pci.h"
45 #include "hw/mips/mips.h"
46 #include "hw/pci/pci_host.h"
47 #include "migration/vmstate.h"
48 #include "sysemu/reset.h"
49 #include "sysemu/runstate.h"
50 #include "exec/address-spaces.h"
52 /* #define DEBUG_BONITO */
55 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
57 #define DPRINTF(fmt, ...)
60 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
61 #define BONITO_BOOT_BASE 0x1fc00000
62 #define BONITO_BOOT_SIZE 0x00100000
63 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1)
64 #define BONITO_FLASH_BASE 0x1c000000
65 #define BONITO_FLASH_SIZE 0x03000000
66 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1)
67 #define BONITO_SOCKET_BASE 0x1f800000
68 #define BONITO_SOCKET_SIZE 0x00400000
69 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1)
70 #define BONITO_REG_BASE 0x1fe00000
71 #define BONITO_REG_SIZE 0x00040000
72 #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1)
73 #define BONITO_DEV_BASE 0x1ff00000
74 #define BONITO_DEV_SIZE 0x00100000
75 #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1)
76 #define BONITO_PCILO_BASE 0x10000000
77 #define BONITO_PCILO_BASE_VA 0xb0000000
78 #define BONITO_PCILO_SIZE 0x0c000000
79 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1)
80 #define BONITO_PCILO0_BASE 0x10000000
81 #define BONITO_PCILO1_BASE 0x14000000
82 #define BONITO_PCILO2_BASE 0x18000000
83 #define BONITO_PCIHI_BASE 0x20000000
84 #define BONITO_PCIHI_SIZE 0x20000000
85 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1)
86 #define BONITO_PCIIO_BASE 0x1fd00000
87 #define BONITO_PCIIO_BASE_VA 0xbfd00000
88 #define BONITO_PCIIO_SIZE 0x00010000
89 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1)
90 #define BONITO_PCICFG_BASE 0x1fe80000
91 #define BONITO_PCICFG_SIZE 0x00080000
92 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1)
95 #define BONITO_PCICONFIGBASE 0x00
96 #define BONITO_REGBASE 0x100
98 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE)
99 #define BONITO_PCICONFIG_SIZE (0x100)
101 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE)
102 #define BONITO_INTERNAL_REG_SIZE (0x70)
104 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
105 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE)
109 /* 1. Bonito h/w Configuration */
110 /* Power on register */
112 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */
113 #define BONITO_BONGENCFG_OFFSET 0x4
114 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */
116 /* 2. IO & IDE configuration */
117 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */
119 /* 3. IO & IDE configuration */
120 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */
122 /* 4. PCI address map control */
123 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */
124 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */
125 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */
127 /* 5. ICU & GPIO regs */
128 /* GPIO Regs - r/w */
129 #define BONITO_GPIODATA_OFFSET 0x1c
130 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */
131 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */
133 /* ICU Configuration Regs - r/w */
134 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */
135 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */
136 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */
138 /* ICU Enable Regs - IntEn & IntISR are r/o. */
139 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */
140 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */
141 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */
142 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */
145 #define BONITO_PCIMAIL0_OFFSET 0x40
146 #define BONITO_PCIMAIL1_OFFSET 0x44
147 #define BONITO_PCIMAIL2_OFFSET 0x48
148 #define BONITO_PCIMAIL3_OFFSET 0x4c
149 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */
150 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */
151 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */
152 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */
155 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */
156 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */
157 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */
158 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */
161 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */
162 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */
163 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */
164 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */
166 #define BONITO_REGS (0x70 >> 2)
168 /* PCI config for south bridge. type 0 */
169 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */
170 #define BONITO_PCICONF_IDSEL_OFFSET 11
171 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */
172 #define BONITO_PCICONF_FUN_OFFSET 8
173 #define BONITO_PCICONF_REG_MASK 0xFC
174 #define BONITO_PCICONF_REG_OFFSET 0
177 /* idsel BIT = pci slot number +12 */
178 #define PCI_SLOT_BASE 12
179 #define PCI_IDSEL_VIA686B_BIT (17)
180 #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT)
182 #define PCI_ADDR(busno , devno , funno , regno) \
183 ((((busno) << 16) & 0xff0000) + (((devno) << 11) & 0xf800) + \
184 (((funno) << 8) & 0x700) + (regno))
186 typedef struct BonitoState BonitoState
;
188 typedef struct PCIBonitoState
{
191 BonitoState
*pcihost
;
192 uint32_t regs
[BONITO_REGS
];
201 /* Based at 1fe00300, bonito Copier */
209 /* Bonito registers */
211 MemoryRegion iomem_ldma
;
212 MemoryRegion iomem_cop
;
213 MemoryRegion bonito_pciio
;
214 MemoryRegion bonito_localio
;
219 PCIHostState parent_obj
;
221 PCIBonitoState
*pci_dev
;
222 MemoryRegion pci_mem
;
225 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
226 #define BONITO_PCI_HOST_BRIDGE(obj) \
227 OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE)
229 #define TYPE_PCI_BONITO "Bonito"
230 #define PCI_BONITO(obj) \
231 OBJECT_CHECK(PCIBonitoState, (obj), TYPE_PCI_BONITO)
233 static void bonito_writel(void *opaque
, hwaddr addr
,
234 uint64_t val
, unsigned size
)
236 PCIBonitoState
*s
= opaque
;
242 DPRINTF("bonito_writel "TARGET_FMT_plx
" val %x saddr %x\n",
245 case BONITO_BONPONCFG
:
246 case BONITO_IODEVCFG
:
249 case BONITO_PCIMEMBASECFG
:
250 case BONITO_PCIMAP_CFG
:
251 case BONITO_GPIODATA
:
254 case BONITO_INTSTEER
:
256 case BONITO_PCIMAIL0
:
257 case BONITO_PCIMAIL1
:
258 case BONITO_PCIMAIL2
:
259 case BONITO_PCIMAIL3
:
260 case BONITO_PCICACHECTRL
:
261 case BONITO_PCICACHETAG
:
262 case BONITO_PCIBADADDR
:
263 case BONITO_PCIMSTAT
:
268 s
->regs
[saddr
] = val
;
270 case BONITO_BONGENCFG
:
271 if (!(s
->regs
[saddr
] & 0x04) && (val
& 0x04)) {
272 reset
= 1; /* bit 2 jump from 0 to 1 cause reset */
274 s
->regs
[saddr
] = val
;
276 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
279 case BONITO_INTENSET
:
280 s
->regs
[BONITO_INTENSET
] = val
;
281 s
->regs
[BONITO_INTEN
] |= val
;
283 case BONITO_INTENCLR
:
284 s
->regs
[BONITO_INTENCLR
] = val
;
285 s
->regs
[BONITO_INTEN
] &= ~val
;
289 DPRINTF("write to readonly bonito register %x\n", saddr
);
292 DPRINTF("write to unknown bonito register %x\n", saddr
);
297 static uint64_t bonito_readl(void *opaque
, hwaddr addr
,
300 PCIBonitoState
*s
= opaque
;
305 DPRINTF("bonito_readl "TARGET_FMT_plx
"\n", addr
);
308 return s
->regs
[saddr
];
310 return s
->regs
[saddr
];
314 static const MemoryRegionOps bonito_ops
= {
315 .read
= bonito_readl
,
316 .write
= bonito_writel
,
317 .endianness
= DEVICE_NATIVE_ENDIAN
,
319 .min_access_size
= 4,
320 .max_access_size
= 4,
324 static void bonito_pciconf_writel(void *opaque
, hwaddr addr
,
325 uint64_t val
, unsigned size
)
327 PCIBonitoState
*s
= opaque
;
328 PCIDevice
*d
= PCI_DEVICE(s
);
330 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx
" val %x\n", addr
, val
);
331 d
->config_write(d
, addr
, val
, 4);
334 static uint64_t bonito_pciconf_readl(void *opaque
, hwaddr addr
,
338 PCIBonitoState
*s
= opaque
;
339 PCIDevice
*d
= PCI_DEVICE(s
);
341 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx
"\n", addr
);
342 return d
->config_read(d
, addr
, 4);
345 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
347 static const MemoryRegionOps bonito_pciconf_ops
= {
348 .read
= bonito_pciconf_readl
,
349 .write
= bonito_pciconf_writel
,
350 .endianness
= DEVICE_NATIVE_ENDIAN
,
352 .min_access_size
= 4,
353 .max_access_size
= 4,
357 static uint64_t bonito_ldma_readl(void *opaque
, hwaddr addr
,
361 PCIBonitoState
*s
= opaque
;
363 if (addr
>= sizeof(s
->bonldma
)) {
367 val
= ((uint32_t *)(&s
->bonldma
))[addr
/ sizeof(uint32_t)];
372 static void bonito_ldma_writel(void *opaque
, hwaddr addr
,
373 uint64_t val
, unsigned size
)
375 PCIBonitoState
*s
= opaque
;
377 if (addr
>= sizeof(s
->bonldma
)) {
381 ((uint32_t *)(&s
->bonldma
))[addr
/ sizeof(uint32_t)] = val
& 0xffffffff;
384 static const MemoryRegionOps bonito_ldma_ops
= {
385 .read
= bonito_ldma_readl
,
386 .write
= bonito_ldma_writel
,
387 .endianness
= DEVICE_NATIVE_ENDIAN
,
389 .min_access_size
= 4,
390 .max_access_size
= 4,
394 static uint64_t bonito_cop_readl(void *opaque
, hwaddr addr
,
398 PCIBonitoState
*s
= opaque
;
400 if (addr
>= sizeof(s
->boncop
)) {
404 val
= ((uint32_t *)(&s
->boncop
))[addr
/ sizeof(uint32_t)];
409 static void bonito_cop_writel(void *opaque
, hwaddr addr
,
410 uint64_t val
, unsigned size
)
412 PCIBonitoState
*s
= opaque
;
414 if (addr
>= sizeof(s
->boncop
)) {
418 ((uint32_t *)(&s
->boncop
))[addr
/ sizeof(uint32_t)] = val
& 0xffffffff;
421 static const MemoryRegionOps bonito_cop_ops
= {
422 .read
= bonito_cop_readl
,
423 .write
= bonito_cop_writel
,
424 .endianness
= DEVICE_NATIVE_ENDIAN
,
426 .min_access_size
= 4,
427 .max_access_size
= 4,
431 static uint32_t bonito_sbridge_pciaddr(void *opaque
, hwaddr addr
)
433 PCIBonitoState
*s
= opaque
;
434 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
->pcihost
);
442 /* support type0 pci config */
443 if ((s
->regs
[BONITO_PCIMAP_CFG
] & 0x10000) != 0x0) {
447 cfgaddr
= addr
& 0xffff;
448 cfgaddr
|= (s
->regs
[BONITO_PCIMAP_CFG
] & 0xffff) << 16;
450 idsel
= (cfgaddr
& BONITO_PCICONF_IDSEL_MASK
) >>
451 BONITO_PCICONF_IDSEL_OFFSET
;
452 devno
= ctz32(idsel
);
453 funno
= (cfgaddr
& BONITO_PCICONF_FUN_MASK
) >> BONITO_PCICONF_FUN_OFFSET
;
454 regno
= (cfgaddr
& BONITO_PCICONF_REG_MASK
) >> BONITO_PCICONF_REG_OFFSET
;
457 error_report("error in bonito pci config address " TARGET_FMT_plx
458 ",pcimap_cfg=%x", addr
, s
->regs
[BONITO_PCIMAP_CFG
]);
461 pciaddr
= PCI_ADDR(pci_bus_num(phb
->bus
), devno
, funno
, regno
);
462 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
463 cfgaddr
, pciaddr
, pci_bus_num(phb
->bus
), devno
, funno
, regno
);
468 static void bonito_spciconf_write(void *opaque
, hwaddr addr
, uint64_t val
,
471 PCIBonitoState
*s
= opaque
;
472 PCIDevice
*d
= PCI_DEVICE(s
);
473 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
->pcihost
);
477 DPRINTF("bonito_spciconf_write "TARGET_FMT_plx
" size %d val %x\n",
480 pciaddr
= bonito_sbridge_pciaddr(s
, addr
);
482 if (pciaddr
== 0xffffffff) {
486 /* set the pci address in s->config_reg */
487 phb
->config_reg
= (pciaddr
) | (1u << 31);
488 pci_data_write(phb
->bus
, phb
->config_reg
, val
, size
);
490 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
491 status
= pci_get_word(d
->config
+ PCI_STATUS
);
492 status
&= ~(PCI_STATUS_REC_MASTER_ABORT
| PCI_STATUS_REC_TARGET_ABORT
);
493 pci_set_word(d
->config
+ PCI_STATUS
, status
);
496 static uint64_t bonito_spciconf_read(void *opaque
, hwaddr addr
, unsigned size
)
498 PCIBonitoState
*s
= opaque
;
499 PCIDevice
*d
= PCI_DEVICE(s
);
500 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
->pcihost
);
504 DPRINTF("bonito_spciconf_read "TARGET_FMT_plx
" size %d\n", addr
, size
);
506 pciaddr
= bonito_sbridge_pciaddr(s
, addr
);
508 if (pciaddr
== 0xffffffff) {
509 return MAKE_64BIT_MASK(0, size
* 8);
512 /* set the pci address in s->config_reg */
513 phb
->config_reg
= (pciaddr
) | (1u << 31);
515 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
516 status
= pci_get_word(d
->config
+ PCI_STATUS
);
517 status
&= ~(PCI_STATUS_REC_MASTER_ABORT
| PCI_STATUS_REC_TARGET_ABORT
);
518 pci_set_word(d
->config
+ PCI_STATUS
, status
);
520 return pci_data_read(phb
->bus
, phb
->config_reg
, size
);
523 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
524 static const MemoryRegionOps bonito_spciconf_ops
= {
525 .read
= bonito_spciconf_read
,
526 .write
= bonito_spciconf_write
,
527 .valid
.min_access_size
= 1,
528 .valid
.max_access_size
= 4,
529 .impl
.min_access_size
= 1,
530 .impl
.max_access_size
= 4,
531 .endianness
= DEVICE_NATIVE_ENDIAN
,
534 #define BONITO_IRQ_BASE 32
536 static void pci_bonito_set_irq(void *opaque
, int irq_num
, int level
)
538 BonitoState
*s
= opaque
;
539 qemu_irq
*pic
= s
->pic
;
540 PCIBonitoState
*bonito_state
= s
->pci_dev
;
541 int internal_irq
= irq_num
- BONITO_IRQ_BASE
;
543 if (bonito_state
->regs
[BONITO_INTEDGE
] & (1 << internal_irq
)) {
544 qemu_irq_pulse(*pic
);
545 } else { /* level triggered */
546 if (bonito_state
->regs
[BONITO_INTPOL
] & (1 << internal_irq
)) {
547 qemu_irq_raise(*pic
);
549 qemu_irq_lower(*pic
);
554 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
555 static int pci_bonito_map_irq(PCIDevice
*pci_dev
, int irq_num
)
559 slot
= (pci_dev
->devfn
>> 3);
562 case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
563 return irq_num
% 4 + BONITO_IRQ_BASE
;
564 case 6: /* FULONG2E_ATI_SLOT, VGA */
565 return 4 + BONITO_IRQ_BASE
;
566 case 7: /* FULONG2E_RTL_SLOT, RTL8139 */
567 return 5 + BONITO_IRQ_BASE
;
568 case 8 ... 12: /* PCI slot 1 to 4 */
569 return (slot
- 8 + irq_num
) + 6 + BONITO_IRQ_BASE
;
570 default: /* Unknown device, don't do any translation */
575 static void bonito_reset(void *opaque
)
577 PCIBonitoState
*s
= opaque
;
579 /* set the default value of north bridge registers */
581 s
->regs
[BONITO_BONPONCFG
] = 0xc40;
582 s
->regs
[BONITO_BONGENCFG
] = 0x1384;
583 s
->regs
[BONITO_IODEVCFG
] = 0x2bff8010;
584 s
->regs
[BONITO_SDCFG
] = 0x255e0091;
586 s
->regs
[BONITO_GPIODATA
] = 0x1ff;
587 s
->regs
[BONITO_GPIOIE
] = 0x1ff;
588 s
->regs
[BONITO_DQCFG
] = 0x8;
589 s
->regs
[BONITO_MEMSIZE
] = 0x10000000;
590 s
->regs
[BONITO_PCIMAP
] = 0x6140;
593 static const VMStateDescription vmstate_bonito
= {
596 .minimum_version_id
= 1,
597 .fields
= (VMStateField
[]) {
598 VMSTATE_PCI_DEVICE(dev
, PCIBonitoState
),
599 VMSTATE_END_OF_LIST()
603 static void bonito_pcihost_realize(DeviceState
*dev
, Error
**errp
)
605 PCIHostState
*phb
= PCI_HOST_BRIDGE(dev
);
606 BonitoState
*bs
= BONITO_PCI_HOST_BRIDGE(dev
);
608 memory_region_init(&bs
->pci_mem
, OBJECT(dev
), "pci.mem", BONITO_PCILO_SIZE
);
609 phb
->bus
= pci_register_root_bus(DEVICE(dev
), "pci",
610 pci_bonito_set_irq
, pci_bonito_map_irq
,
611 dev
, &bs
->pci_mem
, get_system_io(),
612 0x28, 32, TYPE_PCI_BUS
);
613 memory_region_add_subregion(get_system_memory(), BONITO_PCILO_BASE
,
617 static void bonito_realize(PCIDevice
*dev
, Error
**errp
)
619 PCIBonitoState
*s
= PCI_BONITO(dev
);
620 SysBusDevice
*sysbus
= SYS_BUS_DEVICE(s
->pcihost
);
621 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
->pcihost
);
624 * Bonito North Bridge, built on FPGA,
625 * VENDOR_ID/DEVICE_ID are "undefined"
627 pci_config_set_prog_interface(dev
->config
, 0x00);
629 /* set the north bridge register mapping */
630 memory_region_init_io(&s
->iomem
, OBJECT(s
), &bonito_ops
, s
,
631 "north-bridge-register", BONITO_INTERNAL_REG_SIZE
);
632 sysbus_init_mmio(sysbus
, &s
->iomem
);
633 sysbus_mmio_map(sysbus
, 0, BONITO_INTERNAL_REG_BASE
);
635 /* set the north bridge pci configure mapping */
636 memory_region_init_io(&phb
->conf_mem
, OBJECT(s
), &bonito_pciconf_ops
, s
,
637 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE
);
638 sysbus_init_mmio(sysbus
, &phb
->conf_mem
);
639 sysbus_mmio_map(sysbus
, 1, BONITO_PCICONFIG_BASE
);
641 /* set the south bridge pci configure mapping */
642 memory_region_init_io(&phb
->data_mem
, OBJECT(s
), &bonito_spciconf_ops
, s
,
643 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE
);
644 sysbus_init_mmio(sysbus
, &phb
->data_mem
);
645 sysbus_mmio_map(sysbus
, 2, BONITO_SPCICONFIG_BASE
);
647 memory_region_init_io(&s
->iomem_ldma
, OBJECT(s
), &bonito_ldma_ops
, s
,
649 sysbus_init_mmio(sysbus
, &s
->iomem_ldma
);
650 sysbus_mmio_map(sysbus
, 3, 0xbfe00200);
652 memory_region_init_io(&s
->iomem_cop
, OBJECT(s
), &bonito_cop_ops
, s
,
654 sysbus_init_mmio(sysbus
, &s
->iomem_cop
);
655 sysbus_mmio_map(sysbus
, 4, 0xbfe00300);
657 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
658 memory_region_init_alias(&s
->bonito_pciio
, OBJECT(s
), "isa_mmio",
659 get_system_io(), 0, BONITO_PCIIO_SIZE
);
660 sysbus_init_mmio(sysbus
, &s
->bonito_pciio
);
661 sysbus_mmio_map(sysbus
, 5, BONITO_PCIIO_BASE
);
663 /* add pci local io mapping */
664 memory_region_init_alias(&s
->bonito_localio
, OBJECT(s
), "isa_mmio",
665 get_system_io(), 0, BONITO_DEV_SIZE
);
666 sysbus_init_mmio(sysbus
, &s
->bonito_localio
);
667 sysbus_mmio_map(sysbus
, 6, BONITO_DEV_BASE
);
669 /* set the default value of north bridge pci config */
670 pci_set_word(dev
->config
+ PCI_COMMAND
, 0x0000);
671 pci_set_word(dev
->config
+ PCI_STATUS
, 0x0000);
672 pci_set_word(dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
, 0x0000);
673 pci_set_word(dev
->config
+ PCI_SUBSYSTEM_ID
, 0x0000);
675 pci_set_byte(dev
->config
+ PCI_INTERRUPT_LINE
, 0x00);
676 pci_set_byte(dev
->config
+ PCI_INTERRUPT_PIN
, 0x01);
677 pci_set_byte(dev
->config
+ PCI_MIN_GNT
, 0x3c);
678 pci_set_byte(dev
->config
+ PCI_MAX_LAT
, 0x00);
680 qemu_register_reset(bonito_reset
, s
);
683 PCIBus
*bonito_init(qemu_irq
*pic
)
686 BonitoState
*pcihost
;
691 dev
= qdev_create(NULL
, TYPE_BONITO_PCI_HOST_BRIDGE
);
692 phb
= PCI_HOST_BRIDGE(dev
);
693 pcihost
= BONITO_PCI_HOST_BRIDGE(dev
);
695 qdev_init_nofail(dev
);
697 d
= pci_create(phb
->bus
, PCI_DEVFN(0, 0), TYPE_PCI_BONITO
);
699 s
->pcihost
= pcihost
;
700 pcihost
->pci_dev
= s
;
701 qdev_init_nofail(DEVICE(d
));
706 static void bonito_class_init(ObjectClass
*klass
, void *data
)
708 DeviceClass
*dc
= DEVICE_CLASS(klass
);
709 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
711 k
->realize
= bonito_realize
;
712 k
->vendor_id
= 0xdf53;
713 k
->device_id
= 0x00d5;
715 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
716 dc
->desc
= "Host bridge";
717 dc
->vmsd
= &vmstate_bonito
;
719 * PCI-facing part of the host bridge, not usable without the
720 * host-facing part, which can't be device_add'ed, yet.
722 dc
->user_creatable
= false;
725 static const TypeInfo bonito_info
= {
726 .name
= TYPE_PCI_BONITO
,
727 .parent
= TYPE_PCI_DEVICE
,
728 .instance_size
= sizeof(PCIBonitoState
),
729 .class_init
= bonito_class_init
,
730 .interfaces
= (InterfaceInfo
[]) {
731 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
736 static void bonito_pcihost_class_init(ObjectClass
*klass
, void *data
)
738 DeviceClass
*dc
= DEVICE_CLASS(klass
);
740 dc
->realize
= bonito_pcihost_realize
;
743 static const TypeInfo bonito_pcihost_info
= {
744 .name
= TYPE_BONITO_PCI_HOST_BRIDGE
,
745 .parent
= TYPE_PCI_HOST_BRIDGE
,
746 .instance_size
= sizeof(BonitoState
),
747 .class_init
= bonito_pcihost_class_init
,
750 static void bonito_register_types(void)
752 type_register_static(&bonito_pcihost_info
);
753 type_register_static(&bonito_info
);
756 type_init(bonito_register_types
)