include/hw/arm/xlnx-zynqmp.h

   1 /*
   2  * Xilinx Zynq MPSoC emulation
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #ifndef XLNX_ZYNQMP_H
  19 #define XLNX_ZYNQMP_H
  20
  21 #include "hw/arm/boot.h"
  22 #include "hw/intc/arm_gic.h"
  23 #include "hw/net/cadence_gem.h"
  24 #include "hw/char/cadence_uart.h"
  25 #include "hw/net/xlnx-zynqmp-can.h"
  26 #include "hw/ide/ahci.h"
  27 #include "hw/sd/sdhci.h"
  28 #include "hw/ssi/xilinx_spips.h"
  29 #include "hw/dma/xlnx_dpdma.h"
  30 #include "hw/dma/xlnx-zdma.h"
  31 #include "hw/display/xlnx_dp.h"
  32 #include "hw/intc/xlnx-zynqmp-ipi.h"
  33 #include "hw/rtc/xlnx-zynqmp-rtc.h"
  34 #include "hw/cpu/cluster.h"
  35 #include "target/arm/cpu.h"
  36 #include "qom/object.h"
  37 #include "net/can_emu.h"
  38
  39 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
  40 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
  41
  42 #define XLNX_ZYNQMP_NUM_APU_CPUS 4
  43 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
  44 #define XLNX_ZYNQMP_NUM_GEMS 4
  45 #define XLNX_ZYNQMP_NUM_UARTS 2
  46 #define XLNX_ZYNQMP_NUM_CAN 2
  47 #define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
  48 #define XLNX_ZYNQMP_NUM_SDHCI 2
  49 #define XLNX_ZYNQMP_NUM_SPIS 2
  50 #define XLNX_ZYNQMP_NUM_GDMA_CH 8
  51 #define XLNX_ZYNQMP_NUM_ADMA_CH 8
  52
  53 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
  54 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
  55 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
  56
  57 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
  58 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
  59 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
  60
  61 #define XLNX_ZYNQMP_GIC_REGIONS 6
  62
  63 /*
  64  * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
  65  * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
  66  * aligned address in the 64k region. To implement each GIC region needs a
  67  * number of memory region aliases.
  68  */
  69
  70 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
  71 #define XLNX_ZYNQMP_GIC_ALIASES     (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE)
  72
  73 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE    0x80000000ull
  74
  75 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE   0x800000000ull
  76 #define XLNX_ZYNQMP_HIGH_RAM_START      0x800000000ull
  77
  78 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
  79                                   XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
  80
  81 struct XlnxZynqMPState {
  82     /*< private >*/
  83     DeviceState parent_obj;
  84
  85     /*< public >*/
  86     CPUClusterState apu_cluster;
  87     CPUClusterState rpu_cluster;
  88     ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
  89     ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
  90     GICState gic;
  91     MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
  92
  93     MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
  94
  95     MemoryRegion *ddr_ram;
  96     MemoryRegion ddr_ram_low, ddr_ram_high;
  97
  98     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
  99     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
 100     XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
 101     SysbusAHCIState sata;
 102     SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
 103     XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
 104     XlnxZynqMPQSPIPS qspi;
 105     XlnxDPState dp;
 106     XlnxDPDMAState dpdma;
 107     XlnxZynqMPIPI ipi;
 108     XlnxZynqMPRTC rtc;
 109     XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
 110     XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
 111
 112     char *boot_cpu;
 113     ARMCPU *boot_cpu_ptr;
 114
 115     /* Has the ARM Security extensions?  */
 116     bool secure;
 117     /* Has the ARM Virtualization extensions?  */
 118     bool virt;
 119
 120     /* CAN bus. */
 121     CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
 122 };
 123
 124 #endif