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i386: drop x86_cpu_get_supported_feature_word() forward declaration
[qemu/ar7.git] / target / i386 / cpu.c
bloba33af2359c829cc8f5cfdec91ad07a61511b9fb0
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
25
26 #include "cpu.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/hvf.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/xen.h"
33 #include "kvm_i386.h"
34 #include "sev_i386.h"
35
36 #include "qemu/error-report.h"
37 #include "qemu/module.h"
38 #include "qemu/option.h"
39 #include "qemu/config-file.h"
40 #include "qapi/error.h"
41 #include "qapi/qapi-visit-machine.h"
42 #include "qapi/qapi-visit-run-state.h"
43 #include "qapi/qmp/qdict.h"
44 #include "qapi/qmp/qerror.h"
45 #include "qapi/visitor.h"
46 #include "qom/qom-qobject.h"
47 #include "sysemu/arch_init.h"
48 #include "qapi/qapi-commands-machine-target.h"
49
50 #include "standard-headers/asm-x86/kvm_para.h"
51
52 #include "sysemu/sysemu.h"
53 #include "sysemu/tcg.h"
54 #include "hw/qdev-properties.h"
55 #include "hw/i386/topology.h"
56 #ifndef CONFIG_USER_ONLY
57 #include "exec/address-spaces.h"
58 #include "hw/i386/apic_internal.h"
59 #include "hw/boards.h"
60 #endif
61
62 #include "disas/capstone.h"
63
64 /* Helpers for building CPUID[2] descriptors: */
65
66 struct CPUID2CacheDescriptorInfo {
67 enum CacheType type;
68 int level;
69 int size;
70 int line_size;
71 int associativity;
72 };
73
74 /*
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
77 */
78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
80 .associativity = 4, .line_size = 32, },
81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
82 .associativity = 4, .line_size = 32, },
83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
84 .associativity = 4, .line_size = 64, },
85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
86 .associativity = 2, .line_size = 32, },
87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
88 .associativity = 4, .line_size = 32, },
89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
90 .associativity = 4, .line_size = 64, },
91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
92 .associativity = 6, .line_size = 64, },
93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
94 .associativity = 2, .line_size = 64, },
95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
96 .associativity = 8, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
99 */
100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
101 .associativity = 16, .line_size = 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
104 */
105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
106 .associativity = 8, .line_size = 64, },
107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
108 .associativity = 8, .line_size = 64, },
109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
112 .associativity = 4, .line_size = 32, },
113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
114 .associativity = 4, .line_size = 32, },
115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
116 .associativity = 4, .line_size = 32, },
117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
118 .associativity = 4, .line_size = 32, },
119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
120 .associativity = 4, .line_size = 64, },
121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
122 .associativity = 8, .line_size = 64, },
123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
124 .associativity = 12, .line_size = 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
127 .associativity = 12, .line_size = 64, },
128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
129 .associativity = 16, .line_size = 64, },
130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
131 .associativity = 12, .line_size = 64, },
132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
133 .associativity = 16, .line_size = 64, },
134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
135 .associativity = 24, .line_size = 64, },
136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
137 .associativity = 8, .line_size = 64, },
138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
141 .associativity = 4, .line_size = 64, },
142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
143 .associativity = 4, .line_size = 64, },
144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
145 .associativity = 4, .line_size = 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
148 */
149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
150 .associativity = 8, .line_size = 64, },
151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
152 .associativity = 2, .line_size = 64, },
153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 .associativity = 8, .line_size = 64, },
155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
156 .associativity = 8, .line_size = 32, },
157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
158 .associativity = 8, .line_size = 32, },
159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
160 .associativity = 8, .line_size = 32, },
161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
162 .associativity = 8, .line_size = 32, },
163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
164 .associativity = 4, .line_size = 64, },
165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
166 .associativity = 8, .line_size = 64, },
167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
170 .associativity = 4, .line_size = 64, },
171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
172 .associativity = 4, .line_size = 64, },
173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
176 .associativity = 8, .line_size = 64, },
177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
178 .associativity = 8, .line_size = 64, },
179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
182 .associativity = 12, .line_size = 64, },
183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
184 .associativity = 12, .line_size = 64, },
185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
188 .associativity = 16, .line_size = 64, },
189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
190 .associativity = 16, .line_size = 64, },
191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
192 .associativity = 24, .line_size = 64, },
193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
194 .associativity = 24, .line_size = 64, },
195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
196 .associativity = 24, .line_size = 64, },
197 };
198
199 /*
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
202 */
203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
204
205 /*
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
208 */
209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210 {
211 int i;
212
213 assert(cache->size > 0);
214 assert(cache->level > 0);
215 assert(cache->line_size > 0);
216 assert(cache->associativity > 0);
217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
219 if (d->level == cache->level && d->type == cache->type &&
220 d->size == cache->size && d->line_size == cache->line_size &&
221 d->associativity == cache->associativity) {
222 return i;
223 }
224 }
225
226 return CACHE_DESCRIPTOR_UNAVAILABLE;
227 }
228
229 /* CPUID Leaf 4 constants: */
230
231 /* EAX: */
232 #define CACHE_TYPE_D 1
233 #define CACHE_TYPE_I 2
234 #define CACHE_TYPE_UNIFIED 3
235
236 #define CACHE_LEVEL(l) (l << 5)
237
238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
239
240 /* EDX: */
241 #define CACHE_NO_INVD_SHARING (1 << 0)
242 #define CACHE_INCLUSIVE (1 << 1)
243 #define CACHE_COMPLEX_IDX (1 << 2)
244
245 /* Encode CacheType for CPUID[4].EAX */
246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
250
251
252 /* Encode cache info for CPUID[4] */
253 static void encode_cache_cpuid4(CPUCacheInfo *cache,
254 int num_apic_ids, int num_cores,
255 uint32_t *eax, uint32_t *ebx,
256 uint32_t *ecx, uint32_t *edx)
257 {
258 assert(cache->size == cache->line_size * cache->associativity *
259 cache->partitions * cache->sets);
260
261 assert(num_apic_ids > 0);
262 *eax = CACHE_TYPE(cache->type) |
263 CACHE_LEVEL(cache->level) |
264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
265 ((num_cores - 1) << 26) |
266 ((num_apic_ids - 1) << 14);
267
268 assert(cache->line_size > 0);
269 assert(cache->partitions > 0);
270 assert(cache->associativity > 0);
271 /* We don't implement fully-associative caches */
272 assert(cache->associativity < cache->sets);
273 *ebx = (cache->line_size - 1) |
274 ((cache->partitions - 1) << 12) |
275 ((cache->associativity - 1) << 22);
276
277 assert(cache->sets > 0);
278 *ecx = cache->sets - 1;
279
280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
281 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
283 }
284
285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
287 {
288 assert(cache->size % 1024 == 0);
289 assert(cache->lines_per_tag > 0);
290 assert(cache->associativity > 0);
291 assert(cache->line_size > 0);
292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
293 (cache->lines_per_tag << 8) | (cache->line_size);
294 }
295
296 #define ASSOC_FULL 0xFF
297
298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
300 a == 2 ? 0x2 : \
301 a == 4 ? 0x4 : \
302 a == 8 ? 0x6 : \
303 a == 16 ? 0x8 : \
304 a == 32 ? 0xA : \
305 a == 48 ? 0xB : \
306 a == 64 ? 0xC : \
307 a == 96 ? 0xD : \
308 a == 128 ? 0xE : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
311
312 /*
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
314 * @l3 can be NULL.
315 */
316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
317 CPUCacheInfo *l3,
318 uint32_t *ecx, uint32_t *edx)
319 {
320 assert(l2->size % 1024 == 0);
321 assert(l2->associativity > 0);
322 assert(l2->lines_per_tag > 0);
323 assert(l2->line_size > 0);
324 *ecx = ((l2->size / 1024) << 16) |
325 (AMD_ENC_ASSOC(l2->associativity) << 12) |
326 (l2->lines_per_tag << 8) | (l2->line_size);
327
328 if (l3) {
329 assert(l3->size % (512 * 1024) == 0);
330 assert(l3->associativity > 0);
331 assert(l3->lines_per_tag > 0);
332 assert(l3->line_size > 0);
333 *edx = ((l3->size / (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3->associativity) << 12) |
335 (l3->lines_per_tag << 8) | (l3->line_size);
336 } else {
337 *edx = 0;
338 }
339 }
340
341 /* Encode cache info for CPUID[8000001D] */
342 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
343 X86CPUTopoInfo *topo_info,
344 uint32_t *eax, uint32_t *ebx,
345 uint32_t *ecx, uint32_t *edx)
346 {
347 uint32_t l3_threads;
348 assert(cache->size == cache->line_size * cache->associativity *
349 cache->partitions * cache->sets);
350
351 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
352 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
353
354 /* L3 is shared among multiple cores */
355 if (cache->level == 3) {
356 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
357 *eax |= (l3_threads - 1) << 14;
358 } else {
359 *eax |= ((topo_info->threads_per_core - 1) << 14);
360 }
361
362 assert(cache->line_size > 0);
363 assert(cache->partitions > 0);
364 assert(cache->associativity > 0);
365 /* We don't implement fully-associative caches */
366 assert(cache->associativity < cache->sets);
367 *ebx = (cache->line_size - 1) |
368 ((cache->partitions - 1) << 12) |
369 ((cache->associativity - 1) << 22);
370
371 assert(cache->sets > 0);
372 *ecx = cache->sets - 1;
373
374 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
375 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
376 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
377 }
378
379 /* Encode cache info for CPUID[8000001E] */
380 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
381 uint32_t *eax, uint32_t *ebx,
382 uint32_t *ecx, uint32_t *edx)
383 {
384 X86CPUTopoIDs topo_ids;
385
386 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
387
388 *eax = cpu->apic_id;
389
390 /*
391 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
392 * Read-only. Reset: 0000_XXXXh.
393 * See Core::X86::Cpuid::ExtApicId.
394 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
395 * Bits Description
396 * 31:16 Reserved.
397 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
398 * The number of threads per core is ThreadsPerCore+1.
399 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
400 *
401 * NOTE: CoreId is already part of apic_id. Just use it. We can
402 * use all the 8 bits to represent the core_id here.
403 */
404 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
405
406 /*
407 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
408 * Read-only. Reset: 0000_0XXXh.
409 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
410 * Bits Description
411 * 31:11 Reserved.
412 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
413 * ValidValues:
414 * Value Description
415 * 000b 1 node per processor.
416 * 001b 2 nodes per processor.
417 * 010b Reserved.
418 * 011b 4 nodes per processor.
419 * 111b-100b Reserved.
420 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
421 *
422 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
423 * But users can create more nodes than the actual hardware can
424 * support. To genaralize we can use all the upper 8 bits for nodes.
425 * NodeId is combination of node and socket_id which is already decoded
426 * in apic_id. Just use it by shifting.
427 */
428 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
429 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
430
431 *edx = 0;
432 }
433
434 /*
435 * Definitions of the hardcoded cache entries we expose:
436 * These are legacy cache values. If there is a need to change any
437 * of these values please use builtin_x86_defs
438 */
439
440 /* L1 data cache: */
441 static CPUCacheInfo legacy_l1d_cache = {
442 .type = DATA_CACHE,
443 .level = 1,
444 .size = 32 * KiB,
445 .self_init = 1,
446 .line_size = 64,
447 .associativity = 8,
448 .sets = 64,
449 .partitions = 1,
450 .no_invd_sharing = true,
451 };
452
453 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
454 static CPUCacheInfo legacy_l1d_cache_amd = {
455 .type = DATA_CACHE,
456 .level = 1,
457 .size = 64 * KiB,
458 .self_init = 1,
459 .line_size = 64,
460 .associativity = 2,
461 .sets = 512,
462 .partitions = 1,
463 .lines_per_tag = 1,
464 .no_invd_sharing = true,
465 };
466
467 /* L1 instruction cache: */
468 static CPUCacheInfo legacy_l1i_cache = {
469 .type = INSTRUCTION_CACHE,
470 .level = 1,
471 .size = 32 * KiB,
472 .self_init = 1,
473 .line_size = 64,
474 .associativity = 8,
475 .sets = 64,
476 .partitions = 1,
477 .no_invd_sharing = true,
478 };
479
480 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
481 static CPUCacheInfo legacy_l1i_cache_amd = {
482 .type = INSTRUCTION_CACHE,
483 .level = 1,
484 .size = 64 * KiB,
485 .self_init = 1,
486 .line_size = 64,
487 .associativity = 2,
488 .sets = 512,
489 .partitions = 1,
490 .lines_per_tag = 1,
491 .no_invd_sharing = true,
492 };
493
494 /* Level 2 unified cache: */
495 static CPUCacheInfo legacy_l2_cache = {
496 .type = UNIFIED_CACHE,
497 .level = 2,
498 .size = 4 * MiB,
499 .self_init = 1,
500 .line_size = 64,
501 .associativity = 16,
502 .sets = 4096,
503 .partitions = 1,
504 .no_invd_sharing = true,
505 };
506
507 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
508 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
509 .type = UNIFIED_CACHE,
510 .level = 2,
511 .size = 2 * MiB,
512 .line_size = 64,
513 .associativity = 8,
514 };
515
516
517 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
518 static CPUCacheInfo legacy_l2_cache_amd = {
519 .type = UNIFIED_CACHE,
520 .level = 2,
521 .size = 512 * KiB,
522 .line_size = 64,
523 .lines_per_tag = 1,
524 .associativity = 16,
525 .sets = 512,
526 .partitions = 1,
527 };
528
529 /* Level 3 unified cache: */
530 static CPUCacheInfo legacy_l3_cache = {
531 .type = UNIFIED_CACHE,
532 .level = 3,
533 .size = 16 * MiB,
534 .line_size = 64,
535 .associativity = 16,
536 .sets = 16384,
537 .partitions = 1,
538 .lines_per_tag = 1,
539 .self_init = true,
540 .inclusive = true,
541 .complex_indexing = true,
542 };
543
544 /* TLB definitions: */
545
546 #define L1_DTLB_2M_ASSOC 1
547 #define L1_DTLB_2M_ENTRIES 255
548 #define L1_DTLB_4K_ASSOC 1
549 #define L1_DTLB_4K_ENTRIES 255
550
551 #define L1_ITLB_2M_ASSOC 1
552 #define L1_ITLB_2M_ENTRIES 255
553 #define L1_ITLB_4K_ASSOC 1
554 #define L1_ITLB_4K_ENTRIES 255
555
556 #define L2_DTLB_2M_ASSOC 0 /* disabled */
557 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
558 #define L2_DTLB_4K_ASSOC 4
559 #define L2_DTLB_4K_ENTRIES 512
560
561 #define L2_ITLB_2M_ASSOC 0 /* disabled */
562 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
563 #define L2_ITLB_4K_ASSOC 4
564 #define L2_ITLB_4K_ENTRIES 512
565
566 /* CPUID Leaf 0x14 constants: */
567 #define INTEL_PT_MAX_SUBLEAF 0x1
568 /*
569 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
570 * MSR can be accessed;
571 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
572 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
573 * of Intel PT MSRs across warm reset;
574 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
575 */
576 #define INTEL_PT_MINIMAL_EBX 0xf
577 /*
578 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
579 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
580 * accessed;
581 * bit[01]: ToPA tables can hold any number of output entries, up to the
582 * maximum allowed by the MaskOrTableOffset field of
583 * IA32_RTIT_OUTPUT_MASK_PTRS;
584 * bit[02]: Support Single-Range Output scheme;
585 */
586 #define INTEL_PT_MINIMAL_ECX 0x7
587 /* generated packets which contain IP payloads have LIP values */
588 #define INTEL_PT_IP_LIP (1 << 31)
589 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
590 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
591 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
592 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
593 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
594
595 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
596 uint32_t vendor2, uint32_t vendor3)
597 {
598 int i;
599 for (i = 0; i < 4; i++) {
600 dst[i] = vendor1 >> (8 * i);
601 dst[i + 4] = vendor2 >> (8 * i);
602 dst[i + 8] = vendor3 >> (8 * i);
603 }
604 dst[CPUID_VENDOR_SZ] = '\0';
605 }
606
607 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
608 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
609 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
610 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
611 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
612 CPUID_PSE36 | CPUID_FXSR)
613 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
614 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
615 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
616 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
617 CPUID_PAE | CPUID_SEP | CPUID_APIC)
618
619 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
620 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
621 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
622 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
623 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
624 /* partly implemented:
625 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
626 /* missing:
627 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
628 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
629 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
630 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
631 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
632 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
633 CPUID_EXT_RDRAND)
634 /* missing:
635 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
636 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
637 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
638 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
639 CPUID_EXT_F16C */
640
641 #ifdef TARGET_X86_64
642 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
643 #else
644 #define TCG_EXT2_X86_64_FEATURES 0
645 #endif
646
647 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
648 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
649 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
650 TCG_EXT2_X86_64_FEATURES)
651 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
652 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
653 #define TCG_EXT4_FEATURES 0
654 #define TCG_SVM_FEATURES CPUID_SVM_NPT
655 #define TCG_KVM_FEATURES 0
656 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
657 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
658 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
659 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
660 CPUID_7_0_EBX_ERMS)
661 /* missing:
662 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
663 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
664 CPUID_7_0_EBX_RDSEED */
665 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
666 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
667 CPUID_7_0_ECX_LA57)
668 #define TCG_7_0_EDX_FEATURES 0
669 #define TCG_7_1_EAX_FEATURES 0
670 #define TCG_APM_FEATURES 0
671 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
672 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
673 /* missing:
674 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
675
676 typedef enum FeatureWordType {
677 CPUID_FEATURE_WORD,
678 MSR_FEATURE_WORD,
679 } FeatureWordType;
680
681 typedef struct FeatureWordInfo {
682 FeatureWordType type;
683 /* feature flags names are taken from "Intel Processor Identification and
684 * the CPUID Instruction" and AMD's "CPUID Specification".
685 * In cases of disagreement between feature naming conventions,
686 * aliases may be added.
687 */
688 const char *feat_names[64];
689 union {
690 /* If type==CPUID_FEATURE_WORD */
691 struct {
692 uint32_t eax; /* Input EAX for CPUID */
693 bool needs_ecx; /* CPUID instruction uses ECX as input */
694 uint32_t ecx; /* Input ECX value for CPUID */
695 int reg; /* output register (R_* constant) */
696 } cpuid;
697 /* If type==MSR_FEATURE_WORD */
698 struct {
699 uint32_t index;
700 } msr;
701 };
702 uint64_t tcg_features; /* Feature flags supported by TCG */
703 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
704 uint64_t migratable_flags; /* Feature flags known to be migratable */
705 /* Features that shouldn't be auto-enabled by "-cpu host" */
706 uint64_t no_autoenable_flags;
707 } FeatureWordInfo;
708
709 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
710 [FEAT_1_EDX] = {
711 .type = CPUID_FEATURE_WORD,
712 .feat_names = {
713 "fpu", "vme", "de", "pse",
714 "tsc", "msr", "pae", "mce",
715 "cx8", "apic", NULL, "sep",
716 "mtrr", "pge", "mca", "cmov",
717 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
718 NULL, "ds" /* Intel dts */, "acpi", "mmx",
719 "fxsr", "sse", "sse2", "ss",
720 "ht" /* Intel htt */, "tm", "ia64", "pbe",
721 },
722 .cpuid = {.eax = 1, .reg = R_EDX, },
723 .tcg_features = TCG_FEATURES,
724 },
725 [FEAT_1_ECX] = {
726 .type = CPUID_FEATURE_WORD,
727 .feat_names = {
728 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
729 "ds-cpl", "vmx", "smx", "est",
730 "tm2", "ssse3", "cid", NULL,
731 "fma", "cx16", "xtpr", "pdcm",
732 NULL, "pcid", "dca", "sse4.1",
733 "sse4.2", "x2apic", "movbe", "popcnt",
734 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
735 "avx", "f16c", "rdrand", "hypervisor",
736 },
737 .cpuid = { .eax = 1, .reg = R_ECX, },
738 .tcg_features = TCG_EXT_FEATURES,
739 },
740 /* Feature names that are already defined on feature_name[] but
741 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
742 * names on feat_names below. They are copied automatically
743 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
744 */
745 [FEAT_8000_0001_EDX] = {
746 .type = CPUID_FEATURE_WORD,
747 .feat_names = {
748 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
749 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
750 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
751 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
752 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
753 "nx", NULL, "mmxext", NULL /* mmx */,
754 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
755 NULL, "lm", "3dnowext", "3dnow",
756 },
757 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
758 .tcg_features = TCG_EXT2_FEATURES,
759 },
760 [FEAT_8000_0001_ECX] = {
761 .type = CPUID_FEATURE_WORD,
762 .feat_names = {
763 "lahf-lm", "cmp-legacy", "svm", "extapic",
764 "cr8legacy", "abm", "sse4a", "misalignsse",
765 "3dnowprefetch", "osvw", "ibs", "xop",
766 "skinit", "wdt", NULL, "lwp",
767 "fma4", "tce", NULL, "nodeid-msr",
768 NULL, "tbm", "topoext", "perfctr-core",
769 "perfctr-nb", NULL, NULL, NULL,
770 NULL, NULL, NULL, NULL,
771 },
772 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
773 .tcg_features = TCG_EXT3_FEATURES,
774 /*
775 * TOPOEXT is always allowed but can't be enabled blindly by
776 * "-cpu host", as it requires consistent cache topology info
777 * to be provided so it doesn't confuse guests.
778 */
779 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
780 },
781 [FEAT_C000_0001_EDX] = {
782 .type = CPUID_FEATURE_WORD,
783 .feat_names = {
784 NULL, NULL, "xstore", "xstore-en",
785 NULL, NULL, "xcrypt", "xcrypt-en",
786 "ace2", "ace2-en", "phe", "phe-en",
787 "pmm", "pmm-en", NULL, NULL,
788 NULL, NULL, NULL, NULL,
789 NULL, NULL, NULL, NULL,
790 NULL, NULL, NULL, NULL,
791 NULL, NULL, NULL, NULL,
792 },
793 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
794 .tcg_features = TCG_EXT4_FEATURES,
795 },
796 [FEAT_KVM] = {
797 .type = CPUID_FEATURE_WORD,
798 .feat_names = {
799 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
800 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
801 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
802 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", NULL,
803 NULL, NULL, NULL, NULL,
804 NULL, NULL, NULL, NULL,
805 "kvmclock-stable-bit", NULL, NULL, NULL,
806 NULL, NULL, NULL, NULL,
807 },
808 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
809 .tcg_features = TCG_KVM_FEATURES,
810 },
811 [FEAT_KVM_HINTS] = {
812 .type = CPUID_FEATURE_WORD,
813 .feat_names = {
814 "kvm-hint-dedicated", NULL, NULL, NULL,
815 NULL, NULL, NULL, NULL,
816 NULL, NULL, NULL, NULL,
817 NULL, NULL, NULL, NULL,
818 NULL, NULL, NULL, NULL,
819 NULL, NULL, NULL, NULL,
820 NULL, NULL, NULL, NULL,
821 NULL, NULL, NULL, NULL,
822 },
823 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
824 .tcg_features = TCG_KVM_FEATURES,
825 /*
826 * KVM hints aren't auto-enabled by -cpu host, they need to be
827 * explicitly enabled in the command-line.
828 */
829 .no_autoenable_flags = ~0U,
830 },
831 /*
832 * .feat_names are commented out for Hyper-V enlightenments because we
833 * don't want to have two different ways for enabling them on QEMU command
834 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
835 * enabling several feature bits simultaneously, exposing these bits
836 * individually may just confuse guests.
837 */
838 [FEAT_HYPERV_EAX] = {
839 .type = CPUID_FEATURE_WORD,
840 .feat_names = {
841 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
842 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
843 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
844 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
845 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
846 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
847 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
848 NULL, NULL,
849 NULL, NULL, NULL, NULL,
850 NULL, NULL, NULL, NULL,
851 NULL, NULL, NULL, NULL,
852 NULL, NULL, NULL, NULL,
853 },
854 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
855 },
856 [FEAT_HYPERV_EBX] = {
857 .type = CPUID_FEATURE_WORD,
858 .feat_names = {
859 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
860 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
861 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
862 NULL /* hv_create_port */, NULL /* hv_connect_port */,
863 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
864 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
865 NULL, NULL,
866 NULL, NULL, NULL, NULL,
867 NULL, NULL, NULL, NULL,
868 NULL, NULL, NULL, NULL,
869 NULL, NULL, NULL, NULL,
870 },
871 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
872 },
873 [FEAT_HYPERV_EDX] = {
874 .type = CPUID_FEATURE_WORD,
875 .feat_names = {
876 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
877 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
878 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
879 NULL, NULL,
880 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
881 NULL, NULL, NULL, NULL,
882 NULL, NULL, NULL, NULL,
883 NULL, NULL, NULL, NULL,
884 NULL, NULL, NULL, NULL,
885 NULL, NULL, NULL, NULL,
886 },
887 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
888 },
889 [FEAT_HV_RECOMM_EAX] = {
890 .type = CPUID_FEATURE_WORD,
891 .feat_names = {
892 NULL /* hv_recommend_pv_as_switch */,
893 NULL /* hv_recommend_pv_tlbflush_local */,
894 NULL /* hv_recommend_pv_tlbflush_remote */,
895 NULL /* hv_recommend_msr_apic_access */,
896 NULL /* hv_recommend_msr_reset */,
897 NULL /* hv_recommend_relaxed_timing */,
898 NULL /* hv_recommend_dma_remapping */,
899 NULL /* hv_recommend_int_remapping */,
900 NULL /* hv_recommend_x2apic_msrs */,
901 NULL /* hv_recommend_autoeoi_deprecation */,
902 NULL /* hv_recommend_pv_ipi */,
903 NULL /* hv_recommend_ex_hypercalls */,
904 NULL /* hv_hypervisor_is_nested */,
905 NULL /* hv_recommend_int_mbec */,
906 NULL /* hv_recommend_evmcs */,
907 NULL,
908 NULL, NULL, NULL, NULL,
909 NULL, NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 NULL, NULL, NULL, NULL,
912 },
913 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
914 },
915 [FEAT_HV_NESTED_EAX] = {
916 .type = CPUID_FEATURE_WORD,
917 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
918 },
919 [FEAT_SVM] = {
920 .type = CPUID_FEATURE_WORD,
921 .feat_names = {
922 "npt", "lbrv", "svm-lock", "nrip-save",
923 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
924 NULL, NULL, "pause-filter", NULL,
925 "pfthreshold", NULL, NULL, NULL,
926 NULL, NULL, NULL, NULL,
927 NULL, NULL, NULL, NULL,
928 NULL, NULL, NULL, NULL,
929 NULL, NULL, NULL, NULL,
930 },
931 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
932 .tcg_features = TCG_SVM_FEATURES,
933 },
934 [FEAT_7_0_EBX] = {
935 .type = CPUID_FEATURE_WORD,
936 .feat_names = {
937 "fsgsbase", "tsc-adjust", NULL, "bmi1",
938 "hle", "avx2", NULL, "smep",
939 "bmi2", "erms", "invpcid", "rtm",
940 NULL, NULL, "mpx", NULL,
941 "avx512f", "avx512dq", "rdseed", "adx",
942 "smap", "avx512ifma", "pcommit", "clflushopt",
943 "clwb", "intel-pt", "avx512pf", "avx512er",
944 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
945 },
946 .cpuid = {
947 .eax = 7,
948 .needs_ecx = true, .ecx = 0,
949 .reg = R_EBX,
950 },
951 .tcg_features = TCG_7_0_EBX_FEATURES,
952 },
953 [FEAT_7_0_ECX] = {
954 .type = CPUID_FEATURE_WORD,
955 .feat_names = {
956 NULL, "avx512vbmi", "umip", "pku",
957 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
958 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
959 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
960 "la57", NULL, NULL, NULL,
961 NULL, NULL, "rdpid", NULL,
962 NULL, "cldemote", NULL, "movdiri",
963 "movdir64b", NULL, NULL, NULL,
964 },
965 .cpuid = {
966 .eax = 7,
967 .needs_ecx = true, .ecx = 0,
968 .reg = R_ECX,
969 },
970 .tcg_features = TCG_7_0_ECX_FEATURES,
971 },
972 [FEAT_7_0_EDX] = {
973 .type = CPUID_FEATURE_WORD,
974 .feat_names = {
975 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
976 "fsrm", NULL, NULL, NULL,
977 "avx512-vp2intersect", NULL, "md-clear", NULL,
978 NULL, NULL, "serialize", NULL,
979 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
980 NULL, NULL, NULL, NULL,
981 NULL, NULL, "spec-ctrl", "stibp",
982 NULL, "arch-capabilities", "core-capability", "ssbd",
983 },
984 .cpuid = {
985 .eax = 7,
986 .needs_ecx = true, .ecx = 0,
987 .reg = R_EDX,
988 },
989 .tcg_features = TCG_7_0_EDX_FEATURES,
990 },
991 [FEAT_7_1_EAX] = {
992 .type = CPUID_FEATURE_WORD,
993 .feat_names = {
994 NULL, NULL, NULL, NULL,
995 NULL, "avx512-bf16", NULL, NULL,
996 NULL, NULL, NULL, NULL,
997 NULL, NULL, NULL, NULL,
998 NULL, NULL, NULL, NULL,
999 NULL, NULL, NULL, NULL,
1000 NULL, NULL, NULL, NULL,
1001 NULL, NULL, NULL, NULL,
1002 },
1003 .cpuid = {
1004 .eax = 7,
1005 .needs_ecx = true, .ecx = 1,
1006 .reg = R_EAX,
1007 },
1008 .tcg_features = TCG_7_1_EAX_FEATURES,
1009 },
1010 [FEAT_8000_0007_EDX] = {
1011 .type = CPUID_FEATURE_WORD,
1012 .feat_names = {
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 "invtsc", NULL, NULL, NULL,
1016 NULL, NULL, NULL, NULL,
1017 NULL, NULL, NULL, NULL,
1018 NULL, NULL, NULL, NULL,
1019 NULL, NULL, NULL, NULL,
1020 NULL, NULL, NULL, NULL,
1021 },
1022 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1023 .tcg_features = TCG_APM_FEATURES,
1024 .unmigratable_flags = CPUID_APM_INVTSC,
1025 },
1026 [FEAT_8000_0008_EBX] = {
1027 .type = CPUID_FEATURE_WORD,
1028 .feat_names = {
1029 "clzero", NULL, "xsaveerptr", NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, "wbnoinvd", NULL, NULL,
1032 "ibpb", NULL, NULL, "amd-stibp",
1033 NULL, NULL, NULL, NULL,
1034 NULL, NULL, NULL, NULL,
1035 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1036 NULL, NULL, NULL, NULL,
1037 },
1038 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1039 .tcg_features = 0,
1040 .unmigratable_flags = 0,
1041 },
1042 [FEAT_XSAVE] = {
1043 .type = CPUID_FEATURE_WORD,
1044 .feat_names = {
1045 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1046 NULL, NULL, NULL, NULL,
1047 NULL, NULL, NULL, NULL,
1048 NULL, NULL, NULL, NULL,
1049 NULL, NULL, NULL, NULL,
1050 NULL, NULL, NULL, NULL,
1051 NULL, NULL, NULL, NULL,
1052 NULL, NULL, NULL, NULL,
1053 },
1054 .cpuid = {
1055 .eax = 0xd,
1056 .needs_ecx = true, .ecx = 1,
1057 .reg = R_EAX,
1058 },
1059 .tcg_features = TCG_XSAVE_FEATURES,
1060 },
1061 [FEAT_6_EAX] = {
1062 .type = CPUID_FEATURE_WORD,
1063 .feat_names = {
1064 NULL, NULL, "arat", NULL,
1065 NULL, NULL, NULL, NULL,
1066 NULL, NULL, NULL, NULL,
1067 NULL, NULL, NULL, NULL,
1068 NULL, NULL, NULL, NULL,
1069 NULL, NULL, NULL, NULL,
1070 NULL, NULL, NULL, NULL,
1071 NULL, NULL, NULL, NULL,
1072 },
1073 .cpuid = { .eax = 6, .reg = R_EAX, },
1074 .tcg_features = TCG_6_EAX_FEATURES,
1075 },
1076 [FEAT_XSAVE_COMP_LO] = {
1077 .type = CPUID_FEATURE_WORD,
1078 .cpuid = {
1079 .eax = 0xD,
1080 .needs_ecx = true, .ecx = 0,
1081 .reg = R_EAX,
1082 },
1083 .tcg_features = ~0U,
1084 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1085 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1086 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1087 XSTATE_PKRU_MASK,
1088 },
1089 [FEAT_XSAVE_COMP_HI] = {
1090 .type = CPUID_FEATURE_WORD,
1091 .cpuid = {
1092 .eax = 0xD,
1093 .needs_ecx = true, .ecx = 0,
1094 .reg = R_EDX,
1095 },
1096 .tcg_features = ~0U,
1097 },
1098 /*Below are MSR exposed features*/
1099 [FEAT_ARCH_CAPABILITIES] = {
1100 .type = MSR_FEATURE_WORD,
1101 .feat_names = {
1102 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1103 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1104 "taa-no", NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 NULL, NULL, NULL, NULL,
1107 NULL, NULL, NULL, NULL,
1108 NULL, NULL, NULL, NULL,
1109 NULL, NULL, NULL, NULL,
1110 },
1111 .msr = {
1112 .index = MSR_IA32_ARCH_CAPABILITIES,
1113 },
1114 },
1115 [FEAT_CORE_CAPABILITY] = {
1116 .type = MSR_FEATURE_WORD,
1117 .feat_names = {
1118 NULL, NULL, NULL, NULL,
1119 NULL, "split-lock-detect", NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL,
1125 NULL, NULL, NULL, NULL,
1126 },
1127 .msr = {
1128 .index = MSR_IA32_CORE_CAPABILITY,
1129 },
1130 },
1131 [FEAT_PERF_CAPABILITIES] = {
1132 .type = MSR_FEATURE_WORD,
1133 .feat_names = {
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 NULL, "full-width-write", NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL,
1141 NULL, NULL, NULL, NULL,
1142 },
1143 .msr = {
1144 .index = MSR_IA32_PERF_CAPABILITIES,
1145 },
1146 },
1147
1148 [FEAT_VMX_PROCBASED_CTLS] = {
1149 .type = MSR_FEATURE_WORD,
1150 .feat_names = {
1151 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1152 NULL, NULL, NULL, "vmx-hlt-exit",
1153 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1154 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1155 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1156 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1157 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1158 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1159 },
1160 .msr = {
1161 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1162 }
1163 },
1164
1165 [FEAT_VMX_SECONDARY_CTLS] = {
1166 .type = MSR_FEATURE_WORD,
1167 .feat_names = {
1168 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1169 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1170 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1171 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1172 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1173 "vmx-xsaves", NULL, NULL, NULL,
1174 NULL, NULL, NULL, NULL,
1175 NULL, NULL, NULL, NULL,
1176 },
1177 .msr = {
1178 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1179 }
1180 },
1181
1182 [FEAT_VMX_PINBASED_CTLS] = {
1183 .type = MSR_FEATURE_WORD,
1184 .feat_names = {
1185 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1186 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1187 NULL, NULL, NULL, NULL,
1188 NULL, NULL, NULL, NULL,
1189 NULL, NULL, NULL, NULL,
1190 NULL, NULL, NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 },
1194 .msr = {
1195 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1196 }
1197 },
1198
1199 [FEAT_VMX_EXIT_CTLS] = {
1200 .type = MSR_FEATURE_WORD,
1201 /*
1202 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1203 * the LM CPUID bit.
1204 */
1205 .feat_names = {
1206 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1207 NULL, NULL, NULL, NULL,
1208 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1209 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1210 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1211 "vmx-exit-save-efer", "vmx-exit-load-efer",
1212 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1213 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1214 NULL, NULL, NULL, NULL,
1215 },
1216 .msr = {
1217 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1218 }
1219 },
1220
1221 [FEAT_VMX_ENTRY_CTLS] = {
1222 .type = MSR_FEATURE_WORD,
1223 .feat_names = {
1224 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1225 NULL, NULL, NULL, NULL,
1226 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1227 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1228 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1229 NULL, NULL, NULL, NULL,
1230 NULL, NULL, NULL, NULL,
1231 NULL, NULL, NULL, NULL,
1232 },
1233 .msr = {
1234 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1235 }
1236 },
1237
1238 [FEAT_VMX_MISC] = {
1239 .type = MSR_FEATURE_WORD,
1240 .feat_names = {
1241 NULL, NULL, NULL, NULL,
1242 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1243 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1244 NULL, NULL, NULL, NULL,
1245 NULL, NULL, NULL, NULL,
1246 NULL, NULL, NULL, NULL,
1247 NULL, NULL, NULL, NULL,
1248 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1249 },
1250 .msr = {
1251 .index = MSR_IA32_VMX_MISC,
1252 }
1253 },
1254
1255 [FEAT_VMX_EPT_VPID_CAPS] = {
1256 .type = MSR_FEATURE_WORD,
1257 .feat_names = {
1258 "vmx-ept-execonly", NULL, NULL, NULL,
1259 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1260 NULL, NULL, NULL, NULL,
1261 NULL, NULL, NULL, NULL,
1262 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1263 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1264 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1265 NULL, NULL, NULL, NULL,
1266 "vmx-invvpid", NULL, NULL, NULL,
1267 NULL, NULL, NULL, NULL,
1268 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1269 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1270 NULL, NULL, NULL, NULL,
1271 NULL, NULL, NULL, NULL,
1272 NULL, NULL, NULL, NULL,
1273 NULL, NULL, NULL, NULL,
1274 NULL, NULL, NULL, NULL,
1275 },
1276 .msr = {
1277 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1278 }
1279 },
1280
1281 [FEAT_VMX_BASIC] = {
1282 .type = MSR_FEATURE_WORD,
1283 .feat_names = {
1284 [54] = "vmx-ins-outs",
1285 [55] = "vmx-true-ctls",
1286 },
1287 .msr = {
1288 .index = MSR_IA32_VMX_BASIC,
1289 },
1290 /* Just to be safe - we don't support setting the MSEG version field. */
1291 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1292 },
1293
1294 [FEAT_VMX_VMFUNC] = {
1295 .type = MSR_FEATURE_WORD,
1296 .feat_names = {
1297 [0] = "vmx-eptp-switching",
1298 },
1299 .msr = {
1300 .index = MSR_IA32_VMX_VMFUNC,
1301 }
1302 },
1303
1304 };
1305
1306 typedef struct FeatureMask {
1307 FeatureWord index;
1308 uint64_t mask;
1309 } FeatureMask;
1310
1311 typedef struct FeatureDep {
1312 FeatureMask from, to;
1313 } FeatureDep;
1314
1315 static FeatureDep feature_dependencies[] = {
1316 {
1317 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
1318 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1319 },
1320 {
1321 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
1322 .to = { FEAT_CORE_CAPABILITY, ~0ull },
1323 },
1324 {
1325 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1326 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1327 },
1328 {
1329 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1330 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1331 },
1332 {
1333 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1334 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1335 },
1336 {
1337 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1338 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1339 },
1340 {
1341 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1342 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1343 },
1344 {
1345 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1346 .to = { FEAT_VMX_MISC, ~0ull },
1347 },
1348 {
1349 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1350 .to = { FEAT_VMX_BASIC, ~0ull },
1351 },
1352 {
1353 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1354 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1355 },
1356 {
1357 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1358 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1359 },
1360 {
1361 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1362 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1363 },
1364 {
1365 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1366 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1367 },
1368 {
1369 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1370 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1371 },
1372 {
1373 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1374 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1375 },
1376 {
1377 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1378 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1379 },
1380 {
1381 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1382 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1383 },
1384 {
1385 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1386 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1387 },
1388 {
1389 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1390 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1391 },
1392 {
1393 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1394 .to = { FEAT_VMX_VMFUNC, ~0ull },
1395 },
1396 {
1397 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1398 .to = { FEAT_SVM, ~0ull },
1399 },
1400 };
1401
1402 typedef struct X86RegisterInfo32 {
1403 /* Name of register */
1404 const char *name;
1405 /* QAPI enum value register */
1406 X86CPURegister32 qapi_enum;
1407 } X86RegisterInfo32;
1408
1409 #define REGISTER(reg) \
1410 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1411 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1412 REGISTER(EAX),
1413 REGISTER(ECX),
1414 REGISTER(EDX),
1415 REGISTER(EBX),
1416 REGISTER(ESP),
1417 REGISTER(EBP),
1418 REGISTER(ESI),
1419 REGISTER(EDI),
1420 };
1421 #undef REGISTER
1422
1423 typedef struct ExtSaveArea {
1424 uint32_t feature, bits;
1425 uint32_t offset, size;
1426 } ExtSaveArea;
1427
1428 static const ExtSaveArea x86_ext_save_areas[] = {
1429 [XSTATE_FP_BIT] = {
1430 /* x87 FP state component is always enabled if XSAVE is supported */
1431 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1432 /* x87 state is in the legacy region of the XSAVE area */
1433 .offset = 0,
1434 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1435 },
1436 [XSTATE_SSE_BIT] = {
1437 /* SSE state component is always enabled if XSAVE is supported */
1438 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1439 /* SSE state is in the legacy region of the XSAVE area */
1440 .offset = 0,
1441 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1442 },
1443 [XSTATE_YMM_BIT] =
1444 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1445 .offset = offsetof(X86XSaveArea, avx_state),
1446 .size = sizeof(XSaveAVX) },
1447 [XSTATE_BNDREGS_BIT] =
1448 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1449 .offset = offsetof(X86XSaveArea, bndreg_state),
1450 .size = sizeof(XSaveBNDREG) },
1451 [XSTATE_BNDCSR_BIT] =
1452 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1453 .offset = offsetof(X86XSaveArea, bndcsr_state),
1454 .size = sizeof(XSaveBNDCSR) },
1455 [XSTATE_OPMASK_BIT] =
1456 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1457 .offset = offsetof(X86XSaveArea, opmask_state),
1458 .size = sizeof(XSaveOpmask) },
1459 [XSTATE_ZMM_Hi256_BIT] =
1460 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1461 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1462 .size = sizeof(XSaveZMM_Hi256) },
1463 [XSTATE_Hi16_ZMM_BIT] =
1464 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1465 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1466 .size = sizeof(XSaveHi16_ZMM) },
1467 [XSTATE_PKRU_BIT] =
1468 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1469 .offset = offsetof(X86XSaveArea, pkru_state),
1470 .size = sizeof(XSavePKRU) },
1471 };
1472
1473 static uint32_t xsave_area_size(uint64_t mask)
1474 {
1475 int i;
1476 uint64_t ret = 0;
1477
1478 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1479 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1480 if ((mask >> i) & 1) {
1481 ret = MAX(ret, esa->offset + esa->size);
1482 }
1483 }
1484 return ret;
1485 }
1486
1487 static inline bool accel_uses_host_cpuid(void)
1488 {
1489 return kvm_enabled() || hvf_enabled();
1490 }
1491
1492 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1493 {
1494 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1495 cpu->env.features[FEAT_XSAVE_COMP_LO];
1496 }
1497
1498 const char *get_register_name_32(unsigned int reg)
1499 {
1500 if (reg >= CPU_NB_REGS32) {
1501 return NULL;
1502 }
1503 return x86_reg_info_32[reg].name;
1504 }
1505
1506 /*
1507 * Returns the set of feature flags that are supported and migratable by
1508 * QEMU, for a given FeatureWord.
1509 */
1510 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1511 {
1512 FeatureWordInfo *wi = &feature_word_info[w];
1513 uint64_t r = 0;
1514 int i;
1515
1516 for (i = 0; i < 64; i++) {
1517 uint64_t f = 1ULL << i;
1518
1519 /* If the feature name is known, it is implicitly considered migratable,
1520 * unless it is explicitly set in unmigratable_flags */
1521 if ((wi->migratable_flags & f) ||
1522 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1523 r |= f;
1524 }
1525 }
1526 return r;
1527 }
1528
1529 void host_cpuid(uint32_t function, uint32_t count,
1530 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1531 {
1532 uint32_t vec[4];
1533
1534 #ifdef __x86_64__
1535 asm volatile("cpuid"
1536 : "=a"(vec[0]), "=b"(vec[1]),
1537 "=c"(vec[2]), "=d"(vec[3])
1538 : "0"(function), "c"(count) : "cc");
1539 #elif defined(__i386__)
1540 asm volatile("pusha \n\t"
1541 "cpuid \n\t"
1542 "mov %%eax, 0(%2) \n\t"
1543 "mov %%ebx, 4(%2) \n\t"
1544 "mov %%ecx, 8(%2) \n\t"
1545 "mov %%edx, 12(%2) \n\t"
1546 "popa"
1547 : : "a"(function), "c"(count), "S"(vec)
1548 : "memory", "cc");
1549 #else
1550 abort();
1551 #endif
1552
1553 if (eax)
1554 *eax = vec[0];
1555 if (ebx)
1556 *ebx = vec[1];
1557 if (ecx)
1558 *ecx = vec[2];
1559 if (edx)
1560 *edx = vec[3];
1561 }
1562
1563 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1564 {
1565 uint32_t eax, ebx, ecx, edx;
1566
1567 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1568 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1569
1570 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1571 if (family) {
1572 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1573 }
1574 if (model) {
1575 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1576 }
1577 if (stepping) {
1578 *stepping = eax & 0x0F;
1579 }
1580 }
1581
1582 /* CPU class name definitions: */
1583
1584 /* Return type name for a given CPU model name
1585 * Caller is responsible for freeing the returned string.
1586 */
1587 static char *x86_cpu_type_name(const char *model_name)
1588 {
1589 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1590 }
1591
1592 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1593 {
1594 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1595 return object_class_by_name(typename);
1596 }
1597
1598 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1599 {
1600 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1601 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1602 return g_strndup(class_name,
1603 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1604 }
1605
1606 typedef struct PropValue {
1607 const char *prop, *value;
1608 } PropValue;
1609
1610 typedef struct X86CPUVersionDefinition {
1611 X86CPUVersion version;
1612 const char *alias;
1613 const char *note;
1614 PropValue *props;
1615 } X86CPUVersionDefinition;
1616
1617 /* Base definition for a CPU model */
1618 typedef struct X86CPUDefinition {
1619 const char *name;
1620 uint32_t level;
1621 uint32_t xlevel;
1622 /* vendor is zero-terminated, 12 character ASCII string */
1623 char vendor[CPUID_VENDOR_SZ + 1];
1624 int family;
1625 int model;
1626 int stepping;
1627 FeatureWordArray features;
1628 const char *model_id;
1629 CPUCaches *cache_info;
1630 /*
1631 * Definitions for alternative versions of CPU model.
1632 * List is terminated by item with version == 0.
1633 * If NULL, version 1 will be registered automatically.
1634 */
1635 const X86CPUVersionDefinition *versions;
1636 } X86CPUDefinition;
1637
1638 /* Reference to a specific CPU model version */
1639 struct X86CPUModel {
1640 /* Base CPU definition */
1641 X86CPUDefinition *cpudef;
1642 /* CPU model version */
1643 X86CPUVersion version;
1644 const char *note;
1645 /*
1646 * If true, this is an alias CPU model.
1647 * This matters only for "-cpu help" and query-cpu-definitions
1648 */
1649 bool is_alias;
1650 };
1651
1652 /* Get full model name for CPU version */
1653 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1654 X86CPUVersion version)
1655 {
1656 assert(version > 0);
1657 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1658 }
1659
1660 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1661 {
1662 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1663 static const X86CPUVersionDefinition default_version_list[] = {
1664 { 1 },
1665 { /* end of list */ }
1666 };
1667
1668 return def->versions ?: default_version_list;
1669 }
1670
1671 static CPUCaches epyc_cache_info = {
1672 .l1d_cache = &(CPUCacheInfo) {
1673 .type = DATA_CACHE,
1674 .level = 1,
1675 .size = 32 * KiB,
1676 .line_size = 64,
1677 .associativity = 8,
1678 .partitions = 1,
1679 .sets = 64,
1680 .lines_per_tag = 1,
1681 .self_init = 1,
1682 .no_invd_sharing = true,
1683 },
1684 .l1i_cache = &(CPUCacheInfo) {
1685 .type = INSTRUCTION_CACHE,
1686 .level = 1,
1687 .size = 64 * KiB,
1688 .line_size = 64,
1689 .associativity = 4,
1690 .partitions = 1,
1691 .sets = 256,
1692 .lines_per_tag = 1,
1693 .self_init = 1,
1694 .no_invd_sharing = true,
1695 },
1696 .l2_cache = &(CPUCacheInfo) {
1697 .type = UNIFIED_CACHE,
1698 .level = 2,
1699 .size = 512 * KiB,
1700 .line_size = 64,
1701 .associativity = 8,
1702 .partitions = 1,
1703 .sets = 1024,
1704 .lines_per_tag = 1,
1705 },
1706 .l3_cache = &(CPUCacheInfo) {
1707 .type = UNIFIED_CACHE,
1708 .level = 3,
1709 .size = 8 * MiB,
1710 .line_size = 64,
1711 .associativity = 16,
1712 .partitions = 1,
1713 .sets = 8192,
1714 .lines_per_tag = 1,
1715 .self_init = true,
1716 .inclusive = true,
1717 .complex_indexing = true,
1718 },
1719 };
1720
1721 static CPUCaches epyc_rome_cache_info = {
1722 .l1d_cache = &(CPUCacheInfo) {
1723 .type = DATA_CACHE,
1724 .level = 1,
1725 .size = 32 * KiB,
1726 .line_size = 64,
1727 .associativity = 8,
1728 .partitions = 1,
1729 .sets = 64,
1730 .lines_per_tag = 1,
1731 .self_init = 1,
1732 .no_invd_sharing = true,
1733 },
1734 .l1i_cache = &(CPUCacheInfo) {
1735 .type = INSTRUCTION_CACHE,
1736 .level = 1,
1737 .size = 32 * KiB,
1738 .line_size = 64,
1739 .associativity = 8,
1740 .partitions = 1,
1741 .sets = 64,
1742 .lines_per_tag = 1,
1743 .self_init = 1,
1744 .no_invd_sharing = true,
1745 },
1746 .l2_cache = &(CPUCacheInfo) {
1747 .type = UNIFIED_CACHE,
1748 .level = 2,
1749 .size = 512 * KiB,
1750 .line_size = 64,
1751 .associativity = 8,
1752 .partitions = 1,
1753 .sets = 1024,
1754 .lines_per_tag = 1,
1755 },
1756 .l3_cache = &(CPUCacheInfo) {
1757 .type = UNIFIED_CACHE,
1758 .level = 3,
1759 .size = 16 * MiB,
1760 .line_size = 64,
1761 .associativity = 16,
1762 .partitions = 1,
1763 .sets = 16384,
1764 .lines_per_tag = 1,
1765 .self_init = true,
1766 .inclusive = true,
1767 .complex_indexing = true,
1768 },
1769 };
1770
1771 /* The following VMX features are not supported by KVM and are left out in the
1772 * CPU definitions:
1773 *
1774 * Dual-monitor support (all processors)
1775 * Entry to SMM
1776 * Deactivate dual-monitor treatment
1777 * Number of CR3-target values
1778 * Shutdown activity state
1779 * Wait-for-SIPI activity state
1780 * PAUSE-loop exiting (Westmere and newer)
1781 * EPT-violation #VE (Broadwell and newer)
1782 * Inject event with insn length=0 (Skylake and newer)
1783 * Conceal non-root operation from PT
1784 * Conceal VM exits from PT
1785 * Conceal VM entries from PT
1786 * Enable ENCLS exiting
1787 * Mode-based execute control (XS/XU)
1788 s TSC scaling (Skylake Server and newer)
1789 * GPA translation for PT (IceLake and newer)
1790 * User wait and pause
1791 * ENCLV exiting
1792 * Load IA32_RTIT_CTL
1793 * Clear IA32_RTIT_CTL
1794 * Advanced VM-exit information for EPT violations
1795 * Sub-page write permissions
1796 * PT in VMX operation
1797 */
1798
1799 static X86CPUDefinition builtin_x86_defs[] = {
1800 {
1801 .name = "qemu64",
1802 .level = 0xd,
1803 .vendor = CPUID_VENDOR_AMD,
1804 .family = 6,
1805 .model = 6,
1806 .stepping = 3,
1807 .features[FEAT_1_EDX] =
1808 PPRO_FEATURES |
1809 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1810 CPUID_PSE36,
1811 .features[FEAT_1_ECX] =
1812 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1813 .features[FEAT_8000_0001_EDX] =
1814 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1815 .features[FEAT_8000_0001_ECX] =
1816 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1817 .xlevel = 0x8000000A,
1818 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1819 },
1820 {
1821 .name = "phenom",
1822 .level = 5,
1823 .vendor = CPUID_VENDOR_AMD,
1824 .family = 16,
1825 .model = 2,
1826 .stepping = 3,
1827 /* Missing: CPUID_HT */
1828 .features[FEAT_1_EDX] =
1829 PPRO_FEATURES |
1830 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1831 CPUID_PSE36 | CPUID_VME,
1832 .features[FEAT_1_ECX] =
1833 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1834 CPUID_EXT_POPCNT,
1835 .features[FEAT_8000_0001_EDX] =
1836 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1837 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1838 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1839 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1840 CPUID_EXT3_CR8LEG,
1841 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1842 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1843 .features[FEAT_8000_0001_ECX] =
1844 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1845 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1846 /* Missing: CPUID_SVM_LBRV */
1847 .features[FEAT_SVM] =
1848 CPUID_SVM_NPT,
1849 .xlevel = 0x8000001A,
1850 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1851 },
1852 {
1853 .name = "core2duo",
1854 .level = 10,
1855 .vendor = CPUID_VENDOR_INTEL,
1856 .family = 6,
1857 .model = 15,
1858 .stepping = 11,
1859 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1860 .features[FEAT_1_EDX] =
1861 PPRO_FEATURES |
1862 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1863 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1864 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1865 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1866 .features[FEAT_1_ECX] =
1867 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1868 CPUID_EXT_CX16,
1869 .features[FEAT_8000_0001_EDX] =
1870 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1871 .features[FEAT_8000_0001_ECX] =
1872 CPUID_EXT3_LAHF_LM,
1873 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1874 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1875 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1876 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1877 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1878 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1879 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1880 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1881 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1882 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1883 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1884 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1885 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1886 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1887 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1888 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1889 .features[FEAT_VMX_SECONDARY_CTLS] =
1890 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1891 .xlevel = 0x80000008,
1892 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1893 },
1894 {
1895 .name = "kvm64",
1896 .level = 0xd,
1897 .vendor = CPUID_VENDOR_INTEL,
1898 .family = 15,
1899 .model = 6,
1900 .stepping = 1,
1901 /* Missing: CPUID_HT */
1902 .features[FEAT_1_EDX] =
1903 PPRO_FEATURES | CPUID_VME |
1904 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1905 CPUID_PSE36,
1906 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1907 .features[FEAT_1_ECX] =
1908 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1909 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1910 .features[FEAT_8000_0001_EDX] =
1911 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1912 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1913 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1914 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1915 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1916 .features[FEAT_8000_0001_ECX] =
1917 0,
1918 /* VMX features from Cedar Mill/Prescott */
1919 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1920 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1921 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1922 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1923 VMX_PIN_BASED_NMI_EXITING,
1924 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1925 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1926 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1927 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1928 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1929 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1930 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1931 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
1932 .xlevel = 0x80000008,
1933 .model_id = "Common KVM processor"
1934 },
1935 {
1936 .name = "qemu32",
1937 .level = 4,
1938 .vendor = CPUID_VENDOR_INTEL,
1939 .family = 6,
1940 .model = 6,
1941 .stepping = 3,
1942 .features[FEAT_1_EDX] =
1943 PPRO_FEATURES,
1944 .features[FEAT_1_ECX] =
1945 CPUID_EXT_SSE3,
1946 .xlevel = 0x80000004,
1947 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1948 },
1949 {
1950 .name = "kvm32",
1951 .level = 5,
1952 .vendor = CPUID_VENDOR_INTEL,
1953 .family = 15,
1954 .model = 6,
1955 .stepping = 1,
1956 .features[FEAT_1_EDX] =
1957 PPRO_FEATURES | CPUID_VME |
1958 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1959 .features[FEAT_1_ECX] =
1960 CPUID_EXT_SSE3,
1961 .features[FEAT_8000_0001_ECX] =
1962 0,
1963 /* VMX features from Yonah */
1964 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1965 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1966 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1967 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1968 VMX_PIN_BASED_NMI_EXITING,
1969 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1970 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1971 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1972 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1973 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1974 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1975 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
1976 .xlevel = 0x80000008,
1977 .model_id = "Common 32-bit KVM processor"
1978 },
1979 {
1980 .name = "coreduo",
1981 .level = 10,
1982 .vendor = CPUID_VENDOR_INTEL,
1983 .family = 6,
1984 .model = 14,
1985 .stepping = 8,
1986 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1987 .features[FEAT_1_EDX] =
1988 PPRO_FEATURES | CPUID_VME |
1989 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1990 CPUID_SS,
1991 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1992 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1993 .features[FEAT_1_ECX] =
1994 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
1995 .features[FEAT_8000_0001_EDX] =
1996 CPUID_EXT2_NX,
1997 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1998 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1999 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2000 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2001 VMX_PIN_BASED_NMI_EXITING,
2002 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2003 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2004 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2005 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2006 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2007 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2008 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2009 .xlevel = 0x80000008,
2010 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2011 },
2012 {
2013 .name = "486",
2014 .level = 1,
2015 .vendor = CPUID_VENDOR_INTEL,
2016 .family = 4,
2017 .model = 8,
2018 .stepping = 0,
2019 .features[FEAT_1_EDX] =
2020 I486_FEATURES,
2021 .xlevel = 0,
2022 .model_id = "",
2023 },
2024 {
2025 .name = "pentium",
2026 .level = 1,
2027 .vendor = CPUID_VENDOR_INTEL,
2028 .family = 5,
2029 .model = 4,
2030 .stepping = 3,
2031 .features[FEAT_1_EDX] =
2032 PENTIUM_FEATURES,
2033 .xlevel = 0,
2034 .model_id = "",
2035 },
2036 {
2037 .name = "pentium2",
2038 .level = 2,
2039 .vendor = CPUID_VENDOR_INTEL,
2040 .family = 6,
2041 .model = 5,
2042 .stepping = 2,
2043 .features[FEAT_1_EDX] =
2044 PENTIUM2_FEATURES,
2045 .xlevel = 0,
2046 .model_id = "",
2047 },
2048 {
2049 .name = "pentium3",
2050 .level = 3,
2051 .vendor = CPUID_VENDOR_INTEL,
2052 .family = 6,
2053 .model = 7,
2054 .stepping = 3,
2055 .features[FEAT_1_EDX] =
2056 PENTIUM3_FEATURES,
2057 .xlevel = 0,
2058 .model_id = "",
2059 },
2060 {
2061 .name = "athlon",
2062 .level = 2,
2063 .vendor = CPUID_VENDOR_AMD,
2064 .family = 6,
2065 .model = 2,
2066 .stepping = 3,
2067 .features[FEAT_1_EDX] =
2068 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
2069 CPUID_MCA,
2070 .features[FEAT_8000_0001_EDX] =
2071 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
2072 .xlevel = 0x80000008,
2073 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2074 },
2075 {
2076 .name = "n270",
2077 .level = 10,
2078 .vendor = CPUID_VENDOR_INTEL,
2079 .family = 6,
2080 .model = 28,
2081 .stepping = 2,
2082 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2083 .features[FEAT_1_EDX] =
2084 PPRO_FEATURES |
2085 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2086 CPUID_ACPI | CPUID_SS,
2087 /* Some CPUs got no CPUID_SEP */
2088 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2089 * CPUID_EXT_XTPR */
2090 .features[FEAT_1_ECX] =
2091 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2092 CPUID_EXT_MOVBE,
2093 .features[FEAT_8000_0001_EDX] =
2094 CPUID_EXT2_NX,
2095 .features[FEAT_8000_0001_ECX] =
2096 CPUID_EXT3_LAHF_LM,
2097 .xlevel = 0x80000008,
2098 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2099 },
2100 {
2101 .name = "Conroe",
2102 .level = 10,
2103 .vendor = CPUID_VENDOR_INTEL,
2104 .family = 6,
2105 .model = 15,
2106 .stepping = 3,
2107 .features[FEAT_1_EDX] =
2108 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2109 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2110 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2111 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2112 CPUID_DE | CPUID_FP87,
2113 .features[FEAT_1_ECX] =
2114 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2115 .features[FEAT_8000_0001_EDX] =
2116 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2117 .features[FEAT_8000_0001_ECX] =
2118 CPUID_EXT3_LAHF_LM,
2119 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2120 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2121 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2122 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2123 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2124 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2125 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2126 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2127 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2128 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2129 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2130 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2131 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2132 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2133 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2134 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2135 .features[FEAT_VMX_SECONDARY_CTLS] =
2136 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2137 .xlevel = 0x80000008,
2138 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2139 },
2140 {
2141 .name = "Penryn",
2142 .level = 10,
2143 .vendor = CPUID_VENDOR_INTEL,
2144 .family = 6,
2145 .model = 23,
2146 .stepping = 3,
2147 .features[FEAT_1_EDX] =
2148 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2149 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2150 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2151 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2152 CPUID_DE | CPUID_FP87,
2153 .features[FEAT_1_ECX] =
2154 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2155 CPUID_EXT_SSE3,
2156 .features[FEAT_8000_0001_EDX] =
2157 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2158 .features[FEAT_8000_0001_ECX] =
2159 CPUID_EXT3_LAHF_LM,
2160 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2161 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2162 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2163 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2164 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2165 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2166 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2167 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2168 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2169 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2170 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2171 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2172 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2173 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2174 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2175 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2176 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2177 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2178 .features[FEAT_VMX_SECONDARY_CTLS] =
2179 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2180 VMX_SECONDARY_EXEC_WBINVD_EXITING,
2181 .xlevel = 0x80000008,
2182 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2183 },
2184 {
2185 .name = "Nehalem",
2186 .level = 11,
2187 .vendor = CPUID_VENDOR_INTEL,
2188 .family = 6,
2189 .model = 26,
2190 .stepping = 3,
2191 .features[FEAT_1_EDX] =
2192 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2193 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2194 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2195 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2196 CPUID_DE | CPUID_FP87,
2197 .features[FEAT_1_ECX] =
2198 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2199 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2200 .features[FEAT_8000_0001_EDX] =
2201 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2202 .features[FEAT_8000_0001_ECX] =
2203 CPUID_EXT3_LAHF_LM,
2204 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2205 MSR_VMX_BASIC_TRUE_CTLS,
2206 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2207 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2208 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2209 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2210 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2211 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2212 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2213 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2214 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2216 .features[FEAT_VMX_EXIT_CTLS] =
2217 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2218 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2219 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2220 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2221 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2222 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2223 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2224 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2225 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2226 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2227 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2228 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2229 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2230 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2231 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2232 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2233 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2234 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2235 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2236 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2237 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2238 .features[FEAT_VMX_SECONDARY_CTLS] =
2239 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2240 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2241 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2242 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2243 VMX_SECONDARY_EXEC_ENABLE_VPID,
2244 .xlevel = 0x80000008,
2245 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2246 .versions = (X86CPUVersionDefinition[]) {
2247 { .version = 1 },
2248 {
2249 .version = 2,
2250 .alias = "Nehalem-IBRS",
2251 .props = (PropValue[]) {
2252 { "spec-ctrl", "on" },
2253 { "model-id",
2254 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2255 { /* end of list */ }
2256 }
2257 },
2258 { /* end of list */ }
2259 }
2260 },
2261 {
2262 .name = "Westmere",
2263 .level = 11,
2264 .vendor = CPUID_VENDOR_INTEL,
2265 .family = 6,
2266 .model = 44,
2267 .stepping = 1,
2268 .features[FEAT_1_EDX] =
2269 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2270 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2271 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2272 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2273 CPUID_DE | CPUID_FP87,
2274 .features[FEAT_1_ECX] =
2275 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2276 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2277 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2278 .features[FEAT_8000_0001_EDX] =
2279 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2280 .features[FEAT_8000_0001_ECX] =
2281 CPUID_EXT3_LAHF_LM,
2282 .features[FEAT_6_EAX] =
2283 CPUID_6_EAX_ARAT,
2284 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2285 MSR_VMX_BASIC_TRUE_CTLS,
2286 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2287 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2288 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2289 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2290 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2291 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2292 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2293 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2294 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2295 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2296 .features[FEAT_VMX_EXIT_CTLS] =
2297 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2298 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2299 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2300 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2301 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2302 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2303 MSR_VMX_MISC_STORE_LMA,
2304 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2305 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2306 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2307 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2308 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2309 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2310 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2311 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2312 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2313 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2314 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2315 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2316 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2317 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2318 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2319 .features[FEAT_VMX_SECONDARY_CTLS] =
2320 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2321 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2322 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2323 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2324 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2325 .xlevel = 0x80000008,
2326 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2327 .versions = (X86CPUVersionDefinition[]) {
2328 { .version = 1 },
2329 {
2330 .version = 2,
2331 .alias = "Westmere-IBRS",
2332 .props = (PropValue[]) {
2333 { "spec-ctrl", "on" },
2334 { "model-id",
2335 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2336 { /* end of list */ }
2337 }
2338 },
2339 { /* end of list */ }
2340 }
2341 },
2342 {
2343 .name = "SandyBridge",
2344 .level = 0xd,
2345 .vendor = CPUID_VENDOR_INTEL,
2346 .family = 6,
2347 .model = 42,
2348 .stepping = 1,
2349 .features[FEAT_1_EDX] =
2350 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2351 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2352 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2353 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2354 CPUID_DE | CPUID_FP87,
2355 .features[FEAT_1_ECX] =
2356 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2357 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2358 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2359 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2360 CPUID_EXT_SSE3,
2361 .features[FEAT_8000_0001_EDX] =
2362 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2363 CPUID_EXT2_SYSCALL,
2364 .features[FEAT_8000_0001_ECX] =
2365 CPUID_EXT3_LAHF_LM,
2366 .features[FEAT_XSAVE] =
2367 CPUID_XSAVE_XSAVEOPT,
2368 .features[FEAT_6_EAX] =
2369 CPUID_6_EAX_ARAT,
2370 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2371 MSR_VMX_BASIC_TRUE_CTLS,
2372 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2373 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2374 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2375 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2376 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2377 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2378 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2379 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2380 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2381 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2382 .features[FEAT_VMX_EXIT_CTLS] =
2383 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2384 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2385 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2386 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2387 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2388 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2389 MSR_VMX_MISC_STORE_LMA,
2390 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2391 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2392 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2393 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2394 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2395 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2396 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2397 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2398 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2399 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2400 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2401 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2402 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2403 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2404 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2405 .features[FEAT_VMX_SECONDARY_CTLS] =
2406 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2407 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2408 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2409 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2410 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2411 .xlevel = 0x80000008,
2412 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2413 .versions = (X86CPUVersionDefinition[]) {
2414 { .version = 1 },
2415 {
2416 .version = 2,
2417 .alias = "SandyBridge-IBRS",
2418 .props = (PropValue[]) {
2419 { "spec-ctrl", "on" },
2420 { "model-id",
2421 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2422 { /* end of list */ }
2423 }
2424 },
2425 { /* end of list */ }
2426 }
2427 },
2428 {
2429 .name = "IvyBridge",
2430 .level = 0xd,
2431 .vendor = CPUID_VENDOR_INTEL,
2432 .family = 6,
2433 .model = 58,
2434 .stepping = 9,
2435 .features[FEAT_1_EDX] =
2436 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2437 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2438 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2439 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2440 CPUID_DE | CPUID_FP87,
2441 .features[FEAT_1_ECX] =
2442 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2443 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2444 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2445 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2446 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2447 .features[FEAT_7_0_EBX] =
2448 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2449 CPUID_7_0_EBX_ERMS,
2450 .features[FEAT_8000_0001_EDX] =
2451 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2452 CPUID_EXT2_SYSCALL,
2453 .features[FEAT_8000_0001_ECX] =
2454 CPUID_EXT3_LAHF_LM,
2455 .features[FEAT_XSAVE] =
2456 CPUID_XSAVE_XSAVEOPT,
2457 .features[FEAT_6_EAX] =
2458 CPUID_6_EAX_ARAT,
2459 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2460 MSR_VMX_BASIC_TRUE_CTLS,
2461 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2462 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2463 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2464 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2465 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2466 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2467 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2468 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2469 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2470 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2471 .features[FEAT_VMX_EXIT_CTLS] =
2472 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2473 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2474 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2475 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2476 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2477 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2478 MSR_VMX_MISC_STORE_LMA,
2479 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2480 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2481 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2482 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2483 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2484 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2485 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2486 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2487 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2488 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2489 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2490 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2491 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2492 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2493 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2494 .features[FEAT_VMX_SECONDARY_CTLS] =
2495 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2496 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2497 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2498 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2499 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2500 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2501 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2502 VMX_SECONDARY_EXEC_RDRAND_EXITING,
2503 .xlevel = 0x80000008,
2504 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2505 .versions = (X86CPUVersionDefinition[]) {
2506 { .version = 1 },
2507 {
2508 .version = 2,
2509 .alias = "IvyBridge-IBRS",
2510 .props = (PropValue[]) {
2511 { "spec-ctrl", "on" },
2512 { "model-id",
2513 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2514 { /* end of list */ }
2515 }
2516 },
2517 { /* end of list */ }
2518 }
2519 },
2520 {
2521 .name = "Haswell",
2522 .level = 0xd,
2523 .vendor = CPUID_VENDOR_INTEL,
2524 .family = 6,
2525 .model = 60,
2526 .stepping = 4,
2527 .features[FEAT_1_EDX] =
2528 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2529 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2530 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2531 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2532 CPUID_DE | CPUID_FP87,
2533 .features[FEAT_1_ECX] =
2534 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2535 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2536 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2537 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2538 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2539 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2540 .features[FEAT_8000_0001_EDX] =
2541 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2542 CPUID_EXT2_SYSCALL,
2543 .features[FEAT_8000_0001_ECX] =
2544 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2545 .features[FEAT_7_0_EBX] =
2546 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2547 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2548 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2549 CPUID_7_0_EBX_RTM,
2550 .features[FEAT_XSAVE] =
2551 CPUID_XSAVE_XSAVEOPT,
2552 .features[FEAT_6_EAX] =
2553 CPUID_6_EAX_ARAT,
2554 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2555 MSR_VMX_BASIC_TRUE_CTLS,
2556 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2557 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2558 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2559 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2560 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2561 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2562 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2563 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2564 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2565 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2566 .features[FEAT_VMX_EXIT_CTLS] =
2567 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2568 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2569 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2570 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2571 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2572 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2573 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2574 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2575 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2576 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2577 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2578 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2579 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2580 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2581 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2582 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2583 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2584 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2585 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2586 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2587 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2588 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2589 .features[FEAT_VMX_SECONDARY_CTLS] =
2590 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2591 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2592 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2593 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2594 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2595 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2596 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2597 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2598 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2599 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2600 .xlevel = 0x80000008,
2601 .model_id = "Intel Core Processor (Haswell)",
2602 .versions = (X86CPUVersionDefinition[]) {
2603 { .version = 1 },
2604 {
2605 .version = 2,
2606 .alias = "Haswell-noTSX",
2607 .props = (PropValue[]) {
2608 { "hle", "off" },
2609 { "rtm", "off" },
2610 { "stepping", "1" },
2611 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2612 { /* end of list */ }
2613 },
2614 },
2615 {
2616 .version = 3,
2617 .alias = "Haswell-IBRS",
2618 .props = (PropValue[]) {
2619 /* Restore TSX features removed by -v2 above */
2620 { "hle", "on" },
2621 { "rtm", "on" },
2622 /*
2623 * Haswell and Haswell-IBRS had stepping=4 in
2624 * QEMU 4.0 and older
2625 */
2626 { "stepping", "4" },
2627 { "spec-ctrl", "on" },
2628 { "model-id",
2629 "Intel Core Processor (Haswell, IBRS)" },
2630 { /* end of list */ }
2631 }
2632 },
2633 {
2634 .version = 4,
2635 .alias = "Haswell-noTSX-IBRS",
2636 .props = (PropValue[]) {
2637 { "hle", "off" },
2638 { "rtm", "off" },
2639 /* spec-ctrl was already enabled by -v3 above */
2640 { "stepping", "1" },
2641 { "model-id",
2642 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2643 { /* end of list */ }
2644 }
2645 },
2646 { /* end of list */ }
2647 }
2648 },
2649 {
2650 .name = "Broadwell",
2651 .level = 0xd,
2652 .vendor = CPUID_VENDOR_INTEL,
2653 .family = 6,
2654 .model = 61,
2655 .stepping = 2,
2656 .features[FEAT_1_EDX] =
2657 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2658 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2659 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2660 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2661 CPUID_DE | CPUID_FP87,
2662 .features[FEAT_1_ECX] =
2663 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2664 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2665 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2666 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2667 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2668 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2669 .features[FEAT_8000_0001_EDX] =
2670 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2671 CPUID_EXT2_SYSCALL,
2672 .features[FEAT_8000_0001_ECX] =
2673 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2674 .features[FEAT_7_0_EBX] =
2675 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2676 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2677 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2678 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2679 CPUID_7_0_EBX_SMAP,
2680 .features[FEAT_XSAVE] =
2681 CPUID_XSAVE_XSAVEOPT,
2682 .features[FEAT_6_EAX] =
2683 CPUID_6_EAX_ARAT,
2684 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2685 MSR_VMX_BASIC_TRUE_CTLS,
2686 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2687 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2688 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2689 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2690 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2691 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2692 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2693 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2694 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2695 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2696 .features[FEAT_VMX_EXIT_CTLS] =
2697 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2698 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2699 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2700 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2701 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2702 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2703 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2704 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2705 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2706 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2707 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2708 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2709 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2710 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2711 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2712 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2713 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2714 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2715 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2716 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2717 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2718 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2719 .features[FEAT_VMX_SECONDARY_CTLS] =
2720 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2721 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2722 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2723 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2724 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2725 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2726 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2727 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2728 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2729 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2730 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2731 .xlevel = 0x80000008,
2732 .model_id = "Intel Core Processor (Broadwell)",
2733 .versions = (X86CPUVersionDefinition[]) {
2734 { .version = 1 },
2735 {
2736 .version = 2,
2737 .alias = "Broadwell-noTSX",
2738 .props = (PropValue[]) {
2739 { "hle", "off" },
2740 { "rtm", "off" },
2741 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2742 { /* end of list */ }
2743 },
2744 },
2745 {
2746 .version = 3,
2747 .alias = "Broadwell-IBRS",
2748 .props = (PropValue[]) {
2749 /* Restore TSX features removed by -v2 above */
2750 { "hle", "on" },
2751 { "rtm", "on" },
2752 { "spec-ctrl", "on" },
2753 { "model-id",
2754 "Intel Core Processor (Broadwell, IBRS)" },
2755 { /* end of list */ }
2756 }
2757 },
2758 {
2759 .version = 4,
2760 .alias = "Broadwell-noTSX-IBRS",
2761 .props = (PropValue[]) {
2762 { "hle", "off" },
2763 { "rtm", "off" },
2764 /* spec-ctrl was already enabled by -v3 above */
2765 { "model-id",
2766 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2767 { /* end of list */ }
2768 }
2769 },
2770 { /* end of list */ }
2771 }
2772 },
2773 {
2774 .name = "Skylake-Client",
2775 .level = 0xd,
2776 .vendor = CPUID_VENDOR_INTEL,
2777 .family = 6,
2778 .model = 94,
2779 .stepping = 3,
2780 .features[FEAT_1_EDX] =
2781 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2782 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2783 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2784 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2785 CPUID_DE | CPUID_FP87,
2786 .features[FEAT_1_ECX] =
2787 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2788 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2789 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2790 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2791 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2792 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2793 .features[FEAT_8000_0001_EDX] =
2794 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2795 CPUID_EXT2_SYSCALL,
2796 .features[FEAT_8000_0001_ECX] =
2797 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2798 .features[FEAT_7_0_EBX] =
2799 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2800 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2801 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2802 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2803 CPUID_7_0_EBX_SMAP,
2804 /* Missing: XSAVES (not supported by some Linux versions,
2805 * including v4.1 to v4.12).
2806 * KVM doesn't yet expose any XSAVES state save component,
2807 * and the only one defined in Skylake (processor tracing)
2808 * probably will block migration anyway.
2809 */
2810 .features[FEAT_XSAVE] =
2811 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2812 CPUID_XSAVE_XGETBV1,
2813 .features[FEAT_6_EAX] =
2814 CPUID_6_EAX_ARAT,
2815 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2816 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2817 MSR_VMX_BASIC_TRUE_CTLS,
2818 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2819 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2820 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2821 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2822 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2823 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2824 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2825 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2826 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2827 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2828 .features[FEAT_VMX_EXIT_CTLS] =
2829 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2830 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2831 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2832 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2833 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2834 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2835 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2836 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2837 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2838 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2839 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2840 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2841 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2842 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2843 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2844 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2845 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2846 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2847 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2848 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2849 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2850 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2851 .features[FEAT_VMX_SECONDARY_CTLS] =
2852 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2853 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2854 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2855 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2856 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2857 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2858 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2859 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2860 .xlevel = 0x80000008,
2861 .model_id = "Intel Core Processor (Skylake)",
2862 .versions = (X86CPUVersionDefinition[]) {
2863 { .version = 1 },
2864 {
2865 .version = 2,
2866 .alias = "Skylake-Client-IBRS",
2867 .props = (PropValue[]) {
2868 { "spec-ctrl", "on" },
2869 { "model-id",
2870 "Intel Core Processor (Skylake, IBRS)" },
2871 { /* end of list */ }
2872 }
2873 },
2874 {
2875 .version = 3,
2876 .alias = "Skylake-Client-noTSX-IBRS",
2877 .props = (PropValue[]) {
2878 { "hle", "off" },
2879 { "rtm", "off" },
2880 { "model-id",
2881 "Intel Core Processor (Skylake, IBRS, no TSX)" },
2882 { /* end of list */ }
2883 }
2884 },
2885 { /* end of list */ }
2886 }
2887 },
2888 {
2889 .name = "Skylake-Server",
2890 .level = 0xd,
2891 .vendor = CPUID_VENDOR_INTEL,
2892 .family = 6,
2893 .model = 85,
2894 .stepping = 4,
2895 .features[FEAT_1_EDX] =
2896 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2897 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2898 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2899 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2900 CPUID_DE | CPUID_FP87,
2901 .features[FEAT_1_ECX] =
2902 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2903 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2904 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2905 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2906 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2907 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2908 .features[FEAT_8000_0001_EDX] =
2909 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2910 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2911 .features[FEAT_8000_0001_ECX] =
2912 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2913 .features[FEAT_7_0_EBX] =
2914 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2915 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2916 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2917 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2918 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2919 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2920 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2921 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2922 .features[FEAT_7_0_ECX] =
2923 CPUID_7_0_ECX_PKU,
2924 /* Missing: XSAVES (not supported by some Linux versions,
2925 * including v4.1 to v4.12).
2926 * KVM doesn't yet expose any XSAVES state save component,
2927 * and the only one defined in Skylake (processor tracing)
2928 * probably will block migration anyway.
2929 */
2930 .features[FEAT_XSAVE] =
2931 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2932 CPUID_XSAVE_XGETBV1,
2933 .features[FEAT_6_EAX] =
2934 CPUID_6_EAX_ARAT,
2935 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2936 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2937 MSR_VMX_BASIC_TRUE_CTLS,
2938 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2939 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2940 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2941 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2942 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2943 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2944 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2945 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2946 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2947 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2948 .features[FEAT_VMX_EXIT_CTLS] =
2949 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2950 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2951 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2952 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2953 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2954 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2955 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2956 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2957 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2958 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2959 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2960 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2961 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2962 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2963 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2964 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2965 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2966 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2967 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2968 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2969 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2970 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2971 .features[FEAT_VMX_SECONDARY_CTLS] =
2972 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2973 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2974 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2975 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2976 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2977 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2978 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2979 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2980 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2981 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2982 .xlevel = 0x80000008,
2983 .model_id = "Intel Xeon Processor (Skylake)",
2984 .versions = (X86CPUVersionDefinition[]) {
2985 { .version = 1 },
2986 {
2987 .version = 2,
2988 .alias = "Skylake-Server-IBRS",
2989 .props = (PropValue[]) {
2990 /* clflushopt was not added to Skylake-Server-IBRS */
2991 /* TODO: add -v3 including clflushopt */
2992 { "clflushopt", "off" },
2993 { "spec-ctrl", "on" },
2994 { "model-id",
2995 "Intel Xeon Processor (Skylake, IBRS)" },
2996 { /* end of list */ }
2997 }
2998 },
2999 {
3000 .version = 3,
3001 .alias = "Skylake-Server-noTSX-IBRS",
3002 .props = (PropValue[]) {
3003 { "hle", "off" },
3004 { "rtm", "off" },
3005 { "model-id",
3006 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3007 { /* end of list */ }
3008 }
3009 },
3010 {
3011 .version = 4,
3012 .props = (PropValue[]) {
3013 { "vmx-eptp-switching", "on" },
3014 { /* end of list */ }
3015 }
3016 },
3017 { /* end of list */ }
3018 }
3019 },
3020 {
3021 .name = "Cascadelake-Server",
3022 .level = 0xd,
3023 .vendor = CPUID_VENDOR_INTEL,
3024 .family = 6,
3025 .model = 85,
3026 .stepping = 6,
3027 .features[FEAT_1_EDX] =
3028 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3029 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3030 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3031 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3032 CPUID_DE | CPUID_FP87,
3033 .features[FEAT_1_ECX] =
3034 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3035 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3036 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3037 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3038 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3039 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3040 .features[FEAT_8000_0001_EDX] =
3041 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3042 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3043 .features[FEAT_8000_0001_ECX] =
3044 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3045 .features[FEAT_7_0_EBX] =
3046 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3047 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3048 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3049 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3050 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3051 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3052 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3053 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3054 .features[FEAT_7_0_ECX] =
3055 CPUID_7_0_ECX_PKU |
3056 CPUID_7_0_ECX_AVX512VNNI,
3057 .features[FEAT_7_0_EDX] =
3058 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3059 /* Missing: XSAVES (not supported by some Linux versions,
3060 * including v4.1 to v4.12).
3061 * KVM doesn't yet expose any XSAVES state save component,
3062 * and the only one defined in Skylake (processor tracing)
3063 * probably will block migration anyway.
3064 */
3065 .features[FEAT_XSAVE] =
3066 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3067 CPUID_XSAVE_XGETBV1,
3068 .features[FEAT_6_EAX] =
3069 CPUID_6_EAX_ARAT,
3070 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3071 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3072 MSR_VMX_BASIC_TRUE_CTLS,
3073 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3074 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3075 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3076 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3077 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3078 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3079 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3080 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3081 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3082 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3083 .features[FEAT_VMX_EXIT_CTLS] =
3084 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3085 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3086 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3087 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3088 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3089 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3090 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3091 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3092 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3093 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3094 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3095 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3096 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3097 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3098 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3099 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3100 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3101 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3102 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3103 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3104 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3105 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3106 .features[FEAT_VMX_SECONDARY_CTLS] =
3107 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3108 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3109 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3110 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3111 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3112 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3113 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3114 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3115 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3116 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3117 .xlevel = 0x80000008,
3118 .model_id = "Intel Xeon Processor (Cascadelake)",
3119 .versions = (X86CPUVersionDefinition[]) {
3120 { .version = 1 },
3121 { .version = 2,
3122 .note = "ARCH_CAPABILITIES",
3123 .props = (PropValue[]) {
3124 { "arch-capabilities", "on" },
3125 { "rdctl-no", "on" },
3126 { "ibrs-all", "on" },
3127 { "skip-l1dfl-vmentry", "on" },
3128 { "mds-no", "on" },
3129 { /* end of list */ }
3130 },
3131 },
3132 { .version = 3,
3133 .alias = "Cascadelake-Server-noTSX",
3134 .note = "ARCH_CAPABILITIES, no TSX",
3135 .props = (PropValue[]) {
3136 { "hle", "off" },
3137 { "rtm", "off" },
3138 { /* end of list */ }
3139 },
3140 },
3141 { .version = 4,
3142 .note = "ARCH_CAPABILITIES, no TSX",
3143 .props = (PropValue[]) {
3144 { "vmx-eptp-switching", "on" },
3145 { /* end of list */ }
3146 },
3147 },
3148 { /* end of list */ }
3149 }
3150 },
3151 {
3152 .name = "Cooperlake",
3153 .level = 0xd,
3154 .vendor = CPUID_VENDOR_INTEL,
3155 .family = 6,
3156 .model = 85,
3157 .stepping = 10,
3158 .features[FEAT_1_EDX] =
3159 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3160 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3161 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3162 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3163 CPUID_DE | CPUID_FP87,
3164 .features[FEAT_1_ECX] =
3165 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3166 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3167 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3168 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3169 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3170 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3171 .features[FEAT_8000_0001_EDX] =
3172 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3173 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3174 .features[FEAT_8000_0001_ECX] =
3175 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3176 .features[FEAT_7_0_EBX] =
3177 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3178 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3179 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3180 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3181 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3182 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3183 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3184 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3185 .features[FEAT_7_0_ECX] =
3186 CPUID_7_0_ECX_PKU |
3187 CPUID_7_0_ECX_AVX512VNNI,
3188 .features[FEAT_7_0_EDX] =
3189 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3190 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3191 .features[FEAT_ARCH_CAPABILITIES] =
3192 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3193 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3194 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3195 .features[FEAT_7_1_EAX] =
3196 CPUID_7_1_EAX_AVX512_BF16,
3197 /*
3198 * Missing: XSAVES (not supported by some Linux versions,
3199 * including v4.1 to v4.12).
3200 * KVM doesn't yet expose any XSAVES state save component,
3201 * and the only one defined in Skylake (processor tracing)
3202 * probably will block migration anyway.
3203 */
3204 .features[FEAT_XSAVE] =
3205 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3206 CPUID_XSAVE_XGETBV1,
3207 .features[FEAT_6_EAX] =
3208 CPUID_6_EAX_ARAT,
3209 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3210 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3211 MSR_VMX_BASIC_TRUE_CTLS,
3212 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3213 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3214 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3215 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3216 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3217 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3218 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3219 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3220 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3221 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3222 .features[FEAT_VMX_EXIT_CTLS] =
3223 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3224 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3225 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3226 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3227 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3228 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3229 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3230 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3231 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3232 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3233 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3234 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3235 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3236 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3237 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3238 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3239 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3240 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3241 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3242 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3243 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3244 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3245 .features[FEAT_VMX_SECONDARY_CTLS] =
3246 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3247 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3248 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3249 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3250 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3251 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3252 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3253 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3254 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3255 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3256 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3257 .xlevel = 0x80000008,
3258 .model_id = "Intel Xeon Processor (Cooperlake)",
3259 },
3260 {
3261 .name = "Icelake-Client",
3262 .level = 0xd,
3263 .vendor = CPUID_VENDOR_INTEL,
3264 .family = 6,
3265 .model = 126,
3266 .stepping = 0,
3267 .features[FEAT_1_EDX] =
3268 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3269 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3270 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3271 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3272 CPUID_DE | CPUID_FP87,
3273 .features[FEAT_1_ECX] =
3274 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3275 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3276 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3277 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3278 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3279 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3280 .features[FEAT_8000_0001_EDX] =
3281 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3282 CPUID_EXT2_SYSCALL,
3283 .features[FEAT_8000_0001_ECX] =
3284 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3285 .features[FEAT_8000_0008_EBX] =
3286 CPUID_8000_0008_EBX_WBNOINVD,
3287 .features[FEAT_7_0_EBX] =
3288 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3289 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3290 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3291 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3292 CPUID_7_0_EBX_SMAP,
3293 .features[FEAT_7_0_ECX] =
3294 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3295 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3296 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3297 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3298 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3299 .features[FEAT_7_0_EDX] =
3300 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3301 /* Missing: XSAVES (not supported by some Linux versions,
3302 * including v4.1 to v4.12).
3303 * KVM doesn't yet expose any XSAVES state save component,
3304 * and the only one defined in Skylake (processor tracing)
3305 * probably will block migration anyway.
3306 */
3307 .features[FEAT_XSAVE] =
3308 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3309 CPUID_XSAVE_XGETBV1,
3310 .features[FEAT_6_EAX] =
3311 CPUID_6_EAX_ARAT,
3312 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3313 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3314 MSR_VMX_BASIC_TRUE_CTLS,
3315 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3316 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3317 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3318 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3319 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3320 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3321 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3322 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3323 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3324 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3325 .features[FEAT_VMX_EXIT_CTLS] =
3326 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3327 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3328 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3329 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3330 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3331 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3332 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3333 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3334 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3335 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3336 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3337 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3338 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3339 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3340 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3341 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3342 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3343 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3344 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3345 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3346 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3347 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3348 .features[FEAT_VMX_SECONDARY_CTLS] =
3349 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3350 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3351 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3352 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3353 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3354 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3355 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3356 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3357 .xlevel = 0x80000008,
3358 .model_id = "Intel Core Processor (Icelake)",
3359 .versions = (X86CPUVersionDefinition[]) {
3360 { .version = 1 },
3361 {
3362 .version = 2,
3363 .note = "no TSX",
3364 .alias = "Icelake-Client-noTSX",
3365 .props = (PropValue[]) {
3366 { "hle", "off" },
3367 { "rtm", "off" },
3368 { /* end of list */ }
3369 },
3370 },
3371 { /* end of list */ }
3372 }
3373 },
3374 {
3375 .name = "Icelake-Server",
3376 .level = 0xd,
3377 .vendor = CPUID_VENDOR_INTEL,
3378 .family = 6,
3379 .model = 134,
3380 .stepping = 0,
3381 .features[FEAT_1_EDX] =
3382 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3383 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3384 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3385 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3386 CPUID_DE | CPUID_FP87,
3387 .features[FEAT_1_ECX] =
3388 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3389 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3390 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3391 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3392 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3393 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3394 .features[FEAT_8000_0001_EDX] =
3395 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3396 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3397 .features[FEAT_8000_0001_ECX] =
3398 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3399 .features[FEAT_8000_0008_EBX] =
3400 CPUID_8000_0008_EBX_WBNOINVD,
3401 .features[FEAT_7_0_EBX] =
3402 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3403 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3404 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3405 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3406 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3407 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3408 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3409 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3410 .features[FEAT_7_0_ECX] =
3411 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3412 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3413 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3414 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3415 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3416 .features[FEAT_7_0_EDX] =
3417 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3418 /* Missing: XSAVES (not supported by some Linux versions,
3419 * including v4.1 to v4.12).
3420 * KVM doesn't yet expose any XSAVES state save component,
3421 * and the only one defined in Skylake (processor tracing)
3422 * probably will block migration anyway.
3423 */
3424 .features[FEAT_XSAVE] =
3425 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3426 CPUID_XSAVE_XGETBV1,
3427 .features[FEAT_6_EAX] =
3428 CPUID_6_EAX_ARAT,
3429 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3430 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3431 MSR_VMX_BASIC_TRUE_CTLS,
3432 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3433 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3434 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3435 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3436 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3437 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3438 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3439 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3440 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3441 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3442 .features[FEAT_VMX_EXIT_CTLS] =
3443 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3444 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3445 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3446 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3447 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3448 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3449 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3450 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3451 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3452 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3453 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3454 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3455 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3456 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3457 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3458 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3459 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3460 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3461 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3462 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3463 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3464 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3465 .features[FEAT_VMX_SECONDARY_CTLS] =
3466 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3467 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3468 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3469 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3470 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3471 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3472 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3473 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3474 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
3475 .xlevel = 0x80000008,
3476 .model_id = "Intel Xeon Processor (Icelake)",
3477 .versions = (X86CPUVersionDefinition[]) {
3478 { .version = 1 },
3479 {
3480 .version = 2,
3481 .note = "no TSX",
3482 .alias = "Icelake-Server-noTSX",
3483 .props = (PropValue[]) {
3484 { "hle", "off" },
3485 { "rtm", "off" },
3486 { /* end of list */ }
3487 },
3488 },
3489 {
3490 .version = 3,
3491 .props = (PropValue[]) {
3492 { "arch-capabilities", "on" },
3493 { "rdctl-no", "on" },
3494 { "ibrs-all", "on" },
3495 { "skip-l1dfl-vmentry", "on" },
3496 { "mds-no", "on" },
3497 { "pschange-mc-no", "on" },
3498 { "taa-no", "on" },
3499 { /* end of list */ }
3500 },
3501 },
3502 {
3503 .version = 4,
3504 .props = (PropValue[]) {
3505 { "sha-ni", "on" },
3506 { "avx512ifma", "on" },
3507 { "rdpid", "on" },
3508 { "fsrm", "on" },
3509 { "vmx-rdseed-exit", "on" },
3510 { "vmx-pml", "on" },
3511 { "vmx-eptp-switching", "on" },
3512 { "model", "106" },
3513 { /* end of list */ }
3514 },
3515 },
3516 { /* end of list */ }
3517 }
3518 },
3519 {
3520 .name = "Denverton",
3521 .level = 21,
3522 .vendor = CPUID_VENDOR_INTEL,
3523 .family = 6,
3524 .model = 95,
3525 .stepping = 1,
3526 .features[FEAT_1_EDX] =
3527 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3528 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3529 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3530 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3531 CPUID_SSE | CPUID_SSE2,
3532 .features[FEAT_1_ECX] =
3533 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3534 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3535 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3536 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3537 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3538 .features[FEAT_8000_0001_EDX] =
3539 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3540 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3541 .features[FEAT_8000_0001_ECX] =
3542 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3543 .features[FEAT_7_0_EBX] =
3544 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3545 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3546 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3547 .features[FEAT_7_0_EDX] =
3548 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3549 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3550 /*
3551 * Missing: XSAVES (not supported by some Linux versions,
3552 * including v4.1 to v4.12).
3553 * KVM doesn't yet expose any XSAVES state save component,
3554 * and the only one defined in Skylake (processor tracing)
3555 * probably will block migration anyway.
3556 */
3557 .features[FEAT_XSAVE] =
3558 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3559 .features[FEAT_6_EAX] =
3560 CPUID_6_EAX_ARAT,
3561 .features[FEAT_ARCH_CAPABILITIES] =
3562 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
3563 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3564 MSR_VMX_BASIC_TRUE_CTLS,
3565 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3566 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3567 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3568 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3569 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3570 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3571 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3572 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3573 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3574 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3575 .features[FEAT_VMX_EXIT_CTLS] =
3576 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3577 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3578 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3579 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3580 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3581 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3582 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3583 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3584 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3585 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3586 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3587 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3588 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3589 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3590 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3591 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3592 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3593 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3594 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3595 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3596 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3597 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3598 .features[FEAT_VMX_SECONDARY_CTLS] =
3599 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3600 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3601 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3602 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3603 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3604 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3605 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3606 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3607 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3608 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3609 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3610 .xlevel = 0x80000008,
3611 .model_id = "Intel Atom Processor (Denverton)",
3612 .versions = (X86CPUVersionDefinition[]) {
3613 { .version = 1 },
3614 {
3615 .version = 2,
3616 .note = "no MPX, no MONITOR",
3617 .props = (PropValue[]) {
3618 { "monitor", "off" },
3619 { "mpx", "off" },
3620 { /* end of list */ },
3621 },
3622 },
3623 { /* end of list */ },
3624 },
3625 },
3626 {
3627 .name = "Snowridge",
3628 .level = 27,
3629 .vendor = CPUID_VENDOR_INTEL,
3630 .family = 6,
3631 .model = 134,
3632 .stepping = 1,
3633 .features[FEAT_1_EDX] =
3634 /* missing: CPUID_PN CPUID_IA64 */
3635 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3636 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3637 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3638 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3639 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3640 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3641 CPUID_MMX |
3642 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3643 .features[FEAT_1_ECX] =
3644 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3645 CPUID_EXT_SSSE3 |
3646 CPUID_EXT_CX16 |
3647 CPUID_EXT_SSE41 |
3648 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3649 CPUID_EXT_POPCNT |
3650 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3651 CPUID_EXT_RDRAND,
3652 .features[FEAT_8000_0001_EDX] =
3653 CPUID_EXT2_SYSCALL |
3654 CPUID_EXT2_NX |
3655 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3656 CPUID_EXT2_LM,
3657 .features[FEAT_8000_0001_ECX] =
3658 CPUID_EXT3_LAHF_LM |
3659 CPUID_EXT3_3DNOWPREFETCH,
3660 .features[FEAT_7_0_EBX] =
3661 CPUID_7_0_EBX_FSGSBASE |
3662 CPUID_7_0_EBX_SMEP |
3663 CPUID_7_0_EBX_ERMS |
3664 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3665 CPUID_7_0_EBX_RDSEED |
3666 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3667 CPUID_7_0_EBX_CLWB |
3668 CPUID_7_0_EBX_SHA_NI,
3669 .features[FEAT_7_0_ECX] =
3670 CPUID_7_0_ECX_UMIP |
3671 /* missing bit 5 */
3672 CPUID_7_0_ECX_GFNI |
3673 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3674 CPUID_7_0_ECX_MOVDIR64B,
3675 .features[FEAT_7_0_EDX] =
3676 CPUID_7_0_EDX_SPEC_CTRL |
3677 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3678 CPUID_7_0_EDX_CORE_CAPABILITY,
3679 .features[FEAT_CORE_CAPABILITY] =
3680 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
3681 /*
3682 * Missing: XSAVES (not supported by some Linux versions,
3683 * including v4.1 to v4.12).
3684 * KVM doesn't yet expose any XSAVES state save component,
3685 * and the only one defined in Skylake (processor tracing)
3686 * probably will block migration anyway.
3687 */
3688 .features[FEAT_XSAVE] =
3689 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3690 CPUID_XSAVE_XGETBV1,
3691 .features[FEAT_6_EAX] =
3692 CPUID_6_EAX_ARAT,
3693 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3694 MSR_VMX_BASIC_TRUE_CTLS,
3695 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3696 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3697 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3698 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3699 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3700 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3701 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3702 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3703 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3704 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3705 .features[FEAT_VMX_EXIT_CTLS] =
3706 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3707 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3708 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3709 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3710 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3711 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3712 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3713 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3714 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3715 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3716 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3717 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3718 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3719 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3720 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3721 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3722 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3723 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3724 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3725 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3726 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3727 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3728 .features[FEAT_VMX_SECONDARY_CTLS] =
3729 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3730 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3731 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3732 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3733 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3734 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3735 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3736 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3737 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3738 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3739 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3740 .xlevel = 0x80000008,
3741 .model_id = "Intel Atom Processor (SnowRidge)",
3742 .versions = (X86CPUVersionDefinition[]) {
3743 { .version = 1 },
3744 {
3745 .version = 2,
3746 .props = (PropValue[]) {
3747 { "mpx", "off" },
3748 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3749 { /* end of list */ },
3750 },
3751 },
3752 { /* end of list */ },
3753 },
3754 },
3755 {
3756 .name = "KnightsMill",
3757 .level = 0xd,
3758 .vendor = CPUID_VENDOR_INTEL,
3759 .family = 6,
3760 .model = 133,
3761 .stepping = 0,
3762 .features[FEAT_1_EDX] =
3763 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3764 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3765 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3766 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3767 CPUID_PSE | CPUID_DE | CPUID_FP87,
3768 .features[FEAT_1_ECX] =
3769 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3770 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3771 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3772 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3773 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3774 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3775 .features[FEAT_8000_0001_EDX] =
3776 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3777 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3778 .features[FEAT_8000_0001_ECX] =
3779 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3780 .features[FEAT_7_0_EBX] =
3781 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3782 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3783 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3784 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3785 CPUID_7_0_EBX_AVX512ER,
3786 .features[FEAT_7_0_ECX] =
3787 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3788 .features[FEAT_7_0_EDX] =
3789 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3790 .features[FEAT_XSAVE] =
3791 CPUID_XSAVE_XSAVEOPT,
3792 .features[FEAT_6_EAX] =
3793 CPUID_6_EAX_ARAT,
3794 .xlevel = 0x80000008,
3795 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3796 },
3797 {
3798 .name = "Opteron_G1",
3799 .level = 5,
3800 .vendor = CPUID_VENDOR_AMD,
3801 .family = 15,
3802 .model = 6,
3803 .stepping = 1,
3804 .features[FEAT_1_EDX] =
3805 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3806 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3807 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3808 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3809 CPUID_DE | CPUID_FP87,
3810 .features[FEAT_1_ECX] =
3811 CPUID_EXT_SSE3,
3812 .features[FEAT_8000_0001_EDX] =
3813 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3814 .xlevel = 0x80000008,
3815 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3816 },
3817 {
3818 .name = "Opteron_G2",
3819 .level = 5,
3820 .vendor = CPUID_VENDOR_AMD,
3821 .family = 15,
3822 .model = 6,
3823 .stepping = 1,
3824 .features[FEAT_1_EDX] =
3825 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3826 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3827 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3828 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3829 CPUID_DE | CPUID_FP87,
3830 .features[FEAT_1_ECX] =
3831 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
3832 .features[FEAT_8000_0001_EDX] =
3833 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3834 .features[FEAT_8000_0001_ECX] =
3835 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3836 .xlevel = 0x80000008,
3837 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3838 },
3839 {
3840 .name = "Opteron_G3",
3841 .level = 5,
3842 .vendor = CPUID_VENDOR_AMD,
3843 .family = 16,
3844 .model = 2,
3845 .stepping = 3,
3846 .features[FEAT_1_EDX] =
3847 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3848 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3849 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3850 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3851 CPUID_DE | CPUID_FP87,
3852 .features[FEAT_1_ECX] =
3853 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3854 CPUID_EXT_SSE3,
3855 .features[FEAT_8000_0001_EDX] =
3856 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3857 CPUID_EXT2_RDTSCP,
3858 .features[FEAT_8000_0001_ECX] =
3859 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3860 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3861 .xlevel = 0x80000008,
3862 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3863 },
3864 {
3865 .name = "Opteron_G4",
3866 .level = 0xd,
3867 .vendor = CPUID_VENDOR_AMD,
3868 .family = 21,
3869 .model = 1,
3870 .stepping = 2,
3871 .features[FEAT_1_EDX] =
3872 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3873 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3874 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3875 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3876 CPUID_DE | CPUID_FP87,
3877 .features[FEAT_1_ECX] =
3878 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3879 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3880 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3881 CPUID_EXT_SSE3,
3882 .features[FEAT_8000_0001_EDX] =
3883 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3884 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3885 .features[FEAT_8000_0001_ECX] =
3886 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3887 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3888 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3889 CPUID_EXT3_LAHF_LM,
3890 .features[FEAT_SVM] =
3891 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3892 /* no xsaveopt! */
3893 .xlevel = 0x8000001A,
3894 .model_id = "AMD Opteron 62xx class CPU",
3895 },
3896 {
3897 .name = "Opteron_G5",
3898 .level = 0xd,
3899 .vendor = CPUID_VENDOR_AMD,
3900 .family = 21,
3901 .model = 2,
3902 .stepping = 0,
3903 .features[FEAT_1_EDX] =
3904 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3905 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3906 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3907 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3908 CPUID_DE | CPUID_FP87,
3909 .features[FEAT_1_ECX] =
3910 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
3911 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3912 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3913 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3914 .features[FEAT_8000_0001_EDX] =
3915 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3916 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3917 .features[FEAT_8000_0001_ECX] =
3918 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3919 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3920 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3921 CPUID_EXT3_LAHF_LM,
3922 .features[FEAT_SVM] =
3923 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3924 /* no xsaveopt! */
3925 .xlevel = 0x8000001A,
3926 .model_id = "AMD Opteron 63xx class CPU",
3927 },
3928 {
3929 .name = "EPYC",
3930 .level = 0xd,
3931 .vendor = CPUID_VENDOR_AMD,
3932 .family = 23,
3933 .model = 1,
3934 .stepping = 2,
3935 .features[FEAT_1_EDX] =
3936 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3937 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3938 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3939 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3940 CPUID_VME | CPUID_FP87,
3941 .features[FEAT_1_ECX] =
3942 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3943 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3944 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3945 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3946 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3947 .features[FEAT_8000_0001_EDX] =
3948 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3949 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3950 CPUID_EXT2_SYSCALL,
3951 .features[FEAT_8000_0001_ECX] =
3952 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3953 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3954 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3955 CPUID_EXT3_TOPOEXT,
3956 .features[FEAT_7_0_EBX] =
3957 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3958 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3959 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3960 CPUID_7_0_EBX_SHA_NI,
3961 .features[FEAT_XSAVE] =
3962 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3963 CPUID_XSAVE_XGETBV1,
3964 .features[FEAT_6_EAX] =
3965 CPUID_6_EAX_ARAT,
3966 .features[FEAT_SVM] =
3967 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3968 .xlevel = 0x8000001E,
3969 .model_id = "AMD EPYC Processor",
3970 .cache_info = &epyc_cache_info,
3971 .versions = (X86CPUVersionDefinition[]) {
3972 { .version = 1 },
3973 {
3974 .version = 2,
3975 .alias = "EPYC-IBPB",
3976 .props = (PropValue[]) {
3977 { "ibpb", "on" },
3978 { "model-id",
3979 "AMD EPYC Processor (with IBPB)" },
3980 { /* end of list */ }
3981 }
3982 },
3983 {
3984 .version = 3,
3985 .props = (PropValue[]) {
3986 { "ibpb", "on" },
3987 { "perfctr-core", "on" },
3988 { "clzero", "on" },
3989 { "xsaveerptr", "on" },
3990 { "xsaves", "on" },
3991 { "model-id",
3992 "AMD EPYC Processor" },
3993 { /* end of list */ }
3994 }
3995 },
3996 { /* end of list */ }
3997 }
3998 },
3999 {
4000 .name = "Dhyana",
4001 .level = 0xd,
4002 .vendor = CPUID_VENDOR_HYGON,
4003 .family = 24,
4004 .model = 0,
4005 .stepping = 1,
4006 .features[FEAT_1_EDX] =
4007 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4008 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4009 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4010 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4011 CPUID_VME | CPUID_FP87,
4012 .features[FEAT_1_ECX] =
4013 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4014 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4015 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4016 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4017 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4018 .features[FEAT_8000_0001_EDX] =
4019 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4020 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4021 CPUID_EXT2_SYSCALL,
4022 .features[FEAT_8000_0001_ECX] =
4023 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4024 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4025 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4026 CPUID_EXT3_TOPOEXT,
4027 .features[FEAT_8000_0008_EBX] =
4028 CPUID_8000_0008_EBX_IBPB,
4029 .features[FEAT_7_0_EBX] =
4030 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4031 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4032 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
4033 /*
4034 * Missing: XSAVES (not supported by some Linux versions,
4035 * including v4.1 to v4.12).
4036 * KVM doesn't yet expose any XSAVES state save component.
4037 */
4038 .features[FEAT_XSAVE] =
4039 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4040 CPUID_XSAVE_XGETBV1,
4041 .features[FEAT_6_EAX] =
4042 CPUID_6_EAX_ARAT,
4043 .features[FEAT_SVM] =
4044 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4045 .xlevel = 0x8000001E,
4046 .model_id = "Hygon Dhyana Processor",
4047 .cache_info = &epyc_cache_info,
4048 },
4049 {
4050 .name = "EPYC-Rome",
4051 .level = 0xd,
4052 .vendor = CPUID_VENDOR_AMD,
4053 .family = 23,
4054 .model = 49,
4055 .stepping = 0,
4056 .features[FEAT_1_EDX] =
4057 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4058 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4059 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4060 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4061 CPUID_VME | CPUID_FP87,
4062 .features[FEAT_1_ECX] =
4063 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4064 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4065 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4066 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4067 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4068 .features[FEAT_8000_0001_EDX] =
4069 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4070 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4071 CPUID_EXT2_SYSCALL,
4072 .features[FEAT_8000_0001_ECX] =
4073 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4074 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4075 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4076 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4077 .features[FEAT_8000_0008_EBX] =
4078 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4079 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4080 CPUID_8000_0008_EBX_STIBP,
4081 .features[FEAT_7_0_EBX] =
4082 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4083 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4084 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4085 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4086 .features[FEAT_7_0_ECX] =
4087 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4088 .features[FEAT_XSAVE] =
4089 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4090 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4091 .features[FEAT_6_EAX] =
4092 CPUID_6_EAX_ARAT,
4093 .features[FEAT_SVM] =
4094 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4095 .xlevel = 0x8000001E,
4096 .model_id = "AMD EPYC-Rome Processor",
4097 .cache_info = &epyc_rome_cache_info,
4098 },
4099 };
4100
4101 /* KVM-specific features that are automatically added/removed
4102 * from all CPU models when KVM is enabled.
4103 */
4104 static PropValue kvm_default_props[] = {
4105 { "kvmclock", "on" },
4106 { "kvm-nopiodelay", "on" },
4107 { "kvm-asyncpf", "on" },
4108 { "kvm-steal-time", "on" },
4109 { "kvm-pv-eoi", "on" },
4110 { "kvmclock-stable-bit", "on" },
4111 { "x2apic", "on" },
4112 { "acpi", "off" },
4113 { "monitor", "off" },
4114 { "svm", "off" },
4115 { NULL, NULL },
4116 };
4117
4118 /* TCG-specific defaults that override all CPU models when using TCG
4119 */
4120 static PropValue tcg_default_props[] = {
4121 { "vme", "off" },
4122 { NULL, NULL },
4123 };
4124
4125
4126 /*
4127 * We resolve CPU model aliases using -v1 when using "-machine
4128 * none", but this is just for compatibility while libvirt isn't
4129 * adapted to resolve CPU model versions before creating VMs.
4130 * See "Runnability guarantee of CPU models" at
4131 * docs/system/deprecated.rst.
4132 */
4133 X86CPUVersion default_cpu_version = 1;
4134
4135 void x86_cpu_set_default_version(X86CPUVersion version)
4136 {
4137 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4138 assert(version != CPU_VERSION_AUTO);
4139 default_cpu_version = version;
4140 }
4141
4142 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4143 {
4144 int v = 0;
4145 const X86CPUVersionDefinition *vdef =
4146 x86_cpu_def_get_versions(model->cpudef);
4147 while (vdef->version) {
4148 v = vdef->version;
4149 vdef++;
4150 }
4151 return v;
4152 }
4153
4154 /* Return the actual version being used for a specific CPU model */
4155 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4156 {
4157 X86CPUVersion v = model->version;
4158 if (v == CPU_VERSION_AUTO) {
4159 v = default_cpu_version;
4160 }
4161 if (v == CPU_VERSION_LATEST) {
4162 return x86_cpu_model_last_version(model);
4163 }
4164 return v;
4165 }
4166
4167 void x86_cpu_change_kvm_default(const char *prop, const char *value)
4168 {
4169 PropValue *pv;
4170 for (pv = kvm_default_props; pv->prop; pv++) {
4171 if (!strcmp(pv->prop, prop)) {
4172 pv->value = value;
4173 break;
4174 }
4175 }
4176
4177 /* It is valid to call this function only for properties that
4178 * are already present in the kvm_default_props table.
4179 */
4180 assert(pv->prop);
4181 }
4182
4183 static bool lmce_supported(void)
4184 {
4185 uint64_t mce_cap = 0;
4186
4187 #ifdef CONFIG_KVM
4188 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
4189 return false;
4190 }
4191 #endif
4192
4193 return !!(mce_cap & MCG_LMCE_P);
4194 }
4195
4196 #define CPUID_MODEL_ID_SZ 48
4197
4198 /**
4199 * cpu_x86_fill_model_id:
4200 * Get CPUID model ID string from host CPU.
4201 *
4202 * @str should have at least CPUID_MODEL_ID_SZ bytes
4203 *
4204 * The function does NOT add a null terminator to the string
4205 * automatically.
4206 */
4207 static int cpu_x86_fill_model_id(char *str)
4208 {
4209 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
4210 int i;
4211
4212 for (i = 0; i < 3; i++) {
4213 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
4214 memcpy(str + i * 16 + 0, &eax, 4);
4215 memcpy(str + i * 16 + 4, &ebx, 4);
4216 memcpy(str + i * 16 + 8, &ecx, 4);
4217 memcpy(str + i * 16 + 12, &edx, 4);
4218 }
4219 return 0;
4220 }
4221
4222 static Property max_x86_cpu_properties[] = {
4223 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
4224 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
4225 DEFINE_PROP_END_OF_LIST()
4226 };
4227
4228 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
4229 {
4230 DeviceClass *dc = DEVICE_CLASS(oc);
4231 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4232
4233 xcc->ordering = 9;
4234
4235 xcc->model_description =
4236 "Enables all features supported by the accelerator in the current host";
4237
4238 device_class_set_props(dc, max_x86_cpu_properties);
4239 }
4240
4241 static void max_x86_cpu_initfn(Object *obj)
4242 {
4243 X86CPU *cpu = X86_CPU(obj);
4244 CPUX86State *env = &cpu->env;
4245 KVMState *s = kvm_state;
4246
4247 /* We can't fill the features array here because we don't know yet if
4248 * "migratable" is true or false.
4249 */
4250 cpu->max_features = true;
4251
4252 if (accel_uses_host_cpuid()) {
4253 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
4254 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
4255 int family, model, stepping;
4256
4257 host_vendor_fms(vendor, &family, &model, &stepping);
4258 cpu_x86_fill_model_id(model_id);
4259
4260 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
4261 object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
4262 object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
4263 object_property_set_int(OBJECT(cpu), "stepping", stepping,
4264 &error_abort);
4265 object_property_set_str(OBJECT(cpu), "model-id", model_id,
4266 &error_abort);
4267
4268 if (kvm_enabled()) {
4269 env->cpuid_min_level =
4270 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
4271 env->cpuid_min_xlevel =
4272 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
4273 env->cpuid_min_xlevel2 =
4274 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
4275 } else {
4276 env->cpuid_min_level =
4277 hvf_get_supported_cpuid(0x0, 0, R_EAX);
4278 env->cpuid_min_xlevel =
4279 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
4280 env->cpuid_min_xlevel2 =
4281 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
4282 }
4283
4284 if (lmce_supported()) {
4285 object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
4286 }
4287 } else {
4288 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4289 &error_abort);
4290 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4291 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4292 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
4293 object_property_set_str(OBJECT(cpu), "model-id",
4294 "QEMU TCG CPU version " QEMU_HW_VERSION,
4295 &error_abort);
4296 }
4297
4298 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
4299 }
4300
4301 static const TypeInfo max_x86_cpu_type_info = {
4302 .name = X86_CPU_TYPE_NAME("max"),
4303 .parent = TYPE_X86_CPU,
4304 .instance_init = max_x86_cpu_initfn,
4305 .class_init = max_x86_cpu_class_init,
4306 };
4307
4308 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
4309 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
4310 {
4311 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4312
4313 xcc->host_cpuid_required = true;
4314 xcc->ordering = 8;
4315
4316 #if defined(CONFIG_KVM)
4317 xcc->model_description =
4318 "KVM processor with all supported host features ";
4319 #elif defined(CONFIG_HVF)
4320 xcc->model_description =
4321 "HVF processor with all supported host features ";
4322 #endif
4323 }
4324
4325 static const TypeInfo host_x86_cpu_type_info = {
4326 .name = X86_CPU_TYPE_NAME("host"),
4327 .parent = X86_CPU_TYPE_NAME("max"),
4328 .class_init = host_x86_cpu_class_init,
4329 };
4330
4331 #endif
4332
4333 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4334 {
4335 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4336
4337 switch (f->type) {
4338 case CPUID_FEATURE_WORD:
4339 {
4340 const char *reg = get_register_name_32(f->cpuid.reg);
4341 assert(reg);
4342 return g_strdup_printf("CPUID.%02XH:%s",
4343 f->cpuid.eax, reg);
4344 }
4345 case MSR_FEATURE_WORD:
4346 return g_strdup_printf("MSR(%02XH)",
4347 f->msr.index);
4348 }
4349
4350 return NULL;
4351 }
4352
4353 static bool x86_cpu_have_filtered_features(X86CPU *cpu)
4354 {
4355 FeatureWord w;
4356
4357 for (w = 0; w < FEATURE_WORDS; w++) {
4358 if (cpu->filtered_features[w]) {
4359 return true;
4360 }
4361 }
4362
4363 return false;
4364 }
4365
4366 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
4367 const char *verbose_prefix)
4368 {
4369 CPUX86State *env = &cpu->env;
4370 FeatureWordInfo *f = &feature_word_info[w];
4371 int i;
4372
4373 if (!cpu->force_features) {
4374 env->features[w] &= ~mask;
4375 }
4376 cpu->filtered_features[w] |= mask;
4377
4378 if (!verbose_prefix) {
4379 return;
4380 }
4381
4382 for (i = 0; i < 64; ++i) {
4383 if ((1ULL << i) & mask) {
4384 g_autofree char *feat_word_str = feature_word_description(f, i);
4385 warn_report("%s: %s%s%s [bit %d]",
4386 verbose_prefix,
4387 feat_word_str,
4388 f->feat_names[i] ? "." : "",
4389 f->feat_names[i] ? f->feat_names[i] : "", i);
4390 }
4391 }
4392 }
4393
4394 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4395 const char *name, void *opaque,
4396 Error **errp)
4397 {
4398 X86CPU *cpu = X86_CPU(obj);
4399 CPUX86State *env = &cpu->env;
4400 int64_t value;
4401
4402 value = (env->cpuid_version >> 8) & 0xf;
4403 if (value == 0xf) {
4404 value += (env->cpuid_version >> 20) & 0xff;
4405 }
4406 visit_type_int(v, name, &value, errp);
4407 }
4408
4409 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4410 const char *name, void *opaque,
4411 Error **errp)
4412 {
4413 X86CPU *cpu = X86_CPU(obj);
4414 CPUX86State *env = &cpu->env;
4415 const int64_t min = 0;
4416 const int64_t max = 0xff + 0xf;
4417 int64_t value;
4418
4419 if (!visit_type_int(v, name, &value, errp)) {
4420 return;
4421 }
4422 if (value < min || value > max) {
4423 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4424 name ? name : "null", value, min, max);
4425 return;
4426 }
4427
4428 env->cpuid_version &= ~0xff00f00;
4429 if (value > 0x0f) {
4430 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
4431 } else {
4432 env->cpuid_version |= value << 8;
4433 }
4434 }
4435
4436 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4437 const char *name, void *opaque,
4438 Error **errp)
4439 {
4440 X86CPU *cpu = X86_CPU(obj);
4441 CPUX86State *env = &cpu->env;
4442 int64_t value;
4443
4444 value = (env->cpuid_version >> 4) & 0xf;
4445 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
4446 visit_type_int(v, name, &value, errp);
4447 }
4448
4449 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4450 const char *name, void *opaque,
4451 Error **errp)
4452 {
4453 X86CPU *cpu = X86_CPU(obj);
4454 CPUX86State *env = &cpu->env;
4455 const int64_t min = 0;
4456 const int64_t max = 0xff;
4457 int64_t value;
4458
4459 if (!visit_type_int(v, name, &value, errp)) {
4460 return;
4461 }
4462 if (value < min || value > max) {
4463 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4464 name ? name : "null", value, min, max);
4465 return;
4466 }
4467
4468 env->cpuid_version &= ~0xf00f0;
4469 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
4470 }
4471
4472 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
4473 const char *name, void *opaque,
4474 Error **errp)
4475 {
4476 X86CPU *cpu = X86_CPU(obj);
4477 CPUX86State *env = &cpu->env;
4478 int64_t value;
4479
4480 value = env->cpuid_version & 0xf;
4481 visit_type_int(v, name, &value, errp);
4482 }
4483
4484 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
4485 const char *name, void *opaque,
4486 Error **errp)
4487 {
4488 X86CPU *cpu = X86_CPU(obj);
4489 CPUX86State *env = &cpu->env;
4490 const int64_t min = 0;
4491 const int64_t max = 0xf;
4492 int64_t value;
4493
4494 if (!visit_type_int(v, name, &value, errp)) {
4495 return;
4496 }
4497 if (value < min || value > max) {
4498 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4499 name ? name : "null", value, min, max);
4500 return;
4501 }
4502
4503 env->cpuid_version &= ~0xf;
4504 env->cpuid_version |= value & 0xf;
4505 }
4506
4507 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4508 {
4509 X86CPU *cpu = X86_CPU(obj);
4510 CPUX86State *env = &cpu->env;
4511 char *value;
4512
4513 value = g_malloc(CPUID_VENDOR_SZ + 1);
4514 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4515 env->cpuid_vendor3);
4516 return value;
4517 }
4518
4519 static void x86_cpuid_set_vendor(Object *obj, const char *value,
4520 Error **errp)
4521 {
4522 X86CPU *cpu = X86_CPU(obj);
4523 CPUX86State *env = &cpu->env;
4524 int i;
4525
4526 if (strlen(value) != CPUID_VENDOR_SZ) {
4527 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
4528 return;
4529 }
4530
4531 env->cpuid_vendor1 = 0;
4532 env->cpuid_vendor2 = 0;
4533 env->cpuid_vendor3 = 0;
4534 for (i = 0; i < 4; i++) {
4535 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4536 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4537 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4538 }
4539 }
4540
4541 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4542 {
4543 X86CPU *cpu = X86_CPU(obj);
4544 CPUX86State *env = &cpu->env;
4545 char *value;
4546 int i;
4547
4548 value = g_malloc(48 + 1);
4549 for (i = 0; i < 48; i++) {
4550 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4551 }
4552 value[48] = '\0';
4553 return value;
4554 }
4555
4556 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4557 Error **errp)
4558 {
4559 X86CPU *cpu = X86_CPU(obj);
4560 CPUX86State *env = &cpu->env;
4561 int c, len, i;
4562
4563 if (model_id == NULL) {
4564 model_id = "";
4565 }
4566 len = strlen(model_id);
4567 memset(env->cpuid_model, 0, 48);
4568 for (i = 0; i < 48; i++) {
4569 if (i >= len) {
4570 c = '\0';
4571 } else {
4572 c = (uint8_t)model_id[i];
4573 }
4574 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4575 }
4576 }
4577
4578 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4579 void *opaque, Error **errp)
4580 {
4581 X86CPU *cpu = X86_CPU(obj);
4582 int64_t value;
4583
4584 value = cpu->env.tsc_khz * 1000;
4585 visit_type_int(v, name, &value, errp);
4586 }
4587
4588 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4589 void *opaque, Error **errp)
4590 {
4591 X86CPU *cpu = X86_CPU(obj);
4592 const int64_t min = 0;
4593 const int64_t max = INT64_MAX;
4594 int64_t value;
4595
4596 if (!visit_type_int(v, name, &value, errp)) {
4597 return;
4598 }
4599 if (value < min || value > max) {
4600 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4601 name ? name : "null", value, min, max);
4602 return;
4603 }
4604
4605 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
4606 }
4607
4608 /* Generic getter for "feature-words" and "filtered-features" properties */
4609 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4610 const char *name, void *opaque,
4611 Error **errp)
4612 {
4613 uint64_t *array = (uint64_t *)opaque;
4614 FeatureWord w;
4615 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4616 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4617 X86CPUFeatureWordInfoList *list = NULL;
4618
4619 for (w = 0; w < FEATURE_WORDS; w++) {
4620 FeatureWordInfo *wi = &feature_word_info[w];
4621 /*
4622 * We didn't have MSR features when "feature-words" was
4623 * introduced. Therefore skipped other type entries.
4624 */
4625 if (wi->type != CPUID_FEATURE_WORD) {
4626 continue;
4627 }
4628 X86CPUFeatureWordInfo *qwi = &word_infos[w];
4629 qwi->cpuid_input_eax = wi->cpuid.eax;
4630 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4631 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4632 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
4633 qwi->features = array[w];
4634
4635 /* List will be in reverse order, but order shouldn't matter */
4636 list_entries[w].next = list;
4637 list_entries[w].value = &word_infos[w];
4638 list = &list_entries[w];
4639 }
4640
4641 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
4642 }
4643
4644 /* Convert all '_' in a feature string option name to '-', to make feature
4645 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4646 */
4647 static inline void feat2prop(char *s)
4648 {
4649 while ((s = strchr(s, '_'))) {
4650 *s = '-';
4651 }
4652 }
4653
4654 /* Return the feature property name for a feature flag bit */
4655 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4656 {
4657 const char *name;
4658 /* XSAVE components are automatically enabled by other features,
4659 * so return the original feature name instead
4660 */
4661 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4662 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4663
4664 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4665 x86_ext_save_areas[comp].bits) {
4666 w = x86_ext_save_areas[comp].feature;
4667 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4668 }
4669 }
4670
4671 assert(bitnr < 64);
4672 assert(w < FEATURE_WORDS);
4673 name = feature_word_info[w].feat_names[bitnr];
4674 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4675 return name;
4676 }
4677
4678 /* Compatibily hack to maintain legacy +-feat semantic,
4679 * where +-feat overwrites any feature set by
4680 * feat=on|feat even if the later is parsed after +-feat
4681 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4682 */
4683 static GList *plus_features, *minus_features;
4684
4685 static gint compare_string(gconstpointer a, gconstpointer b)
4686 {
4687 return g_strcmp0(a, b);
4688 }
4689
4690 /* Parse "+feature,-feature,feature=foo" CPU feature string
4691 */
4692 static void x86_cpu_parse_featurestr(const char *typename, char *features,
4693 Error **errp)
4694 {
4695 char *featurestr; /* Single 'key=value" string being parsed */
4696 static bool cpu_globals_initialized;
4697 bool ambiguous = false;
4698
4699 if (cpu_globals_initialized) {
4700 return;
4701 }
4702 cpu_globals_initialized = true;
4703
4704 if (!features) {
4705 return;
4706 }
4707
4708 for (featurestr = strtok(features, ",");
4709 featurestr;
4710 featurestr = strtok(NULL, ",")) {
4711 const char *name;
4712 const char *val = NULL;
4713 char *eq = NULL;
4714 char num[32];
4715 GlobalProperty *prop;
4716
4717 /* Compatibility syntax: */
4718 if (featurestr[0] == '+') {
4719 plus_features = g_list_append(plus_features,
4720 g_strdup(featurestr + 1));
4721 continue;
4722 } else if (featurestr[0] == '-') {
4723 minus_features = g_list_append(minus_features,
4724 g_strdup(featurestr + 1));
4725 continue;
4726 }
4727
4728 eq = strchr(featurestr, '=');
4729 if (eq) {
4730 *eq++ = 0;
4731 val = eq;
4732 } else {
4733 val = "on";
4734 }
4735
4736 feat2prop(featurestr);
4737 name = featurestr;
4738
4739 if (g_list_find_custom(plus_features, name, compare_string)) {
4740 warn_report("Ambiguous CPU model string. "
4741 "Don't mix both \"+%s\" and \"%s=%s\"",
4742 name, name, val);
4743 ambiguous = true;
4744 }
4745 if (g_list_find_custom(minus_features, name, compare_string)) {
4746 warn_report("Ambiguous CPU model string. "
4747 "Don't mix both \"-%s\" and \"%s=%s\"",
4748 name, name, val);
4749 ambiguous = true;
4750 }
4751
4752 /* Special case: */
4753 if (!strcmp(name, "tsc-freq")) {
4754 int ret;
4755 uint64_t tsc_freq;
4756
4757 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
4758 if (ret < 0 || tsc_freq > INT64_MAX) {
4759 error_setg(errp, "bad numerical value %s", val);
4760 return;
4761 }
4762 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4763 val = num;
4764 name = "tsc-frequency";
4765 }
4766
4767 prop = g_new0(typeof(*prop), 1);
4768 prop->driver = typename;
4769 prop->property = g_strdup(name);
4770 prop->value = g_strdup(val);
4771 qdev_prop_register_global(prop);
4772 }
4773
4774 if (ambiguous) {
4775 warn_report("Compatibility of ambiguous CPU model "
4776 "strings won't be kept on future QEMU versions");
4777 }
4778 }
4779
4780 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
4781 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
4782
4783 /* Build a list with the name of all features on a feature word array */
4784 static void x86_cpu_list_feature_names(FeatureWordArray features,
4785 strList **feat_names)
4786 {
4787 FeatureWord w;
4788 strList **next = feat_names;
4789
4790 for (w = 0; w < FEATURE_WORDS; w++) {
4791 uint64_t filtered = features[w];
4792 int i;
4793 for (i = 0; i < 64; i++) {
4794 if (filtered & (1ULL << i)) {
4795 strList *new = g_new0(strList, 1);
4796 new->value = g_strdup(x86_cpu_feature_name(w, i));
4797 *next = new;
4798 next = &new->next;
4799 }
4800 }
4801 }
4802 }
4803
4804 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4805 const char *name, void *opaque,
4806 Error **errp)
4807 {
4808 X86CPU *xc = X86_CPU(obj);
4809 strList *result = NULL;
4810
4811 x86_cpu_list_feature_names(xc->filtered_features, &result);
4812 visit_type_strList(v, "unavailable-features", &result, errp);
4813 }
4814
4815 /* Check for missing features that may prevent the CPU class from
4816 * running using the current machine and accelerator.
4817 */
4818 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
4819 strList **missing_feats)
4820 {
4821 X86CPU *xc;
4822 Error *err = NULL;
4823 strList **next = missing_feats;
4824
4825 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
4826 strList *new = g_new0(strList, 1);
4827 new->value = g_strdup("kvm");
4828 *missing_feats = new;
4829 return;
4830 }
4831
4832 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
4833
4834 x86_cpu_expand_features(xc, &err);
4835 if (err) {
4836 /* Errors at x86_cpu_expand_features should never happen,
4837 * but in case it does, just report the model as not
4838 * runnable at all using the "type" property.
4839 */
4840 strList *new = g_new0(strList, 1);
4841 new->value = g_strdup("type");
4842 *next = new;
4843 next = &new->next;
4844 error_free(err);
4845 }
4846
4847 x86_cpu_filter_features(xc, false);
4848
4849 x86_cpu_list_feature_names(xc->filtered_features, next);
4850
4851 object_unref(OBJECT(xc));
4852 }
4853
4854 /* Print all cpuid feature names in featureset
4855 */
4856 static void listflags(GList *features)
4857 {
4858 size_t len = 0;
4859 GList *tmp;
4860
4861 for (tmp = features; tmp; tmp = tmp->next) {
4862 const char *name = tmp->data;
4863 if ((len + strlen(name) + 1) >= 75) {
4864 qemu_printf("\n");
4865 len = 0;
4866 }
4867 qemu_printf("%s%s", len == 0 ? " " : " ", name);
4868 len += strlen(name) + 1;
4869 }
4870 qemu_printf("\n");
4871 }
4872
4873 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
4874 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4875 {
4876 ObjectClass *class_a = (ObjectClass *)a;
4877 ObjectClass *class_b = (ObjectClass *)b;
4878 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4879 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
4880 int ret;
4881
4882 if (cc_a->ordering != cc_b->ordering) {
4883 ret = cc_a->ordering - cc_b->ordering;
4884 } else {
4885 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4886 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
4887 ret = strcmp(name_a, name_b);
4888 }
4889 return ret;
4890 }
4891
4892 static GSList *get_sorted_cpu_model_list(void)
4893 {
4894 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4895 list = g_slist_sort(list, x86_cpu_list_compare);
4896 return list;
4897 }
4898
4899 static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4900 {
4901 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
4902 char *r = object_property_get_str(obj, "model-id", &error_abort);
4903 object_unref(obj);
4904 return r;
4905 }
4906
4907 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4908 {
4909 X86CPUVersion version;
4910
4911 if (!cc->model || !cc->model->is_alias) {
4912 return NULL;
4913 }
4914 version = x86_cpu_model_resolve_version(cc->model);
4915 if (version <= 0) {
4916 return NULL;
4917 }
4918 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4919 }
4920
4921 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4922 {
4923 ObjectClass *oc = data;
4924 X86CPUClass *cc = X86_CPU_CLASS(oc);
4925 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4926 g_autofree char *desc = g_strdup(cc->model_description);
4927 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
4928 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
4929
4930 if (!desc && alias_of) {
4931 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4932 desc = g_strdup("(alias configured by machine type)");
4933 } else {
4934 desc = g_strdup_printf("(alias of %s)", alias_of);
4935 }
4936 }
4937 if (!desc && cc->model && cc->model->note) {
4938 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4939 }
4940 if (!desc) {
4941 desc = g_strdup_printf("%s", model_id);
4942 }
4943
4944 qemu_printf("x86 %-20s %-58s\n", name, desc);
4945 }
4946
4947 /* list available CPU models and flags */
4948 void x86_cpu_list(void)
4949 {
4950 int i, j;
4951 GSList *list;
4952 GList *names = NULL;
4953
4954 qemu_printf("Available CPUs:\n");
4955 list = get_sorted_cpu_model_list();
4956 g_slist_foreach(list, x86_cpu_list_entry, NULL);
4957 g_slist_free(list);
4958
4959 names = NULL;
4960 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4961 FeatureWordInfo *fw = &feature_word_info[i];
4962 for (j = 0; j < 64; j++) {
4963 if (fw->feat_names[j]) {
4964 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4965 }
4966 }
4967 }
4968
4969 names = g_list_sort(names, (GCompareFunc)strcmp);
4970
4971 qemu_printf("\nRecognized CPUID flags:\n");
4972 listflags(names);
4973 qemu_printf("\n");
4974 g_list_free(names);
4975 }
4976
4977 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4978 {
4979 ObjectClass *oc = data;
4980 X86CPUClass *cc = X86_CPU_CLASS(oc);
4981 CpuDefinitionInfoList **cpu_list = user_data;
4982 CpuDefinitionInfoList *entry;
4983 CpuDefinitionInfo *info;
4984
4985 info = g_malloc0(sizeof(*info));
4986 info->name = x86_cpu_class_get_model_name(cc);
4987 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4988 info->has_unavailable_features = true;
4989 info->q_typename = g_strdup(object_class_get_name(oc));
4990 info->migration_safe = cc->migration_safe;
4991 info->has_migration_safe = true;
4992 info->q_static = cc->static_model;
4993 /*
4994 * Old machine types won't report aliases, so that alias translation
4995 * doesn't break compatibility with previous QEMU versions.
4996 */
4997 if (default_cpu_version != CPU_VERSION_LEGACY) {
4998 info->alias_of = x86_cpu_class_get_alias_of(cc);
4999 info->has_alias_of = !!info->alias_of;
5000 }
5001
5002 entry = g_malloc0(sizeof(*entry));
5003 entry->value = info;
5004 entry->next = *cpu_list;
5005 *cpu_list = entry;
5006 }
5007
5008 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
5009 {
5010 CpuDefinitionInfoList *cpu_list = NULL;
5011 GSList *list = get_sorted_cpu_model_list();
5012 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
5013 g_slist_free(list);
5014 return cpu_list;
5015 }
5016
5017 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
5018 bool migratable_only)
5019 {
5020 FeatureWordInfo *wi = &feature_word_info[w];
5021 uint64_t r = 0;
5022
5023 if (kvm_enabled()) {
5024 switch (wi->type) {
5025 case CPUID_FEATURE_WORD:
5026 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
5027 wi->cpuid.ecx,
5028 wi->cpuid.reg);
5029 break;
5030 case MSR_FEATURE_WORD:
5031 r = kvm_arch_get_supported_msr_feature(kvm_state,
5032 wi->msr.index);
5033 break;
5034 }
5035 } else if (hvf_enabled()) {
5036 if (wi->type != CPUID_FEATURE_WORD) {
5037 return 0;
5038 }
5039 r = hvf_get_supported_cpuid(wi->cpuid.eax,
5040 wi->cpuid.ecx,
5041 wi->cpuid.reg);
5042 } else if (tcg_enabled()) {
5043 r = wi->tcg_features;
5044 } else {
5045 return ~0;
5046 }
5047 if (migratable_only) {
5048 r &= x86_cpu_get_migratable_flags(w);
5049 }
5050 return r;
5051 }
5052
5053 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5054 {
5055 PropValue *pv;
5056 for (pv = props; pv->prop; pv++) {
5057 if (!pv->value) {
5058 continue;
5059 }
5060 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5061 &error_abort);
5062 }
5063 }
5064
5065 /* Apply properties for the CPU model version specified in model */
5066 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5067 {
5068 const X86CPUVersionDefinition *vdef;
5069 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5070
5071 if (version == CPU_VERSION_LEGACY) {
5072 return;
5073 }
5074
5075 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5076 PropValue *p;
5077
5078 for (p = vdef->props; p && p->prop; p++) {
5079 object_property_parse(OBJECT(cpu), p->prop, p->value,
5080 &error_abort);
5081 }
5082
5083 if (vdef->version == version) {
5084 break;
5085 }
5086 }
5087
5088 /*
5089 * If we reached the end of the list, version number was invalid
5090 */
5091 assert(vdef->version == version);
5092 }
5093
5094 /* Load data from X86CPUDefinition into a X86CPU object
5095 */
5096 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
5097 {
5098 X86CPUDefinition *def = model->cpudef;
5099 CPUX86State *env = &cpu->env;
5100 const char *vendor;
5101 char host_vendor[CPUID_VENDOR_SZ + 1];
5102 FeatureWord w;
5103
5104 /*NOTE: any property set by this function should be returned by
5105 * x86_cpu_static_props(), so static expansion of
5106 * query-cpu-model-expansion is always complete.
5107 */
5108
5109 /* CPU models only set _minimum_ values for level/xlevel: */
5110 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
5111 &error_abort);
5112 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
5113 &error_abort);
5114
5115 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5116 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5117 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
5118 &error_abort);
5119 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
5120 &error_abort);
5121 for (w = 0; w < FEATURE_WORDS; w++) {
5122 env->features[w] = def->features[w];
5123 }
5124
5125 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5126 cpu->legacy_cache = !def->cache_info;
5127
5128 /* Special cases not set in the X86CPUDefinition structs: */
5129 /* TODO: in-kernel irqchip for hvf */
5130 if (kvm_enabled()) {
5131 if (!kvm_irqchip_in_kernel()) {
5132 x86_cpu_change_kvm_default("x2apic", "off");
5133 }
5134
5135 x86_cpu_apply_props(cpu, kvm_default_props);
5136 } else if (tcg_enabled()) {
5137 x86_cpu_apply_props(cpu, tcg_default_props);
5138 }
5139
5140 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
5141
5142 /* sysenter isn't supported in compatibility mode on AMD,
5143 * syscall isn't supported in compatibility mode on Intel.
5144 * Normally we advertise the actual CPU vendor, but you can
5145 * override this using the 'vendor' property if you want to use
5146 * KVM's sysenter/syscall emulation in compatibility mode and
5147 * when doing cross vendor migration
5148 */
5149 vendor = def->vendor;
5150 if (accel_uses_host_cpuid()) {
5151 uint32_t ebx = 0, ecx = 0, edx = 0;
5152 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
5153 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
5154 vendor = host_vendor;
5155 }
5156
5157 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
5158
5159 x86_cpu_apply_version_props(cpu, model);
5160
5161 /*
5162 * Properties in versioned CPU model are not user specified features.
5163 * We can simply clear env->user_features here since it will be filled later
5164 * in x86_cpu_expand_features() based on plus_features and minus_features.
5165 */
5166 memset(&env->user_features, 0, sizeof(env->user_features));
5167 }
5168
5169 #ifndef CONFIG_USER_ONLY
5170 /* Return a QDict containing keys for all properties that can be included
5171 * in static expansion of CPU models. All properties set by x86_cpu_load_model()
5172 * must be included in the dictionary.
5173 */
5174 static QDict *x86_cpu_static_props(void)
5175 {
5176 FeatureWord w;
5177 int i;
5178 static const char *props[] = {
5179 "min-level",
5180 "min-xlevel",
5181 "family",
5182 "model",
5183 "stepping",
5184 "model-id",
5185 "vendor",
5186 "lmce",
5187 NULL,
5188 };
5189 static QDict *d;
5190
5191 if (d) {
5192 return d;
5193 }
5194
5195 d = qdict_new();
5196 for (i = 0; props[i]; i++) {
5197 qdict_put_null(d, props[i]);
5198 }
5199
5200 for (w = 0; w < FEATURE_WORDS; w++) {
5201 FeatureWordInfo *fi = &feature_word_info[w];
5202 int bit;
5203 for (bit = 0; bit < 64; bit++) {
5204 if (!fi->feat_names[bit]) {
5205 continue;
5206 }
5207 qdict_put_null(d, fi->feat_names[bit]);
5208 }
5209 }
5210
5211 return d;
5212 }
5213
5214 /* Add an entry to @props dict, with the value for property. */
5215 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
5216 {
5217 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
5218 &error_abort);
5219
5220 qdict_put_obj(props, prop, value);
5221 }
5222
5223 /* Convert CPU model data from X86CPU object to a property dictionary
5224 * that can recreate exactly the same CPU model.
5225 */
5226 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
5227 {
5228 QDict *sprops = x86_cpu_static_props();
5229 const QDictEntry *e;
5230
5231 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
5232 const char *prop = qdict_entry_key(e);
5233 x86_cpu_expand_prop(cpu, props, prop);
5234 }
5235 }
5236
5237 /* Convert CPU model data from X86CPU object to a property dictionary
5238 * that can recreate exactly the same CPU model, including every
5239 * writeable QOM property.
5240 */
5241 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
5242 {
5243 ObjectPropertyIterator iter;
5244 ObjectProperty *prop;
5245
5246 object_property_iter_init(&iter, OBJECT(cpu));
5247 while ((prop = object_property_iter_next(&iter))) {
5248 /* skip read-only or write-only properties */
5249 if (!prop->get || !prop->set) {
5250 continue;
5251 }
5252
5253 /* "hotplugged" is the only property that is configurable
5254 * on the command-line but will be set differently on CPUs
5255 * created using "-cpu ... -smp ..." and by CPUs created
5256 * on the fly by x86_cpu_from_model() for querying. Skip it.
5257 */
5258 if (!strcmp(prop->name, "hotplugged")) {
5259 continue;
5260 }
5261 x86_cpu_expand_prop(cpu, props, prop->name);
5262 }
5263 }
5264
5265 static void object_apply_props(Object *obj, QDict *props, Error **errp)
5266 {
5267 const QDictEntry *prop;
5268
5269 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
5270 if (!object_property_set_qobject(obj, qdict_entry_key(prop),
5271 qdict_entry_value(prop), errp)) {
5272 break;
5273 }
5274 }
5275 }
5276
5277 /* Create X86CPU object according to model+props specification */
5278 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
5279 {
5280 X86CPU *xc = NULL;
5281 X86CPUClass *xcc;
5282 Error *err = NULL;
5283
5284 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
5285 if (xcc == NULL) {
5286 error_setg(&err, "CPU model '%s' not found", model);
5287 goto out;
5288 }
5289
5290 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
5291 if (props) {
5292 object_apply_props(OBJECT(xc), props, &err);
5293 if (err) {
5294 goto out;
5295 }
5296 }
5297
5298 x86_cpu_expand_features(xc, &err);
5299 if (err) {
5300 goto out;
5301 }
5302
5303 out:
5304 if (err) {
5305 error_propagate(errp, err);
5306 object_unref(OBJECT(xc));
5307 xc = NULL;
5308 }
5309 return xc;
5310 }
5311
5312 CpuModelExpansionInfo *
5313 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
5314 CpuModelInfo *model,
5315 Error **errp)
5316 {
5317 X86CPU *xc = NULL;
5318 Error *err = NULL;
5319 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
5320 QDict *props = NULL;
5321 const char *base_name;
5322
5323 xc = x86_cpu_from_model(model->name,
5324 model->has_props ?
5325 qobject_to(QDict, model->props) :
5326 NULL, &err);
5327 if (err) {
5328 goto out;
5329 }
5330
5331 props = qdict_new();
5332 ret->model = g_new0(CpuModelInfo, 1);
5333 ret->model->props = QOBJECT(props);
5334 ret->model->has_props = true;
5335
5336 switch (type) {
5337 case CPU_MODEL_EXPANSION_TYPE_STATIC:
5338 /* Static expansion will be based on "base" only */
5339 base_name = "base";
5340 x86_cpu_to_dict(xc, props);
5341 break;
5342 case CPU_MODEL_EXPANSION_TYPE_FULL:
5343 /* As we don't return every single property, full expansion needs
5344 * to keep the original model name+props, and add extra
5345 * properties on top of that.
5346 */
5347 base_name = model->name;
5348 x86_cpu_to_dict_full(xc, props);
5349 break;
5350 default:
5351 error_setg(&err, "Unsupported expansion type");
5352 goto out;
5353 }
5354
5355 x86_cpu_to_dict(xc, props);
5356
5357 ret->model->name = g_strdup(base_name);
5358
5359 out:
5360 object_unref(OBJECT(xc));
5361 if (err) {
5362 error_propagate(errp, err);
5363 qapi_free_CpuModelExpansionInfo(ret);
5364 ret = NULL;
5365 }
5366 return ret;
5367 }
5368 #endif /* !CONFIG_USER_ONLY */
5369
5370 static gchar *x86_gdb_arch_name(CPUState *cs)
5371 {
5372 #ifdef TARGET_X86_64
5373 return g_strdup("i386:x86-64");
5374 #else
5375 return g_strdup("i386");
5376 #endif
5377 }
5378
5379 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5380 {
5381 X86CPUModel *model = data;
5382 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5383
5384 xcc->model = model;
5385 xcc->migration_safe = true;
5386 }
5387
5388 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
5389 {
5390 g_autofree char *typename = x86_cpu_type_name(name);
5391 TypeInfo ti = {
5392 .name = typename,
5393 .parent = TYPE_X86_CPU,
5394 .class_init = x86_cpu_cpudef_class_init,
5395 .class_data = model,
5396 };
5397
5398 type_register(&ti);
5399 }
5400
5401 static void x86_register_cpudef_types(X86CPUDefinition *def)
5402 {
5403 X86CPUModel *m;
5404 const X86CPUVersionDefinition *vdef;
5405
5406 /* AMD aliases are handled at runtime based on CPUID vendor, so
5407 * they shouldn't be set on the CPU model table.
5408 */
5409 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
5410 /* catch mistakes instead of silently truncating model_id when too long */
5411 assert(def->model_id && strlen(def->model_id) <= 48);
5412
5413 /* Unversioned model: */
5414 m = g_new0(X86CPUModel, 1);
5415 m->cpudef = def;
5416 m->version = CPU_VERSION_AUTO;
5417 m->is_alias = true;
5418 x86_register_cpu_model_type(def->name, m);
5419
5420 /* Versioned models: */
5421
5422 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5423 X86CPUModel *m = g_new0(X86CPUModel, 1);
5424 g_autofree char *name =
5425 x86_cpu_versioned_model_name(def, vdef->version);
5426 m->cpudef = def;
5427 m->version = vdef->version;
5428 m->note = vdef->note;
5429 x86_register_cpu_model_type(name, m);
5430
5431 if (vdef->alias) {
5432 X86CPUModel *am = g_new0(X86CPUModel, 1);
5433 am->cpudef = def;
5434 am->version = vdef->version;
5435 am->is_alias = true;
5436 x86_register_cpu_model_type(vdef->alias, am);
5437 }
5438 }
5439
5440 }
5441
5442 #if !defined(CONFIG_USER_ONLY)
5443
5444 void cpu_clear_apic_feature(CPUX86State *env)
5445 {
5446 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
5447 }
5448
5449 #endif /* !CONFIG_USER_ONLY */
5450
5451 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5452 uint32_t *eax, uint32_t *ebx,
5453 uint32_t *ecx, uint32_t *edx)
5454 {
5455 X86CPU *cpu = env_archcpu(env);
5456 CPUState *cs = env_cpu(env);
5457 uint32_t die_offset;
5458 uint32_t limit;
5459 uint32_t signature[3];
5460 X86CPUTopoInfo topo_info;
5461
5462 topo_info.dies_per_pkg = env->nr_dies;
5463 topo_info.cores_per_die = cs->nr_cores;
5464 topo_info.threads_per_core = cs->nr_threads;
5465
5466 /* Calculate & apply limits for different index ranges */
5467 if (index >= 0xC0000000) {
5468 limit = env->cpuid_xlevel2;
5469 } else if (index >= 0x80000000) {
5470 limit = env->cpuid_xlevel;
5471 } else if (index >= 0x40000000) {
5472 limit = 0x40000001;
5473 } else {
5474 limit = env->cpuid_level;
5475 }
5476
5477 if (index > limit) {
5478 /* Intel documentation states that invalid EAX input will
5479 * return the same information as EAX=cpuid_level
5480 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5481 */
5482 index = env->cpuid_level;
5483 }
5484
5485 switch(index) {
5486 case 0:
5487 *eax = env->cpuid_level;
5488 *ebx = env->cpuid_vendor1;
5489 *edx = env->cpuid_vendor2;
5490 *ecx = env->cpuid_vendor3;
5491 break;
5492 case 1:
5493 *eax = env->cpuid_version;
5494 *ebx = (cpu->apic_id << 24) |
5495 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
5496 *ecx = env->features[FEAT_1_ECX];
5497 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5498 *ecx |= CPUID_EXT_OSXSAVE;
5499 }
5500 *edx = env->features[FEAT_1_EDX];
5501 if (cs->nr_cores * cs->nr_threads > 1) {
5502 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
5503 *edx |= CPUID_HT;
5504 }
5505 if (!cpu->enable_pmu) {
5506 *ecx &= ~CPUID_EXT_PDCM;
5507 }
5508 break;
5509 case 2:
5510 /* cache info: needed for Pentium Pro compatibility */
5511 if (cpu->cache_info_passthrough) {
5512 host_cpuid(index, 0, eax, ebx, ecx, edx);
5513 break;
5514 }
5515 *eax = 1; /* Number of CPUID[EAX=2] calls required */
5516 *ebx = 0;
5517 if (!cpu->enable_l3_cache) {
5518 *ecx = 0;
5519 } else {
5520 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
5521 }
5522 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5523 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5524 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
5525 break;
5526 case 4:
5527 /* cache info: needed for Core compatibility */
5528 if (cpu->cache_info_passthrough) {
5529 host_cpuid(index, count, eax, ebx, ecx, edx);
5530 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
5531 *eax &= ~0xFC000000;
5532 if ((*eax & 31) && cs->nr_cores > 1) {
5533 *eax |= (cs->nr_cores - 1) << 26;
5534 }
5535 } else {
5536 *eax = 0;
5537 switch (count) {
5538 case 0: /* L1 dcache info */
5539 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5540 1, cs->nr_cores,
5541 eax, ebx, ecx, edx);
5542 break;
5543 case 1: /* L1 icache info */
5544 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5545 1, cs->nr_cores,
5546 eax, ebx, ecx, edx);
5547 break;
5548 case 2: /* L2 cache info */
5549 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5550 cs->nr_threads, cs->nr_cores,
5551 eax, ebx, ecx, edx);
5552 break;
5553 case 3: /* L3 cache info */
5554 die_offset = apicid_die_offset(&topo_info);
5555 if (cpu->enable_l3_cache) {
5556 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
5557 (1 << die_offset), cs->nr_cores,
5558 eax, ebx, ecx, edx);
5559 break;
5560 }
5561 /* fall through */
5562 default: /* end of info */
5563 *eax = *ebx = *ecx = *edx = 0;
5564 break;
5565 }
5566 }
5567 break;
5568 case 5:
5569 /* MONITOR/MWAIT Leaf */
5570 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5571 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5572 *ecx = cpu->mwait.ecx; /* flags */
5573 *edx = cpu->mwait.edx; /* mwait substates */
5574 break;
5575 case 6:
5576 /* Thermal and Power Leaf */
5577 *eax = env->features[FEAT_6_EAX];
5578 *ebx = 0;
5579 *ecx = 0;
5580 *edx = 0;
5581 break;
5582 case 7:
5583 /* Structured Extended Feature Flags Enumeration Leaf */
5584 if (count == 0) {
5585 /* Maximum ECX value for sub-leaves */
5586 *eax = env->cpuid_level_func7;
5587 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
5588 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
5589 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5590 *ecx |= CPUID_7_0_ECX_OSPKE;
5591 }
5592 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
5593 } else if (count == 1) {
5594 *eax = env->features[FEAT_7_1_EAX];
5595 *ebx = 0;
5596 *ecx = 0;
5597 *edx = 0;
5598 } else {
5599 *eax = 0;
5600 *ebx = 0;
5601 *ecx = 0;
5602 *edx = 0;
5603 }
5604 break;
5605 case 9:
5606 /* Direct Cache Access Information Leaf */
5607 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5608 *ebx = 0;
5609 *ecx = 0;
5610 *edx = 0;
5611 break;
5612 case 0xA:
5613 /* Architectural Performance Monitoring Leaf */
5614 if (kvm_enabled() && cpu->enable_pmu) {
5615 KVMState *s = cs->kvm_state;
5616
5617 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5618 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5619 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5620 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
5621 } else if (hvf_enabled() && cpu->enable_pmu) {
5622 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5623 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5624 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5625 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
5626 } else {
5627 *eax = 0;
5628 *ebx = 0;
5629 *ecx = 0;
5630 *edx = 0;
5631 }
5632 break;
5633 case 0xB:
5634 /* Extended Topology Enumeration Leaf */
5635 if (!cpu->enable_cpuid_0xb) {
5636 *eax = *ebx = *ecx = *edx = 0;
5637 break;
5638 }
5639
5640 *ecx = count & 0xff;
5641 *edx = cpu->apic_id;
5642
5643 switch (count) {
5644 case 0:
5645 *eax = apicid_core_offset(&topo_info);
5646 *ebx = cs->nr_threads;
5647 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5648 break;
5649 case 1:
5650 *eax = apicid_pkg_offset(&topo_info);
5651 *ebx = cs->nr_cores * cs->nr_threads;
5652 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5653 break;
5654 default:
5655 *eax = 0;
5656 *ebx = 0;
5657 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5658 }
5659
5660 assert(!(*eax & ~0x1f));
5661 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5662 break;
5663 case 0x1F:
5664 /* V2 Extended Topology Enumeration Leaf */
5665 if (env->nr_dies < 2) {
5666 *eax = *ebx = *ecx = *edx = 0;
5667 break;
5668 }
5669
5670 *ecx = count & 0xff;
5671 *edx = cpu->apic_id;
5672 switch (count) {
5673 case 0:
5674 *eax = apicid_core_offset(&topo_info);
5675 *ebx = cs->nr_threads;
5676 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5677 break;
5678 case 1:
5679 *eax = apicid_die_offset(&topo_info);
5680 *ebx = cs->nr_cores * cs->nr_threads;
5681 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5682 break;
5683 case 2:
5684 *eax = apicid_pkg_offset(&topo_info);
5685 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5686 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5687 break;
5688 default:
5689 *eax = 0;
5690 *ebx = 0;
5691 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5692 }
5693 assert(!(*eax & ~0x1f));
5694 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5695 break;
5696 case 0xD: {
5697 /* Processor Extended State */
5698 *eax = 0;
5699 *ebx = 0;
5700 *ecx = 0;
5701 *edx = 0;
5702 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
5703 break;
5704 }
5705
5706 if (count == 0) {
5707 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5708 *eax = env->features[FEAT_XSAVE_COMP_LO];
5709 *edx = env->features[FEAT_XSAVE_COMP_HI];
5710 /*
5711 * The initial value of xcr0 and ebx == 0, On host without kvm
5712 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5713 * even through guest update xcr0, this will crash some legacy guest
5714 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5715 */
5716 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
5717 } else if (count == 1) {
5718 *eax = env->features[FEAT_XSAVE];
5719 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
5720 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5721 const ExtSaveArea *esa = &x86_ext_save_areas[count];
5722 *eax = esa->size;
5723 *ebx = esa->offset;
5724 }
5725 }
5726 break;
5727 }
5728 case 0x14: {
5729 /* Intel Processor Trace Enumeration */
5730 *eax = 0;
5731 *ebx = 0;
5732 *ecx = 0;
5733 *edx = 0;
5734 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5735 !kvm_enabled()) {
5736 break;
5737 }
5738
5739 if (count == 0) {
5740 *eax = INTEL_PT_MAX_SUBLEAF;
5741 *ebx = INTEL_PT_MINIMAL_EBX;
5742 *ecx = INTEL_PT_MINIMAL_ECX;
5743 } else if (count == 1) {
5744 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5745 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5746 }
5747 break;
5748 }
5749 case 0x40000000:
5750 /*
5751 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5752 * set here, but we restrict to TCG none the less.
5753 */
5754 if (tcg_enabled() && cpu->expose_tcg) {
5755 memcpy(signature, "TCGTCGTCGTCG", 12);
5756 *eax = 0x40000001;
5757 *ebx = signature[0];
5758 *ecx = signature[1];
5759 *edx = signature[2];
5760 } else {
5761 *eax = 0;
5762 *ebx = 0;
5763 *ecx = 0;
5764 *edx = 0;
5765 }
5766 break;
5767 case 0x40000001:
5768 *eax = 0;
5769 *ebx = 0;
5770 *ecx = 0;
5771 *edx = 0;
5772 break;
5773 case 0x80000000:
5774 *eax = env->cpuid_xlevel;
5775 *ebx = env->cpuid_vendor1;
5776 *edx = env->cpuid_vendor2;
5777 *ecx = env->cpuid_vendor3;
5778 break;
5779 case 0x80000001:
5780 *eax = env->cpuid_version;
5781 *ebx = 0;
5782 *ecx = env->features[FEAT_8000_0001_ECX];
5783 *edx = env->features[FEAT_8000_0001_EDX];
5784
5785 /* The Linux kernel checks for the CMPLegacy bit and
5786 * discards multiple thread information if it is set.
5787 * So don't set it here for Intel to make Linux guests happy.
5788 */
5789 if (cs->nr_cores * cs->nr_threads > 1) {
5790 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5791 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5792 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
5793 *ecx |= 1 << 1; /* CmpLegacy bit */
5794 }
5795 }
5796 break;
5797 case 0x80000002:
5798 case 0x80000003:
5799 case 0x80000004:
5800 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5801 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5802 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5803 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5804 break;
5805 case 0x80000005:
5806 /* cache info (L1 cache) */
5807 if (cpu->cache_info_passthrough) {
5808 host_cpuid(index, 0, eax, ebx, ecx, edx);
5809 break;
5810 }
5811 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5812 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
5813 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5814 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
5815 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5816 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
5817 break;
5818 case 0x80000006:
5819 /* cache info (L2 cache) */
5820 if (cpu->cache_info_passthrough) {
5821 host_cpuid(index, 0, eax, ebx, ecx, edx);
5822 break;
5823 }
5824 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5825 (L2_DTLB_2M_ENTRIES << 16) |
5826 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5827 (L2_ITLB_2M_ENTRIES);
5828 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5829 (L2_DTLB_4K_ENTRIES << 16) |
5830 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5831 (L2_ITLB_4K_ENTRIES);
5832 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5833 cpu->enable_l3_cache ?
5834 env->cache_info_amd.l3_cache : NULL,
5835 ecx, edx);
5836 break;
5837 case 0x80000007:
5838 *eax = 0;
5839 *ebx = 0;
5840 *ecx = 0;
5841 *edx = env->features[FEAT_8000_0007_EDX];
5842 break;
5843 case 0x80000008:
5844 /* virtual & phys address size in low 2 bytes. */
5845 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5846 /* 64 bit processor */
5847 *eax = cpu->phys_bits; /* configurable physical bits */
5848 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5849 *eax |= 0x00003900; /* 57 bits virtual */
5850 } else {
5851 *eax |= 0x00003000; /* 48 bits virtual */
5852 }
5853 } else {
5854 *eax = cpu->phys_bits;
5855 }
5856 *ebx = env->features[FEAT_8000_0008_EBX];
5857 if (cs->nr_cores * cs->nr_threads > 1) {
5858 /*
5859 * Bits 15:12 is "The number of bits in the initial
5860 * Core::X86::Apic::ApicId[ApicId] value that indicate
5861 * thread ID within a package".
5862 * Bits 7:0 is "The number of threads in the package is NC+1"
5863 */
5864 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
5865 ((cs->nr_cores * cs->nr_threads) - 1);
5866 } else {
5867 *ecx = 0;
5868 }
5869 *edx = 0;
5870 break;
5871 case 0x8000000A:
5872 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5873 *eax = 0x00000001; /* SVM Revision */
5874 *ebx = 0x00000010; /* nr of ASIDs */
5875 *ecx = 0;
5876 *edx = env->features[FEAT_SVM]; /* optional features */
5877 } else {
5878 *eax = 0;
5879 *ebx = 0;
5880 *ecx = 0;
5881 *edx = 0;
5882 }
5883 break;
5884 case 0x8000001D:
5885 *eax = 0;
5886 if (cpu->cache_info_passthrough) {
5887 host_cpuid(index, count, eax, ebx, ecx, edx);
5888 break;
5889 }
5890 switch (count) {
5891 case 0: /* L1 dcache info */
5892 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5893 &topo_info, eax, ebx, ecx, edx);
5894 break;
5895 case 1: /* L1 icache info */
5896 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5897 &topo_info, eax, ebx, ecx, edx);
5898 break;
5899 case 2: /* L2 cache info */
5900 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5901 &topo_info, eax, ebx, ecx, edx);
5902 break;
5903 case 3: /* L3 cache info */
5904 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5905 &topo_info, eax, ebx, ecx, edx);
5906 break;
5907 default: /* end of info */
5908 *eax = *ebx = *ecx = *edx = 0;
5909 break;
5910 }
5911 break;
5912 case 0x8000001E:
5913 assert(cpu->core_id <= 255);
5914 encode_topo_cpuid8000001e(cpu, &topo_info,
5915 eax, ebx, ecx, edx);
5916 break;
5917 case 0xC0000000:
5918 *eax = env->cpuid_xlevel2;
5919 *ebx = 0;
5920 *ecx = 0;
5921 *edx = 0;
5922 break;
5923 case 0xC0000001:
5924 /* Support for VIA CPU's CPUID instruction */
5925 *eax = env->cpuid_version;
5926 *ebx = 0;
5927 *ecx = 0;
5928 *edx = env->features[FEAT_C000_0001_EDX];
5929 break;
5930 case 0xC0000002:
5931 case 0xC0000003:
5932 case 0xC0000004:
5933 /* Reserved for the future, and now filled with zero */
5934 *eax = 0;
5935 *ebx = 0;
5936 *ecx = 0;
5937 *edx = 0;
5938 break;
5939 case 0x8000001F:
5940 *eax = sev_enabled() ? 0x2 : 0;
5941 *ebx = sev_get_cbit_position();
5942 *ebx |= sev_get_reduced_phys_bits() << 6;
5943 *ecx = 0;
5944 *edx = 0;
5945 break;
5946 default:
5947 /* reserved values: zero */
5948 *eax = 0;
5949 *ebx = 0;
5950 *ecx = 0;
5951 *edx = 0;
5952 break;
5953 }
5954 }
5955
5956 static void x86_cpu_reset(DeviceState *dev)
5957 {
5958 CPUState *s = CPU(dev);
5959 X86CPU *cpu = X86_CPU(s);
5960 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5961 CPUX86State *env = &cpu->env;
5962 target_ulong cr4;
5963 uint64_t xcr0;
5964 int i;
5965
5966 xcc->parent_reset(dev);
5967
5968 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
5969
5970 env->old_exception = -1;
5971
5972 /* init to reset state */
5973
5974 env->hflags2 |= HF2_GIF_MASK;
5975 env->hflags &= ~HF_GUEST_MASK;
5976
5977 cpu_x86_update_cr0(env, 0x60000010);
5978 env->a20_mask = ~0x0;
5979 env->smbase = 0x30000;
5980 env->msr_smi_count = 0;
5981
5982 env->idt.limit = 0xffff;
5983 env->gdt.limit = 0xffff;
5984 env->ldt.limit = 0xffff;
5985 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5986 env->tr.limit = 0xffff;
5987 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5988
5989 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5990 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5991 DESC_R_MASK | DESC_A_MASK);
5992 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5993 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5994 DESC_A_MASK);
5995 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5996 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5997 DESC_A_MASK);
5998 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5999 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6000 DESC_A_MASK);
6001 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
6002 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6003 DESC_A_MASK);
6004 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
6005 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6006 DESC_A_MASK);
6007
6008 env->eip = 0xfff0;
6009 env->regs[R_EDX] = env->cpuid_version;
6010
6011 env->eflags = 0x2;
6012
6013 /* FPU init */
6014 for (i = 0; i < 8; i++) {
6015 env->fptags[i] = 1;
6016 }
6017 cpu_set_fpuc(env, 0x37f);
6018
6019 env->mxcsr = 0x1f80;
6020 /* All units are in INIT state. */
6021 env->xstate_bv = 0;
6022
6023 env->pat = 0x0007040600070406ULL;
6024 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
6025 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
6026 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
6027 }
6028
6029 memset(env->dr, 0, sizeof(env->dr));
6030 env->dr[6] = DR6_FIXED_1;
6031 env->dr[7] = DR7_FIXED_1;
6032 cpu_breakpoint_remove_all(s, BP_CPU);
6033 cpu_watchpoint_remove_all(s, BP_CPU);
6034
6035 cr4 = 0;
6036 xcr0 = XSTATE_FP_MASK;
6037
6038 #ifdef CONFIG_USER_ONLY
6039 /* Enable all the features for user-mode. */
6040 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
6041 xcr0 |= XSTATE_SSE_MASK;
6042 }
6043 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6044 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6045 if (env->features[esa->feature] & esa->bits) {
6046 xcr0 |= 1ull << i;
6047 }
6048 }
6049
6050 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
6051 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
6052 }
6053 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
6054 cr4 |= CR4_FSGSBASE_MASK;
6055 }
6056 #endif
6057
6058 env->xcr0 = xcr0;
6059 cpu_x86_update_cr4(env, cr4);
6060
6061 /*
6062 * SDM 11.11.5 requires:
6063 * - IA32_MTRR_DEF_TYPE MSR.E = 0
6064 * - IA32_MTRR_PHYSMASKn.V = 0
6065 * All other bits are undefined. For simplification, zero it all.
6066 */
6067 env->mtrr_deftype = 0;
6068 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
6069 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
6070
6071 env->interrupt_injected = -1;
6072 env->exception_nr = -1;
6073 env->exception_pending = 0;
6074 env->exception_injected = 0;
6075 env->exception_has_payload = false;
6076 env->exception_payload = 0;
6077 env->nmi_injected = false;
6078 #if !defined(CONFIG_USER_ONLY)
6079 /* We hard-wire the BSP to the first CPU. */
6080 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
6081
6082 s->halted = !cpu_is_bsp(cpu);
6083
6084 if (kvm_enabled()) {
6085 kvm_arch_reset_vcpu(cpu);
6086 }
6087 #endif
6088 }
6089
6090 #ifndef CONFIG_USER_ONLY
6091 bool cpu_is_bsp(X86CPU *cpu)
6092 {
6093 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
6094 }
6095
6096 /* TODO: remove me, when reset over QOM tree is implemented */
6097 static void x86_cpu_machine_reset_cb(void *opaque)
6098 {
6099 X86CPU *cpu = opaque;
6100 cpu_reset(CPU(cpu));
6101 }
6102 #endif
6103
6104 static void mce_init(X86CPU *cpu)
6105 {
6106 CPUX86State *cenv = &cpu->env;
6107 unsigned int bank;
6108
6109 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
6110 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
6111 (CPUID_MCE | CPUID_MCA)) {
6112 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6113 (cpu->enable_lmce ? MCG_LMCE_P : 0);
6114 cenv->mcg_ctl = ~(uint64_t)0;
6115 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6116 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6117 }
6118 }
6119 }
6120
6121 #ifndef CONFIG_USER_ONLY
6122 APICCommonClass *apic_get_class(void)
6123 {
6124 const char *apic_type = "apic";
6125
6126 /* TODO: in-kernel irqchip for hvf */
6127 if (kvm_apic_in_kernel()) {
6128 apic_type = "kvm-apic";
6129 } else if (xen_enabled()) {
6130 apic_type = "xen-apic";
6131 }
6132
6133 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
6134 }
6135
6136 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
6137 {
6138 APICCommonState *apic;
6139 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
6140
6141 cpu->apic_state = DEVICE(object_new_with_class(apic_class));
6142
6143 object_property_add_child(OBJECT(cpu), "lapic",
6144 OBJECT(cpu->apic_state));
6145 object_unref(OBJECT(cpu->apic_state));
6146
6147 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
6148 /* TODO: convert to link<> */
6149 apic = APIC_COMMON(cpu->apic_state);
6150 apic->cpu = cpu;
6151 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
6152 }
6153
6154 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6155 {
6156 APICCommonState *apic;
6157 static bool apic_mmio_map_once;
6158
6159 if (cpu->apic_state == NULL) {
6160 return;
6161 }
6162 qdev_realize(DEVICE(cpu->apic_state), NULL, errp);
6163
6164 /* Map APIC MMIO area */
6165 apic = APIC_COMMON(cpu->apic_state);
6166 if (!apic_mmio_map_once) {
6167 memory_region_add_subregion_overlap(get_system_memory(),
6168 apic->apicbase &
6169 MSR_IA32_APICBASE_BASE,
6170 &apic->io_memory,
6171 0x1000);
6172 apic_mmio_map_once = true;
6173 }
6174 }
6175
6176 static void x86_cpu_machine_done(Notifier *n, void *unused)
6177 {
6178 X86CPU *cpu = container_of(n, X86CPU, machine_done);
6179 MemoryRegion *smram =
6180 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
6181
6182 if (smram) {
6183 cpu->smram = g_new(MemoryRegion, 1);
6184 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
6185 smram, 0, 4 * GiB);
6186 memory_region_set_enabled(cpu->smram, true);
6187 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
6188 }
6189 }
6190 #else
6191 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6192 {
6193 }
6194 #endif
6195
6196 /* Note: Only safe for use on x86(-64) hosts */
6197 static uint32_t x86_host_phys_bits(void)
6198 {
6199 uint32_t eax;
6200 uint32_t host_phys_bits;
6201
6202 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
6203 if (eax >= 0x80000008) {
6204 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
6205 /* Note: According to AMD doc 25481 rev 2.34 they have a field
6206 * at 23:16 that can specify a maximum physical address bits for
6207 * the guest that can override this value; but I've not seen
6208 * anything with that set.
6209 */
6210 host_phys_bits = eax & 0xff;
6211 } else {
6212 /* It's an odd 64 bit machine that doesn't have the leaf for
6213 * physical address bits; fall back to 36 that's most older
6214 * Intel.
6215 */
6216 host_phys_bits = 36;
6217 }
6218
6219 return host_phys_bits;
6220 }
6221
6222 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6223 {
6224 if (*min < value) {
6225 *min = value;
6226 }
6227 }
6228
6229 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6230 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6231 {
6232 CPUX86State *env = &cpu->env;
6233 FeatureWordInfo *fi = &feature_word_info[w];
6234 uint32_t eax = fi->cpuid.eax;
6235 uint32_t region = eax & 0xF0000000;
6236
6237 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
6238 if (!env->features[w]) {
6239 return;
6240 }
6241
6242 switch (region) {
6243 case 0x00000000:
6244 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6245 break;
6246 case 0x80000000:
6247 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6248 break;
6249 case 0xC0000000:
6250 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6251 break;
6252 }
6253
6254 if (eax == 7) {
6255 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6256 fi->cpuid.ecx);
6257 }
6258 }
6259
6260 /* Calculate XSAVE components based on the configured CPU feature flags */
6261 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6262 {
6263 CPUX86State *env = &cpu->env;
6264 int i;
6265 uint64_t mask;
6266
6267 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
6268 env->features[FEAT_XSAVE_COMP_LO] = 0;
6269 env->features[FEAT_XSAVE_COMP_HI] = 0;
6270 return;
6271 }
6272
6273 mask = 0;
6274 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6275 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6276 if (env->features[esa->feature] & esa->bits) {
6277 mask |= (1ULL << i);
6278 }
6279 }
6280
6281 env->features[FEAT_XSAVE_COMP_LO] = mask;
6282 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
6283 }
6284
6285 /***** Steps involved on loading and filtering CPUID data
6286 *
6287 * When initializing and realizing a CPU object, the steps
6288 * involved in setting up CPUID data are:
6289 *
6290 * 1) Loading CPU model definition (X86CPUDefinition). This is
6291 * implemented by x86_cpu_load_model() and should be completely
6292 * transparent, as it is done automatically by instance_init.
6293 * No code should need to look at X86CPUDefinition structs
6294 * outside instance_init.
6295 *
6296 * 2) CPU expansion. This is done by realize before CPUID
6297 * filtering, and will make sure host/accelerator data is
6298 * loaded for CPU models that depend on host capabilities
6299 * (e.g. "host"). Done by x86_cpu_expand_features().
6300 *
6301 * 3) CPUID filtering. This initializes extra data related to
6302 * CPUID, and checks if the host supports all capabilities
6303 * required by the CPU. Runnability of a CPU model is
6304 * determined at this step. Done by x86_cpu_filter_features().
6305 *
6306 * Some operations don't require all steps to be performed.
6307 * More precisely:
6308 *
6309 * - CPU instance creation (instance_init) will run only CPU
6310 * model loading. CPU expansion can't run at instance_init-time
6311 * because host/accelerator data may be not available yet.
6312 * - CPU realization will perform both CPU model expansion and CPUID
6313 * filtering, and return an error in case one of them fails.
6314 * - query-cpu-definitions needs to run all 3 steps. It needs
6315 * to run CPUID filtering, as the 'unavailable-features'
6316 * field is set based on the filtering results.
6317 * - The query-cpu-model-expansion QMP command only needs to run
6318 * CPU model loading and CPU expansion. It should not filter
6319 * any CPUID data based on host capabilities.
6320 */
6321
6322 /* Expand CPU configuration data, based on configured features
6323 * and host/accelerator capabilities when appropriate.
6324 */
6325 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
6326 {
6327 CPUX86State *env = &cpu->env;
6328 FeatureWord w;
6329 int i;
6330 GList *l;
6331
6332 for (l = plus_features; l; l = l->next) {
6333 const char *prop = l->data;
6334 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
6335 return;
6336 }
6337 }
6338
6339 for (l = minus_features; l; l = l->next) {
6340 const char *prop = l->data;
6341 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
6342 return;
6343 }
6344 }
6345
6346 /*TODO: Now cpu->max_features doesn't overwrite features
6347 * set using QOM properties, and we can convert
6348 * plus_features & minus_features to global properties
6349 * inside x86_cpu_parse_featurestr() too.
6350 */
6351 if (cpu->max_features) {
6352 for (w = 0; w < FEATURE_WORDS; w++) {
6353 /* Override only features that weren't set explicitly
6354 * by the user.
6355 */
6356 env->features[w] |=
6357 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
6358 ~env->user_features[w] &
6359 ~feature_word_info[w].no_autoenable_flags;
6360 }
6361 }
6362
6363 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6364 FeatureDep *d = &feature_dependencies[i];
6365 if (!(env->features[d->from.index] & d->from.mask)) {
6366 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
6367
6368 /* Not an error unless the dependent feature was added explicitly. */
6369 mark_unavailable_features(cpu, d->to.index,
6370 unavailable_features & env->user_features[d->to.index],
6371 "This feature depends on other features that were not requested");
6372
6373 env->features[d->to.index] &= ~unavailable_features;
6374 }
6375 }
6376
6377 if (!kvm_enabled() || !cpu->expose_kvm) {
6378 env->features[FEAT_KVM] = 0;
6379 }
6380
6381 x86_cpu_enable_xsave_components(cpu);
6382
6383 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6384 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6385 if (cpu->full_cpuid_auto_level) {
6386 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6387 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6388 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6389 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
6390 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
6391 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6392 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6393 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
6394 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
6395 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6396 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6397 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
6398
6399 /* Intel Processor Trace requires CPUID[0x14] */
6400 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6401 if (cpu->intel_pt_auto_level) {
6402 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6403 } else if (cpu->env.cpuid_min_level < 0x14) {
6404 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6405 CPUID_7_0_EBX_INTEL_PT,
6406 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,+intel-pt,min-level=0x14\"");
6407 }
6408 }
6409
6410 /* CPU topology with multi-dies support requires CPUID[0x1F] */
6411 if (env->nr_dies > 1) {
6412 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6413 }
6414
6415 /* SVM requires CPUID[0x8000000A] */
6416 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6417 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6418 }
6419
6420 /* SEV requires CPUID[0x8000001F] */
6421 if (sev_enabled()) {
6422 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6423 }
6424 }
6425
6426 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
6427 if (env->cpuid_level_func7 == UINT32_MAX) {
6428 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6429 }
6430 if (env->cpuid_level == UINT32_MAX) {
6431 env->cpuid_level = env->cpuid_min_level;
6432 }
6433 if (env->cpuid_xlevel == UINT32_MAX) {
6434 env->cpuid_xlevel = env->cpuid_min_xlevel;
6435 }
6436 if (env->cpuid_xlevel2 == UINT32_MAX) {
6437 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
6438 }
6439 }
6440
6441 /*
6442 * Finishes initialization of CPUID data, filters CPU feature
6443 * words based on host availability of each feature.
6444 *
6445 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6446 */
6447 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
6448 {
6449 CPUX86State *env = &cpu->env;
6450 FeatureWord w;
6451 const char *prefix = NULL;
6452
6453 if (verbose) {
6454 prefix = accel_uses_host_cpuid()
6455 ? "host doesn't support requested feature"
6456 : "TCG doesn't support requested feature";
6457 }
6458
6459 for (w = 0; w < FEATURE_WORDS; w++) {
6460 uint64_t host_feat =
6461 x86_cpu_get_supported_feature_word(w, false);
6462 uint64_t requested_features = env->features[w];
6463 uint64_t unavailable_features = requested_features & ~host_feat;
6464 mark_unavailable_features(cpu, w, unavailable_features, prefix);
6465 }
6466
6467 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6468 kvm_enabled()) {
6469 KVMState *s = CPU(cpu)->kvm_state;
6470 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6471 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6472 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6473 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6474 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6475
6476 if (!eax_0 ||
6477 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6478 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6479 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6480 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6481 INTEL_PT_ADDR_RANGES_NUM) ||
6482 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
6483 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
6484 (ecx_0 & INTEL_PT_IP_LIP)) {
6485 /*
6486 * Processor Trace capabilities aren't configurable, so if the
6487 * host can't emulate the capabilities we report on
6488 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6489 */
6490 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
6491 }
6492 }
6493 }
6494
6495 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6496 {
6497 CPUState *cs = CPU(dev);
6498 X86CPU *cpu = X86_CPU(dev);
6499 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6500 CPUX86State *env = &cpu->env;
6501 Error *local_err = NULL;
6502 static bool ht_warned;
6503
6504 if (xcc->host_cpuid_required) {
6505 if (!accel_uses_host_cpuid()) {
6506 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6507 error_setg(&local_err, "CPU model '%s' requires KVM", name);
6508 goto out;
6509 }
6510 }
6511
6512 if (cpu->max_features && accel_uses_host_cpuid()) {
6513 if (enable_cpu_pm) {
6514 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
6515 &cpu->mwait.ecx, &cpu->mwait.edx);
6516 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
6517 if (kvm_enabled() && kvm_has_waitpkg()) {
6518 env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG;
6519 }
6520 }
6521 if (kvm_enabled() && cpu->ucode_rev == 0) {
6522 cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
6523 MSR_IA32_UCODE_REV);
6524 }
6525 }
6526
6527 if (cpu->ucode_rev == 0) {
6528 /* The default is the same as KVM's. */
6529 if (IS_AMD_CPU(env)) {
6530 cpu->ucode_rev = 0x01000065;
6531 } else {
6532 cpu->ucode_rev = 0x100000000ULL;
6533 }
6534 }
6535
6536 /* mwait extended info: needed for Core compatibility */
6537 /* We always wake on interrupt even if host does not have the capability */
6538 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6539
6540 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6541 error_setg(errp, "apic-id property was not initialized properly");
6542 return;
6543 }
6544
6545 x86_cpu_expand_features(cpu, &local_err);
6546 if (local_err) {
6547 goto out;
6548 }
6549
6550 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6551
6552 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6553 error_setg(&local_err,
6554 accel_uses_host_cpuid() ?
6555 "Host doesn't support requested features" :
6556 "TCG doesn't support requested features");
6557 goto out;
6558 }
6559
6560 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6561 * CPUID[1].EDX.
6562 */
6563 if (IS_AMD_CPU(env)) {
6564 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6565 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
6566 & CPUID_EXT2_AMD_ALIASES);
6567 }
6568
6569 /* For 64bit systems think about the number of physical bits to present.
6570 * ideally this should be the same as the host; anything other than matching
6571 * the host can cause incorrect guest behaviour.
6572 * QEMU used to pick the magic value of 40 bits that corresponds to
6573 * consumer AMD devices but nothing else.
6574 */
6575 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6576 if (accel_uses_host_cpuid()) {
6577 uint32_t host_phys_bits = x86_host_phys_bits();
6578 static bool warned;
6579
6580 /* Print a warning if the user set it to a value that's not the
6581 * host value.
6582 */
6583 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
6584 !warned) {
6585 warn_report("Host physical bits (%u)"
6586 " does not match phys-bits property (%u)",
6587 host_phys_bits, cpu->phys_bits);
6588 warned = true;
6589 }
6590
6591 if (cpu->host_phys_bits) {
6592 /* The user asked for us to use the host physical bits */
6593 cpu->phys_bits = host_phys_bits;
6594 if (cpu->host_phys_bits_limit &&
6595 cpu->phys_bits > cpu->host_phys_bits_limit) {
6596 cpu->phys_bits = cpu->host_phys_bits_limit;
6597 }
6598 }
6599
6600 if (cpu->phys_bits &&
6601 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6602 cpu->phys_bits < 32)) {
6603 error_setg(errp, "phys-bits should be between 32 and %u "
6604 " (but is %u)",
6605 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6606 return;
6607 }
6608 } else {
6609 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
6610 error_setg(errp, "TCG only supports phys-bits=%u",
6611 TCG_PHYS_ADDR_BITS);
6612 return;
6613 }
6614 }
6615 /* 0 means it was not explicitly set by the user (or by machine
6616 * compat_props or by the host code above). In this case, the default
6617 * is the value used by TCG (40).
6618 */
6619 if (cpu->phys_bits == 0) {
6620 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6621 }
6622 } else {
6623 /* For 32 bit systems don't use the user set value, but keep
6624 * phys_bits consistent with what we tell the guest.
6625 */
6626 if (cpu->phys_bits != 0) {
6627 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6628 return;
6629 }
6630
6631 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6632 cpu->phys_bits = 36;
6633 } else {
6634 cpu->phys_bits = 32;
6635 }
6636 }
6637
6638 /* Cache information initialization */
6639 if (!cpu->legacy_cache) {
6640 if (!xcc->model || !xcc->model->cpudef->cache_info) {
6641 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6642 error_setg(errp,
6643 "CPU model '%s' doesn't support legacy-cache=off", name);
6644 return;
6645 }
6646 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
6647 *xcc->model->cpudef->cache_info;
6648 } else {
6649 /* Build legacy cache information */
6650 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6651 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6652 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6653 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6654
6655 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6656 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6657 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6658 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6659
6660 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6661 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6662 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6663 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6664 }
6665
6666
6667 cpu_exec_realizefn(cs, &local_err);
6668 if (local_err != NULL) {
6669 error_propagate(errp, local_err);
6670 return;
6671 }
6672
6673 #ifndef CONFIG_USER_ONLY
6674 MachineState *ms = MACHINE(qdev_get_machine());
6675 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
6676
6677 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
6678 x86_cpu_apic_create(cpu, &local_err);
6679 if (local_err != NULL) {
6680 goto out;
6681 }
6682 }
6683 #endif
6684
6685 mce_init(cpu);
6686
6687 #ifndef CONFIG_USER_ONLY
6688 if (tcg_enabled()) {
6689 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
6690 cpu->cpu_as_root = g_new(MemoryRegion, 1);
6691
6692 /* Outer container... */
6693 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
6694 memory_region_set_enabled(cpu->cpu_as_root, true);
6695
6696 /* ... with two regions inside: normal system memory with low
6697 * priority, and...
6698 */
6699 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
6700 get_system_memory(), 0, ~0ull);
6701 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
6702 memory_region_set_enabled(cpu->cpu_as_mem, true);
6703
6704 cs->num_ases = 2;
6705 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
6706 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
6707
6708 /* ... SMRAM with higher priority, linked from /machine/smram. */
6709 cpu->machine_done.notify = x86_cpu_machine_done;
6710 qemu_add_machine_init_done_notifier(&cpu->machine_done);
6711 }
6712 #endif
6713
6714 qemu_init_vcpu(cs);
6715
6716 /*
6717 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6718 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6719 * based on inputs (sockets,cores,threads), it is still better to give
6720 * users a warning.
6721 *
6722 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6723 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6724 */
6725 if (IS_AMD_CPU(env) &&
6726 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6727 cs->nr_threads > 1 && !ht_warned) {
6728 warn_report("This family of AMD CPU doesn't support "
6729 "hyperthreading(%d)",
6730 cs->nr_threads);
6731 error_printf("Please configure -smp options properly"
6732 " or try enabling topoext feature.\n");
6733 ht_warned = true;
6734 }
6735
6736 x86_cpu_apic_realize(cpu, &local_err);
6737 if (local_err != NULL) {
6738 goto out;
6739 }
6740 cpu_reset(cs);
6741
6742 xcc->parent_realize(dev, &local_err);
6743
6744 out:
6745 if (local_err != NULL) {
6746 error_propagate(errp, local_err);
6747 return;
6748 }
6749 }
6750
6751 static void x86_cpu_unrealizefn(DeviceState *dev)
6752 {
6753 X86CPU *cpu = X86_CPU(dev);
6754 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6755
6756 #ifndef CONFIG_USER_ONLY
6757 cpu_remove_sync(CPU(dev));
6758 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6759 #endif
6760
6761 if (cpu->apic_state) {
6762 object_unparent(OBJECT(cpu->apic_state));
6763 cpu->apic_state = NULL;
6764 }
6765
6766 xcc->parent_unrealize(dev);
6767 }
6768
6769 typedef struct BitProperty {
6770 FeatureWord w;
6771 uint64_t mask;
6772 } BitProperty;
6773
6774 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6775 void *opaque, Error **errp)
6776 {
6777 X86CPU *cpu = X86_CPU(obj);
6778 BitProperty *fp = opaque;
6779 uint64_t f = cpu->env.features[fp->w];
6780 bool value = (f & fp->mask) == fp->mask;
6781 visit_type_bool(v, name, &value, errp);
6782 }
6783
6784 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6785 void *opaque, Error **errp)
6786 {
6787 DeviceState *dev = DEVICE(obj);
6788 X86CPU *cpu = X86_CPU(obj);
6789 BitProperty *fp = opaque;
6790 bool value;
6791
6792 if (dev->realized) {
6793 qdev_prop_set_after_realize(dev, name, errp);
6794 return;
6795 }
6796
6797 if (!visit_type_bool(v, name, &value, errp)) {
6798 return;
6799 }
6800
6801 if (value) {
6802 cpu->env.features[fp->w] |= fp->mask;
6803 } else {
6804 cpu->env.features[fp->w] &= ~fp->mask;
6805 }
6806 cpu->env.user_features[fp->w] |= fp->mask;
6807 }
6808
6809 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
6810 void *opaque)
6811 {
6812 BitProperty *prop = opaque;
6813 g_free(prop);
6814 }
6815
6816 /* Register a boolean property to get/set a single bit in a uint32_t field.
6817 *
6818 * The same property name can be registered multiple times to make it affect
6819 * multiple bits in the same FeatureWord. In that case, the getter will return
6820 * true only if all bits are set.
6821 */
6822 static void x86_cpu_register_bit_prop(X86CPU *cpu,
6823 const char *prop_name,
6824 FeatureWord w,
6825 int bitnr)
6826 {
6827 BitProperty *fp;
6828 ObjectProperty *op;
6829 uint64_t mask = (1ULL << bitnr);
6830
6831 op = object_property_find(OBJECT(cpu), prop_name);
6832 if (op) {
6833 fp = op->opaque;
6834 assert(fp->w == w);
6835 fp->mask |= mask;
6836 } else {
6837 fp = g_new0(BitProperty, 1);
6838 fp->w = w;
6839 fp->mask = mask;
6840 object_property_add(OBJECT(cpu), prop_name, "bool",
6841 x86_cpu_get_bit_prop,
6842 x86_cpu_set_bit_prop,
6843 x86_cpu_release_bit_prop, fp);
6844 }
6845 }
6846
6847 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
6848 FeatureWord w,
6849 int bitnr)
6850 {
6851 FeatureWordInfo *fi = &feature_word_info[w];
6852 const char *name = fi->feat_names[bitnr];
6853
6854 if (!name) {
6855 return;
6856 }
6857
6858 /* Property names should use "-" instead of "_".
6859 * Old names containing underscores are registered as aliases
6860 * using object_property_add_alias()
6861 */
6862 assert(!strchr(name, '_'));
6863 /* aliases don't use "|" delimiters anymore, they are registered
6864 * manually using object_property_add_alias() */
6865 assert(!strchr(name, '|'));
6866 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
6867 }
6868
6869 #if !defined(CONFIG_USER_ONLY)
6870 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
6871 {
6872 X86CPU *cpu = X86_CPU(cs);
6873 CPUX86State *env = &cpu->env;
6874 GuestPanicInformation *panic_info = NULL;
6875
6876 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
6877 panic_info = g_malloc0(sizeof(GuestPanicInformation));
6878
6879 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
6880
6881 assert(HV_CRASH_PARAMS >= 5);
6882 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
6883 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
6884 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
6885 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
6886 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
6887 }
6888
6889 return panic_info;
6890 }
6891 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
6892 const char *name, void *opaque,
6893 Error **errp)
6894 {
6895 CPUState *cs = CPU(obj);
6896 GuestPanicInformation *panic_info;
6897
6898 if (!cs->crash_occurred) {
6899 error_setg(errp, "No crash occured");
6900 return;
6901 }
6902
6903 panic_info = x86_cpu_get_crash_info(cs);
6904 if (panic_info == NULL) {
6905 error_setg(errp, "No crash information");
6906 return;
6907 }
6908
6909 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
6910 errp);
6911 qapi_free_GuestPanicInformation(panic_info);
6912 }
6913 #endif /* !CONFIG_USER_ONLY */
6914
6915 static void x86_cpu_initfn(Object *obj)
6916 {
6917 X86CPU *cpu = X86_CPU(obj);
6918 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
6919 CPUX86State *env = &cpu->env;
6920 FeatureWord w;
6921
6922 env->nr_dies = 1;
6923 cpu_set_cpustate_pointers(cpu);
6924
6925 object_property_add(obj, "family", "int",
6926 x86_cpuid_version_get_family,
6927 x86_cpuid_version_set_family, NULL, NULL);
6928 object_property_add(obj, "model", "int",
6929 x86_cpuid_version_get_model,
6930 x86_cpuid_version_set_model, NULL, NULL);
6931 object_property_add(obj, "stepping", "int",
6932 x86_cpuid_version_get_stepping,
6933 x86_cpuid_version_set_stepping, NULL, NULL);
6934 object_property_add_str(obj, "vendor",
6935 x86_cpuid_get_vendor,
6936 x86_cpuid_set_vendor);
6937 object_property_add_str(obj, "model-id",
6938 x86_cpuid_get_model_id,
6939 x86_cpuid_set_model_id);
6940 object_property_add(obj, "tsc-frequency", "int",
6941 x86_cpuid_get_tsc_freq,
6942 x86_cpuid_set_tsc_freq, NULL, NULL);
6943 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6944 x86_cpu_get_feature_words,
6945 NULL, NULL, (void *)env->features);
6946 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6947 x86_cpu_get_feature_words,
6948 NULL, NULL, (void *)cpu->filtered_features);
6949 /*
6950 * The "unavailable-features" property has the same semantics as
6951 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6952 * QMP command: they list the features that would have prevented the
6953 * CPU from running if the "enforce" flag was set.
6954 */
6955 object_property_add(obj, "unavailable-features", "strList",
6956 x86_cpu_get_unavailable_features,
6957 NULL, NULL, NULL);
6958
6959 #if !defined(CONFIG_USER_ONLY)
6960 object_property_add(obj, "crash-information", "GuestPanicInformation",
6961 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
6962 #endif
6963
6964 for (w = 0; w < FEATURE_WORDS; w++) {
6965 int bitnr;
6966
6967 for (bitnr = 0; bitnr < 64; bitnr++) {
6968 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
6969 }
6970 }
6971
6972 object_property_add_alias(obj, "sse3", obj, "pni");
6973 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6974 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6975 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6976 object_property_add_alias(obj, "xd", obj, "nx");
6977 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6978 object_property_add_alias(obj, "i64", obj, "lm");
6979
6980 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6981 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6982 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6983 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6984 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6985 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
6986 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
6987 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
6988 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
6989 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
6990 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
6991 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
6992 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
6993 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
6994 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
6995 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
6996 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
6997 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
6998 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
6999 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
7000 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
7001 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
7002 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
7003
7004 if (xcc->model) {
7005 x86_cpu_load_model(cpu, xcc->model);
7006 }
7007 }
7008
7009 static int64_t x86_cpu_get_arch_id(CPUState *cs)
7010 {
7011 X86CPU *cpu = X86_CPU(cs);
7012
7013 return cpu->apic_id;
7014 }
7015
7016 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
7017 {
7018 X86CPU *cpu = X86_CPU(cs);
7019
7020 return cpu->env.cr[0] & CR0_PG_MASK;
7021 }
7022
7023 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
7024 {
7025 X86CPU *cpu = X86_CPU(cs);
7026
7027 cpu->env.eip = value;
7028 }
7029
7030 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
7031 {
7032 X86CPU *cpu = X86_CPU(cs);
7033
7034 cpu->env.eip = tb->pc - tb->cs_base;
7035 }
7036
7037 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
7038 {
7039 X86CPU *cpu = X86_CPU(cs);
7040 CPUX86State *env = &cpu->env;
7041
7042 #if !defined(CONFIG_USER_ONLY)
7043 if (interrupt_request & CPU_INTERRUPT_POLL) {
7044 return CPU_INTERRUPT_POLL;
7045 }
7046 #endif
7047 if (interrupt_request & CPU_INTERRUPT_SIPI) {
7048 return CPU_INTERRUPT_SIPI;
7049 }
7050
7051 if (env->hflags2 & HF2_GIF_MASK) {
7052 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
7053 !(env->hflags & HF_SMM_MASK)) {
7054 return CPU_INTERRUPT_SMI;
7055 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
7056 !(env->hflags2 & HF2_NMI_MASK)) {
7057 return CPU_INTERRUPT_NMI;
7058 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
7059 return CPU_INTERRUPT_MCE;
7060 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
7061 (((env->hflags2 & HF2_VINTR_MASK) &&
7062 (env->hflags2 & HF2_HIF_MASK)) ||
7063 (!(env->hflags2 & HF2_VINTR_MASK) &&
7064 (env->eflags & IF_MASK &&
7065 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
7066 return CPU_INTERRUPT_HARD;
7067 #if !defined(CONFIG_USER_ONLY)
7068 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
7069 (env->eflags & IF_MASK) &&
7070 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
7071 return CPU_INTERRUPT_VIRQ;
7072 #endif
7073 }
7074 }
7075
7076 return 0;
7077 }
7078
7079 static bool x86_cpu_has_work(CPUState *cs)
7080 {
7081 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
7082 }
7083
7084 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7085 {
7086 X86CPU *cpu = X86_CPU(cs);
7087 CPUX86State *env = &cpu->env;
7088
7089 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7090 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7091 : bfd_mach_i386_i8086);
7092 info->print_insn = print_insn_i386;
7093
7094 info->cap_arch = CS_ARCH_X86;
7095 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7096 : env->hflags & HF_CS32_MASK ? CS_MODE_32
7097 : CS_MODE_16);
7098 info->cap_insn_unit = 1;
7099 info->cap_insn_split = 8;
7100 }
7101
7102 void x86_update_hflags(CPUX86State *env)
7103 {
7104 uint32_t hflags;
7105 #define HFLAG_COPY_MASK \
7106 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7107 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7108 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7109 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7110
7111 hflags = env->hflags & HFLAG_COPY_MASK;
7112 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7113 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7114 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7115 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7116 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7117
7118 if (env->cr[4] & CR4_OSFXSR_MASK) {
7119 hflags |= HF_OSFXSR_MASK;
7120 }
7121
7122 if (env->efer & MSR_EFER_LMA) {
7123 hflags |= HF_LMA_MASK;
7124 }
7125
7126 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7127 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7128 } else {
7129 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7130 (DESC_B_SHIFT - HF_CS32_SHIFT);
7131 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7132 (DESC_B_SHIFT - HF_SS32_SHIFT);
7133 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7134 !(hflags & HF_CS32_MASK)) {
7135 hflags |= HF_ADDSEG_MASK;
7136 } else {
7137 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7138 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7139 }
7140 }
7141 env->hflags = hflags;
7142 }
7143
7144 static Property x86_cpu_properties[] = {
7145 #ifdef CONFIG_USER_ONLY
7146 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7147 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
7148 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7149 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
7150 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
7151 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
7152 #else
7153 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
7154 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7155 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
7156 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
7157 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
7158 #endif
7159 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
7160 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
7161
7162 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
7163 HYPERV_SPINLOCK_NEVER_NOTIFY),
7164 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7165 HYPERV_FEAT_RELAXED, 0),
7166 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7167 HYPERV_FEAT_VAPIC, 0),
7168 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7169 HYPERV_FEAT_TIME, 0),
7170 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7171 HYPERV_FEAT_CRASH, 0),
7172 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7173 HYPERV_FEAT_RESET, 0),
7174 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7175 HYPERV_FEAT_VPINDEX, 0),
7176 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7177 HYPERV_FEAT_RUNTIME, 0),
7178 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7179 HYPERV_FEAT_SYNIC, 0),
7180 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7181 HYPERV_FEAT_STIMER, 0),
7182 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7183 HYPERV_FEAT_FREQUENCIES, 0),
7184 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7185 HYPERV_FEAT_REENLIGHTENMENT, 0),
7186 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7187 HYPERV_FEAT_TLBFLUSH, 0),
7188 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7189 HYPERV_FEAT_EVMCS, 0),
7190 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7191 HYPERV_FEAT_IPI, 0),
7192 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7193 HYPERV_FEAT_STIMER_DIRECT, 0),
7194 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7195 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
7196 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
7197
7198 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
7199 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
7200 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
7201 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
7202 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
7203 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
7204 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
7205 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
7206 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7207 UINT32_MAX),
7208 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7209 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7210 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7211 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7212 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7213 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
7214 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
7215 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
7216 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
7217 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
7218 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
7219 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
7220 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7221 false),
7222 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
7223 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
7224 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7225 true),
7226 /*
7227 * lecacy_cache defaults to true unless the CPU model provides its
7228 * own cache information (see x86_cpu_load_def()).
7229 */
7230 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
7231
7232 /*
7233 * From "Requirements for Implementing the Microsoft
7234 * Hypervisor Interface":
7235 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7236 *
7237 * "Starting with Windows Server 2012 and Windows 8, if
7238 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7239 * the hypervisor imposes no specific limit to the number of VPs.
7240 * In this case, Windows Server 2012 guest VMs may use more than
7241 * 64 VPs, up to the maximum supported number of processors applicable
7242 * to the specific Windows version being used."
7243 */
7244 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
7245 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7246 false),
7247 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7248 true),
7249 DEFINE_PROP_END_OF_LIST()
7250 };
7251
7252 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7253 {
7254 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7255 CPUClass *cc = CPU_CLASS(oc);
7256 DeviceClass *dc = DEVICE_CLASS(oc);
7257
7258 device_class_set_parent_realize(dc, x86_cpu_realizefn,
7259 &xcc->parent_realize);
7260 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7261 &xcc->parent_unrealize);
7262 device_class_set_props(dc, x86_cpu_properties);
7263
7264 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
7265 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
7266
7267 cc->class_by_name = x86_cpu_class_by_name;
7268 cc->parse_features = x86_cpu_parse_featurestr;
7269 cc->has_work = x86_cpu_has_work;
7270 #ifdef CONFIG_TCG
7271 cc->do_interrupt = x86_cpu_do_interrupt;
7272 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
7273 #endif
7274 cc->dump_state = x86_cpu_dump_state;
7275 cc->set_pc = x86_cpu_set_pc;
7276 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
7277 cc->gdb_read_register = x86_cpu_gdb_read_register;
7278 cc->gdb_write_register = x86_cpu_gdb_write_register;
7279 cc->get_arch_id = x86_cpu_get_arch_id;
7280 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7281 #ifndef CONFIG_USER_ONLY
7282 cc->asidx_from_attrs = x86_asidx_from_attrs;
7283 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
7284 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
7285 cc->get_crash_info = x86_cpu_get_crash_info;
7286 cc->write_elf64_note = x86_cpu_write_elf64_note;
7287 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
7288 cc->write_elf32_note = x86_cpu_write_elf32_note;
7289 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
7290 cc->vmsd = &vmstate_x86_cpu;
7291 #endif
7292 cc->gdb_arch_name = x86_gdb_arch_name;
7293 #ifdef TARGET_X86_64
7294 cc->gdb_core_xml_file = "i386-64bit.xml";
7295 cc->gdb_num_core_regs = 66;
7296 #else
7297 cc->gdb_core_xml_file = "i386-32bit.xml";
7298 cc->gdb_num_core_regs = 50;
7299 #endif
7300 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
7301 cc->debug_excp_handler = breakpoint_handler;
7302 #endif
7303 cc->cpu_exec_enter = x86_cpu_exec_enter;
7304 cc->cpu_exec_exit = x86_cpu_exec_exit;
7305 #ifdef CONFIG_TCG
7306 cc->tcg_initialize = tcg_x86_init;
7307 cc->tlb_fill = x86_cpu_tlb_fill;
7308 #endif
7309 cc->disas_set_info = x86_disas_set_info;
7310
7311 dc->user_creatable = true;
7312 }
7313
7314 static const TypeInfo x86_cpu_type_info = {
7315 .name = TYPE_X86_CPU,
7316 .parent = TYPE_CPU,
7317 .instance_size = sizeof(X86CPU),
7318 .instance_init = x86_cpu_initfn,
7319 .abstract = true,
7320 .class_size = sizeof(X86CPUClass),
7321 .class_init = x86_cpu_common_class_init,
7322 };
7323
7324
7325 /* "base" CPU model, used by query-cpu-model-expansion */
7326 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7327 {
7328 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7329
7330 xcc->static_model = true;
7331 xcc->migration_safe = true;
7332 xcc->model_description = "base CPU model type with no features enabled";
7333 xcc->ordering = 8;
7334 }
7335
7336 static const TypeInfo x86_base_cpu_type_info = {
7337 .name = X86_CPU_TYPE_NAME("base"),
7338 .parent = TYPE_X86_CPU,
7339 .class_init = x86_cpu_base_class_init,
7340 };
7341
7342 static void x86_cpu_register_types(void)
7343 {
7344 int i;
7345
7346 type_register_static(&x86_cpu_type_info);
7347 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
7348 x86_register_cpudef_types(&builtin_x86_defs[i]);
7349 }
7350 type_register_static(&max_x86_cpu_type_info);
7351 type_register_static(&x86_base_cpu_type_info);
7352 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
7353 type_register_static(&host_x86_cpu_type_info);
7354 #endif
7355 }
7356
7357 type_init(x86_cpu_register_types)
AR7 emulation for QEMU