target/sparc/cpu.h

   1 #ifndef SPARC_CPU_H
   2 #define SPARC_CPU_H
   3
   4 #include "qemu-common.h"
   5 #include "qemu/bswap.h"
   6 #include "cpu-qom.h"
   7 #include "exec/cpu-defs.h"
   8
   9 #define ALIGNED_ONLY
  10
  11 #if !defined(TARGET_SPARC64)
  12 #define TARGET_DPREGS 16
  13 #else
  14 #define TARGET_DPREGS 32
  15 #endif
  16
  17 /*#define EXCP_INTERRUPT 0x100*/
  18
  19 /* trap definitions */
  20 #ifndef TARGET_SPARC64
  21 #define TT_TFAULT   0x01
  22 #define TT_ILL_INSN 0x02
  23 #define TT_PRIV_INSN 0x03
  24 #define TT_NFPU_INSN 0x04
  25 #define TT_WIN_OVF  0x05
  26 #define TT_WIN_UNF  0x06
  27 #define TT_UNALIGNED 0x07
  28 #define TT_FP_EXCP  0x08
  29 #define TT_DFAULT   0x09
  30 #define TT_TOVF     0x0a
  31 #define TT_EXTINT   0x10
  32 #define TT_CODE_ACCESS 0x21
  33 #define TT_UNIMP_FLUSH 0x25
  34 #define TT_DATA_ACCESS 0x29
  35 #define TT_DIV_ZERO 0x2a
  36 #define TT_NCP_INSN 0x24
  37 #define TT_TRAP     0x80
  38 #else
  39 #define TT_POWER_ON_RESET 0x01
  40 #define TT_TFAULT   0x08
  41 #define TT_CODE_ACCESS 0x0a
  42 #define TT_ILL_INSN 0x10
  43 #define TT_UNIMP_FLUSH TT_ILL_INSN
  44 #define TT_PRIV_INSN 0x11
  45 #define TT_NFPU_INSN 0x20
  46 #define TT_FP_EXCP  0x21
  47 #define TT_TOVF     0x23
  48 #define TT_CLRWIN   0x24
  49 #define TT_DIV_ZERO 0x28
  50 #define TT_DFAULT   0x30
  51 #define TT_DATA_ACCESS 0x32
  52 #define TT_UNALIGNED 0x34
  53 #define TT_PRIV_ACT 0x37
  54 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e
  55 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f
  56 #define TT_EXTINT   0x40
  57 #define TT_IVEC     0x60
  58 #define TT_TMISS    0x64
  59 #define TT_DMISS    0x68
  60 #define TT_DPROT    0x6c
  61 #define TT_SPILL    0x80
  62 #define TT_FILL     0xc0
  63 #define TT_WOTHER   (1 << 5)
  64 #define TT_TRAP     0x100
  65 #define TT_HTRAP    0x180
  66 #endif
  67
  68 #define PSR_NEG_SHIFT 23
  69 #define PSR_NEG   (1 << PSR_NEG_SHIFT)
  70 #define PSR_ZERO_SHIFT 22
  71 #define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
  72 #define PSR_OVF_SHIFT 21
  73 #define PSR_OVF   (1 << PSR_OVF_SHIFT)
  74 #define PSR_CARRY_SHIFT 20
  75 #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
  76 #define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
  77 #if !defined(TARGET_SPARC64)
  78 #define PSR_EF    (1<<12)
  79 #define PSR_PIL   0xf00
  80 #define PSR_S     (1<<7)
  81 #define PSR_PS    (1<<6)
  82 #define PSR_ET    (1<<5)
  83 #define PSR_CWP   0x1f
  84 #endif
  85
  86 #define CC_SRC (env->cc_src)
  87 #define CC_SRC2 (env->cc_src2)
  88 #define CC_DST (env->cc_dst)
  89 #define CC_OP  (env->cc_op)
  90
  91 /* Even though lazy evaluation of CPU condition codes tends to be less
  92  * important on RISC systems where condition codes are only updated
  93  * when explicitly requested, SPARC uses it to update 32-bit and 64-bit
  94  * condition codes.
  95  */
  96 enum {
  97     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
  98     CC_OP_FLAGS,   /* all cc are back in status register */
  99     CC_OP_DIV,     /* modify N, Z and V, C = 0*/
 100     CC_OP_ADD,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 101     CC_OP_ADDX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 102     CC_OP_TADD,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 103     CC_OP_TADDTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 104     CC_OP_SUB,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 105     CC_OP_SUBX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 106     CC_OP_TSUB,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 107     CC_OP_TSUBTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 108     CC_OP_LOGIC,   /* modify N and Z, C = V = 0, CC_DST = res */
 109     CC_OP_NB,
 110 };
 111
 112 /* Trap base register */
 113 #define TBR_BASE_MASK 0xfffff000
 114
 115 #if defined(TARGET_SPARC64)
 116 #define PS_TCT   (1<<12) /* UA2007, impl.dep. trap on control transfer */
 117 #define PS_IG    (1<<11) /* v9, zero on UA2007 */
 118 #define PS_MG    (1<<10) /* v9, zero on UA2007 */
 119 #define PS_CLE   (1<<9) /* UA2007 */
 120 #define PS_TLE   (1<<8) /* UA2007 */
 121 #define PS_RMO   (1<<7)
 122 #define PS_RED   (1<<5) /* v9, zero on UA2007 */
 123 #define PS_PEF   (1<<4) /* enable fpu */
 124 #define PS_AM    (1<<3) /* address mask */
 125 #define PS_PRIV  (1<<2)
 126 #define PS_IE    (1<<1)
 127 #define PS_AG    (1<<0) /* v9, zero on UA2007 */
 128
 129 #define FPRS_FEF (1<<2)
 130
 131 #define HS_PRIV  (1<<2)
 132 #endif
 133
 134 /* Fcc */
 135 #define FSR_RD1        (1ULL << 31)
 136 #define FSR_RD0        (1ULL << 30)
 137 #define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
 138 #define FSR_RD_NEAREST 0
 139 #define FSR_RD_ZERO    FSR_RD0
 140 #define FSR_RD_POS     FSR_RD1
 141 #define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
 142
 143 #define FSR_NVM   (1ULL << 27)
 144 #define FSR_OFM   (1ULL << 26)
 145 #define FSR_UFM   (1ULL << 25)
 146 #define FSR_DZM   (1ULL << 24)
 147 #define FSR_NXM   (1ULL << 23)
 148 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
 149
 150 #define FSR_NVA   (1ULL << 9)
 151 #define FSR_OFA   (1ULL << 8)
 152 #define FSR_UFA   (1ULL << 7)
 153 #define FSR_DZA   (1ULL << 6)
 154 #define FSR_NXA   (1ULL << 5)
 155 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 156
 157 #define FSR_NVC   (1ULL << 4)
 158 #define FSR_OFC   (1ULL << 3)
 159 #define FSR_UFC   (1ULL << 2)
 160 #define FSR_DZC   (1ULL << 1)
 161 #define FSR_NXC   (1ULL << 0)
 162 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
 163
 164 #define FSR_FTT2   (1ULL << 16)
 165 #define FSR_FTT1   (1ULL << 15)
 166 #define FSR_FTT0   (1ULL << 14)
 167 //gcc warns about constant overflow for ~FSR_FTT_MASK
 168 //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
 169 #ifdef TARGET_SPARC64
 170 #define FSR_FTT_NMASK      0xfffffffffffe3fffULL
 171 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
 172 #define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
 173 #define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
 174 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
 175 #else
 176 #define FSR_FTT_NMASK      0xfffe3fffULL
 177 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
 178 #define FSR_LDFSR_OLDMASK  0x000fc000ULL
 179 #endif
 180 #define FSR_LDFSR_MASK     0xcfc00fffULL
 181 #define FSR_FTT_IEEE_EXCP (1ULL << 14)
 182 #define FSR_FTT_UNIMPFPOP (3ULL << 14)
 183 #define FSR_FTT_SEQ_ERROR (4ULL << 14)
 184 #define FSR_FTT_INVAL_FPR (6ULL << 14)
 185
 186 #define FSR_FCC1_SHIFT 11
 187 #define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
 188 #define FSR_FCC0_SHIFT 10
 189 #define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)
 190
 191 /* MMU */
 192 #define MMU_E     (1<<0)
 193 #define MMU_NF    (1<<1)
 194
 195 #define PTE_ENTRYTYPE_MASK 3
 196 #define PTE_ACCESS_MASK    0x1c
 197 #define PTE_ACCESS_SHIFT   2
 198 #define PTE_PPN_SHIFT      7
 199 #define PTE_ADDR_MASK      0xffffff00
 200
 201 #define PG_ACCESSED_BIT 5
 202 #define PG_MODIFIED_BIT 6
 203 #define PG_CACHE_BIT    7
 204
 205 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 206 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
 207 #define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
 208
 209 /* 3 <= NWINDOWS <= 32. */
 210 #define MIN_NWINDOWS 3
 211 #define MAX_NWINDOWS 32
 212
 213 #ifdef TARGET_SPARC64
 214 typedef struct trap_state {
 215     uint64_t tpc;
 216     uint64_t tnpc;
 217     uint64_t tstate;
 218     uint32_t tt;
 219 } trap_state;
 220 #endif
 221 #define TARGET_INSN_START_EXTRA_WORDS 1
 222
 223 struct sparc_def_t {
 224     const char *name;
 225     target_ulong iu_version;
 226     uint32_t fpu_version;
 227     uint32_t mmu_version;
 228     uint32_t mmu_bm;
 229     uint32_t mmu_ctpr_mask;
 230     uint32_t mmu_cxr_mask;
 231     uint32_t mmu_sfsr_mask;
 232     uint32_t mmu_trcr_mask;
 233     uint32_t mxcc_version;
 234     uint32_t features;
 235     uint32_t nwindows;
 236     uint32_t maxtl;
 237 };
 238
 239 #define CPU_FEATURE_FLOAT        (1 << 0)
 240 #define CPU_FEATURE_FLOAT128     (1 << 1)
 241 #define CPU_FEATURE_SWAP         (1 << 2)
 242 #define CPU_FEATURE_MUL          (1 << 3)
 243 #define CPU_FEATURE_DIV          (1 << 4)
 244 #define CPU_FEATURE_FLUSH        (1 << 5)
 245 #define CPU_FEATURE_FSQRT        (1 << 6)
 246 #define CPU_FEATURE_FMUL         (1 << 7)
 247 #define CPU_FEATURE_VIS1         (1 << 8)
 248 #define CPU_FEATURE_VIS2         (1 << 9)
 249 #define CPU_FEATURE_FSMULD       (1 << 10)
 250 #define CPU_FEATURE_HYPV         (1 << 11)
 251 #define CPU_FEATURE_CMT          (1 << 12)
 252 #define CPU_FEATURE_GL           (1 << 13)
 253 #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
 254 #define CPU_FEATURE_ASR17        (1 << 15)
 255 #define CPU_FEATURE_CACHE_CTRL   (1 << 16)
 256 #define CPU_FEATURE_POWERDOWN    (1 << 17)
 257 #define CPU_FEATURE_CASA         (1 << 18)
 258
 259 #ifndef TARGET_SPARC64
 260 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 261                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 262                               CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 263                               CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
 264 #else
 265 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 266                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 267                               CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 268                               CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
 269                               CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
 270                               CPU_FEATURE_CASA)
 271 enum {
 272     mmu_us_12, // Ultrasparc < III (64 entry TLB)
 273     mmu_us_3,  // Ultrasparc III (512 entry TLB)
 274     mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
 275     mmu_sun4v, // T1, T2
 276 };
 277 #endif
 278
 279 #define TTE_VALID_BIT       (1ULL << 63)
 280 #define TTE_NFO_BIT         (1ULL << 60)
 281 #define TTE_USED_BIT        (1ULL << 41)
 282 #define TTE_LOCKED_BIT      (1ULL <<  6)
 283 #define TTE_SIDEEFFECT_BIT  (1ULL <<  3)
 284 #define TTE_PRIV_BIT        (1ULL <<  2)
 285 #define TTE_W_OK_BIT        (1ULL <<  1)
 286 #define TTE_GLOBAL_BIT      (1ULL <<  0)
 287
 288 #define TTE_NFO_BIT_UA2005  (1ULL << 62)
 289 #define TTE_USED_BIT_UA2005 (1ULL << 47)
 290 #define TTE_LOCKED_BIT_UA2005 (1ULL <<  61)
 291 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL <<  11)
 292 #define TTE_PRIV_BIT_UA2005 (1ULL <<  8)
 293 #define TTE_W_OK_BIT_UA2005 (1ULL <<  6)
 294
 295 #define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
 296 #define TTE_IS_NFO(tte)     ((tte) & TTE_NFO_BIT)
 297 #define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)
 298 #define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
 299 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
 300 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
 301 #define TTE_IS_PRIV(tte)    ((tte) & TTE_PRIV_BIT)
 302 #define TTE_IS_W_OK(tte)    ((tte) & TTE_W_OK_BIT)
 303
 304 #define TTE_IS_NFO_UA2005(tte)     ((tte) & TTE_NFO_BIT_UA2005)
 305 #define TTE_IS_USED_UA2005(tte)    ((tte) & TTE_USED_BIT_UA2005)
 306 #define TTE_IS_LOCKED_UA2005(tte)  ((tte) & TTE_LOCKED_BIT_UA2005)
 307 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005)
 308 #define TTE_IS_PRIV_UA2005(tte)    ((tte) & TTE_PRIV_BIT_UA2005)
 309 #define TTE_IS_W_OK_UA2005(tte)    ((tte) & TTE_W_OK_BIT_UA2005)
 310
 311 #define TTE_IS_GLOBAL(tte)  ((tte) & TTE_GLOBAL_BIT)
 312
 313 #define TTE_SET_USED(tte)   ((tte) |= TTE_USED_BIT)
 314 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
 315
 316 #define TTE_PGSIZE(tte)     (((tte) >> 61) & 3ULL)
 317 #define TTE_PGSIZE_UA2005(tte)     ((tte) & 7ULL)
 318 #define TTE_PA(tte)         ((tte) & 0x1ffffffe000ULL)
 319
 320 /* UltraSPARC T1 specific */
 321 #define TLB_UST1_IS_REAL_BIT   (1ULL << 9)  /* Real translation entry */
 322 #define TLB_UST1_IS_SUN4V_BIT  (1ULL << 10) /* sun4u/sun4v TTE format switch */
 323
 324 #define SFSR_NF_BIT         (1ULL << 24)   /* JPS1 NoFault */
 325 #define SFSR_TM_BIT         (1ULL << 15)   /* JPS1 TLB Miss */
 326 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13)   /* USIIi VA out of range (IMMU) */
 327 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12)   /* USIIi VA out of range (DMMU) */
 328 #define SFSR_FT_NFO_BIT     (1ULL << 11)   /* NFO page access */
 329 #define SFSR_FT_ILL_BIT     (1ULL << 10)   /* illegal LDA/STA ASI */
 330 #define SFSR_FT_ATOMIC_BIT  (1ULL <<  9)   /* atomic op on noncacheable area */
 331 #define SFSR_FT_NF_E_BIT    (1ULL <<  8)   /* NF access on side effect area */
 332 #define SFSR_FT_PRIV_BIT    (1ULL <<  7)   /* privilege violation */
 333 #define SFSR_PR_BIT         (1ULL <<  3)   /* privilege mode */
 334 #define SFSR_WRITE_BIT      (1ULL <<  2)   /* write access mode */
 335 #define SFSR_OW_BIT         (1ULL <<  1)   /* status overwritten */
 336 #define SFSR_VALID_BIT      (1ULL <<  0)   /* status valid */
 337
 338 #define SFSR_ASI_SHIFT      16             /* 23:16 ASI value */
 339 #define SFSR_ASI_MASK       (0xffULL << SFSR_ASI_SHIFT)
 340 #define SFSR_CT_PRIMARY     (0ULL <<  4)   /* 5:4 context type */
 341 #define SFSR_CT_SECONDARY   (1ULL <<  4)
 342 #define SFSR_CT_NUCLEUS     (2ULL <<  4)
 343 #define SFSR_CT_NOTRANS     (3ULL <<  4)
 344 #define SFSR_CT_MASK        (3ULL <<  4)
 345
 346 /* Leon3 cache control */
 347
 348 /* Cache control: emulate the behavior of cache control registers but without
 349    any effect on the emulated */
 350
 351 #define CACHE_STATE_MASK 0x3
 352 #define CACHE_DISABLED   0x0
 353 #define CACHE_FROZEN     0x1
 354 #define CACHE_ENABLED    0x3
 355
 356 /* Cache Control register fields */
 357
 358 #define CACHE_CTRL_IF (1 <<  4)  /* Instruction Cache Freeze on Interrupt */
 359 #define CACHE_CTRL_DF (1 <<  5)  /* Data Cache Freeze on Interrupt */
 360 #define CACHE_CTRL_DP (1 << 14)  /* Data cache flush pending */
 361 #define CACHE_CTRL_IP (1 << 15)  /* Instruction cache flush pending */
 362 #define CACHE_CTRL_IB (1 << 16)  /* Instruction burst fetch */
 363 #define CACHE_CTRL_FI (1 << 21)  /* Flush Instruction cache (Write only) */
 364 #define CACHE_CTRL_FD (1 << 22)  /* Flush Data cache (Write only) */
 365 #define CACHE_CTRL_DS (1 << 23)  /* Data cache snoop enable */
 366
 367 #define CONVERT_BIT(X, SRC, DST) \
 368          (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC))
 369
 370 typedef struct SparcTLBEntry {
 371     uint64_t tag;
 372     uint64_t tte;
 373 } SparcTLBEntry;
 374
 375 struct CPUTimer
 376 {
 377     const char *name;
 378     uint32_t    frequency;
 379     uint32_t    disabled;
 380     uint64_t    disabled_mask;
 381     uint32_t    npt;
 382     uint64_t    npt_mask;
 383     int64_t     clock_offset;
 384     QEMUTimer  *qtimer;
 385 };
 386
 387 typedef struct CPUTimer CPUTimer;
 388
 389 typedef struct CPUSPARCState CPUSPARCState;
 390 #if defined(TARGET_SPARC64)
 391 typedef union {
 392    uint64_t mmuregs[16];
 393    struct {
 394     uint64_t tsb_tag_target;
 395     uint64_t mmu_primary_context;
 396     uint64_t mmu_secondary_context;
 397     uint64_t sfsr;
 398     uint64_t sfar;
 399     uint64_t tsb;
 400     uint64_t tag_access;
 401     uint64_t virtual_watchpoint;
 402     uint64_t physical_watchpoint;
 403     uint64_t sun4v_ctx_config[2];
 404     uint64_t sun4v_tsb_pointers[4];
 405    };
 406 } SparcV9MMU;
 407 #endif
 408 struct CPUSPARCState {
 409     target_ulong gregs[8]; /* general registers */
 410     target_ulong *regwptr; /* pointer to current register window */
 411     target_ulong pc;       /* program counter */
 412     target_ulong npc;      /* next program counter */
 413     target_ulong y;        /* multiply/divide register */
 414
 415     /* emulator internal flags handling */
 416     target_ulong cc_src, cc_src2;
 417     target_ulong cc_dst;
 418     uint32_t cc_op;
 419
 420     target_ulong cond; /* conditional branch result (XXX: save it in a
 421                           temporary register when possible) */
 422
 423     uint32_t psr;      /* processor state register */
 424     target_ulong fsr;      /* FPU state register */
 425     CPU_DoubleU fpr[TARGET_DPREGS];  /* floating point registers */
 426     uint32_t cwp;      /* index of current register window (extracted
 427                           from PSR) */
 428 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 429     uint32_t wim;      /* window invalid mask */
 430 #endif
 431     target_ulong tbr;  /* trap base register */
 432 #if !defined(TARGET_SPARC64)
 433     int      psrs;     /* supervisor mode (extracted from PSR) */
 434     int      psrps;    /* previous supervisor mode */
 435     int      psret;    /* enable traps */
 436 #endif
 437     uint32_t psrpil;   /* interrupt blocking level */
 438     uint32_t pil_in;   /* incoming interrupt level bitmap */
 439 #if !defined(TARGET_SPARC64)
 440     int      psref;    /* enable fpu */
 441 #endif
 442     int interrupt_index;
 443     /* NOTE: we allow 8 more registers to handle wrapping */
 444     target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 445
 446     /* Fields up to this point are cleared by a CPU reset */
 447     struct {} end_reset_fields;
 448
 449     CPU_COMMON
 450
 451     /* Fields from here on are preserved across CPU reset. */
 452     target_ulong version;
 453     uint32_t nwindows;
 454
 455     /* MMU regs */
 456 #if defined(TARGET_SPARC64)
 457     uint64_t lsu;
 458 #define DMMU_E 0x8
 459 #define IMMU_E 0x4
 460     SparcV9MMU immu;
 461     SparcV9MMU dmmu;
 462     SparcTLBEntry itlb[64];
 463     SparcTLBEntry dtlb[64];
 464     uint32_t mmu_version;
 465 #else
 466     uint32_t mmuregs[32];
 467     uint64_t mxccdata[4];
 468     uint64_t mxccregs[8];
 469     uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
 470     uint64_t mmubpaction;
 471     uint64_t mmubpregs[4];
 472     uint64_t prom_addr;
 473 #endif
 474     /* temporary float registers */
 475     float128 qt0, qt1;
 476     float_status fp_status;
 477 #if defined(TARGET_SPARC64)
 478 #define MAXTL_MAX 8
 479 #define MAXTL_MASK (MAXTL_MAX - 1)
 480     trap_state ts[MAXTL_MAX];
 481     uint32_t xcc;               /* Extended integer condition codes */
 482     uint32_t asi;
 483     uint32_t pstate;
 484     uint32_t tl;
 485     uint32_t maxtl;
 486     uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
 487     uint64_t agregs[8]; /* alternate general registers */
 488     uint64_t bgregs[8]; /* backup for normal global registers */
 489     uint64_t igregs[8]; /* interrupt general registers */
 490     uint64_t mgregs[8]; /* mmu general registers */
 491     uint64_t glregs[8 * MAXTL_MAX];
 492     uint64_t fprs;
 493     uint64_t tick_cmpr, stick_cmpr;
 494     CPUTimer *tick, *stick;
 495 #define TICK_NPT_MASK        0x8000000000000000ULL
 496 #define TICK_INT_DIS         0x8000000000000000ULL
 497     uint64_t gsr;
 498     uint32_t gl; // UA2005
 499     /* UA 2005 hyperprivileged registers */
 500     uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
 501     uint64_t scratch[8];
 502     CPUTimer *hstick; // UA 2005
 503     /* Interrupt vector registers */
 504     uint64_t ivec_status;
 505     uint64_t ivec_data[3];
 506     uint32_t softint;
 507 #define SOFTINT_TIMER   1
 508 #define SOFTINT_STIMER  (1 << 16)
 509 #define SOFTINT_INTRMASK (0xFFFE)
 510 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
 511 #endif
 512     sparc_def_t def;
 513
 514     void *irq_manager;
 515     void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
 516
 517     /* Leon3 cache control */
 518     uint32_t cache_control;
 519 };
 520
 521 /**
 522  * SPARCCPU:
 523  * @env: #CPUSPARCState
 524  *
 525  * A SPARC CPU.
 526  */
 527 struct SPARCCPU {
 528     /*< private >*/
 529     CPUState parent_obj;
 530     /*< public >*/
 531
 532     CPUSPARCState env;
 533 };
 534
 535 static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
 536 {
 537     return container_of(env, SPARCCPU, env);
 538 }
 539
 540 #define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e))
 541
 542 #define ENV_OFFSET offsetof(SPARCCPU, env)
 543
 544 #ifndef CONFIG_USER_ONLY
 545 extern const struct VMStateDescription vmstate_sparc_cpu;
 546 #endif
 547
 548 void sparc_cpu_do_interrupt(CPUState *cpu);
 549 void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 550 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 551 int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 552 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 553 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 554                                                  MMUAccessType access_type,
 555                                                  int mmu_idx,
 556                                                  uintptr_t retaddr);
 557 void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN;
 558
 559 #ifndef NO_CPU_IO_DEFS
 560 /* cpu_init.c */
 561 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
 562 void sparc_cpu_list(void);
 563 /* mmu_helper.c */
 564 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 565                         MMUAccessType access_type, int mmu_idx,
 566                         bool probe, uintptr_t retaddr);
 567 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
 568 void dump_mmu(CPUSPARCState *env);
 569
 570 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 571 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 572                               uint8_t *buf, int len, bool is_write);
 573 #endif
 574
 575
 576 /* translate.c */
 577 void sparc_tcg_init(void);
 578
 579 /* cpu-exec.c */
 580
 581 /* win_helper.c */
 582 target_ulong cpu_get_psr(CPUSPARCState *env1);
 583 void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
 584 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
 585 #ifdef TARGET_SPARC64
 586 target_ulong cpu_get_ccr(CPUSPARCState *env1);
 587 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
 588 target_ulong cpu_get_cwp64(CPUSPARCState *env1);
 589 void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
 590 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
 591 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl);
 592 #endif
 593 int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
 594 int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
 595 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
 596
 597 /* int_helper.c */
 598 void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
 599
 600 /* sun4m.c, sun4u.c */
 601 void cpu_check_irqs(CPUSPARCState *env);
 602
 603 /* leon3.c */
 604 void leon3_irq_ack(void *irq_manager, int intno);
 605
 606 #if defined (TARGET_SPARC64)
 607
 608 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
 609 {
 610     return (x & mask) == (y & mask);
 611 }
 612
 613 #define MMU_CONTEXT_BITS 13
 614 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
 615
 616 static inline int tlb_compare_context(const SparcTLBEntry *tlb,
 617                                       uint64_t context)
 618 {
 619     return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
 620 }
 621
 622 #endif
 623 #endif
 624
 625 /* cpu-exec.c */
 626 #if !defined(CONFIG_USER_ONLY)
 627 void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 628                                  bool is_write, bool is_exec, int is_asi,
 629                                  unsigned size);
 630 #if defined(TARGET_SPARC64)
 631 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
 632                                            int mmu_idx);
 633 #endif
 634 #endif
 635 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 636
 637 #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
 638 #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
 639 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU
 640
 641 #define cpu_signal_handler cpu_sparc_signal_handler
 642 #define cpu_list sparc_cpu_list
 643
 644 /* MMU modes definitions */
 645 #if defined (TARGET_SPARC64)
 646 #define MMU_USER_IDX   0
 647 #define MMU_USER_SECONDARY_IDX   1
 648 #define MMU_KERNEL_IDX 2
 649 #define MMU_KERNEL_SECONDARY_IDX 3
 650 #define MMU_NUCLEUS_IDX 4
 651 #define MMU_PHYS_IDX   5
 652 #else
 653 #define MMU_USER_IDX   0
 654 #define MMU_KERNEL_IDX 1
 655 #define MMU_PHYS_IDX   2
 656 #endif
 657
 658 #if defined (TARGET_SPARC64)
 659 static inline int cpu_has_hypervisor(CPUSPARCState *env1)
 660 {
 661     return env1->def.features & CPU_FEATURE_HYPV;
 662 }
 663
 664 static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
 665 {
 666     return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
 667 }
 668
 669 static inline int cpu_supervisor_mode(CPUSPARCState *env1)
 670 {
 671     return env1->pstate & PS_PRIV;
 672 }
 673 #else
 674 static inline int cpu_supervisor_mode(CPUSPARCState *env1)
 675 {
 676     return env1->psrs;
 677 }
 678 #endif
 679
 680 static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
 681 {
 682 #if defined(CONFIG_USER_ONLY)
 683     return MMU_USER_IDX;
 684 #elif !defined(TARGET_SPARC64)
 685     if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
 686         return MMU_PHYS_IDX;
 687     } else {
 688         return env->psrs;
 689     }
 690 #else
 691     /* IMMU or DMMU disabled.  */
 692     if (ifetch
 693         ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
 694         : (env->lsu & DMMU_E) == 0) {
 695         return MMU_PHYS_IDX;
 696     } else if (cpu_hypervisor_mode(env)) {
 697         return MMU_PHYS_IDX;
 698     } else if (env->tl > 0) {
 699         return MMU_NUCLEUS_IDX;
 700     } else if (cpu_supervisor_mode(env)) {
 701         return MMU_KERNEL_IDX;
 702     } else {
 703         return MMU_USER_IDX;
 704     }
 705 #endif
 706 }
 707
 708 static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
 709 {
 710 #if !defined (TARGET_SPARC64)
 711     if (env1->psret != 0)
 712         return 1;
 713 #else
 714     if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) {
 715         return 1;
 716     }
 717 #endif
 718
 719     return 0;
 720 }
 721
 722 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
 723 {
 724 #if !defined(TARGET_SPARC64)
 725     /* level 15 is non-maskable on sparc v8 */
 726     return pil == 15 || pil > env1->psrpil;
 727 #else
 728     return pil > env1->psrpil;
 729 #endif
 730 }
 731
 732 typedef CPUSPARCState CPUArchState;
 733 typedef SPARCCPU ArchCPU;
 734
 735 #include "exec/cpu-all.h"
 736
 737 #ifdef TARGET_SPARC64
 738 /* sun4u.c */
 739 void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
 740 uint64_t cpu_tick_get_count(CPUTimer *timer);
 741 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
 742 trap_state* cpu_tsptr(CPUSPARCState* env);
 743 #endif
 744
 745 #define TB_FLAG_MMU_MASK     7
 746 #define TB_FLAG_FPU_ENABLED  (1 << 4)
 747 #define TB_FLAG_AM_ENABLED   (1 << 5)
 748 #define TB_FLAG_SUPER        (1 << 6)
 749 #define TB_FLAG_HYPER        (1 << 7)
 750 #define TB_FLAG_ASI_SHIFT    24
 751
 752 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
 753                                         target_ulong *cs_base, uint32_t *pflags)
 754 {
 755     uint32_t flags;
 756     *pc = env->pc;
 757     *cs_base = env->npc;
 758     flags = cpu_mmu_index(env, false);
 759 #ifndef CONFIG_USER_ONLY
 760     if (cpu_supervisor_mode(env)) {
 761         flags |= TB_FLAG_SUPER;
 762     }
 763 #endif
 764 #ifdef TARGET_SPARC64
 765 #ifndef CONFIG_USER_ONLY
 766     if (cpu_hypervisor_mode(env)) {
 767         flags |= TB_FLAG_HYPER;
 768     }
 769 #endif
 770     if (env->pstate & PS_AM) {
 771         flags |= TB_FLAG_AM_ENABLED;
 772     }
 773     if ((env->def.features & CPU_FEATURE_FLOAT)
 774         && (env->pstate & PS_PEF)
 775         && (env->fprs & FPRS_FEF)) {
 776         flags |= TB_FLAG_FPU_ENABLED;
 777     }
 778     flags |= env->asi << TB_FLAG_ASI_SHIFT;
 779 #else
 780     if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
 781         flags |= TB_FLAG_FPU_ENABLED;
 782     }
 783 #endif
 784     *pflags = flags;
 785 }
 786
 787 static inline bool tb_fpu_enabled(int tb_flags)
 788 {
 789 #if defined(CONFIG_USER_ONLY)
 790     return true;
 791 #else
 792     return tb_flags & TB_FLAG_FPU_ENABLED;
 793 #endif
 794 }
 795
 796 static inline bool tb_am_enabled(int tb_flags)
 797 {
 798 #ifndef TARGET_SPARC64
 799     return false;
 800 #else
 801     return tb_flags & TB_FLAG_AM_ENABLED;
 802 #endif
 803 }
 804
 805 #endif