2 * PA-RISC emulation cpu definitions for qemu.
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
25 #include "exec/cpu-defs.h"
28 /* PA-RISC 1.x processors have a strong memory model. */
29 /* ??? While we do not yet implement PA-RISC 2.0, those processors have
30 a weak memory model, but with TLB bits that force ordering on a per-page
31 basis. It's probably easier to fall back to a strong memory model. */
32 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
35 #define MMU_KERNEL_IDX 0
36 #define MMU_USER_IDX 3
37 #define MMU_PHYS_IDX 4
38 #define TARGET_INSN_START_EXTRA_WORDS 1
40 /* Hardware exceptions, interupts, faults, and traps. */
41 #define EXCP_HPMC 1 /* high priority machine check */
42 #define EXCP_POWER_FAIL 2
43 #define EXCP_RC 3 /* recovery counter */
44 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */
45 #define EXCP_LPMC 5 /* low priority machine check */
46 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */
47 #define EXCP_IMP 7 /* instruction memory protection trap */
48 #define EXCP_ILL 8 /* illegal instruction trap */
49 #define EXCP_BREAK 9 /* break instruction */
50 #define EXCP_PRIV_OPR 10 /* privileged operation trap */
51 #define EXCP_PRIV_REG 11 /* privileged register trap */
52 #define EXCP_OVERFLOW 12 /* signed overflow trap */
53 #define EXCP_COND 13 /* trap-on-condition */
54 #define EXCP_ASSIST 14 /* assist exception trap */
55 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */
56 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */
57 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */
58 #define EXCP_DMP 18 /* data memory protection trap */
59 #define EXCP_DMB 19 /* data memory break trap */
60 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */
61 #define EXCP_PAGE_REF 21 /* page reference trap */
62 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */
63 #define EXCP_HPT 23 /* high-privilege transfer trap */
64 #define EXCP_LPT 24 /* low-privilege transfer trap */
65 #define EXCP_TB 25 /* taken branch trap */
66 #define EXCP_DMAR 26 /* data memory access rights trap */
67 #define EXCP_DMPI 27 /* data memory protection id trap */
68 #define EXCP_UNALIGN 28 /* unaligned data reference trap */
69 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */
71 /* Exceptions for linux-user emulation. */
72 #define EXCP_SYSCALL 30
73 #define EXCP_SYSCALL_LWS 31
75 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
76 #define PSW_I 0x00000001
77 #define PSW_D 0x00000002
78 #define PSW_P 0x00000004
79 #define PSW_Q 0x00000008
80 #define PSW_R 0x00000010
81 #define PSW_F 0x00000020
82 #define PSW_G 0x00000040 /* PA1.x only */
83 #define PSW_O 0x00000080 /* PA2.0 only */
84 #define PSW_CB 0x0000ff00
85 #define PSW_M 0x00010000
86 #define PSW_V 0x00020000
87 #define PSW_C 0x00040000
88 #define PSW_B 0x00080000
89 #define PSW_X 0x00100000
90 #define PSW_N 0x00200000
91 #define PSW_L 0x00400000
92 #define PSW_H 0x00800000
93 #define PSW_T 0x01000000
94 #define PSW_S 0x02000000
95 #define PSW_E 0x04000000
97 #define PSW_W 0x08000000 /* PA2.0 only */
101 #define PSW_Z 0x40000000 /* PA1.x only */
102 #define PSW_Y 0x80000000 /* PA1.x only */
104 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
105 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
107 /* ssm/rsm instructions number PSW_W and PSW_E differently */
108 #define PSW_SM_I PSW_I /* Enable External Interrupts */
109 #define PSW_SM_D PSW_D
110 #define PSW_SM_P PSW_P
111 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
112 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
114 #define PSW_SM_E 0x100
115 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
139 typedef struct CPUHPPAState CPUHPPAState
;
141 #if TARGET_REGISTER_BITS == 32
142 typedef uint32_t target_ureg
;
143 typedef int32_t target_sreg
;
144 #define TREG_FMT_lx "%08"PRIx32
145 #define TREG_FMT_ld "%"PRId32
147 typedef uint64_t target_ureg
;
148 typedef int64_t target_sreg
;
149 #define TREG_FMT_lx "%016"PRIx64
150 #define TREG_FMT_ld "%"PRId64
161 unsigned page_size
: 4;
162 unsigned ar_type
: 3;
165 unsigned entry_valid
: 1;
166 unsigned access_id
: 16;
169 struct CPUHPPAState
{
172 uint64_t sr
[8]; /* stored shifted into place for gva */
174 target_ureg psw
; /* All psw bits except the following: */
175 target_ureg psw_n
; /* boolean */
176 target_sreg psw_v
; /* in most significant bit */
178 /* Splitting the carry-borrow field into the MSB and "the rest", allows
179 * for "the rest" to be deleted when it is unused, but the MSB is in use.
180 * In addition, it's easier to compute carry-in for bit B+1 than it is to
181 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the
182 * host has the appropriate add-with-carry insn to compute the msb).
183 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
185 target_ureg psw_cb
; /* in least significant bit of next nibble */
186 target_ureg psw_cb_msb
; /* boolean */
188 target_ureg iaoq_f
; /* front */
189 target_ureg iaoq_b
; /* back, aka next instruction */
193 uint32_t fr0_shadow
; /* flags, c, ca/cq, rm, d, enables */
194 float_status fp_status
;
196 target_ureg cr
[32]; /* control registers */
197 target_ureg cr_back
[2]; /* back of cr17/cr18 */
198 target_ureg shadow
[7]; /* shadow registers */
200 /* Those resources are used only in QEMU core */
203 /* ??? The number of entries isn't specified by the architecture. */
204 /* ??? Implement a unified itlb/dtlb for the moment. */
205 /* ??? We should use a more intelligent data structure. */
206 hppa_tlb_entry tlb
[256];
212 * @env: #CPUHPPAState
222 QEMUTimer
*alarm_timer
;
225 static inline HPPACPU
*hppa_env_get_cpu(CPUHPPAState
*env
)
227 return container_of(env
, HPPACPU
, env
);
230 #define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e))
231 #define ENV_OFFSET offsetof(HPPACPU, env)
233 typedef CPUHPPAState CPUArchState
;
234 typedef HPPACPU ArchCPU
;
236 #include "exec/cpu-all.h"
238 static inline int cpu_mmu_index(CPUHPPAState
*env
, bool ifetch
)
240 #ifdef CONFIG_USER_ONLY
243 if (env
->psw
& (ifetch
? PSW_C
: PSW_D
)) {
244 return env
->iaoq_f
& 3;
246 return MMU_PHYS_IDX
; /* mmu disabled */
250 void hppa_translate_init(void);
252 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
254 void hppa_cpu_list(void);
256 static inline target_ulong
hppa_form_gva_psw(target_ureg psw
, uint64_t spc
,
259 #ifdef CONFIG_USER_ONLY
262 off
&= (psw
& PSW_W
? 0x3fffffffffffffffull
: 0xffffffffull
);
267 static inline target_ulong
hppa_form_gva(CPUHPPAState
*env
, uint64_t spc
,
270 return hppa_form_gva_psw(env
->psw
, spc
, off
);
273 /* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
274 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
277 #define TB_FLAG_SR_SAME PSW_I
278 #define TB_FLAG_PRIV_SHIFT 8
280 static inline void cpu_get_tb_cpu_state(CPUHPPAState
*env
, target_ulong
*pc
,
281 target_ulong
*cs_base
,
284 uint32_t flags
= env
->psw_n
* PSW_N
;
286 /* TB lookup assumes that PC contains the complete virtual address.
287 If we leave space+offset separate, we'll get ITLB misses to an
288 incomplete virtual address. This also means that we must separate
289 out current cpu priviledge from the low bits of IAOQ_F. */
290 #ifdef CONFIG_USER_ONLY
291 *pc
= env
->iaoq_f
& -4;
292 *cs_base
= env
->iaoq_b
& -4;
294 /* ??? E, T, H, L, B, P bits need to be here, when implemented. */
295 flags
|= env
->psw
& (PSW_W
| PSW_C
| PSW_D
);
296 flags
|= (env
->iaoq_f
& 3) << TB_FLAG_PRIV_SHIFT
;
298 *pc
= (env
->psw
& PSW_C
299 ? hppa_form_gva_psw(env
->psw
, env
->iasq_f
, env
->iaoq_f
& -4)
301 *cs_base
= env
->iasq_f
;
303 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
304 low 32-bits of CS_BASE. This will succeed for all direct branches,
305 which is the primary case we care about -- using goto_tb within a page.
306 Failure is indicated by a zero difference. */
307 if (env
->iasq_f
== env
->iasq_b
) {
308 target_sreg diff
= env
->iaoq_b
- env
->iaoq_f
;
309 if (TARGET_REGISTER_BITS
== 32 || diff
== (int32_t)diff
) {
310 *cs_base
|= (uint32_t)diff
;
313 if ((env
->sr
[4] == env
->sr
[5])
314 & (env
->sr
[4] == env
->sr
[6])
315 & (env
->sr
[4] == env
->sr
[7])) {
316 flags
|= TB_FLAG_SR_SAME
;
323 target_ureg
cpu_hppa_get_psw(CPUHPPAState
*env
);
324 void cpu_hppa_put_psw(CPUHPPAState
*env
, target_ureg
);
325 void cpu_hppa_loaded_fr0(CPUHPPAState
*env
);
327 #ifdef CONFIG_USER_ONLY
328 static inline void cpu_hppa_change_prot_id(CPUHPPAState
*env
) { }
330 void cpu_hppa_change_prot_id(CPUHPPAState
*env
);
333 #define cpu_signal_handler cpu_hppa_signal_handler
335 int cpu_hppa_signal_handler(int host_signum
, void *pinfo
, void *puc
);
336 hwaddr
hppa_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
);
337 int hppa_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
338 int hppa_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
339 void hppa_cpu_do_interrupt(CPUState
*cpu
);
340 bool hppa_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
341 void hppa_cpu_dump_state(CPUState
*cs
, FILE *f
, int);
342 bool hppa_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
343 MMUAccessType access_type
, int mmu_idx
,
344 bool probe
, uintptr_t retaddr
);
345 #ifndef CONFIG_USER_ONLY
346 int hppa_get_physical_address(CPUHPPAState
*env
, vaddr addr
, int mmu_idx
,
347 int type
, hwaddr
*pphys
, int *pprot
);
348 extern const MemoryRegionOps hppa_io_eir_ops
;
349 extern const struct VMStateDescription vmstate_hppa_cpu
;
350 void hppa_cpu_alarm_timer(void *);
351 int hppa_artype_for_page(CPUHPPAState
*env
, target_ulong vaddr
);
353 void QEMU_NORETURN
hppa_dynamic_excp(CPUHPPAState
*env
, int excp
, uintptr_t ra
);
355 #endif /* HPPA_CPU_H */