3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
38 #include "qemu/qemu-print.h"
39 #include "exec/cpu_ldst.h"
40 #include "hw/semihosting/semihost.h"
41 #include "exec/translator.h"
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
46 #include "trace-tcg.h"
51 DisasContextBase base
;
52 const XtensaConfig
*config
;
61 bool sar_m32_allocated
;
75 xtensa_insnbuf insnbuf
;
76 xtensa_insnbuf slotbuf
;
79 static TCGv_i32 cpu_pc
;
80 static TCGv_i32 cpu_R
[16];
81 static TCGv_i32 cpu_FR
[16];
82 static TCGv_i32 cpu_MR
[4];
83 static TCGv_i32 cpu_BR
[16];
84 static TCGv_i32 cpu_BR4
[4];
85 static TCGv_i32 cpu_BR8
[2];
86 static TCGv_i32 cpu_SR
[256];
87 static TCGv_i32 cpu_UR
[256];
88 static TCGv_i32 cpu_windowbase_next
;
89 static TCGv_i32 cpu_exclusive_addr
;
90 static TCGv_i32 cpu_exclusive_val
;
92 static GHashTable
*xtensa_regfile_table
;
94 #include "exec/gen-icount.h"
96 static char *sr_name
[256];
97 static char *ur_name
[256];
99 void xtensa_collect_sr_names(const XtensaConfig
*config
)
101 xtensa_isa isa
= config
->isa
;
102 int n
= xtensa_isa_num_sysregs(isa
);
105 for (i
= 0; i
< n
; ++i
) {
106 int sr
= xtensa_sysreg_number(isa
, i
);
108 if (sr
>= 0 && sr
< 256) {
109 const char *name
= xtensa_sysreg_name(isa
, i
);
111 (xtensa_sysreg_is_user(isa
, i
) ? ur_name
: sr_name
) + sr
;
114 if (strstr(*pname
, name
) == NULL
) {
116 malloc(strlen(*pname
) + strlen(name
) + 2);
118 strcpy(new_name
, *pname
);
119 strcat(new_name
, "/");
120 strcat(new_name
, name
);
125 *pname
= strdup(name
);
131 void xtensa_translate_init(void)
133 static const char * const regnames
[] = {
134 "ar0", "ar1", "ar2", "ar3",
135 "ar4", "ar5", "ar6", "ar7",
136 "ar8", "ar9", "ar10", "ar11",
137 "ar12", "ar13", "ar14", "ar15",
139 static const char * const fregnames
[] = {
140 "f0", "f1", "f2", "f3",
141 "f4", "f5", "f6", "f7",
142 "f8", "f9", "f10", "f11",
143 "f12", "f13", "f14", "f15",
145 static const char * const mregnames
[] = {
146 "m0", "m1", "m2", "m3",
148 static const char * const bregnames
[] = {
149 "b0", "b1", "b2", "b3",
150 "b4", "b5", "b6", "b7",
151 "b8", "b9", "b10", "b11",
152 "b12", "b13", "b14", "b15",
156 cpu_pc
= tcg_global_mem_new_i32(cpu_env
,
157 offsetof(CPUXtensaState
, pc
), "pc");
159 for (i
= 0; i
< 16; i
++) {
160 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
161 offsetof(CPUXtensaState
, regs
[i
]),
165 for (i
= 0; i
< 16; i
++) {
166 cpu_FR
[i
] = tcg_global_mem_new_i32(cpu_env
,
167 offsetof(CPUXtensaState
,
168 fregs
[i
].f32
[FP_F32_LOW
]),
172 for (i
= 0; i
< 4; i
++) {
173 cpu_MR
[i
] = tcg_global_mem_new_i32(cpu_env
,
174 offsetof(CPUXtensaState
,
179 for (i
= 0; i
< 16; i
++) {
180 cpu_BR
[i
] = tcg_global_mem_new_i32(cpu_env
,
181 offsetof(CPUXtensaState
,
185 cpu_BR4
[i
/ 4] = tcg_global_mem_new_i32(cpu_env
,
186 offsetof(CPUXtensaState
,
191 cpu_BR8
[i
/ 8] = tcg_global_mem_new_i32(cpu_env
,
192 offsetof(CPUXtensaState
,
198 for (i
= 0; i
< 256; ++i
) {
200 cpu_SR
[i
] = tcg_global_mem_new_i32(cpu_env
,
201 offsetof(CPUXtensaState
,
207 for (i
= 0; i
< 256; ++i
) {
209 cpu_UR
[i
] = tcg_global_mem_new_i32(cpu_env
,
210 offsetof(CPUXtensaState
,
216 cpu_windowbase_next
=
217 tcg_global_mem_new_i32(cpu_env
,
218 offsetof(CPUXtensaState
, windowbase_next
),
221 tcg_global_mem_new_i32(cpu_env
,
222 offsetof(CPUXtensaState
, exclusive_addr
),
225 tcg_global_mem_new_i32(cpu_env
,
226 offsetof(CPUXtensaState
, exclusive_val
),
230 void **xtensa_get_regfile_by_name(const char *name
)
232 if (xtensa_regfile_table
== NULL
) {
233 xtensa_regfile_table
= g_hash_table_new(g_str_hash
, g_str_equal
);
234 g_hash_table_insert(xtensa_regfile_table
,
235 (void *)"AR", (void *)cpu_R
);
236 g_hash_table_insert(xtensa_regfile_table
,
237 (void *)"MR", (void *)cpu_MR
);
238 g_hash_table_insert(xtensa_regfile_table
,
239 (void *)"FR", (void *)cpu_FR
);
240 g_hash_table_insert(xtensa_regfile_table
,
241 (void *)"BR", (void *)cpu_BR
);
242 g_hash_table_insert(xtensa_regfile_table
,
243 (void *)"BR4", (void *)cpu_BR4
);
244 g_hash_table_insert(xtensa_regfile_table
,
245 (void *)"BR8", (void *)cpu_BR8
);
247 return (void **)g_hash_table_lookup(xtensa_regfile_table
, (void *)name
);
250 static inline bool option_enabled(DisasContext
*dc
, int opt
)
252 return xtensa_option_enabled(dc
->config
, opt
);
255 static void init_sar_tracker(DisasContext
*dc
)
257 dc
->sar_5bit
= false;
258 dc
->sar_m32_5bit
= false;
259 dc
->sar_m32_allocated
= false;
262 static void reset_sar_tracker(DisasContext
*dc
)
264 if (dc
->sar_m32_allocated
) {
265 tcg_temp_free(dc
->sar_m32
);
269 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
271 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
272 if (dc
->sar_m32_5bit
) {
273 tcg_gen_discard_i32(dc
->sar_m32
);
276 dc
->sar_m32_5bit
= false;
279 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
281 TCGv_i32 tmp
= tcg_const_i32(32);
282 if (!dc
->sar_m32_allocated
) {
283 dc
->sar_m32
= tcg_temp_local_new_i32();
284 dc
->sar_m32_allocated
= true;
286 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
287 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
288 dc
->sar_5bit
= false;
289 dc
->sar_m32_5bit
= true;
293 static void gen_exception(DisasContext
*dc
, int excp
)
295 TCGv_i32 tmp
= tcg_const_i32(excp
);
296 gen_helper_exception(cpu_env
, tmp
);
300 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
302 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
303 TCGv_i32 tcause
= tcg_const_i32(cause
);
304 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
306 tcg_temp_free(tcause
);
307 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
308 cause
== SYSCALL_CAUSE
) {
309 dc
->base
.is_jmp
= DISAS_NORETURN
;
313 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
316 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
317 TCGv_i32 tcause
= tcg_const_i32(cause
);
318 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
320 tcg_temp_free(tcause
);
323 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
325 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
326 TCGv_i32 tcause
= tcg_const_i32(cause
);
327 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
329 tcg_temp_free(tcause
);
330 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
331 dc
->base
.is_jmp
= DISAS_NORETURN
;
335 static bool gen_check_privilege(DisasContext
*dc
)
337 #ifndef CONFIG_USER_ONLY
342 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
343 dc
->base
.is_jmp
= DISAS_NORETURN
;
347 static bool gen_check_cpenable(DisasContext
*dc
, uint32_t cp_mask
)
349 cp_mask
&= ~dc
->cpenable
;
351 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) && cp_mask
) {
352 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ ctz32(cp_mask
));
353 dc
->base
.is_jmp
= DISAS_NORETURN
;
359 static int gen_postprocess(DisasContext
*dc
, int slot
);
361 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
363 tcg_gen_mov_i32(cpu_pc
, dest
);
365 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
367 if (dc
->base
.singlestep_enabled
) {
368 gen_exception(dc
, EXCP_DEBUG
);
370 if (dc
->op_flags
& XTENSA_OP_POSTPROCESS
) {
371 slot
= gen_postprocess(dc
, slot
);
374 tcg_gen_goto_tb(slot
);
375 tcg_gen_exit_tb(dc
->base
.tb
, slot
);
377 tcg_gen_exit_tb(NULL
, 0);
380 dc
->base
.is_jmp
= DISAS_NORETURN
;
383 static void gen_jump(DisasContext
*dc
, TCGv dest
)
385 gen_jump_slot(dc
, dest
, -1);
388 static int adjust_jump_slot(DisasContext
*dc
, uint32_t dest
, int slot
)
390 if (((dc
->base
.pc_first
^ dest
) & TARGET_PAGE_MASK
) != 0) {
397 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
399 TCGv_i32 tmp
= tcg_const_i32(dest
);
400 gen_jump_slot(dc
, tmp
, adjust_jump_slot(dc
, dest
, slot
));
404 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
407 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
409 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
410 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
411 tcg_temp_free(tcallinc
);
412 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
413 (callinc
<< 30) | (dc
->base
.pc_next
& 0x3fffffff));
414 gen_jump_slot(dc
, dest
, slot
);
417 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
419 if (dc
->base
.pc_next
== dc
->lend
) {
420 TCGLabel
*label
= gen_new_label();
422 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
423 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
425 gen_jumpi(dc
, dc
->base
.pc_next
- dc
->lbeg_off
, slot
);
427 gen_jump(dc
, cpu_SR
[LBEG
]);
429 gen_set_label(label
);
430 gen_jumpi(dc
, dc
->base
.pc_next
, -1);
436 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
438 if (!gen_check_loop_end(dc
, slot
)) {
439 gen_jumpi(dc
, dc
->base
.pc_next
, slot
);
443 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
444 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t addr
)
446 TCGLabel
*label
= gen_new_label();
448 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
449 gen_jumpi_check_loop_end(dc
, 0);
450 gen_set_label(label
);
451 gen_jumpi(dc
, addr
, 1);
454 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
455 TCGv_i32 t0
, uint32_t t1
, uint32_t addr
)
457 TCGv_i32 tmp
= tcg_const_i32(t1
);
458 gen_brcond(dc
, cond
, t0
, tmp
, addr
);
462 static bool test_ill_sr(DisasContext
*dc
, const OpcodeArg arg
[],
463 const uint32_t par
[])
465 return !xtensa_option_enabled(dc
->config
, par
[1]);
468 static bool test_ill_ccompare(DisasContext
*dc
, const OpcodeArg arg
[],
469 const uint32_t par
[])
471 unsigned n
= par
[0] - CCOMPARE
;
473 return test_ill_sr(dc
, arg
, par
) || n
>= dc
->config
->nccompare
;
476 static bool test_ill_dbreak(DisasContext
*dc
, const OpcodeArg arg
[],
477 const uint32_t par
[])
479 unsigned n
= MAX_NDBREAK
;
481 if (par
[0] >= DBREAKA
&& par
[0] < DBREAKA
+ MAX_NDBREAK
) {
482 n
= par
[0] - DBREAKA
;
484 if (par
[0] >= DBREAKC
&& par
[0] < DBREAKC
+ MAX_NDBREAK
) {
485 n
= par
[0] - DBREAKC
;
487 return test_ill_sr(dc
, arg
, par
) || n
>= dc
->config
->ndbreak
;
490 static bool test_ill_ibreak(DisasContext
*dc
, const OpcodeArg arg
[],
491 const uint32_t par
[])
493 unsigned n
= par
[0] - IBREAKA
;
495 return test_ill_sr(dc
, arg
, par
) || n
>= dc
->config
->nibreak
;
498 static bool test_ill_hpi(DisasContext
*dc
, const OpcodeArg arg
[],
499 const uint32_t par
[])
501 unsigned n
= MAX_NLEVEL
+ 1;
503 if (par
[0] >= EXCSAVE1
&& par
[0] < EXCSAVE1
+ MAX_NLEVEL
) {
504 n
= par
[0] - EXCSAVE1
+ 1;
506 if (par
[0] >= EPC1
&& par
[0] < EPC1
+ MAX_NLEVEL
) {
507 n
= par
[0] - EPC1
+ 1;
509 if (par
[0] >= EPS2
&& par
[0] < EPS2
+ MAX_NLEVEL
- 1) {
510 n
= par
[0] - EPS2
+ 2;
512 return test_ill_sr(dc
, arg
, par
) || n
> dc
->config
->nlevel
;
515 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
516 TCGv_i32 addr
, bool no_hw_alignment
)
518 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
519 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
520 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
522 TCGLabel
*label
= gen_new_label();
523 TCGv_i32 tmp
= tcg_temp_new_i32();
524 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
525 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
526 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
527 gen_set_label(label
);
532 #ifndef CONFIG_USER_ONLY
533 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
535 TCGv_i32 pc
= tcg_const_i32(dc
->base
.pc_next
);
536 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
538 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
541 gen_helper_waiti(cpu_env
, pc
, intlevel
);
543 tcg_temp_free(intlevel
);
547 static bool gen_window_check(DisasContext
*dc
, uint32_t mask
)
549 unsigned r
= 31 - clz32(mask
);
551 if (r
/ 4 > dc
->window
) {
552 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
553 TCGv_i32 w
= tcg_const_i32(r
/ 4);
555 gen_helper_window_check(cpu_env
, pc
, w
);
556 dc
->base
.is_jmp
= DISAS_NORETURN
;
562 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
564 TCGv_i32 m
= tcg_temp_new_i32();
567 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
569 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
574 static void gen_zero_check(DisasContext
*dc
, const OpcodeArg arg
[])
576 TCGLabel
*label
= gen_new_label();
578 tcg_gen_brcondi_i32(TCG_COND_NE
, arg
[2].in
, 0, label
);
579 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
580 gen_set_label(label
);
583 static inline unsigned xtensa_op0_insn_len(DisasContext
*dc
, uint8_t op0
)
585 return xtensa_isa_length_from_chars(dc
->config
->isa
, &op0
);
588 static int gen_postprocess(DisasContext
*dc
, int slot
)
590 uint32_t op_flags
= dc
->op_flags
;
592 #ifndef CONFIG_USER_ONLY
593 if (op_flags
& XTENSA_OP_CHECK_INTERRUPTS
) {
594 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
597 gen_helper_check_interrupts(cpu_env
);
598 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
603 if (op_flags
& XTENSA_OP_SYNC_REGISTER_WINDOW
) {
604 gen_helper_sync_windowbase(cpu_env
);
606 if (op_flags
& XTENSA_OP_EXIT_TB_M1
) {
612 struct opcode_arg_copy
{
618 struct opcode_arg_info
{
624 XtensaOpcodeOps
*ops
;
625 OpcodeArg arg
[MAX_OPCODE_ARGS
];
626 struct opcode_arg_info in
[MAX_OPCODE_ARGS
];
627 struct opcode_arg_info out
[MAX_OPCODE_ARGS
];
639 static uint32_t encode_resource(enum resource_type r
, unsigned g
, unsigned n
)
641 assert(r
< RES_MAX
&& g
< 256 && n
< 65536);
642 return (r
<< 24) | (g
<< 16) | n
;
645 static enum resource_type
get_resource_type(uint32_t resource
)
647 return resource
>> 24;
651 * a depends on b if b must be executed before a,
652 * because a's side effects will destroy b's inputs.
654 static bool op_depends_on(const struct slot_prop
*a
,
655 const struct slot_prop
*b
)
660 if (a
->op_flags
& XTENSA_OP_CONTROL_FLOW
) {
663 if ((a
->op_flags
& XTENSA_OP_LOAD_STORE
) <
664 (b
->op_flags
& XTENSA_OP_LOAD_STORE
)) {
667 while (i
< a
->n_out
&& j
< b
->n_in
) {
668 if (a
->out
[i
].resource
< b
->in
[j
].resource
) {
670 } else if (a
->out
[i
].resource
> b
->in
[j
].resource
) {
680 * Try to break a dependency on b, append temporary register copy records
681 * to the end of copy and update n_copy in case of success.
682 * This is not always possible: e.g. control flow must always be the last,
683 * load/store must be first and state dependencies are not supported yet.
685 static bool break_dependency(struct slot_prop
*a
,
687 struct opcode_arg_copy
*copy
,
692 unsigned n
= *n_copy
;
695 if (a
->op_flags
& XTENSA_OP_CONTROL_FLOW
) {
698 if ((a
->op_flags
& XTENSA_OP_LOAD_STORE
) <
699 (b
->op_flags
& XTENSA_OP_LOAD_STORE
)) {
702 while (i
< a
->n_out
&& j
< b
->n_in
) {
703 if (a
->out
[i
].resource
< b
->in
[j
].resource
) {
705 } else if (a
->out
[i
].resource
> b
->in
[j
].resource
) {
708 int index
= b
->in
[j
].index
;
710 if (get_resource_type(a
->out
[i
].resource
) != RES_REGFILE
||
714 copy
[n
].resource
= b
->in
[j
].resource
;
715 copy
[n
].arg
= b
->arg
+ index
;
726 * Calculate evaluation order for slot opcodes.
727 * Build opcode order graph and output its nodes in topological sort order.
728 * An edge a -> b in the graph means that opcode a must be followed by
731 static bool tsort(struct slot_prop
*slot
,
732 struct slot_prop
*sorted
[],
734 struct opcode_arg_copy
*copy
,
740 unsigned out_edge
[MAX_INSN_SLOTS
];
741 } node
[MAX_INSN_SLOTS
];
743 unsigned in
[MAX_INSN_SLOTS
];
749 unsigned node_idx
= 0;
751 for (i
= 0; i
< n
; ++i
) {
752 node
[i
].n_in_edge
= 0;
753 node
[i
].n_out_edge
= 0;
756 for (i
= 0; i
< n
; ++i
) {
757 unsigned n_out_edge
= 0;
759 for (j
= 0; j
< n
; ++j
) {
760 if (i
!= j
&& op_depends_on(slot
+ j
, slot
+ i
)) {
761 node
[i
].out_edge
[n_out_edge
] = j
;
767 node
[i
].n_out_edge
= n_out_edge
;
770 for (i
= 0; i
< n
; ++i
) {
771 if (!node
[i
].n_in_edge
) {
778 for (; in_idx
< n_in
; ++in_idx
) {
780 sorted
[n_out
] = slot
+ i
;
782 for (j
= 0; j
< node
[i
].n_out_edge
; ++j
) {
784 if (--node
[node
[i
].out_edge
[j
]].n_in_edge
== 0) {
785 in
[n_in
] = node
[i
].out_edge
[j
];
791 for (; node_idx
< n
; ++node_idx
) {
792 struct tsnode
*cnode
= node
+ node_idx
;
794 if (cnode
->n_in_edge
) {
795 for (j
= 0; j
< cnode
->n_out_edge
; ++j
) {
796 unsigned k
= cnode
->out_edge
[j
];
798 if (break_dependency(slot
+ k
, slot
+ node_idx
,
800 --node
[k
].n_in_edge
== 0) {
805 cnode
->out_edge
[cnode
->n_out_edge
- 1];
816 static void opcode_add_resource(struct slot_prop
*op
,
817 uint32_t resource
, char direction
,
823 assert(op
->n_in
< ARRAY_SIZE(op
->in
));
824 op
->in
[op
->n_in
].resource
= resource
;
825 op
->in
[op
->n_in
].index
= index
;
829 if (direction
== 'm' || direction
== 'o') {
830 assert(op
->n_out
< ARRAY_SIZE(op
->out
));
831 op
->out
[op
->n_out
].resource
= resource
;
832 op
->out
[op
->n_out
].index
= index
;
837 g_assert_not_reached();
841 static int resource_compare(const void *a
, const void *b
)
843 const struct opcode_arg_info
*pa
= a
;
844 const struct opcode_arg_info
*pb
= b
;
846 return pa
->resource
< pb
->resource
?
847 -1 : (pa
->resource
> pb
->resource
? 1 : 0);
850 static int arg_copy_compare(const void *a
, const void *b
)
852 const struct opcode_arg_copy
*pa
= a
;
853 const struct opcode_arg_copy
*pb
= b
;
855 return pa
->resource
< pb
->resource
?
856 -1 : (pa
->resource
> pb
->resource
? 1 : 0);
859 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
861 xtensa_isa isa
= dc
->config
->isa
;
862 unsigned char b
[MAX_INSN_LENGTH
] = {cpu_ldub_code(env
, dc
->pc
)};
863 unsigned len
= xtensa_op0_insn_len(dc
, b
[0]);
867 uint32_t op_flags
= 0;
868 struct slot_prop slot_prop
[MAX_INSN_SLOTS
];
869 struct slot_prop
*ordered
[MAX_INSN_SLOTS
];
870 struct opcode_arg_copy arg_copy
[MAX_INSN_SLOTS
* MAX_OPCODE_ARGS
];
871 unsigned n_arg_copy
= 0;
872 uint32_t debug_cause
= 0;
873 uint32_t windowed_register
= 0;
874 uint32_t coprocessor
= 0;
876 if (len
== XTENSA_UNDEFINED
) {
877 qemu_log_mask(LOG_GUEST_ERROR
,
878 "unknown instruction length (pc = %08x)\n",
880 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
884 dc
->base
.pc_next
= dc
->pc
+ len
;
885 for (i
= 1; i
< len
; ++i
) {
886 b
[i
] = cpu_ldub_code(env
, dc
->pc
+ i
);
888 xtensa_insnbuf_from_chars(isa
, dc
->insnbuf
, b
, len
);
889 fmt
= xtensa_format_decode(isa
, dc
->insnbuf
);
890 if (fmt
== XTENSA_UNDEFINED
) {
891 qemu_log_mask(LOG_GUEST_ERROR
,
892 "unrecognized instruction format (pc = %08x)\n",
894 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
897 slots
= xtensa_format_num_slots(isa
, fmt
);
898 for (slot
= 0; slot
< slots
; ++slot
) {
900 int opnd
, vopnd
, opnds
;
901 OpcodeArg
*arg
= slot_prop
[slot
].arg
;
902 XtensaOpcodeOps
*ops
;
904 xtensa_format_get_slot(isa
, fmt
, slot
, dc
->insnbuf
, dc
->slotbuf
);
905 opc
= xtensa_opcode_decode(isa
, fmt
, slot
, dc
->slotbuf
);
906 if (opc
== XTENSA_UNDEFINED
) {
907 qemu_log_mask(LOG_GUEST_ERROR
,
908 "unrecognized opcode in slot %d (pc = %08x)\n",
910 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
913 opnds
= xtensa_opcode_num_operands(isa
, opc
);
915 for (opnd
= vopnd
= 0; opnd
< opnds
; ++opnd
) {
916 void **register_file
= NULL
;
918 if (xtensa_operand_is_register(isa
, opc
, opnd
)) {
919 xtensa_regfile rf
= xtensa_operand_regfile(isa
, opc
, opnd
);
921 register_file
= dc
->config
->regfile
[rf
];
923 if (rf
== dc
->config
->a_regfile
) {
926 xtensa_operand_get_field(isa
, opc
, opnd
, fmt
, slot
,
928 xtensa_operand_decode(isa
, opc
, opnd
, &v
);
929 windowed_register
|= 1u << v
;
932 if (xtensa_operand_is_visible(isa
, opc
, opnd
)) {
935 xtensa_operand_get_field(isa
, opc
, opnd
, fmt
, slot
,
937 xtensa_operand_decode(isa
, opc
, opnd
, &v
);
938 arg
[vopnd
].raw_imm
= v
;
939 if (xtensa_operand_is_PCrelative(isa
, opc
, opnd
)) {
940 xtensa_operand_undo_reloc(isa
, opc
, opnd
, &v
, dc
->pc
);
944 arg
[vopnd
].in
= register_file
[v
];
945 arg
[vopnd
].out
= register_file
[v
];
950 ops
= dc
->config
->opcode_ops
[opc
];
951 slot_prop
[slot
].ops
= ops
;
954 op_flags
|= ops
->op_flags
;
956 qemu_log_mask(LOG_UNIMP
,
957 "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
958 xtensa_opcode_name(isa
, opc
), slot
, dc
->pc
);
959 op_flags
|= XTENSA_OP_ILL
;
961 if ((op_flags
& XTENSA_OP_ILL
) ||
962 (ops
&& ops
->test_ill
&& ops
->test_ill(dc
, arg
, ops
->par
))) {
963 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
966 if (ops
->op_flags
& XTENSA_OP_DEBUG_BREAK
) {
967 debug_cause
|= ops
->par
[0];
969 if (ops
->test_overflow
) {
970 windowed_register
|= ops
->test_overflow(dc
, arg
, ops
->par
);
972 coprocessor
|= ops
->coprocessor
;
975 slot_prop
[slot
].n_in
= 0;
976 slot_prop
[slot
].n_out
= 0;
977 slot_prop
[slot
].op_flags
= ops
->op_flags
& XTENSA_OP_LOAD_STORE
;
979 opnds
= xtensa_opcode_num_operands(isa
, opc
);
981 for (opnd
= vopnd
= 0; opnd
< opnds
; ++opnd
) {
982 bool visible
= xtensa_operand_is_visible(isa
, opc
, opnd
);
984 if (xtensa_operand_is_register(isa
, opc
, opnd
)) {
985 xtensa_regfile rf
= xtensa_operand_regfile(isa
, opc
, opnd
);
988 xtensa_operand_get_field(isa
, opc
, opnd
, fmt
, slot
,
990 xtensa_operand_decode(isa
, opc
, opnd
, &v
);
991 opcode_add_resource(slot_prop
+ slot
,
992 encode_resource(RES_REGFILE
, rf
, v
),
993 xtensa_operand_inout(isa
, opc
, opnd
),
994 visible
? vopnd
: -1);
1001 opnds
= xtensa_opcode_num_stateOperands(isa
, opc
);
1003 for (opnd
= 0; opnd
< opnds
; ++opnd
) {
1004 xtensa_state state
= xtensa_stateOperand_state(isa
, opc
, opnd
);
1006 opcode_add_resource(slot_prop
+ slot
,
1007 encode_resource(RES_STATE
, 0, state
),
1008 xtensa_stateOperand_inout(isa
, opc
, opnd
),
1011 if (xtensa_opcode_is_branch(isa
, opc
) ||
1012 xtensa_opcode_is_jump(isa
, opc
) ||
1013 xtensa_opcode_is_loop(isa
, opc
) ||
1014 xtensa_opcode_is_call(isa
, opc
)) {
1015 slot_prop
[slot
].op_flags
|= XTENSA_OP_CONTROL_FLOW
;
1018 qsort(slot_prop
[slot
].in
, slot_prop
[slot
].n_in
,
1019 sizeof(slot_prop
[slot
].in
[0]), resource_compare
);
1020 qsort(slot_prop
[slot
].out
, slot_prop
[slot
].n_out
,
1021 sizeof(slot_prop
[slot
].out
[0]), resource_compare
);
1026 if (!tsort(slot_prop
, ordered
, slots
, arg_copy
, &n_arg_copy
)) {
1027 qemu_log_mask(LOG_UNIMP
,
1028 "Circular resource dependencies (pc = %08x)\n",
1030 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1034 ordered
[0] = slot_prop
+ 0;
1037 if ((op_flags
& XTENSA_OP_PRIVILEGED
) &&
1038 !gen_check_privilege(dc
)) {
1042 if (op_flags
& XTENSA_OP_SYSCALL
) {
1043 gen_exception_cause(dc
, SYSCALL_CAUSE
);
1047 if ((op_flags
& XTENSA_OP_DEBUG_BREAK
) && dc
->debug
) {
1048 gen_debug_exception(dc
, debug_cause
);
1052 if (windowed_register
&& !gen_window_check(dc
, windowed_register
)) {
1056 if (op_flags
& XTENSA_OP_UNDERFLOW
) {
1057 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
1059 gen_helper_test_underflow_retw(cpu_env
, tmp
);
1063 if (op_flags
& XTENSA_OP_ALLOCA
) {
1064 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
1066 gen_helper_movsp(cpu_env
, tmp
);
1070 if (coprocessor
&& !gen_check_cpenable(dc
, coprocessor
)) {
1079 qsort(arg_copy
, n_arg_copy
, sizeof(*arg_copy
), arg_copy_compare
);
1080 for (i
= j
= 0; i
< n_arg_copy
; ++i
) {
1081 if (i
== 0 || arg_copy
[i
].resource
!= resource
) {
1082 resource
= arg_copy
[i
].resource
;
1083 temp
= tcg_temp_local_new();
1084 tcg_gen_mov_i32(temp
, arg_copy
[i
].arg
->in
);
1085 arg_copy
[i
].temp
= temp
;
1088 arg_copy
[j
] = arg_copy
[i
];
1092 arg_copy
[i
].arg
->in
= temp
;
1097 if (op_flags
& XTENSA_OP_DIVIDE_BY_ZERO
) {
1098 for (slot
= 0; slot
< slots
; ++slot
) {
1099 if (slot_prop
[slot
].ops
->op_flags
& XTENSA_OP_DIVIDE_BY_ZERO
) {
1100 gen_zero_check(dc
, slot_prop
[slot
].arg
);
1105 dc
->op_flags
= op_flags
;
1107 for (slot
= 0; slot
< slots
; ++slot
) {
1108 struct slot_prop
*pslot
= ordered
[slot
];
1109 XtensaOpcodeOps
*ops
= pslot
->ops
;
1111 ops
->translate(dc
, pslot
->arg
, ops
->par
);
1114 for (i
= 0; i
< n_arg_copy
; ++i
) {
1115 tcg_temp_free(arg_copy
[i
].temp
);
1118 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
1119 gen_postprocess(dc
, 0);
1121 if (op_flags
& XTENSA_OP_EXIT_TB_M1
) {
1122 /* Change in mmu index, memory mapping or tb->flags; exit tb */
1123 gen_jumpi_check_loop_end(dc
, -1);
1124 } else if (op_flags
& XTENSA_OP_EXIT_TB_0
) {
1125 gen_jumpi_check_loop_end(dc
, 0);
1127 gen_check_loop_end(dc
, 0);
1130 dc
->pc
= dc
->base
.pc_next
;
1133 static inline unsigned xtensa_insn_len(CPUXtensaState
*env
, DisasContext
*dc
)
1135 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
1136 return xtensa_op0_insn_len(dc
, b0
);
1139 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
1143 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
1144 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
1145 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
1146 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
1152 static void xtensa_tr_init_disas_context(DisasContextBase
*dcbase
,
1155 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1156 CPUXtensaState
*env
= cpu
->env_ptr
;
1157 uint32_t tb_flags
= dc
->base
.tb
->flags
;
1159 dc
->config
= env
->config
;
1160 dc
->pc
= dc
->base
.pc_first
;
1161 dc
->ring
= tb_flags
& XTENSA_TBFLAG_RING_MASK
;
1162 dc
->cring
= (tb_flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
->ring
;
1163 dc
->lbeg_off
= (dc
->base
.tb
->cs_base
& XTENSA_CSBASE_LBEG_OFF_MASK
) >>
1164 XTENSA_CSBASE_LBEG_OFF_SHIFT
;
1165 dc
->lend
= (dc
->base
.tb
->cs_base
& XTENSA_CSBASE_LEND_MASK
) +
1166 (dc
->base
.pc_first
& TARGET_PAGE_MASK
);
1167 dc
->debug
= tb_flags
& XTENSA_TBFLAG_DEBUG
;
1168 dc
->icount
= tb_flags
& XTENSA_TBFLAG_ICOUNT
;
1169 dc
->cpenable
= (tb_flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
1170 XTENSA_TBFLAG_CPENABLE_SHIFT
;
1171 dc
->window
= ((tb_flags
& XTENSA_TBFLAG_WINDOW_MASK
) >>
1172 XTENSA_TBFLAG_WINDOW_SHIFT
);
1173 dc
->cwoe
= tb_flags
& XTENSA_TBFLAG_CWOE
;
1174 dc
->callinc
= ((tb_flags
& XTENSA_TBFLAG_CALLINC_MASK
) >>
1175 XTENSA_TBFLAG_CALLINC_SHIFT
);
1177 if (dc
->config
->isa
) {
1178 dc
->insnbuf
= xtensa_insnbuf_alloc(dc
->config
->isa
);
1179 dc
->slotbuf
= xtensa_insnbuf_alloc(dc
->config
->isa
);
1181 init_sar_tracker(dc
);
1184 static void xtensa_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1186 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1189 dc
->next_icount
= tcg_temp_local_new_i32();
1193 static void xtensa_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1195 tcg_gen_insn_start(dcbase
->pc_next
);
1198 static bool xtensa_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
1199 const CPUBreakpoint
*bp
)
1201 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1203 tcg_gen_movi_i32(cpu_pc
, dc
->base
.pc_next
);
1204 gen_exception(dc
, EXCP_DEBUG
);
1205 dc
->base
.is_jmp
= DISAS_NORETURN
;
1206 /* The address covered by the breakpoint must be included in
1207 [tb->pc, tb->pc + tb->size) in order to for it to be
1208 properly cleared -- thus we increment the PC here so that
1209 the logic setting tb->size below does the right thing. */
1210 dc
->base
.pc_next
+= 2;
1214 static void xtensa_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1216 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1217 CPUXtensaState
*env
= cpu
->env_ptr
;
1218 target_ulong page_start
;
1220 /* These two conditions only apply to the first insn in the TB,
1221 but this is the first TranslateOps hook that allows exiting. */
1222 if ((tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
)
1223 && (dc
->base
.tb
->flags
& XTENSA_TBFLAG_YIELD
)) {
1224 gen_exception(dc
, EXCP_YIELD
);
1225 dc
->base
.is_jmp
= DISAS_NORETURN
;
1228 if (dc
->base
.tb
->flags
& XTENSA_TBFLAG_EXCEPTION
) {
1229 gen_exception(dc
, EXCP_DEBUG
);
1230 dc
->base
.is_jmp
= DISAS_NORETURN
;
1235 TCGLabel
*label
= gen_new_label();
1237 tcg_gen_addi_i32(dc
->next_icount
, cpu_SR
[ICOUNT
], 1);
1238 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
->next_icount
, 0, label
);
1239 tcg_gen_mov_i32(dc
->next_icount
, cpu_SR
[ICOUNT
]);
1241 gen_debug_exception(dc
, DEBUGCAUSE_IC
);
1243 gen_set_label(label
);
1247 gen_ibreak_check(env
, dc
);
1250 disas_xtensa_insn(env
, dc
);
1253 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
1256 /* End the TB if the next insn will cross into the next page. */
1257 page_start
= dc
->base
.pc_first
& TARGET_PAGE_MASK
;
1258 if (dc
->base
.is_jmp
== DISAS_NEXT
&&
1259 (dc
->pc
- page_start
>= TARGET_PAGE_SIZE
||
1260 dc
->pc
- page_start
+ xtensa_insn_len(env
, dc
) > TARGET_PAGE_SIZE
)) {
1261 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
1265 static void xtensa_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1267 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1269 reset_sar_tracker(dc
);
1270 if (dc
->config
->isa
) {
1271 xtensa_insnbuf_free(dc
->config
->isa
, dc
->insnbuf
);
1272 xtensa_insnbuf_free(dc
->config
->isa
, dc
->slotbuf
);
1275 tcg_temp_free(dc
->next_icount
);
1278 switch (dc
->base
.is_jmp
) {
1279 case DISAS_NORETURN
:
1281 case DISAS_TOO_MANY
:
1282 if (dc
->base
.singlestep_enabled
) {
1283 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1284 gen_exception(dc
, EXCP_DEBUG
);
1286 gen_jumpi(dc
, dc
->pc
, 0);
1290 g_assert_not_reached();
1294 static void xtensa_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
1296 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1297 log_target_disas(cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1300 static const TranslatorOps xtensa_translator_ops
= {
1301 .init_disas_context
= xtensa_tr_init_disas_context
,
1302 .tb_start
= xtensa_tr_tb_start
,
1303 .insn_start
= xtensa_tr_insn_start
,
1304 .breakpoint_check
= xtensa_tr_breakpoint_check
,
1305 .translate_insn
= xtensa_tr_translate_insn
,
1306 .tb_stop
= xtensa_tr_tb_stop
,
1307 .disas_log
= xtensa_tr_disas_log
,
1310 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
, int max_insns
)
1312 DisasContext dc
= {};
1313 translator_loop(&xtensa_translator_ops
, &dc
.base
, cpu
, tb
, max_insns
);
1316 void xtensa_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1318 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
1319 CPUXtensaState
*env
= &cpu
->env
;
1320 xtensa_isa isa
= env
->config
->isa
;
1323 qemu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
1325 for (i
= j
= 0; i
< xtensa_isa_num_sysregs(isa
); ++i
) {
1326 const uint32_t *reg
=
1327 xtensa_sysreg_is_user(isa
, i
) ? env
->uregs
: env
->sregs
;
1328 int regno
= xtensa_sysreg_number(isa
, i
);
1331 qemu_fprintf(f
, "%12s=%08x%c",
1332 xtensa_sysreg_name(isa
, i
),
1334 (j
++ % 4) == 3 ? '\n' : ' ');
1338 qemu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1340 for (i
= 0; i
< 16; ++i
) {
1341 qemu_fprintf(f
, " A%02d=%08x%c",
1342 i
, env
->regs
[i
], (i
% 4) == 3 ? '\n' : ' ');
1345 xtensa_sync_phys_from_window(env
);
1346 qemu_fprintf(f
, "\n");
1348 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
1349 qemu_fprintf(f
, "AR%02d=%08x ", i
, env
->phys_regs
[i
]);
1351 bool ws
= (env
->sregs
[WINDOW_START
] & (1 << (i
/ 4))) != 0;
1352 bool cw
= env
->sregs
[WINDOW_BASE
] == i
/ 4;
1354 qemu_fprintf(f
, "%c%c\n", ws
? '<' : ' ', cw
? '=' : ' ');
1358 if ((flags
& CPU_DUMP_FPU
) &&
1359 xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
1360 qemu_fprintf(f
, "\n");
1362 for (i
= 0; i
< 16; ++i
) {
1363 qemu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
1364 float32_val(env
->fregs
[i
].f32
[FP_F32_LOW
]),
1365 *(float *)(env
->fregs
[i
].f32
+ FP_F32_LOW
),
1366 (i
% 2) == 1 ? '\n' : ' ');
1371 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
,
1377 static void translate_abs(DisasContext
*dc
, const OpcodeArg arg
[],
1378 const uint32_t par
[])
1380 tcg_gen_abs_i32(arg
[0].out
, arg
[1].in
);
1383 static void translate_add(DisasContext
*dc
, const OpcodeArg arg
[],
1384 const uint32_t par
[])
1386 tcg_gen_add_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1389 static void translate_addi(DisasContext
*dc
, const OpcodeArg arg
[],
1390 const uint32_t par
[])
1392 tcg_gen_addi_i32(arg
[0].out
, arg
[1].in
, arg
[2].imm
);
1395 static void translate_addx(DisasContext
*dc
, const OpcodeArg arg
[],
1396 const uint32_t par
[])
1398 TCGv_i32 tmp
= tcg_temp_new_i32();
1399 tcg_gen_shli_i32(tmp
, arg
[1].in
, par
[0]);
1400 tcg_gen_add_i32(arg
[0].out
, tmp
, arg
[2].in
);
1404 static void translate_all(DisasContext
*dc
, const OpcodeArg arg
[],
1405 const uint32_t par
[])
1407 uint32_t shift
= par
[1];
1408 TCGv_i32 mask
= tcg_const_i32(((1 << shift
) - 1) << arg
[1].imm
);
1409 TCGv_i32 tmp
= tcg_temp_new_i32();
1411 tcg_gen_and_i32(tmp
, arg
[1].in
, mask
);
1413 tcg_gen_addi_i32(tmp
, tmp
, 1 << arg
[1].imm
);
1415 tcg_gen_add_i32(tmp
, tmp
, mask
);
1417 tcg_gen_shri_i32(tmp
, tmp
, arg
[1].imm
+ shift
);
1418 tcg_gen_deposit_i32(arg
[0].out
, arg
[0].out
,
1419 tmp
, arg
[0].imm
, 1);
1420 tcg_temp_free(mask
);
1424 static void translate_and(DisasContext
*dc
, const OpcodeArg arg
[],
1425 const uint32_t par
[])
1427 tcg_gen_and_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1430 static void translate_ball(DisasContext
*dc
, const OpcodeArg arg
[],
1431 const uint32_t par
[])
1433 TCGv_i32 tmp
= tcg_temp_new_i32();
1434 tcg_gen_and_i32(tmp
, arg
[0].in
, arg
[1].in
);
1435 gen_brcond(dc
, par
[0], tmp
, arg
[1].in
, arg
[2].imm
);
1439 static void translate_bany(DisasContext
*dc
, const OpcodeArg arg
[],
1440 const uint32_t par
[])
1442 TCGv_i32 tmp
= tcg_temp_new_i32();
1443 tcg_gen_and_i32(tmp
, arg
[0].in
, arg
[1].in
);
1444 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2].imm
);
1448 static void translate_b(DisasContext
*dc
, const OpcodeArg arg
[],
1449 const uint32_t par
[])
1451 gen_brcond(dc
, par
[0], arg
[0].in
, arg
[1].in
, arg
[2].imm
);
1454 static void translate_bb(DisasContext
*dc
, const OpcodeArg arg
[],
1455 const uint32_t par
[])
1457 #ifdef TARGET_WORDS_BIGENDIAN
1458 TCGv_i32 bit
= tcg_const_i32(0x80000000u
);
1460 TCGv_i32 bit
= tcg_const_i32(0x00000001u
);
1462 TCGv_i32 tmp
= tcg_temp_new_i32();
1463 tcg_gen_andi_i32(tmp
, arg
[1].in
, 0x1f);
1464 #ifdef TARGET_WORDS_BIGENDIAN
1465 tcg_gen_shr_i32(bit
, bit
, tmp
);
1467 tcg_gen_shl_i32(bit
, bit
, tmp
);
1469 tcg_gen_and_i32(tmp
, arg
[0].in
, bit
);
1470 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2].imm
);
1475 static void translate_bbi(DisasContext
*dc
, const OpcodeArg arg
[],
1476 const uint32_t par
[])
1478 TCGv_i32 tmp
= tcg_temp_new_i32();
1479 #ifdef TARGET_WORDS_BIGENDIAN
1480 tcg_gen_andi_i32(tmp
, arg
[0].in
, 0x80000000u
>> arg
[1].imm
);
1482 tcg_gen_andi_i32(tmp
, arg
[0].in
, 0x00000001u
<< arg
[1].imm
);
1484 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2].imm
);
1488 static void translate_bi(DisasContext
*dc
, const OpcodeArg arg
[],
1489 const uint32_t par
[])
1491 gen_brcondi(dc
, par
[0], arg
[0].in
, arg
[1].imm
, arg
[2].imm
);
1494 static void translate_bz(DisasContext
*dc
, const OpcodeArg arg
[],
1495 const uint32_t par
[])
1497 gen_brcondi(dc
, par
[0], arg
[0].in
, 0, arg
[1].imm
);
1508 static void translate_boolean(DisasContext
*dc
, const OpcodeArg arg
[],
1509 const uint32_t par
[])
1511 static void (* const op
[])(TCGv_i32
, TCGv_i32
, TCGv_i32
) = {
1512 [BOOLEAN_AND
] = tcg_gen_and_i32
,
1513 [BOOLEAN_ANDC
] = tcg_gen_andc_i32
,
1514 [BOOLEAN_OR
] = tcg_gen_or_i32
,
1515 [BOOLEAN_ORC
] = tcg_gen_orc_i32
,
1516 [BOOLEAN_XOR
] = tcg_gen_xor_i32
,
1519 TCGv_i32 tmp1
= tcg_temp_new_i32();
1520 TCGv_i32 tmp2
= tcg_temp_new_i32();
1522 tcg_gen_shri_i32(tmp1
, arg
[1].in
, arg
[1].imm
);
1523 tcg_gen_shri_i32(tmp2
, arg
[2].in
, arg
[2].imm
);
1524 op
[par
[0]](tmp1
, tmp1
, tmp2
);
1525 tcg_gen_deposit_i32(arg
[0].out
, arg
[0].out
, tmp1
, arg
[0].imm
, 1);
1526 tcg_temp_free(tmp1
);
1527 tcg_temp_free(tmp2
);
1530 static void translate_bp(DisasContext
*dc
, const OpcodeArg arg
[],
1531 const uint32_t par
[])
1533 TCGv_i32 tmp
= tcg_temp_new_i32();
1535 tcg_gen_andi_i32(tmp
, arg
[0].in
, 1 << arg
[0].imm
);
1536 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[1].imm
);
1540 static void translate_call0(DisasContext
*dc
, const OpcodeArg arg
[],
1541 const uint32_t par
[])
1543 tcg_gen_movi_i32(cpu_R
[0], dc
->base
.pc_next
);
1544 gen_jumpi(dc
, arg
[0].imm
, 0);
1547 static void translate_callw(DisasContext
*dc
, const OpcodeArg arg
[],
1548 const uint32_t par
[])
1550 TCGv_i32 tmp
= tcg_const_i32(arg
[0].imm
);
1551 gen_callw_slot(dc
, par
[0], tmp
, adjust_jump_slot(dc
, arg
[0].imm
, 0));
1555 static void translate_callx0(DisasContext
*dc
, const OpcodeArg arg
[],
1556 const uint32_t par
[])
1558 TCGv_i32 tmp
= tcg_temp_new_i32();
1559 tcg_gen_mov_i32(tmp
, arg
[0].in
);
1560 tcg_gen_movi_i32(cpu_R
[0], dc
->base
.pc_next
);
1565 static void translate_callxw(DisasContext
*dc
, const OpcodeArg arg
[],
1566 const uint32_t par
[])
1568 TCGv_i32 tmp
= tcg_temp_new_i32();
1570 tcg_gen_mov_i32(tmp
, arg
[0].in
);
1571 gen_callw_slot(dc
, par
[0], tmp
, -1);
1575 static void translate_clamps(DisasContext
*dc
, const OpcodeArg arg
[],
1576 const uint32_t par
[])
1578 TCGv_i32 tmp1
= tcg_const_i32(-1u << arg
[2].imm
);
1579 TCGv_i32 tmp2
= tcg_const_i32((1 << arg
[2].imm
) - 1);
1581 tcg_gen_smax_i32(tmp1
, tmp1
, arg
[1].in
);
1582 tcg_gen_smin_i32(arg
[0].out
, tmp1
, tmp2
);
1583 tcg_temp_free(tmp1
);
1584 tcg_temp_free(tmp2
);
1587 static void translate_clrb_expstate(DisasContext
*dc
, const OpcodeArg arg
[],
1588 const uint32_t par
[])
1590 /* TODO: GPIO32 may be a part of coprocessor */
1591 tcg_gen_andi_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], ~(1u << arg
[0].imm
));
1594 static void translate_clrex(DisasContext
*dc
, const OpcodeArg arg
[],
1595 const uint32_t par
[])
1597 tcg_gen_movi_i32(cpu_exclusive_addr
, -1);
1600 static void translate_const16(DisasContext
*dc
, const OpcodeArg arg
[],
1601 const uint32_t par
[])
1603 TCGv_i32 c
= tcg_const_i32(arg
[1].imm
);
1605 tcg_gen_deposit_i32(arg
[0].out
, c
, arg
[0].in
, 16, 16);
1609 static void translate_dcache(DisasContext
*dc
, const OpcodeArg arg
[],
1610 const uint32_t par
[])
1612 TCGv_i32 addr
= tcg_temp_new_i32();
1613 TCGv_i32 res
= tcg_temp_new_i32();
1615 tcg_gen_addi_i32(addr
, arg
[0].in
, arg
[1].imm
);
1616 tcg_gen_qemu_ld8u(res
, addr
, dc
->cring
);
1617 tcg_temp_free(addr
);
1621 static void translate_depbits(DisasContext
*dc
, const OpcodeArg arg
[],
1622 const uint32_t par
[])
1624 tcg_gen_deposit_i32(arg
[1].out
, arg
[1].in
, arg
[0].in
,
1625 arg
[2].imm
, arg
[3].imm
);
1628 static void translate_diwbuip(DisasContext
*dc
, const OpcodeArg arg
[],
1629 const uint32_t par
[])
1631 tcg_gen_addi_i32(arg
[0].out
, arg
[0].in
, dc
->config
->dcache_line_bytes
);
1634 static bool test_ill_entry(DisasContext
*dc
, const OpcodeArg arg
[],
1635 const uint32_t par
[])
1637 if (arg
[0].imm
> 3 || !dc
->cwoe
) {
1638 qemu_log_mask(LOG_GUEST_ERROR
,
1639 "Illegal entry instruction(pc = %08x)\n", dc
->pc
);
1646 static uint32_t test_overflow_entry(DisasContext
*dc
, const OpcodeArg arg
[],
1647 const uint32_t par
[])
1649 return 1 << (dc
->callinc
* 4);
1652 static void translate_entry(DisasContext
*dc
, const OpcodeArg arg
[],
1653 const uint32_t par
[])
1655 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1656 TCGv_i32 s
= tcg_const_i32(arg
[0].imm
);
1657 TCGv_i32 imm
= tcg_const_i32(arg
[1].imm
);
1658 gen_helper_entry(cpu_env
, pc
, s
, imm
);
1664 static void translate_extui(DisasContext
*dc
, const OpcodeArg arg
[],
1665 const uint32_t par
[])
1667 int maskimm
= (1 << arg
[3].imm
) - 1;
1669 TCGv_i32 tmp
= tcg_temp_new_i32();
1670 tcg_gen_shri_i32(tmp
, arg
[1].in
, arg
[2].imm
);
1671 tcg_gen_andi_i32(arg
[0].out
, tmp
, maskimm
);
1675 static void translate_getex(DisasContext
*dc
, const OpcodeArg arg
[],
1676 const uint32_t par
[])
1678 TCGv_i32 tmp
= tcg_temp_new_i32();
1680 tcg_gen_extract_i32(tmp
, cpu_SR
[ATOMCTL
], 8, 1);
1681 tcg_gen_deposit_i32(cpu_SR
[ATOMCTL
], cpu_SR
[ATOMCTL
], arg
[0].in
, 8, 1);
1682 tcg_gen_mov_i32(arg
[0].out
, tmp
);
1686 static void translate_icache(DisasContext
*dc
, const OpcodeArg arg
[],
1687 const uint32_t par
[])
1689 #ifndef CONFIG_USER_ONLY
1690 TCGv_i32 addr
= tcg_temp_new_i32();
1692 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1693 tcg_gen_addi_i32(addr
, arg
[0].in
, arg
[1].imm
);
1694 gen_helper_itlb_hit_test(cpu_env
, addr
);
1695 tcg_temp_free(addr
);
1699 static void translate_itlb(DisasContext
*dc
, const OpcodeArg arg
[],
1700 const uint32_t par
[])
1702 #ifndef CONFIG_USER_ONLY
1703 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
1705 gen_helper_itlb(cpu_env
, arg
[0].in
, dtlb
);
1706 tcg_temp_free(dtlb
);
1710 static void translate_j(DisasContext
*dc
, const OpcodeArg arg
[],
1711 const uint32_t par
[])
1713 gen_jumpi(dc
, arg
[0].imm
, 0);
1716 static void translate_jx(DisasContext
*dc
, const OpcodeArg arg
[],
1717 const uint32_t par
[])
1719 gen_jump(dc
, arg
[0].in
);
1722 static void translate_l32e(DisasContext
*dc
, const OpcodeArg arg
[],
1723 const uint32_t par
[])
1725 TCGv_i32 addr
= tcg_temp_new_i32();
1727 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
1728 gen_load_store_alignment(dc
, 2, addr
, false);
1729 tcg_gen_qemu_ld_tl(arg
[0].out
, addr
, dc
->ring
, MO_TEUL
);
1730 tcg_temp_free(addr
);
1733 #ifdef CONFIG_USER_ONLY
1734 static void gen_check_exclusive(DisasContext
*dc
, TCGv_i32 addr
, bool is_write
)
1738 static void gen_check_exclusive(DisasContext
*dc
, TCGv_i32 addr
, bool is_write
)
1740 if (!option_enabled(dc
, XTENSA_OPTION_MPU
)) {
1741 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
1742 TCGv_i32 write
= tcg_const_i32(is_write
);
1744 gen_helper_check_exclusive(cpu_env
, tpc
, addr
, write
);
1746 tcg_temp_free(write
);
1751 static void translate_l32ex(DisasContext
*dc
, const OpcodeArg arg
[],
1752 const uint32_t par
[])
1754 TCGv_i32 addr
= tcg_temp_new_i32();
1756 tcg_gen_mov_i32(addr
, arg
[1].in
);
1757 gen_load_store_alignment(dc
, 2, addr
, true);
1758 gen_check_exclusive(dc
, addr
, false);
1759 tcg_gen_qemu_ld_i32(arg
[0].out
, addr
, dc
->ring
, MO_TEUL
);
1760 tcg_gen_mov_i32(cpu_exclusive_addr
, addr
);
1761 tcg_gen_mov_i32(cpu_exclusive_val
, arg
[0].out
);
1762 tcg_temp_free(addr
);
1765 static void translate_ldst(DisasContext
*dc
, const OpcodeArg arg
[],
1766 const uint32_t par
[])
1768 TCGv_i32 addr
= tcg_temp_new_i32();
1770 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
1771 if (par
[0] & MO_SIZE
) {
1772 gen_load_store_alignment(dc
, par
[0] & MO_SIZE
, addr
, par
[1]);
1776 tcg_gen_mb(TCG_BAR_STRL
| TCG_MO_ALL
);
1778 tcg_gen_qemu_st_tl(arg
[0].in
, addr
, dc
->cring
, par
[0]);
1780 tcg_gen_qemu_ld_tl(arg
[0].out
, addr
, dc
->cring
, par
[0]);
1782 tcg_gen_mb(TCG_BAR_LDAQ
| TCG_MO_ALL
);
1785 tcg_temp_free(addr
);
1788 static void translate_l32r(DisasContext
*dc
, const OpcodeArg arg
[],
1789 const uint32_t par
[])
1793 if (dc
->base
.tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
1794 tmp
= tcg_const_i32(arg
[1].raw_imm
- 1);
1795 tcg_gen_add_i32(tmp
, cpu_SR
[LITBASE
], tmp
);
1797 tmp
= tcg_const_i32(arg
[1].imm
);
1799 tcg_gen_qemu_ld32u(arg
[0].out
, tmp
, dc
->cring
);
1803 static void translate_loop(DisasContext
*dc
, const OpcodeArg arg
[],
1804 const uint32_t par
[])
1806 uint32_t lend
= arg
[1].imm
;
1808 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], arg
[0].in
, 1);
1809 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->base
.pc_next
);
1810 tcg_gen_movi_i32(cpu_SR
[LEND
], lend
);
1812 if (par
[0] != TCG_COND_NEVER
) {
1813 TCGLabel
*label
= gen_new_label();
1814 tcg_gen_brcondi_i32(par
[0], arg
[0].in
, 0, label
);
1815 gen_jumpi(dc
, lend
, 1);
1816 gen_set_label(label
);
1819 gen_jumpi(dc
, dc
->base
.pc_next
, 0);
1840 static void translate_mac16(DisasContext
*dc
, const OpcodeArg arg
[],
1841 const uint32_t par
[])
1844 unsigned half
= par
[1];
1845 uint32_t ld_offset
= par
[2];
1846 unsigned off
= ld_offset
? 2 : 0;
1847 TCGv_i32 vaddr
= tcg_temp_new_i32();
1848 TCGv_i32 mem32
= tcg_temp_new_i32();
1851 tcg_gen_addi_i32(vaddr
, arg
[1].in
, ld_offset
);
1852 gen_load_store_alignment(dc
, 2, vaddr
, false);
1853 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
1855 if (op
!= MAC16_NONE
) {
1856 TCGv_i32 m1
= gen_mac16_m(arg
[off
].in
,
1857 half
& MAC16_HX
, op
== MAC16_UMUL
);
1858 TCGv_i32 m2
= gen_mac16_m(arg
[off
+ 1].in
,
1859 half
& MAC16_XH
, op
== MAC16_UMUL
);
1861 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
1862 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
1863 if (op
== MAC16_UMUL
) {
1864 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
1866 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
1869 TCGv_i32 lo
= tcg_temp_new_i32();
1870 TCGv_i32 hi
= tcg_temp_new_i32();
1872 tcg_gen_mul_i32(lo
, m1
, m2
);
1873 tcg_gen_sari_i32(hi
, lo
, 31);
1874 if (op
== MAC16_MULA
) {
1875 tcg_gen_add2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1876 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1879 tcg_gen_sub2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1880 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1883 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
1885 tcg_temp_free_i32(lo
);
1886 tcg_temp_free_i32(hi
);
1892 tcg_gen_mov_i32(arg
[1].out
, vaddr
);
1893 tcg_gen_mov_i32(cpu_SR
[MR
+ arg
[0].imm
], mem32
);
1895 tcg_temp_free(vaddr
);
1896 tcg_temp_free(mem32
);
1899 static void translate_memw(DisasContext
*dc
, const OpcodeArg arg
[],
1900 const uint32_t par
[])
1902 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
1905 static void translate_smin(DisasContext
*dc
, const OpcodeArg arg
[],
1906 const uint32_t par
[])
1908 tcg_gen_smin_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1911 static void translate_umin(DisasContext
*dc
, const OpcodeArg arg
[],
1912 const uint32_t par
[])
1914 tcg_gen_umin_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1917 static void translate_smax(DisasContext
*dc
, const OpcodeArg arg
[],
1918 const uint32_t par
[])
1920 tcg_gen_smax_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1923 static void translate_umax(DisasContext
*dc
, const OpcodeArg arg
[],
1924 const uint32_t par
[])
1926 tcg_gen_umax_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1929 static void translate_mov(DisasContext
*dc
, const OpcodeArg arg
[],
1930 const uint32_t par
[])
1932 tcg_gen_mov_i32(arg
[0].out
, arg
[1].in
);
1935 static void translate_movcond(DisasContext
*dc
, const OpcodeArg arg
[],
1936 const uint32_t par
[])
1938 TCGv_i32 zero
= tcg_const_i32(0);
1940 tcg_gen_movcond_i32(par
[0], arg
[0].out
,
1941 arg
[2].in
, zero
, arg
[1].in
, arg
[0].in
);
1942 tcg_temp_free(zero
);
1945 static void translate_movi(DisasContext
*dc
, const OpcodeArg arg
[],
1946 const uint32_t par
[])
1948 tcg_gen_movi_i32(arg
[0].out
, arg
[1].imm
);
1951 static void translate_movp(DisasContext
*dc
, const OpcodeArg arg
[],
1952 const uint32_t par
[])
1954 TCGv_i32 zero
= tcg_const_i32(0);
1955 TCGv_i32 tmp
= tcg_temp_new_i32();
1957 tcg_gen_andi_i32(tmp
, arg
[2].in
, 1 << arg
[2].imm
);
1958 tcg_gen_movcond_i32(par
[0],
1959 arg
[0].out
, tmp
, zero
,
1960 arg
[1].in
, arg
[0].in
);
1962 tcg_temp_free(zero
);
1965 static void translate_movsp(DisasContext
*dc
, const OpcodeArg arg
[],
1966 const uint32_t par
[])
1968 tcg_gen_mov_i32(arg
[0].out
, arg
[1].in
);
1971 static void translate_mul16(DisasContext
*dc
, const OpcodeArg arg
[],
1972 const uint32_t par
[])
1974 TCGv_i32 v1
= tcg_temp_new_i32();
1975 TCGv_i32 v2
= tcg_temp_new_i32();
1978 tcg_gen_ext16s_i32(v1
, arg
[1].in
);
1979 tcg_gen_ext16s_i32(v2
, arg
[2].in
);
1981 tcg_gen_ext16u_i32(v1
, arg
[1].in
);
1982 tcg_gen_ext16u_i32(v2
, arg
[2].in
);
1984 tcg_gen_mul_i32(arg
[0].out
, v1
, v2
);
1989 static void translate_mull(DisasContext
*dc
, const OpcodeArg arg
[],
1990 const uint32_t par
[])
1992 tcg_gen_mul_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1995 static void translate_mulh(DisasContext
*dc
, const OpcodeArg arg
[],
1996 const uint32_t par
[])
1998 TCGv_i32 lo
= tcg_temp_new();
2001 tcg_gen_muls2_i32(lo
, arg
[0].out
, arg
[1].in
, arg
[2].in
);
2003 tcg_gen_mulu2_i32(lo
, arg
[0].out
, arg
[1].in
, arg
[2].in
);
2008 static void translate_neg(DisasContext
*dc
, const OpcodeArg arg
[],
2009 const uint32_t par
[])
2011 tcg_gen_neg_i32(arg
[0].out
, arg
[1].in
);
2014 static void translate_nop(DisasContext
*dc
, const OpcodeArg arg
[],
2015 const uint32_t par
[])
2019 static void translate_nsa(DisasContext
*dc
, const OpcodeArg arg
[],
2020 const uint32_t par
[])
2022 tcg_gen_clrsb_i32(arg
[0].out
, arg
[1].in
);
2025 static void translate_nsau(DisasContext
*dc
, const OpcodeArg arg
[],
2026 const uint32_t par
[])
2028 tcg_gen_clzi_i32(arg
[0].out
, arg
[1].in
, 32);
2031 static void translate_or(DisasContext
*dc
, const OpcodeArg arg
[],
2032 const uint32_t par
[])
2034 tcg_gen_or_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
2037 static void translate_ptlb(DisasContext
*dc
, const OpcodeArg arg
[],
2038 const uint32_t par
[])
2040 #ifndef CONFIG_USER_ONLY
2041 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2043 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2044 gen_helper_ptlb(arg
[0].out
, cpu_env
, arg
[1].in
, dtlb
);
2045 tcg_temp_free(dtlb
);
2049 static void translate_pptlb(DisasContext
*dc
, const OpcodeArg arg
[],
2050 const uint32_t par
[])
2052 #ifndef CONFIG_USER_ONLY
2053 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
2054 gen_helper_pptlb(arg
[0].out
, cpu_env
, arg
[1].in
);
2058 static void translate_quos(DisasContext
*dc
, const OpcodeArg arg
[],
2059 const uint32_t par
[])
2061 TCGLabel
*label1
= gen_new_label();
2062 TCGLabel
*label2
= gen_new_label();
2064 tcg_gen_brcondi_i32(TCG_COND_NE
, arg
[1].in
, 0x80000000,
2066 tcg_gen_brcondi_i32(TCG_COND_NE
, arg
[2].in
, 0xffffffff,
2068 tcg_gen_movi_i32(arg
[0].out
,
2069 par
[0] ? 0x80000000 : 0);
2071 gen_set_label(label1
);
2073 tcg_gen_div_i32(arg
[0].out
,
2074 arg
[1].in
, arg
[2].in
);
2076 tcg_gen_rem_i32(arg
[0].out
,
2077 arg
[1].in
, arg
[2].in
);
2079 gen_set_label(label2
);
2082 static void translate_quou(DisasContext
*dc
, const OpcodeArg arg
[],
2083 const uint32_t par
[])
2085 tcg_gen_divu_i32(arg
[0].out
,
2086 arg
[1].in
, arg
[2].in
);
2089 static void translate_read_impwire(DisasContext
*dc
, const OpcodeArg arg
[],
2090 const uint32_t par
[])
2092 /* TODO: GPIO32 may be a part of coprocessor */
2093 tcg_gen_movi_i32(arg
[0].out
, 0);
2096 static void translate_remu(DisasContext
*dc
, const OpcodeArg arg
[],
2097 const uint32_t par
[])
2099 tcg_gen_remu_i32(arg
[0].out
,
2100 arg
[1].in
, arg
[2].in
);
2103 static void translate_rer(DisasContext
*dc
, const OpcodeArg arg
[],
2104 const uint32_t par
[])
2106 gen_helper_rer(arg
[0].out
, cpu_env
, arg
[1].in
);
2109 static void translate_ret(DisasContext
*dc
, const OpcodeArg arg
[],
2110 const uint32_t par
[])
2112 gen_jump(dc
, cpu_R
[0]);
2115 static bool test_ill_retw(DisasContext
*dc
, const OpcodeArg arg
[],
2116 const uint32_t par
[])
2119 qemu_log_mask(LOG_GUEST_ERROR
,
2120 "Illegal retw instruction(pc = %08x)\n", dc
->pc
);
2123 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2125 gen_helper_test_ill_retw(cpu_env
, tmp
);
2131 static void translate_retw(DisasContext
*dc
, const OpcodeArg arg
[],
2132 const uint32_t par
[])
2134 TCGv_i32 tmp
= tcg_const_i32(1);
2135 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
2136 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
2137 cpu_SR
[WINDOW_START
], tmp
);
2138 tcg_gen_movi_i32(tmp
, dc
->pc
);
2139 tcg_gen_deposit_i32(tmp
, tmp
, cpu_R
[0], 0, 30);
2140 gen_helper_retw(cpu_env
, cpu_R
[0]);
2145 static void translate_rfde(DisasContext
*dc
, const OpcodeArg arg
[],
2146 const uint32_t par
[])
2148 gen_jump(dc
, cpu_SR
[dc
->config
->ndepc
? DEPC
: EPC1
]);
2151 static void translate_rfe(DisasContext
*dc
, const OpcodeArg arg
[],
2152 const uint32_t par
[])
2154 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2155 gen_jump(dc
, cpu_SR
[EPC1
]);
2158 static void translate_rfi(DisasContext
*dc
, const OpcodeArg arg
[],
2159 const uint32_t par
[])
2161 tcg_gen_mov_i32(cpu_SR
[PS
], cpu_SR
[EPS2
+ arg
[0].imm
- 2]);
2162 gen_jump(dc
, cpu_SR
[EPC1
+ arg
[0].imm
- 1]);
2165 static void translate_rfw(DisasContext
*dc
, const OpcodeArg arg
[],
2166 const uint32_t par
[])
2168 TCGv_i32 tmp
= tcg_const_i32(1);
2170 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2171 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
2174 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
2175 cpu_SR
[WINDOW_START
], tmp
);
2177 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
2178 cpu_SR
[WINDOW_START
], tmp
);
2182 gen_helper_restore_owb(cpu_env
);
2183 gen_jump(dc
, cpu_SR
[EPC1
]);
2186 static void translate_rotw(DisasContext
*dc
, const OpcodeArg arg
[],
2187 const uint32_t par
[])
2189 tcg_gen_addi_i32(cpu_windowbase_next
, cpu_SR
[WINDOW_BASE
], arg
[0].imm
);
2192 static void translate_rsil(DisasContext
*dc
, const OpcodeArg arg
[],
2193 const uint32_t par
[])
2195 tcg_gen_mov_i32(arg
[0].out
, cpu_SR
[PS
]);
2196 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
2197 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], arg
[1].imm
);
2200 static void translate_rsr(DisasContext
*dc
, const OpcodeArg arg
[],
2201 const uint32_t par
[])
2203 tcg_gen_mov_i32(arg
[0].out
, cpu_SR
[par
[0]]);
2206 static void translate_rsr_ccount(DisasContext
*dc
, const OpcodeArg arg
[],
2207 const uint32_t par
[])
2209 #ifndef CONFIG_USER_ONLY
2210 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
2213 gen_helper_update_ccount(cpu_env
);
2214 tcg_gen_mov_i32(arg
[0].out
, cpu_SR
[par
[0]]);
2218 static void translate_rsr_ptevaddr(DisasContext
*dc
, const OpcodeArg arg
[],
2219 const uint32_t par
[])
2221 #ifndef CONFIG_USER_ONLY
2222 TCGv_i32 tmp
= tcg_temp_new_i32();
2224 tcg_gen_shri_i32(tmp
, cpu_SR
[EXCVADDR
], 10);
2225 tcg_gen_or_i32(tmp
, tmp
, cpu_SR
[PTEVADDR
]);
2226 tcg_gen_andi_i32(arg
[0].out
, tmp
, 0xfffffffc);
2231 static void translate_rtlb(DisasContext
*dc
, const OpcodeArg arg
[],
2232 const uint32_t par
[])
2234 #ifndef CONFIG_USER_ONLY
2235 static void (* const helper
[])(TCGv_i32 r
, TCGv_env env
, TCGv_i32 a1
,
2240 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2242 helper
[par
[1]](arg
[0].out
, cpu_env
, arg
[1].in
, dtlb
);
2243 tcg_temp_free(dtlb
);
2247 static void translate_rptlb0(DisasContext
*dc
, const OpcodeArg arg
[],
2248 const uint32_t par
[])
2250 #ifndef CONFIG_USER_ONLY
2251 gen_helper_rptlb0(arg
[0].out
, cpu_env
, arg
[1].in
);
2255 static void translate_rptlb1(DisasContext
*dc
, const OpcodeArg arg
[],
2256 const uint32_t par
[])
2258 #ifndef CONFIG_USER_ONLY
2259 gen_helper_rptlb1(arg
[0].out
, cpu_env
, arg
[1].in
);
2263 static void translate_rur(DisasContext
*dc
, const OpcodeArg arg
[],
2264 const uint32_t par
[])
2266 tcg_gen_mov_i32(arg
[0].out
, cpu_UR
[par
[0]]);
2269 static void translate_setb_expstate(DisasContext
*dc
, const OpcodeArg arg
[],
2270 const uint32_t par
[])
2272 /* TODO: GPIO32 may be a part of coprocessor */
2273 tcg_gen_ori_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], 1u << arg
[0].imm
);
2276 #ifdef CONFIG_USER_ONLY
2277 static void gen_check_atomctl(DisasContext
*dc
, TCGv_i32 addr
)
2281 static void gen_check_atomctl(DisasContext
*dc
, TCGv_i32 addr
)
2283 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
2285 gen_helper_check_atomctl(cpu_env
, tpc
, addr
);
2290 static void translate_s32c1i(DisasContext
*dc
, const OpcodeArg arg
[],
2291 const uint32_t par
[])
2293 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2294 TCGv_i32 addr
= tcg_temp_local_new_i32();
2296 tcg_gen_mov_i32(tmp
, arg
[0].in
);
2297 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
2298 gen_load_store_alignment(dc
, 2, addr
, true);
2299 gen_check_atomctl(dc
, addr
);
2300 tcg_gen_atomic_cmpxchg_i32(arg
[0].out
, addr
, cpu_SR
[SCOMPARE1
],
2301 tmp
, dc
->cring
, MO_TEUL
);
2302 tcg_temp_free(addr
);
2306 static void translate_s32e(DisasContext
*dc
, const OpcodeArg arg
[],
2307 const uint32_t par
[])
2309 TCGv_i32 addr
= tcg_temp_new_i32();
2311 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
2312 gen_load_store_alignment(dc
, 2, addr
, false);
2313 tcg_gen_qemu_st_tl(arg
[0].in
, addr
, dc
->ring
, MO_TEUL
);
2314 tcg_temp_free(addr
);
2317 static void translate_s32ex(DisasContext
*dc
, const OpcodeArg arg
[],
2318 const uint32_t par
[])
2320 TCGv_i32 prev
= tcg_temp_new_i32();
2321 TCGv_i32 addr
= tcg_temp_local_new_i32();
2322 TCGv_i32 res
= tcg_temp_local_new_i32();
2323 TCGLabel
*label
= gen_new_label();
2325 tcg_gen_movi_i32(res
, 0);
2326 tcg_gen_mov_i32(addr
, arg
[1].in
);
2327 gen_load_store_alignment(dc
, 2, addr
, true);
2328 tcg_gen_brcond_i32(TCG_COND_NE
, addr
, cpu_exclusive_addr
, label
);
2329 gen_check_exclusive(dc
, addr
, true);
2330 tcg_gen_atomic_cmpxchg_i32(prev
, cpu_exclusive_addr
, cpu_exclusive_val
,
2331 arg
[0].in
, dc
->cring
, MO_TEUL
);
2332 tcg_gen_setcond_i32(TCG_COND_EQ
, res
, prev
, cpu_exclusive_val
);
2333 tcg_gen_movcond_i32(TCG_COND_EQ
, cpu_exclusive_val
,
2334 prev
, cpu_exclusive_val
, prev
, cpu_exclusive_val
);
2335 tcg_gen_movi_i32(cpu_exclusive_addr
, -1);
2336 gen_set_label(label
);
2337 tcg_gen_extract_i32(arg
[0].out
, cpu_SR
[ATOMCTL
], 8, 1);
2338 tcg_gen_deposit_i32(cpu_SR
[ATOMCTL
], cpu_SR
[ATOMCTL
], res
, 8, 1);
2339 tcg_temp_free(prev
);
2340 tcg_temp_free(addr
);
2344 static void translate_salt(DisasContext
*dc
, const OpcodeArg arg
[],
2345 const uint32_t par
[])
2347 tcg_gen_setcond_i32(par
[0],
2349 arg
[1].in
, arg
[2].in
);
2352 static void translate_sext(DisasContext
*dc
, const OpcodeArg arg
[],
2353 const uint32_t par
[])
2355 int shift
= 31 - arg
[2].imm
;
2358 tcg_gen_ext8s_i32(arg
[0].out
, arg
[1].in
);
2359 } else if (shift
== 16) {
2360 tcg_gen_ext16s_i32(arg
[0].out
, arg
[1].in
);
2362 TCGv_i32 tmp
= tcg_temp_new_i32();
2363 tcg_gen_shli_i32(tmp
, arg
[1].in
, shift
);
2364 tcg_gen_sari_i32(arg
[0].out
, tmp
, shift
);
2369 static bool test_ill_simcall(DisasContext
*dc
, const OpcodeArg arg
[],
2370 const uint32_t par
[])
2372 #ifdef CONFIG_USER_ONLY
2375 bool ill
= !semihosting_enabled();
2378 qemu_log_mask(LOG_GUEST_ERROR
, "SIMCALL but semihosting is disabled\n");
2383 static void translate_simcall(DisasContext
*dc
, const OpcodeArg arg
[],
2384 const uint32_t par
[])
2386 #ifndef CONFIG_USER_ONLY
2387 gen_helper_simcall(cpu_env
);
2392 * Note: 64 bit ops are used here solely because SAR values
2395 #define gen_shift_reg(cmd, reg) do { \
2396 TCGv_i64 tmp = tcg_temp_new_i64(); \
2397 tcg_gen_extu_i32_i64(tmp, reg); \
2398 tcg_gen_##cmd##_i64(v, v, tmp); \
2399 tcg_gen_extrl_i64_i32(arg[0].out, v); \
2400 tcg_temp_free_i64(v); \
2401 tcg_temp_free_i64(tmp); \
2404 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2406 static void translate_sll(DisasContext
*dc
, const OpcodeArg arg
[],
2407 const uint32_t par
[])
2409 if (dc
->sar_m32_5bit
) {
2410 tcg_gen_shl_i32(arg
[0].out
, arg
[1].in
, dc
->sar_m32
);
2412 TCGv_i64 v
= tcg_temp_new_i64();
2413 TCGv_i32 s
= tcg_const_i32(32);
2414 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
2415 tcg_gen_andi_i32(s
, s
, 0x3f);
2416 tcg_gen_extu_i32_i64(v
, arg
[1].in
);
2417 gen_shift_reg(shl
, s
);
2422 static void translate_slli(DisasContext
*dc
, const OpcodeArg arg
[],
2423 const uint32_t par
[])
2425 if (arg
[2].imm
== 32) {
2426 qemu_log_mask(LOG_GUEST_ERROR
, "slli a%d, a%d, 32 is undefined\n",
2427 arg
[0].imm
, arg
[1].imm
);
2429 tcg_gen_shli_i32(arg
[0].out
, arg
[1].in
, arg
[2].imm
& 0x1f);
2432 static void translate_sra(DisasContext
*dc
, const OpcodeArg arg
[],
2433 const uint32_t par
[])
2435 if (dc
->sar_m32_5bit
) {
2436 tcg_gen_sar_i32(arg
[0].out
, arg
[1].in
, cpu_SR
[SAR
]);
2438 TCGv_i64 v
= tcg_temp_new_i64();
2439 tcg_gen_ext_i32_i64(v
, arg
[1].in
);
2444 static void translate_srai(DisasContext
*dc
, const OpcodeArg arg
[],
2445 const uint32_t par
[])
2447 tcg_gen_sari_i32(arg
[0].out
, arg
[1].in
, arg
[2].imm
);
2450 static void translate_src(DisasContext
*dc
, const OpcodeArg arg
[],
2451 const uint32_t par
[])
2453 TCGv_i64 v
= tcg_temp_new_i64();
2454 tcg_gen_concat_i32_i64(v
, arg
[2].in
, arg
[1].in
);
2458 static void translate_srl(DisasContext
*dc
, const OpcodeArg arg
[],
2459 const uint32_t par
[])
2461 if (dc
->sar_m32_5bit
) {
2462 tcg_gen_shr_i32(arg
[0].out
, arg
[1].in
, cpu_SR
[SAR
]);
2464 TCGv_i64 v
= tcg_temp_new_i64();
2465 tcg_gen_extu_i32_i64(v
, arg
[1].in
);
2471 #undef gen_shift_reg
2473 static void translate_srli(DisasContext
*dc
, const OpcodeArg arg
[],
2474 const uint32_t par
[])
2476 tcg_gen_shri_i32(arg
[0].out
, arg
[1].in
, arg
[2].imm
);
2479 static void translate_ssa8b(DisasContext
*dc
, const OpcodeArg arg
[],
2480 const uint32_t par
[])
2482 TCGv_i32 tmp
= tcg_temp_new_i32();
2483 tcg_gen_shli_i32(tmp
, arg
[0].in
, 3);
2484 gen_left_shift_sar(dc
, tmp
);
2488 static void translate_ssa8l(DisasContext
*dc
, const OpcodeArg arg
[],
2489 const uint32_t par
[])
2491 TCGv_i32 tmp
= tcg_temp_new_i32();
2492 tcg_gen_shli_i32(tmp
, arg
[0].in
, 3);
2493 gen_right_shift_sar(dc
, tmp
);
2497 static void translate_ssai(DisasContext
*dc
, const OpcodeArg arg
[],
2498 const uint32_t par
[])
2500 TCGv_i32 tmp
= tcg_const_i32(arg
[0].imm
);
2501 gen_right_shift_sar(dc
, tmp
);
2505 static void translate_ssl(DisasContext
*dc
, const OpcodeArg arg
[],
2506 const uint32_t par
[])
2508 gen_left_shift_sar(dc
, arg
[0].in
);
2511 static void translate_ssr(DisasContext
*dc
, const OpcodeArg arg
[],
2512 const uint32_t par
[])
2514 gen_right_shift_sar(dc
, arg
[0].in
);
2517 static void translate_sub(DisasContext
*dc
, const OpcodeArg arg
[],
2518 const uint32_t par
[])
2520 tcg_gen_sub_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
2523 static void translate_subx(DisasContext
*dc
, const OpcodeArg arg
[],
2524 const uint32_t par
[])
2526 TCGv_i32 tmp
= tcg_temp_new_i32();
2527 tcg_gen_shli_i32(tmp
, arg
[1].in
, par
[0]);
2528 tcg_gen_sub_i32(arg
[0].out
, tmp
, arg
[2].in
);
2532 static void translate_waiti(DisasContext
*dc
, const OpcodeArg arg
[],
2533 const uint32_t par
[])
2535 #ifndef CONFIG_USER_ONLY
2536 gen_waiti(dc
, arg
[0].imm
);
2540 static void translate_wtlb(DisasContext
*dc
, const OpcodeArg arg
[],
2541 const uint32_t par
[])
2543 #ifndef CONFIG_USER_ONLY
2544 TCGv_i32 dtlb
= tcg_const_i32(par
[0]);
2546 gen_helper_wtlb(cpu_env
, arg
[0].in
, arg
[1].in
, dtlb
);
2547 tcg_temp_free(dtlb
);
2551 static void translate_wptlb(DisasContext
*dc
, const OpcodeArg arg
[],
2552 const uint32_t par
[])
2554 #ifndef CONFIG_USER_ONLY
2555 gen_helper_wptlb(cpu_env
, arg
[0].in
, arg
[1].in
);
2559 static void translate_wer(DisasContext
*dc
, const OpcodeArg arg
[],
2560 const uint32_t par
[])
2562 gen_helper_wer(cpu_env
, arg
[0].in
, arg
[1].in
);
2565 static void translate_wrmsk_expstate(DisasContext
*dc
, const OpcodeArg arg
[],
2566 const uint32_t par
[])
2568 /* TODO: GPIO32 may be a part of coprocessor */
2569 tcg_gen_and_i32(cpu_UR
[EXPSTATE
], arg
[0].in
, arg
[1].in
);
2572 static void translate_wsr(DisasContext
*dc
, const OpcodeArg arg
[],
2573 const uint32_t par
[])
2575 tcg_gen_mov_i32(cpu_SR
[par
[0]], arg
[0].in
);
2578 static void translate_wsr_mask(DisasContext
*dc
, const OpcodeArg arg
[],
2579 const uint32_t par
[])
2581 tcg_gen_andi_i32(cpu_SR
[par
[0]], arg
[0].in
, par
[2]);
2584 static void translate_wsr_acchi(DisasContext
*dc
, const OpcodeArg arg
[],
2585 const uint32_t par
[])
2587 tcg_gen_ext8s_i32(cpu_SR
[par
[0]], arg
[0].in
);
2590 static void translate_wsr_ccompare(DisasContext
*dc
, const OpcodeArg arg
[],
2591 const uint32_t par
[])
2593 #ifndef CONFIG_USER_ONLY
2594 uint32_t id
= par
[0] - CCOMPARE
;
2595 TCGv_i32 tmp
= tcg_const_i32(id
);
2597 assert(id
< dc
->config
->nccompare
);
2598 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
2601 tcg_gen_mov_i32(cpu_SR
[par
[0]], arg
[0].in
);
2602 gen_helper_update_ccompare(cpu_env
, tmp
);
2607 static void translate_wsr_ccount(DisasContext
*dc
, const OpcodeArg arg
[],
2608 const uint32_t par
[])
2610 #ifndef CONFIG_USER_ONLY
2611 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
2614 gen_helper_wsr_ccount(cpu_env
, arg
[0].in
);
2618 static void translate_wsr_dbreaka(DisasContext
*dc
, const OpcodeArg arg
[],
2619 const uint32_t par
[])
2621 #ifndef CONFIG_USER_ONLY
2622 unsigned id
= par
[0] - DBREAKA
;
2623 TCGv_i32 tmp
= tcg_const_i32(id
);
2625 assert(id
< dc
->config
->ndbreak
);
2626 gen_helper_wsr_dbreaka(cpu_env
, tmp
, arg
[0].in
);
2631 static void translate_wsr_dbreakc(DisasContext
*dc
, const OpcodeArg arg
[],
2632 const uint32_t par
[])
2634 #ifndef CONFIG_USER_ONLY
2635 unsigned id
= par
[0] - DBREAKC
;
2636 TCGv_i32 tmp
= tcg_const_i32(id
);
2638 assert(id
< dc
->config
->ndbreak
);
2639 gen_helper_wsr_dbreakc(cpu_env
, tmp
, arg
[0].in
);
2644 static void translate_wsr_ibreaka(DisasContext
*dc
, const OpcodeArg arg
[],
2645 const uint32_t par
[])
2647 #ifndef CONFIG_USER_ONLY
2648 unsigned id
= par
[0] - IBREAKA
;
2649 TCGv_i32 tmp
= tcg_const_i32(id
);
2651 assert(id
< dc
->config
->nibreak
);
2652 gen_helper_wsr_ibreaka(cpu_env
, tmp
, arg
[0].in
);
2657 static void translate_wsr_ibreakenable(DisasContext
*dc
, const OpcodeArg arg
[],
2658 const uint32_t par
[])
2660 #ifndef CONFIG_USER_ONLY
2661 gen_helper_wsr_ibreakenable(cpu_env
, arg
[0].in
);
2665 static void translate_wsr_icount(DisasContext
*dc
, const OpcodeArg arg
[],
2666 const uint32_t par
[])
2668 #ifndef CONFIG_USER_ONLY
2670 tcg_gen_mov_i32(dc
->next_icount
, arg
[0].in
);
2672 tcg_gen_mov_i32(cpu_SR
[par
[0]], arg
[0].in
);
2677 static void translate_wsr_intclear(DisasContext
*dc
, const OpcodeArg arg
[],
2678 const uint32_t par
[])
2680 #ifndef CONFIG_USER_ONLY
2681 gen_helper_intclear(cpu_env
, arg
[0].in
);
2685 static void translate_wsr_intset(DisasContext
*dc
, const OpcodeArg arg
[],
2686 const uint32_t par
[])
2688 #ifndef CONFIG_USER_ONLY
2689 gen_helper_intset(cpu_env
, arg
[0].in
);
2693 static void translate_wsr_memctl(DisasContext
*dc
, const OpcodeArg arg
[],
2694 const uint32_t par
[])
2696 #ifndef CONFIG_USER_ONLY
2697 gen_helper_wsr_memctl(cpu_env
, arg
[0].in
);
2701 static void translate_wsr_mpuenb(DisasContext
*dc
, const OpcodeArg arg
[],
2702 const uint32_t par
[])
2704 #ifndef CONFIG_USER_ONLY
2705 gen_helper_wsr_mpuenb(cpu_env
, arg
[0].in
);
2709 static void translate_wsr_ps(DisasContext
*dc
, const OpcodeArg arg
[],
2710 const uint32_t par
[])
2712 #ifndef CONFIG_USER_ONLY
2713 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
2714 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
2716 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
2719 tcg_gen_andi_i32(cpu_SR
[par
[0]], arg
[0].in
, mask
);
2723 static void translate_wsr_rasid(DisasContext
*dc
, const OpcodeArg arg
[],
2724 const uint32_t par
[])
2726 #ifndef CONFIG_USER_ONLY
2727 gen_helper_wsr_rasid(cpu_env
, arg
[0].in
);
2731 static void translate_wsr_sar(DisasContext
*dc
, const OpcodeArg arg
[],
2732 const uint32_t par
[])
2734 tcg_gen_andi_i32(cpu_SR
[par
[0]], arg
[0].in
, 0x3f);
2735 if (dc
->sar_m32_5bit
) {
2736 tcg_gen_discard_i32(dc
->sar_m32
);
2738 dc
->sar_5bit
= false;
2739 dc
->sar_m32_5bit
= false;
2742 static void translate_wsr_windowbase(DisasContext
*dc
, const OpcodeArg arg
[],
2743 const uint32_t par
[])
2745 #ifndef CONFIG_USER_ONLY
2746 tcg_gen_mov_i32(cpu_windowbase_next
, arg
[0].in
);
2750 static void translate_wsr_windowstart(DisasContext
*dc
, const OpcodeArg arg
[],
2751 const uint32_t par
[])
2753 #ifndef CONFIG_USER_ONLY
2754 tcg_gen_andi_i32(cpu_SR
[par
[0]], arg
[0].in
,
2755 (1 << dc
->config
->nareg
/ 4) - 1);
2759 static void translate_wur(DisasContext
*dc
, const OpcodeArg arg
[],
2760 const uint32_t par
[])
2762 tcg_gen_mov_i32(cpu_UR
[par
[0]], arg
[0].in
);
2765 static void translate_wur_fcr(DisasContext
*dc
, const OpcodeArg arg
[],
2766 const uint32_t par
[])
2768 gen_helper_wur_fcr(cpu_env
, arg
[0].in
);
2771 static void translate_wur_fsr(DisasContext
*dc
, const OpcodeArg arg
[],
2772 const uint32_t par
[])
2774 tcg_gen_andi_i32(cpu_UR
[par
[0]], arg
[0].in
, 0xffffff80);
2777 static void translate_xor(DisasContext
*dc
, const OpcodeArg arg
[],
2778 const uint32_t par
[])
2780 tcg_gen_xor_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
2783 static void translate_xsr(DisasContext
*dc
, const OpcodeArg arg
[],
2784 const uint32_t par
[])
2786 TCGv_i32 tmp
= tcg_temp_new_i32();
2788 tcg_gen_mov_i32(tmp
, arg
[0].in
);
2789 tcg_gen_mov_i32(arg
[0].out
, cpu_SR
[par
[0]]);
2790 tcg_gen_mov_i32(cpu_SR
[par
[0]], tmp
);
2794 static void translate_xsr_mask(DisasContext
*dc
, const OpcodeArg arg
[],
2795 const uint32_t par
[])
2797 TCGv_i32 tmp
= tcg_temp_new_i32();
2799 tcg_gen_mov_i32(tmp
, arg
[0].in
);
2800 tcg_gen_mov_i32(arg
[0].out
, cpu_SR
[par
[0]]);
2801 tcg_gen_andi_i32(cpu_SR
[par
[0]], tmp
, par
[2]);
2805 static void translate_xsr_ccount(DisasContext
*dc
, const OpcodeArg arg
[],
2806 const uint32_t par
[])
2808 #ifndef CONFIG_USER_ONLY
2809 TCGv_i32 tmp
= tcg_temp_new_i32();
2811 if (tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
) {
2815 gen_helper_update_ccount(cpu_env
);
2816 tcg_gen_mov_i32(tmp
, cpu_SR
[par
[0]]);
2817 gen_helper_wsr_ccount(cpu_env
, arg
[0].in
);
2818 tcg_gen_mov_i32(arg
[0].out
, tmp
);
2824 #define gen_translate_xsr(name) \
2825 static void translate_xsr_##name(DisasContext *dc, const OpcodeArg arg[], \
2826 const uint32_t par[]) \
2828 TCGv_i32 tmp = tcg_temp_new_i32(); \
2830 tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
2831 translate_wsr_##name(dc, arg, par); \
2832 tcg_gen_mov_i32(arg[0].out, tmp); \
2833 tcg_temp_free(tmp); \
2836 gen_translate_xsr(acchi
)
2837 gen_translate_xsr(ccompare
)
2838 gen_translate_xsr(dbreaka
)
2839 gen_translate_xsr(dbreakc
)
2840 gen_translate_xsr(ibreaka
)
2841 gen_translate_xsr(ibreakenable
)
2842 gen_translate_xsr(icount
)
2843 gen_translate_xsr(memctl
)
2844 gen_translate_xsr(mpuenb
)
2845 gen_translate_xsr(ps
)
2846 gen_translate_xsr(rasid
)
2847 gen_translate_xsr(sar
)
2848 gen_translate_xsr(windowbase
)
2849 gen_translate_xsr(windowstart
)
2851 #undef gen_translate_xsr
2853 static const XtensaOpcodeOps core_ops
[] = {
2856 .translate
= translate_abs
,
2858 .name
= (const char * const[]) {
2859 "add", "add.n", NULL
,
2861 .translate
= translate_add
,
2862 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2864 .name
= (const char * const[]) {
2865 "addi", "addi.n", NULL
,
2867 .translate
= translate_addi
,
2868 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2871 .translate
= translate_addi
,
2874 .translate
= translate_addx
,
2875 .par
= (const uint32_t[]){1},
2878 .translate
= translate_addx
,
2879 .par
= (const uint32_t[]){2},
2882 .translate
= translate_addx
,
2883 .par
= (const uint32_t[]){3},
2886 .translate
= translate_all
,
2887 .par
= (const uint32_t[]){true, 4},
2890 .translate
= translate_all
,
2891 .par
= (const uint32_t[]){true, 8},
2894 .translate
= translate_and
,
2897 .translate
= translate_boolean
,
2898 .par
= (const uint32_t[]){BOOLEAN_AND
},
2901 .translate
= translate_boolean
,
2902 .par
= (const uint32_t[]){BOOLEAN_ANDC
},
2905 .translate
= translate_all
,
2906 .par
= (const uint32_t[]){false, 4},
2909 .translate
= translate_all
,
2910 .par
= (const uint32_t[]){false, 8},
2912 .name
= (const char * const[]) {
2913 "ball", "ball.w15", "ball.w18", NULL
,
2915 .translate
= translate_ball
,
2916 .par
= (const uint32_t[]){TCG_COND_EQ
},
2917 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2919 .name
= (const char * const[]) {
2920 "bany", "bany.w15", "bany.w18", NULL
,
2922 .translate
= translate_bany
,
2923 .par
= (const uint32_t[]){TCG_COND_NE
},
2924 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2926 .name
= (const char * const[]) {
2927 "bbc", "bbc.w15", "bbc.w18", NULL
,
2929 .translate
= translate_bb
,
2930 .par
= (const uint32_t[]){TCG_COND_EQ
},
2931 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2933 .name
= (const char * const[]) {
2934 "bbci", "bbci.w15", "bbci.w18", NULL
,
2936 .translate
= translate_bbi
,
2937 .par
= (const uint32_t[]){TCG_COND_EQ
},
2938 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2940 .name
= (const char * const[]) {
2941 "bbs", "bbs.w15", "bbs.w18", NULL
,
2943 .translate
= translate_bb
,
2944 .par
= (const uint32_t[]){TCG_COND_NE
},
2945 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2947 .name
= (const char * const[]) {
2948 "bbsi", "bbsi.w15", "bbsi.w18", NULL
,
2950 .translate
= translate_bbi
,
2951 .par
= (const uint32_t[]){TCG_COND_NE
},
2952 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2954 .name
= (const char * const[]) {
2955 "beq", "beq.w15", "beq.w18", NULL
,
2957 .translate
= translate_b
,
2958 .par
= (const uint32_t[]){TCG_COND_EQ
},
2959 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2961 .name
= (const char * const[]) {
2962 "beqi", "beqi.w15", "beqi.w18", NULL
,
2964 .translate
= translate_bi
,
2965 .par
= (const uint32_t[]){TCG_COND_EQ
},
2966 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2968 .name
= (const char * const[]) {
2969 "beqz", "beqz.n", "beqz.w15", "beqz.w18", NULL
,
2971 .translate
= translate_bz
,
2972 .par
= (const uint32_t[]){TCG_COND_EQ
},
2973 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2976 .translate
= translate_bp
,
2977 .par
= (const uint32_t[]){TCG_COND_EQ
},
2979 .name
= (const char * const[]) {
2980 "bge", "bge.w15", "bge.w18", NULL
,
2982 .translate
= translate_b
,
2983 .par
= (const uint32_t[]){TCG_COND_GE
},
2984 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2986 .name
= (const char * const[]) {
2987 "bgei", "bgei.w15", "bgei.w18", NULL
,
2989 .translate
= translate_bi
,
2990 .par
= (const uint32_t[]){TCG_COND_GE
},
2991 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2993 .name
= (const char * const[]) {
2994 "bgeu", "bgeu.w15", "bgeu.w18", NULL
,
2996 .translate
= translate_b
,
2997 .par
= (const uint32_t[]){TCG_COND_GEU
},
2998 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3000 .name
= (const char * const[]) {
3001 "bgeui", "bgeui.w15", "bgeui.w18", NULL
,
3003 .translate
= translate_bi
,
3004 .par
= (const uint32_t[]){TCG_COND_GEU
},
3005 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3007 .name
= (const char * const[]) {
3008 "bgez", "bgez.w15", "bgez.w18", NULL
,
3010 .translate
= translate_bz
,
3011 .par
= (const uint32_t[]){TCG_COND_GE
},
3012 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3014 .name
= (const char * const[]) {
3015 "blt", "blt.w15", "blt.w18", NULL
,
3017 .translate
= translate_b
,
3018 .par
= (const uint32_t[]){TCG_COND_LT
},
3019 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3021 .name
= (const char * const[]) {
3022 "blti", "blti.w15", "blti.w18", NULL
,
3024 .translate
= translate_bi
,
3025 .par
= (const uint32_t[]){TCG_COND_LT
},
3026 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3028 .name
= (const char * const[]) {
3029 "bltu", "bltu.w15", "bltu.w18", NULL
,
3031 .translate
= translate_b
,
3032 .par
= (const uint32_t[]){TCG_COND_LTU
},
3033 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3035 .name
= (const char * const[]) {
3036 "bltui", "bltui.w15", "bltui.w18", NULL
,
3038 .translate
= translate_bi
,
3039 .par
= (const uint32_t[]){TCG_COND_LTU
},
3040 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3042 .name
= (const char * const[]) {
3043 "bltz", "bltz.w15", "bltz.w18", NULL
,
3045 .translate
= translate_bz
,
3046 .par
= (const uint32_t[]){TCG_COND_LT
},
3047 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3049 .name
= (const char * const[]) {
3050 "bnall", "bnall.w15", "bnall.w18", NULL
,
3052 .translate
= translate_ball
,
3053 .par
= (const uint32_t[]){TCG_COND_NE
},
3054 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3056 .name
= (const char * const[]) {
3057 "bne", "bne.w15", "bne.w18", NULL
,
3059 .translate
= translate_b
,
3060 .par
= (const uint32_t[]){TCG_COND_NE
},
3061 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3063 .name
= (const char * const[]) {
3064 "bnei", "bnei.w15", "bnei.w18", NULL
,
3066 .translate
= translate_bi
,
3067 .par
= (const uint32_t[]){TCG_COND_NE
},
3068 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3070 .name
= (const char * const[]) {
3071 "bnez", "bnez.n", "bnez.w15", "bnez.w18", NULL
,
3073 .translate
= translate_bz
,
3074 .par
= (const uint32_t[]){TCG_COND_NE
},
3075 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3077 .name
= (const char * const[]) {
3078 "bnone", "bnone.w15", "bnone.w18", NULL
,
3080 .translate
= translate_bany
,
3081 .par
= (const uint32_t[]){TCG_COND_EQ
},
3082 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3085 .translate
= translate_nop
,
3086 .par
= (const uint32_t[]){DEBUGCAUSE_BI
},
3087 .op_flags
= XTENSA_OP_DEBUG_BREAK
,
3090 .translate
= translate_nop
,
3091 .par
= (const uint32_t[]){DEBUGCAUSE_BN
},
3092 .op_flags
= XTENSA_OP_DEBUG_BREAK
,
3095 .translate
= translate_bp
,
3096 .par
= (const uint32_t[]){TCG_COND_NE
},
3099 .translate
= translate_call0
,
3102 .translate
= translate_callw
,
3103 .par
= (const uint32_t[]){3},
3106 .translate
= translate_callw
,
3107 .par
= (const uint32_t[]){1},
3110 .translate
= translate_callw
,
3111 .par
= (const uint32_t[]){2},
3114 .translate
= translate_callx0
,
3117 .translate
= translate_callxw
,
3118 .par
= (const uint32_t[]){3},
3121 .translate
= translate_callxw
,
3122 .par
= (const uint32_t[]){1},
3125 .translate
= translate_callxw
,
3126 .par
= (const uint32_t[]){2},
3129 .translate
= translate_clamps
,
3131 .name
= "clrb_expstate",
3132 .translate
= translate_clrb_expstate
,
3135 .translate
= translate_clrex
,
3138 .translate
= translate_const16
,
3141 .translate
= translate_depbits
,
3144 .translate
= translate_dcache
,
3145 .op_flags
= XTENSA_OP_PRIVILEGED
,
3148 .translate
= translate_nop
,
3151 .translate
= translate_dcache
,
3152 .op_flags
= XTENSA_OP_PRIVILEGED
,
3155 .translate
= translate_dcache
,
3158 .translate
= translate_nop
,
3161 .translate
= translate_dcache
,
3164 .translate
= translate_nop
,
3167 .translate
= translate_nop
,
3168 .op_flags
= XTENSA_OP_PRIVILEGED
,
3171 .translate
= translate_nop
,
3172 .op_flags
= XTENSA_OP_PRIVILEGED
,
3175 .translate
= translate_nop
,
3176 .op_flags
= XTENSA_OP_PRIVILEGED
,
3179 .translate
= translate_nop
,
3180 .op_flags
= XTENSA_OP_PRIVILEGED
,
3183 .translate
= translate_diwbuip
,
3184 .op_flags
= XTENSA_OP_PRIVILEGED
,
3187 .translate
= translate_dcache
,
3188 .op_flags
= XTENSA_OP_PRIVILEGED
,
3191 .translate
= translate_nop
,
3194 .translate
= translate_nop
,
3197 .translate
= translate_nop
,
3200 .translate
= translate_nop
,
3203 .translate
= translate_nop
,
3206 .translate
= translate_nop
,
3209 .translate
= translate_nop
,
3212 .translate
= translate_nop
,
3215 .translate
= translate_nop
,
3218 .translate
= translate_nop
,
3221 .translate
= translate_nop
,
3224 .translate
= translate_entry
,
3225 .test_ill
= test_ill_entry
,
3226 .test_overflow
= test_overflow_entry
,
3227 .op_flags
= XTENSA_OP_EXIT_TB_M1
|
3228 XTENSA_OP_SYNC_REGISTER_WINDOW
,
3231 .translate
= translate_nop
,
3234 .translate
= translate_nop
,
3237 .translate
= translate_extui
,
3240 .translate
= translate_memw
,
3243 .translate
= translate_getex
,
3246 .op_flags
= XTENSA_OP_ILL
,
3249 .op_flags
= XTENSA_OP_ILL
,
3252 .translate
= translate_itlb
,
3253 .par
= (const uint32_t[]){true},
3254 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
3257 .translate
= translate_icache
,
3260 .translate
= translate_icache
,
3261 .op_flags
= XTENSA_OP_PRIVILEGED
,
3264 .translate
= translate_nop
,
3265 .op_flags
= XTENSA_OP_PRIVILEGED
,
3268 .translate
= translate_itlb
,
3269 .par
= (const uint32_t[]){false},
3270 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
3273 .translate
= translate_nop
,
3274 .op_flags
= XTENSA_OP_PRIVILEGED
,
3276 .name
= (const char * const[]) {
3277 "ill", "ill.n", NULL
,
3279 .op_flags
= XTENSA_OP_ILL
| XTENSA_OP_NAME_ARRAY
,
3282 .translate
= translate_nop
,
3285 .translate
= translate_icache
,
3286 .op_flags
= XTENSA_OP_PRIVILEGED
,
3289 .translate
= translate_nop
,
3292 .translate
= translate_j
,
3295 .translate
= translate_jx
,
3298 .translate
= translate_ldst
,
3299 .par
= (const uint32_t[]){MO_TESW
, false, false},
3300 .op_flags
= XTENSA_OP_LOAD
,
3303 .translate
= translate_ldst
,
3304 .par
= (const uint32_t[]){MO_TEUW
, false, false},
3305 .op_flags
= XTENSA_OP_LOAD
,
3308 .translate
= translate_ldst
,
3309 .par
= (const uint32_t[]){MO_TEUL
, true, false},
3310 .op_flags
= XTENSA_OP_LOAD
,
3313 .translate
= translate_l32e
,
3314 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_LOAD
,
3317 .translate
= translate_l32ex
,
3318 .op_flags
= XTENSA_OP_LOAD
,
3320 .name
= (const char * const[]) {
3321 "l32i", "l32i.n", NULL
,
3323 .translate
= translate_ldst
,
3324 .par
= (const uint32_t[]){MO_TEUL
, false, false},
3325 .op_flags
= XTENSA_OP_NAME_ARRAY
| XTENSA_OP_LOAD
,
3328 .translate
= translate_l32r
,
3329 .op_flags
= XTENSA_OP_LOAD
,
3332 .translate
= translate_ldst
,
3333 .par
= (const uint32_t[]){MO_UB
, false, false},
3334 .op_flags
= XTENSA_OP_LOAD
,
3337 .translate
= translate_mac16
,
3338 .par
= (const uint32_t[]){MAC16_NONE
, 0, -4},
3339 .op_flags
= XTENSA_OP_LOAD
,
3342 .translate
= translate_mac16
,
3343 .par
= (const uint32_t[]){MAC16_NONE
, 0, 4},
3344 .op_flags
= XTENSA_OP_LOAD
,
3347 .op_flags
= XTENSA_OP_ILL
,
3349 .name
= (const char * const[]) {
3350 "loop", "loop.w15", NULL
,
3352 .translate
= translate_loop
,
3353 .par
= (const uint32_t[]){TCG_COND_NEVER
},
3354 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3356 .name
= (const char * const[]) {
3357 "loopgtz", "loopgtz.w15", NULL
,
3359 .translate
= translate_loop
,
3360 .par
= (const uint32_t[]){TCG_COND_GT
},
3361 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3363 .name
= (const char * const[]) {
3364 "loopnez", "loopnez.w15", NULL
,
3366 .translate
= translate_loop
,
3367 .par
= (const uint32_t[]){TCG_COND_NE
},
3368 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3371 .translate
= translate_smax
,
3374 .translate
= translate_umax
,
3377 .translate
= translate_memw
,
3380 .translate
= translate_smin
,
3383 .translate
= translate_umin
,
3385 .name
= (const char * const[]) {
3386 "mov", "mov.n", NULL
,
3388 .translate
= translate_mov
,
3389 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3392 .translate
= translate_movcond
,
3393 .par
= (const uint32_t[]){TCG_COND_EQ
},
3396 .translate
= translate_movp
,
3397 .par
= (const uint32_t[]){TCG_COND_EQ
},
3400 .translate
= translate_movcond
,
3401 .par
= (const uint32_t[]){TCG_COND_GE
},
3404 .translate
= translate_movi
,
3407 .translate
= translate_movi
,
3410 .translate
= translate_movcond
,
3411 .par
= (const uint32_t[]){TCG_COND_LT
},
3414 .translate
= translate_movcond
,
3415 .par
= (const uint32_t[]){TCG_COND_NE
},
3418 .translate
= translate_movsp
,
3419 .op_flags
= XTENSA_OP_ALLOCA
,
3422 .translate
= translate_movp
,
3423 .par
= (const uint32_t[]){TCG_COND_NE
},
3425 .name
= "mul.aa.hh",
3426 .translate
= translate_mac16
,
3427 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HH
, 0},
3429 .name
= "mul.aa.hl",
3430 .translate
= translate_mac16
,
3431 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HL
, 0},
3433 .name
= "mul.aa.lh",
3434 .translate
= translate_mac16
,
3435 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LH
, 0},
3437 .name
= "mul.aa.ll",
3438 .translate
= translate_mac16
,
3439 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LL
, 0},
3441 .name
= "mul.ad.hh",
3442 .translate
= translate_mac16
,
3443 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HH
, 0},
3445 .name
= "mul.ad.hl",
3446 .translate
= translate_mac16
,
3447 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HL
, 0},
3449 .name
= "mul.ad.lh",
3450 .translate
= translate_mac16
,
3451 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LH
, 0},
3453 .name
= "mul.ad.ll",
3454 .translate
= translate_mac16
,
3455 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LL
, 0},
3457 .name
= "mul.da.hh",
3458 .translate
= translate_mac16
,
3459 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HH
, 0},
3461 .name
= "mul.da.hl",
3462 .translate
= translate_mac16
,
3463 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HL
, 0},
3465 .name
= "mul.da.lh",
3466 .translate
= translate_mac16
,
3467 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LH
, 0},
3469 .name
= "mul.da.ll",
3470 .translate
= translate_mac16
,
3471 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LL
, 0},
3473 .name
= "mul.dd.hh",
3474 .translate
= translate_mac16
,
3475 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HH
, 0},
3477 .name
= "mul.dd.hl",
3478 .translate
= translate_mac16
,
3479 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HL
, 0},
3481 .name
= "mul.dd.lh",
3482 .translate
= translate_mac16
,
3483 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LH
, 0},
3485 .name
= "mul.dd.ll",
3486 .translate
= translate_mac16
,
3487 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LL
, 0},
3490 .translate
= translate_mul16
,
3491 .par
= (const uint32_t[]){true},
3494 .translate
= translate_mul16
,
3495 .par
= (const uint32_t[]){false},
3497 .name
= "mula.aa.hh",
3498 .translate
= translate_mac16
,
3499 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 0},
3501 .name
= "mula.aa.hl",
3502 .translate
= translate_mac16
,
3503 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 0},
3505 .name
= "mula.aa.lh",
3506 .translate
= translate_mac16
,
3507 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 0},
3509 .name
= "mula.aa.ll",
3510 .translate
= translate_mac16
,
3511 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 0},
3513 .name
= "mula.ad.hh",
3514 .translate
= translate_mac16
,
3515 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 0},
3517 .name
= "mula.ad.hl",
3518 .translate
= translate_mac16
,
3519 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 0},
3521 .name
= "mula.ad.lh",
3522 .translate
= translate_mac16
,
3523 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 0},
3525 .name
= "mula.ad.ll",
3526 .translate
= translate_mac16
,
3527 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 0},
3529 .name
= "mula.da.hh",
3530 .translate
= translate_mac16
,
3531 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 0},
3533 .name
= "mula.da.hh.lddec",
3534 .translate
= translate_mac16
,
3535 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, -4},
3537 .name
= "mula.da.hh.ldinc",
3538 .translate
= translate_mac16
,
3539 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 4},
3541 .name
= "mula.da.hl",
3542 .translate
= translate_mac16
,
3543 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 0},
3545 .name
= "mula.da.hl.lddec",
3546 .translate
= translate_mac16
,
3547 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, -4},
3549 .name
= "mula.da.hl.ldinc",
3550 .translate
= translate_mac16
,
3551 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 4},
3553 .name
= "mula.da.lh",
3554 .translate
= translate_mac16
,
3555 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 0},
3557 .name
= "mula.da.lh.lddec",
3558 .translate
= translate_mac16
,
3559 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, -4},
3561 .name
= "mula.da.lh.ldinc",
3562 .translate
= translate_mac16
,
3563 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 4},
3565 .name
= "mula.da.ll",
3566 .translate
= translate_mac16
,
3567 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 0},
3569 .name
= "mula.da.ll.lddec",
3570 .translate
= translate_mac16
,
3571 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, -4},
3573 .name
= "mula.da.ll.ldinc",
3574 .translate
= translate_mac16
,
3575 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 4},
3577 .name
= "mula.dd.hh",
3578 .translate
= translate_mac16
,
3579 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 0},
3581 .name
= "mula.dd.hh.lddec",
3582 .translate
= translate_mac16
,
3583 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, -4},
3585 .name
= "mula.dd.hh.ldinc",
3586 .translate
= translate_mac16
,
3587 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 4},
3589 .name
= "mula.dd.hl",
3590 .translate
= translate_mac16
,
3591 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 0},
3593 .name
= "mula.dd.hl.lddec",
3594 .translate
= translate_mac16
,
3595 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, -4},
3597 .name
= "mula.dd.hl.ldinc",
3598 .translate
= translate_mac16
,
3599 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 4},
3601 .name
= "mula.dd.lh",
3602 .translate
= translate_mac16
,
3603 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 0},
3605 .name
= "mula.dd.lh.lddec",
3606 .translate
= translate_mac16
,
3607 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, -4},
3609 .name
= "mula.dd.lh.ldinc",
3610 .translate
= translate_mac16
,
3611 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 4},
3613 .name
= "mula.dd.ll",
3614 .translate
= translate_mac16
,
3615 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 0},
3617 .name
= "mula.dd.ll.lddec",
3618 .translate
= translate_mac16
,
3619 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, -4},
3621 .name
= "mula.dd.ll.ldinc",
3622 .translate
= translate_mac16
,
3623 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 4},
3626 .translate
= translate_mull
,
3628 .name
= "muls.aa.hh",
3629 .translate
= translate_mac16
,
3630 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HH
, 0},
3632 .name
= "muls.aa.hl",
3633 .translate
= translate_mac16
,
3634 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HL
, 0},
3636 .name
= "muls.aa.lh",
3637 .translate
= translate_mac16
,
3638 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LH
, 0},
3640 .name
= "muls.aa.ll",
3641 .translate
= translate_mac16
,
3642 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LL
, 0},
3644 .name
= "muls.ad.hh",
3645 .translate
= translate_mac16
,
3646 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HH
, 0},
3648 .name
= "muls.ad.hl",
3649 .translate
= translate_mac16
,
3650 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HL
, 0},
3652 .name
= "muls.ad.lh",
3653 .translate
= translate_mac16
,
3654 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LH
, 0},
3656 .name
= "muls.ad.ll",
3657 .translate
= translate_mac16
,
3658 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LL
, 0},
3660 .name
= "muls.da.hh",
3661 .translate
= translate_mac16
,
3662 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HH
, 0},
3664 .name
= "muls.da.hl",
3665 .translate
= translate_mac16
,
3666 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HL
, 0},
3668 .name
= "muls.da.lh",
3669 .translate
= translate_mac16
,
3670 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LH
, 0},
3672 .name
= "muls.da.ll",
3673 .translate
= translate_mac16
,
3674 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LL
, 0},
3676 .name
= "muls.dd.hh",
3677 .translate
= translate_mac16
,
3678 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HH
, 0},
3680 .name
= "muls.dd.hl",
3681 .translate
= translate_mac16
,
3682 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HL
, 0},
3684 .name
= "muls.dd.lh",
3685 .translate
= translate_mac16
,
3686 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LH
, 0},
3688 .name
= "muls.dd.ll",
3689 .translate
= translate_mac16
,
3690 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LL
, 0},
3693 .translate
= translate_mulh
,
3694 .par
= (const uint32_t[]){true},
3697 .translate
= translate_mulh
,
3698 .par
= (const uint32_t[]){false},
3701 .translate
= translate_neg
,
3703 .name
= (const char * const[]) {
3704 "nop", "nop.n", NULL
,
3706 .translate
= translate_nop
,
3707 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3710 .translate
= translate_nsa
,
3713 .translate
= translate_nsau
,
3716 .translate
= translate_or
,
3719 .translate
= translate_boolean
,
3720 .par
= (const uint32_t[]){BOOLEAN_OR
},
3723 .translate
= translate_boolean
,
3724 .par
= (const uint32_t[]){BOOLEAN_ORC
},
3727 .translate
= translate_ptlb
,
3728 .par
= (const uint32_t[]){true},
3729 .op_flags
= XTENSA_OP_PRIVILEGED
,
3732 .translate
= translate_nop
,
3735 .translate
= translate_nop
,
3738 .translate
= translate_nop
,
3741 .translate
= translate_nop
,
3744 .translate
= translate_nop
,
3747 .translate
= translate_ptlb
,
3748 .par
= (const uint32_t[]){false},
3749 .op_flags
= XTENSA_OP_PRIVILEGED
,
3752 .translate
= translate_pptlb
,
3753 .op_flags
= XTENSA_OP_PRIVILEGED
,
3756 .translate
= translate_quos
,
3757 .par
= (const uint32_t[]){true},
3758 .op_flags
= XTENSA_OP_DIVIDE_BY_ZERO
,
3761 .translate
= translate_quou
,
3762 .op_flags
= XTENSA_OP_DIVIDE_BY_ZERO
,
3765 .translate
= translate_rtlb
,
3766 .par
= (const uint32_t[]){true, 0},
3767 .op_flags
= XTENSA_OP_PRIVILEGED
,
3770 .translate
= translate_rtlb
,
3771 .par
= (const uint32_t[]){true, 1},
3772 .op_flags
= XTENSA_OP_PRIVILEGED
,
3774 .name
= "read_impwire",
3775 .translate
= translate_read_impwire
,
3778 .translate
= translate_quos
,
3779 .par
= (const uint32_t[]){false},
3780 .op_flags
= XTENSA_OP_DIVIDE_BY_ZERO
,
3783 .translate
= translate_remu
,
3784 .op_flags
= XTENSA_OP_DIVIDE_BY_ZERO
,
3787 .translate
= translate_rer
,
3788 .op_flags
= XTENSA_OP_PRIVILEGED
,
3790 .name
= (const char * const[]) {
3791 "ret", "ret.n", NULL
,
3793 .translate
= translate_ret
,
3794 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3796 .name
= (const char * const[]) {
3797 "retw", "retw.n", NULL
,
3799 .translate
= translate_retw
,
3800 .test_ill
= test_ill_retw
,
3801 .op_flags
= XTENSA_OP_UNDERFLOW
| XTENSA_OP_NAME_ARRAY
,
3804 .op_flags
= XTENSA_OP_ILL
,
3807 .translate
= translate_rfde
,
3808 .op_flags
= XTENSA_OP_PRIVILEGED
,
3811 .op_flags
= XTENSA_OP_ILL
,
3814 .translate
= translate_rfe
,
3815 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_CHECK_INTERRUPTS
,
3818 .translate
= translate_rfi
,
3819 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_CHECK_INTERRUPTS
,
3822 .translate
= translate_rfw
,
3823 .par
= (const uint32_t[]){true},
3824 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_CHECK_INTERRUPTS
,
3827 .translate
= translate_rfw
,
3828 .par
= (const uint32_t[]){false},
3829 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_CHECK_INTERRUPTS
,
3832 .translate
= translate_rtlb
,
3833 .par
= (const uint32_t[]){false, 0},
3834 .op_flags
= XTENSA_OP_PRIVILEGED
,
3837 .translate
= translate_rtlb
,
3838 .par
= (const uint32_t[]){false, 1},
3839 .op_flags
= XTENSA_OP_PRIVILEGED
,
3842 .translate
= translate_rptlb0
,
3843 .op_flags
= XTENSA_OP_PRIVILEGED
,
3846 .translate
= translate_rptlb1
,
3847 .op_flags
= XTENSA_OP_PRIVILEGED
,
3850 .translate
= translate_rotw
,
3851 .op_flags
= XTENSA_OP_PRIVILEGED
|
3852 XTENSA_OP_EXIT_TB_M1
|
3853 XTENSA_OP_SYNC_REGISTER_WINDOW
,
3856 .translate
= translate_rsil
,
3858 XTENSA_OP_PRIVILEGED
|
3859 XTENSA_OP_EXIT_TB_0
|
3860 XTENSA_OP_CHECK_INTERRUPTS
,
3863 .translate
= translate_rsr
,
3864 .par
= (const uint32_t[]){176},
3865 .op_flags
= XTENSA_OP_PRIVILEGED
,
3868 .translate
= translate_rsr
,
3869 .par
= (const uint32_t[]){208},
3870 .op_flags
= XTENSA_OP_PRIVILEGED
,
3872 .name
= "rsr.acchi",
3873 .translate
= translate_rsr
,
3874 .test_ill
= test_ill_sr
,
3875 .par
= (const uint32_t[]){
3877 XTENSA_OPTION_MAC16
,
3880 .name
= "rsr.acclo",
3881 .translate
= translate_rsr
,
3882 .test_ill
= test_ill_sr
,
3883 .par
= (const uint32_t[]){
3885 XTENSA_OPTION_MAC16
,
3888 .name
= "rsr.atomctl",
3889 .translate
= translate_rsr
,
3890 .test_ill
= test_ill_sr
,
3891 .par
= (const uint32_t[]){
3893 XTENSA_OPTION_ATOMCTL
,
3895 .op_flags
= XTENSA_OP_PRIVILEGED
,
3898 .translate
= translate_rsr
,
3899 .test_ill
= test_ill_sr
,
3900 .par
= (const uint32_t[]){
3902 XTENSA_OPTION_BOOLEAN
,
3905 .name
= "rsr.cacheadrdis",
3906 .translate
= translate_rsr
,
3907 .test_ill
= test_ill_sr
,
3908 .par
= (const uint32_t[]){
3912 .op_flags
= XTENSA_OP_PRIVILEGED
,
3914 .name
= "rsr.cacheattr",
3915 .translate
= translate_rsr
,
3916 .test_ill
= test_ill_sr
,
3917 .par
= (const uint32_t[]){
3919 XTENSA_OPTION_CACHEATTR
,
3921 .op_flags
= XTENSA_OP_PRIVILEGED
,
3923 .name
= "rsr.ccompare0",
3924 .translate
= translate_rsr
,
3925 .test_ill
= test_ill_ccompare
,
3926 .par
= (const uint32_t[]){
3928 XTENSA_OPTION_TIMER_INTERRUPT
,
3930 .op_flags
= XTENSA_OP_PRIVILEGED
,
3932 .name
= "rsr.ccompare1",
3933 .translate
= translate_rsr
,
3934 .test_ill
= test_ill_ccompare
,
3935 .par
= (const uint32_t[]){
3937 XTENSA_OPTION_TIMER_INTERRUPT
,
3939 .op_flags
= XTENSA_OP_PRIVILEGED
,
3941 .name
= "rsr.ccompare2",
3942 .translate
= translate_rsr
,
3943 .test_ill
= test_ill_ccompare
,
3944 .par
= (const uint32_t[]){
3946 XTENSA_OPTION_TIMER_INTERRUPT
,
3948 .op_flags
= XTENSA_OP_PRIVILEGED
,
3950 .name
= "rsr.ccount",
3951 .translate
= translate_rsr_ccount
,
3952 .test_ill
= test_ill_sr
,
3953 .par
= (const uint32_t[]){
3955 XTENSA_OPTION_TIMER_INTERRUPT
,
3957 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
3959 .name
= "rsr.configid0",
3960 .translate
= translate_rsr
,
3961 .par
= (const uint32_t[]){CONFIGID0
},
3962 .op_flags
= XTENSA_OP_PRIVILEGED
,
3964 .name
= "rsr.configid1",
3965 .translate
= translate_rsr
,
3966 .par
= (const uint32_t[]){CONFIGID1
},
3967 .op_flags
= XTENSA_OP_PRIVILEGED
,
3969 .name
= "rsr.cpenable",
3970 .translate
= translate_rsr
,
3971 .test_ill
= test_ill_sr
,
3972 .par
= (const uint32_t[]){
3974 XTENSA_OPTION_COPROCESSOR
,
3976 .op_flags
= XTENSA_OP_PRIVILEGED
,
3978 .name
= "rsr.dbreaka0",
3979 .translate
= translate_rsr
,
3980 .test_ill
= test_ill_dbreak
,
3981 .par
= (const uint32_t[]){
3983 XTENSA_OPTION_DEBUG
,
3985 .op_flags
= XTENSA_OP_PRIVILEGED
,
3987 .name
= "rsr.dbreaka1",
3988 .translate
= translate_rsr
,
3989 .test_ill
= test_ill_dbreak
,
3990 .par
= (const uint32_t[]){
3992 XTENSA_OPTION_DEBUG
,
3994 .op_flags
= XTENSA_OP_PRIVILEGED
,
3996 .name
= "rsr.dbreakc0",
3997 .translate
= translate_rsr
,
3998 .test_ill
= test_ill_dbreak
,
3999 .par
= (const uint32_t[]){
4001 XTENSA_OPTION_DEBUG
,
4003 .op_flags
= XTENSA_OP_PRIVILEGED
,
4005 .name
= "rsr.dbreakc1",
4006 .translate
= translate_rsr
,
4007 .test_ill
= test_ill_dbreak
,
4008 .par
= (const uint32_t[]){
4010 XTENSA_OPTION_DEBUG
,
4012 .op_flags
= XTENSA_OP_PRIVILEGED
,
4015 .translate
= translate_rsr
,
4016 .test_ill
= test_ill_sr
,
4017 .par
= (const uint32_t[]){
4019 XTENSA_OPTION_DEBUG
,
4021 .op_flags
= XTENSA_OP_PRIVILEGED
,
4023 .name
= "rsr.debugcause",
4024 .translate
= translate_rsr
,
4025 .test_ill
= test_ill_sr
,
4026 .par
= (const uint32_t[]){
4028 XTENSA_OPTION_DEBUG
,
4030 .op_flags
= XTENSA_OP_PRIVILEGED
,
4033 .translate
= translate_rsr
,
4034 .test_ill
= test_ill_sr
,
4035 .par
= (const uint32_t[]){
4037 XTENSA_OPTION_EXCEPTION
,
4039 .op_flags
= XTENSA_OP_PRIVILEGED
,
4041 .name
= "rsr.dtlbcfg",
4042 .translate
= translate_rsr
,
4043 .test_ill
= test_ill_sr
,
4044 .par
= (const uint32_t[]){
4048 .op_flags
= XTENSA_OP_PRIVILEGED
,
4051 .translate
= translate_rsr
,
4052 .test_ill
= test_ill_sr
,
4053 .par
= (const uint32_t[]){
4055 XTENSA_OPTION_EXCEPTION
,
4057 .op_flags
= XTENSA_OP_PRIVILEGED
,
4060 .translate
= translate_rsr
,
4061 .test_ill
= test_ill_hpi
,
4062 .par
= (const uint32_t[]){
4064 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4066 .op_flags
= XTENSA_OP_PRIVILEGED
,
4069 .translate
= translate_rsr
,
4070 .test_ill
= test_ill_hpi
,
4071 .par
= (const uint32_t[]){
4073 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4075 .op_flags
= XTENSA_OP_PRIVILEGED
,
4078 .translate
= translate_rsr
,
4079 .test_ill
= test_ill_hpi
,
4080 .par
= (const uint32_t[]){
4082 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4084 .op_flags
= XTENSA_OP_PRIVILEGED
,
4087 .translate
= translate_rsr
,
4088 .test_ill
= test_ill_hpi
,
4089 .par
= (const uint32_t[]){
4091 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4093 .op_flags
= XTENSA_OP_PRIVILEGED
,
4096 .translate
= translate_rsr
,
4097 .test_ill
= test_ill_hpi
,
4098 .par
= (const uint32_t[]){
4100 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4102 .op_flags
= XTENSA_OP_PRIVILEGED
,
4105 .translate
= translate_rsr
,
4106 .test_ill
= test_ill_hpi
,
4107 .par
= (const uint32_t[]){
4109 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4111 .op_flags
= XTENSA_OP_PRIVILEGED
,
4114 .translate
= translate_rsr
,
4115 .test_ill
= test_ill_hpi
,
4116 .par
= (const uint32_t[]){
4118 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4120 .op_flags
= XTENSA_OP_PRIVILEGED
,
4123 .translate
= translate_rsr
,
4124 .test_ill
= test_ill_hpi
,
4125 .par
= (const uint32_t[]){
4127 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4129 .op_flags
= XTENSA_OP_PRIVILEGED
,
4132 .translate
= translate_rsr
,
4133 .test_ill
= test_ill_hpi
,
4134 .par
= (const uint32_t[]){
4136 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4138 .op_flags
= XTENSA_OP_PRIVILEGED
,
4141 .translate
= translate_rsr
,
4142 .test_ill
= test_ill_hpi
,
4143 .par
= (const uint32_t[]){
4145 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4147 .op_flags
= XTENSA_OP_PRIVILEGED
,
4150 .translate
= translate_rsr
,
4151 .test_ill
= test_ill_hpi
,
4152 .par
= (const uint32_t[]){
4154 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4156 .op_flags
= XTENSA_OP_PRIVILEGED
,
4159 .translate
= translate_rsr
,
4160 .test_ill
= test_ill_hpi
,
4161 .par
= (const uint32_t[]){
4163 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4165 .op_flags
= XTENSA_OP_PRIVILEGED
,
4167 .name
= "rsr.eraccess",
4168 .translate
= translate_rsr
,
4169 .par
= (const uint32_t[]){ERACCESS
},
4170 .op_flags
= XTENSA_OP_PRIVILEGED
,
4172 .name
= "rsr.exccause",
4173 .translate
= translate_rsr
,
4174 .test_ill
= test_ill_sr
,
4175 .par
= (const uint32_t[]){
4177 XTENSA_OPTION_EXCEPTION
,
4179 .op_flags
= XTENSA_OP_PRIVILEGED
,
4181 .name
= "rsr.excsave1",
4182 .translate
= translate_rsr
,
4183 .test_ill
= test_ill_sr
,
4184 .par
= (const uint32_t[]){
4186 XTENSA_OPTION_EXCEPTION
,
4188 .op_flags
= XTENSA_OP_PRIVILEGED
,
4190 .name
= "rsr.excsave2",
4191 .translate
= translate_rsr
,
4192 .test_ill
= test_ill_hpi
,
4193 .par
= (const uint32_t[]){
4195 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4197 .op_flags
= XTENSA_OP_PRIVILEGED
,
4199 .name
= "rsr.excsave3",
4200 .translate
= translate_rsr
,
4201 .test_ill
= test_ill_hpi
,
4202 .par
= (const uint32_t[]){
4204 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4206 .op_flags
= XTENSA_OP_PRIVILEGED
,
4208 .name
= "rsr.excsave4",
4209 .translate
= translate_rsr
,
4210 .test_ill
= test_ill_hpi
,
4211 .par
= (const uint32_t[]){
4213 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4215 .op_flags
= XTENSA_OP_PRIVILEGED
,
4217 .name
= "rsr.excsave5",
4218 .translate
= translate_rsr
,
4219 .test_ill
= test_ill_hpi
,
4220 .par
= (const uint32_t[]){
4222 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4224 .op_flags
= XTENSA_OP_PRIVILEGED
,
4226 .name
= "rsr.excsave6",
4227 .translate
= translate_rsr
,
4228 .test_ill
= test_ill_hpi
,
4229 .par
= (const uint32_t[]){
4231 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4233 .op_flags
= XTENSA_OP_PRIVILEGED
,
4235 .name
= "rsr.excsave7",
4236 .translate
= translate_rsr
,
4237 .test_ill
= test_ill_hpi
,
4238 .par
= (const uint32_t[]){
4240 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4242 .op_flags
= XTENSA_OP_PRIVILEGED
,
4244 .name
= "rsr.excvaddr",
4245 .translate
= translate_rsr
,
4246 .test_ill
= test_ill_sr
,
4247 .par
= (const uint32_t[]){
4249 XTENSA_OPTION_EXCEPTION
,
4251 .op_flags
= XTENSA_OP_PRIVILEGED
,
4253 .name
= "rsr.ibreaka0",
4254 .translate
= translate_rsr
,
4255 .test_ill
= test_ill_ibreak
,
4256 .par
= (const uint32_t[]){
4258 XTENSA_OPTION_DEBUG
,
4260 .op_flags
= XTENSA_OP_PRIVILEGED
,
4262 .name
= "rsr.ibreaka1",
4263 .translate
= translate_rsr
,
4264 .test_ill
= test_ill_ibreak
,
4265 .par
= (const uint32_t[]){
4267 XTENSA_OPTION_DEBUG
,
4269 .op_flags
= XTENSA_OP_PRIVILEGED
,
4271 .name
= "rsr.ibreakenable",
4272 .translate
= translate_rsr
,
4273 .test_ill
= test_ill_sr
,
4274 .par
= (const uint32_t[]){
4276 XTENSA_OPTION_DEBUG
,
4278 .op_flags
= XTENSA_OP_PRIVILEGED
,
4280 .name
= "rsr.icount",
4281 .translate
= translate_rsr
,
4282 .test_ill
= test_ill_sr
,
4283 .par
= (const uint32_t[]){
4285 XTENSA_OPTION_DEBUG
,
4287 .op_flags
= XTENSA_OP_PRIVILEGED
,
4289 .name
= "rsr.icountlevel",
4290 .translate
= translate_rsr
,
4291 .test_ill
= test_ill_sr
,
4292 .par
= (const uint32_t[]){
4294 XTENSA_OPTION_DEBUG
,
4296 .op_flags
= XTENSA_OP_PRIVILEGED
,
4298 .name
= "rsr.intclear",
4299 .translate
= translate_rsr
,
4300 .test_ill
= test_ill_sr
,
4301 .par
= (const uint32_t[]){
4303 XTENSA_OPTION_INTERRUPT
,
4305 .op_flags
= XTENSA_OP_PRIVILEGED
,
4307 .name
= "rsr.intenable",
4308 .translate
= translate_rsr
,
4309 .test_ill
= test_ill_sr
,
4310 .par
= (const uint32_t[]){
4312 XTENSA_OPTION_INTERRUPT
,
4314 .op_flags
= XTENSA_OP_PRIVILEGED
,
4316 .name
= "rsr.interrupt",
4317 .translate
= translate_rsr_ccount
,
4318 .test_ill
= test_ill_sr
,
4319 .par
= (const uint32_t[]){
4321 XTENSA_OPTION_INTERRUPT
,
4323 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4325 .name
= "rsr.intset",
4326 .translate
= translate_rsr_ccount
,
4327 .test_ill
= test_ill_sr
,
4328 .par
= (const uint32_t[]){
4330 XTENSA_OPTION_INTERRUPT
,
4332 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4334 .name
= "rsr.itlbcfg",
4335 .translate
= translate_rsr
,
4336 .test_ill
= test_ill_sr
,
4337 .par
= (const uint32_t[]){
4341 .op_flags
= XTENSA_OP_PRIVILEGED
,
4344 .translate
= translate_rsr
,
4345 .test_ill
= test_ill_sr
,
4346 .par
= (const uint32_t[]){
4351 .name
= "rsr.lcount",
4352 .translate
= translate_rsr
,
4353 .test_ill
= test_ill_sr
,
4354 .par
= (const uint32_t[]){
4360 .translate
= translate_rsr
,
4361 .test_ill
= test_ill_sr
,
4362 .par
= (const uint32_t[]){
4367 .name
= "rsr.litbase",
4368 .translate
= translate_rsr
,
4369 .test_ill
= test_ill_sr
,
4370 .par
= (const uint32_t[]){
4372 XTENSA_OPTION_EXTENDED_L32R
,
4376 .translate
= translate_rsr
,
4377 .test_ill
= test_ill_sr
,
4378 .par
= (const uint32_t[]){
4380 XTENSA_OPTION_MAC16
,
4384 .translate
= translate_rsr
,
4385 .test_ill
= test_ill_sr
,
4386 .par
= (const uint32_t[]){
4388 XTENSA_OPTION_MAC16
,
4392 .translate
= translate_rsr
,
4393 .test_ill
= test_ill_sr
,
4394 .par
= (const uint32_t[]){
4396 XTENSA_OPTION_MAC16
,
4400 .translate
= translate_rsr
,
4401 .test_ill
= test_ill_sr
,
4402 .par
= (const uint32_t[]){
4404 XTENSA_OPTION_MAC16
,
4407 .name
= "rsr.memctl",
4408 .translate
= translate_rsr
,
4409 .par
= (const uint32_t[]){MEMCTL
},
4410 .op_flags
= XTENSA_OP_PRIVILEGED
,
4413 .translate
= translate_rsr
,
4414 .test_ill
= test_ill_sr
,
4415 .par
= (const uint32_t[]){
4417 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4419 .op_flags
= XTENSA_OP_PRIVILEGED
,
4422 .translate
= translate_rsr
,
4423 .test_ill
= test_ill_sr
,
4424 .par
= (const uint32_t[]){
4426 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4428 .op_flags
= XTENSA_OP_PRIVILEGED
,
4431 .translate
= translate_rsr
,
4432 .test_ill
= test_ill_sr
,
4433 .par
= (const uint32_t[]){
4435 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4437 .op_flags
= XTENSA_OP_PRIVILEGED
,
4439 .name
= "rsr.mesave",
4440 .translate
= translate_rsr
,
4441 .test_ill
= test_ill_sr
,
4442 .par
= (const uint32_t[]){
4444 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4446 .op_flags
= XTENSA_OP_PRIVILEGED
,
4449 .translate
= translate_rsr
,
4450 .test_ill
= test_ill_sr
,
4451 .par
= (const uint32_t[]){
4453 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4455 .op_flags
= XTENSA_OP_PRIVILEGED
,
4457 .name
= "rsr.mevaddr",
4458 .translate
= translate_rsr
,
4459 .test_ill
= test_ill_sr
,
4460 .par
= (const uint32_t[]){
4462 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4464 .op_flags
= XTENSA_OP_PRIVILEGED
,
4466 .name
= "rsr.misc0",
4467 .translate
= translate_rsr
,
4468 .test_ill
= test_ill_sr
,
4469 .par
= (const uint32_t[]){
4471 XTENSA_OPTION_MISC_SR
,
4473 .op_flags
= XTENSA_OP_PRIVILEGED
,
4475 .name
= "rsr.misc1",
4476 .translate
= translate_rsr
,
4477 .test_ill
= test_ill_sr
,
4478 .par
= (const uint32_t[]){
4480 XTENSA_OPTION_MISC_SR
,
4482 .op_flags
= XTENSA_OP_PRIVILEGED
,
4484 .name
= "rsr.misc2",
4485 .translate
= translate_rsr
,
4486 .test_ill
= test_ill_sr
,
4487 .par
= (const uint32_t[]){
4489 XTENSA_OPTION_MISC_SR
,
4491 .op_flags
= XTENSA_OP_PRIVILEGED
,
4493 .name
= "rsr.misc3",
4494 .translate
= translate_rsr
,
4495 .test_ill
= test_ill_sr
,
4496 .par
= (const uint32_t[]){
4498 XTENSA_OPTION_MISC_SR
,
4500 .op_flags
= XTENSA_OP_PRIVILEGED
,
4502 .name
= "rsr.mpucfg",
4503 .translate
= translate_rsr
,
4504 .test_ill
= test_ill_sr
,
4505 .par
= (const uint32_t[]){
4509 .op_flags
= XTENSA_OP_PRIVILEGED
,
4511 .name
= "rsr.mpuenb",
4512 .translate
= translate_rsr
,
4513 .test_ill
= test_ill_sr
,
4514 .par
= (const uint32_t[]){
4518 .op_flags
= XTENSA_OP_PRIVILEGED
,
4520 .name
= "rsr.prefctl",
4521 .translate
= translate_rsr
,
4522 .par
= (const uint32_t[]){PREFCTL
},
4525 .translate
= translate_rsr
,
4526 .test_ill
= test_ill_sr
,
4527 .par
= (const uint32_t[]){
4529 XTENSA_OPTION_PROCESSOR_ID
,
4531 .op_flags
= XTENSA_OP_PRIVILEGED
,
4534 .translate
= translate_rsr
,
4535 .test_ill
= test_ill_sr
,
4536 .par
= (const uint32_t[]){
4538 XTENSA_OPTION_EXCEPTION
,
4540 .op_flags
= XTENSA_OP_PRIVILEGED
,
4542 .name
= "rsr.ptevaddr",
4543 .translate
= translate_rsr_ptevaddr
,
4544 .test_ill
= test_ill_sr
,
4545 .par
= (const uint32_t[]){
4549 .op_flags
= XTENSA_OP_PRIVILEGED
,
4551 .name
= "rsr.rasid",
4552 .translate
= translate_rsr
,
4553 .test_ill
= test_ill_sr
,
4554 .par
= (const uint32_t[]){
4558 .op_flags
= XTENSA_OP_PRIVILEGED
,
4561 .translate
= translate_rsr
,
4562 .par
= (const uint32_t[]){SAR
},
4564 .name
= "rsr.scompare1",
4565 .translate
= translate_rsr
,
4566 .test_ill
= test_ill_sr
,
4567 .par
= (const uint32_t[]){
4569 XTENSA_OPTION_CONDITIONAL_STORE
,
4572 .name
= "rsr.vecbase",
4573 .translate
= translate_rsr
,
4574 .test_ill
= test_ill_sr
,
4575 .par
= (const uint32_t[]){
4577 XTENSA_OPTION_RELOCATABLE_VECTOR
,
4579 .op_flags
= XTENSA_OP_PRIVILEGED
,
4581 .name
= "rsr.windowbase",
4582 .translate
= translate_rsr
,
4583 .test_ill
= test_ill_sr
,
4584 .par
= (const uint32_t[]){
4586 XTENSA_OPTION_WINDOWED_REGISTER
,
4588 .op_flags
= XTENSA_OP_PRIVILEGED
,
4590 .name
= "rsr.windowstart",
4591 .translate
= translate_rsr
,
4592 .test_ill
= test_ill_sr
,
4593 .par
= (const uint32_t[]){
4595 XTENSA_OPTION_WINDOWED_REGISTER
,
4597 .op_flags
= XTENSA_OP_PRIVILEGED
,
4600 .translate
= translate_nop
,
4602 .name
= "rur.expstate",
4603 .translate
= translate_rur
,
4604 .par
= (const uint32_t[]){EXPSTATE
},
4607 .translate
= translate_rur
,
4608 .par
= (const uint32_t[]){FCR
},
4612 .translate
= translate_rur
,
4613 .par
= (const uint32_t[]){FSR
},
4616 .name
= "rur.threadptr",
4617 .translate
= translate_rur
,
4618 .par
= (const uint32_t[]){THREADPTR
},
4621 .translate
= translate_ldst
,
4622 .par
= (const uint32_t[]){MO_TEUW
, false, true},
4623 .op_flags
= XTENSA_OP_STORE
,
4626 .translate
= translate_s32c1i
,
4627 .op_flags
= XTENSA_OP_LOAD
| XTENSA_OP_STORE
,
4630 .translate
= translate_s32e
,
4631 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_STORE
,
4634 .translate
= translate_s32ex
,
4635 .op_flags
= XTENSA_OP_LOAD
| XTENSA_OP_STORE
,
4637 .name
= (const char * const[]) {
4638 "s32i", "s32i.n", "s32nb", NULL
,
4640 .translate
= translate_ldst
,
4641 .par
= (const uint32_t[]){MO_TEUL
, false, true},
4642 .op_flags
= XTENSA_OP_NAME_ARRAY
| XTENSA_OP_STORE
,
4645 .translate
= translate_ldst
,
4646 .par
= (const uint32_t[]){MO_TEUL
, true, true},
4647 .op_flags
= XTENSA_OP_STORE
,
4650 .translate
= translate_ldst
,
4651 .par
= (const uint32_t[]){MO_UB
, false, true},
4652 .op_flags
= XTENSA_OP_STORE
,
4655 .translate
= translate_salt
,
4656 .par
= (const uint32_t[]){TCG_COND_LT
},
4659 .translate
= translate_salt
,
4660 .par
= (const uint32_t[]){TCG_COND_LTU
},
4662 .name
= "setb_expstate",
4663 .translate
= translate_setb_expstate
,
4666 .translate
= translate_sext
,
4669 .translate
= translate_simcall
,
4670 .test_ill
= test_ill_simcall
,
4671 .op_flags
= XTENSA_OP_PRIVILEGED
,
4674 .translate
= translate_sll
,
4677 .translate
= translate_slli
,
4680 .translate
= translate_sra
,
4683 .translate
= translate_srai
,
4686 .translate
= translate_src
,
4689 .translate
= translate_srl
,
4692 .translate
= translate_srli
,
4695 .translate
= translate_ssa8b
,
4698 .translate
= translate_ssa8l
,
4701 .translate
= translate_ssai
,
4704 .translate
= translate_ssl
,
4707 .translate
= translate_ssr
,
4710 .translate
= translate_sub
,
4713 .translate
= translate_subx
,
4714 .par
= (const uint32_t[]){1},
4717 .translate
= translate_subx
,
4718 .par
= (const uint32_t[]){2},
4721 .translate
= translate_subx
,
4722 .par
= (const uint32_t[]){3},
4725 .op_flags
= XTENSA_OP_SYSCALL
,
4727 .name
= "umul.aa.hh",
4728 .translate
= translate_mac16
,
4729 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_HH
, 0},
4731 .name
= "umul.aa.hl",
4732 .translate
= translate_mac16
,
4733 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_HL
, 0},
4735 .name
= "umul.aa.lh",
4736 .translate
= translate_mac16
,
4737 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_LH
, 0},
4739 .name
= "umul.aa.ll",
4740 .translate
= translate_mac16
,
4741 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_LL
, 0},
4744 .translate
= translate_waiti
,
4745 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4748 .translate
= translate_wtlb
,
4749 .par
= (const uint32_t[]){true},
4750 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
4753 .translate
= translate_wer
,
4754 .op_flags
= XTENSA_OP_PRIVILEGED
,
4757 .translate
= translate_wtlb
,
4758 .par
= (const uint32_t[]){false},
4759 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
4762 .translate
= translate_wptlb
,
4763 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
4765 .name
= "wrmsk_expstate",
4766 .translate
= translate_wrmsk_expstate
,
4769 .op_flags
= XTENSA_OP_ILL
,
4772 .op_flags
= XTENSA_OP_ILL
,
4774 .name
= "wsr.acchi",
4775 .translate
= translate_wsr_acchi
,
4776 .test_ill
= test_ill_sr
,
4777 .par
= (const uint32_t[]){
4779 XTENSA_OPTION_MAC16
,
4782 .name
= "wsr.acclo",
4783 .translate
= translate_wsr
,
4784 .test_ill
= test_ill_sr
,
4785 .par
= (const uint32_t[]){
4787 XTENSA_OPTION_MAC16
,
4790 .name
= "wsr.atomctl",
4791 .translate
= translate_wsr_mask
,
4792 .test_ill
= test_ill_sr
,
4793 .par
= (const uint32_t[]){
4795 XTENSA_OPTION_ATOMCTL
,
4798 .op_flags
= XTENSA_OP_PRIVILEGED
,
4801 .translate
= translate_wsr_mask
,
4802 .test_ill
= test_ill_sr
,
4803 .par
= (const uint32_t[]){
4805 XTENSA_OPTION_BOOLEAN
,
4809 .name
= "wsr.cacheadrdis",
4810 .translate
= translate_wsr_mask
,
4811 .test_ill
= test_ill_sr
,
4812 .par
= (const uint32_t[]){
4817 .op_flags
= XTENSA_OP_PRIVILEGED
,
4819 .name
= "wsr.cacheattr",
4820 .translate
= translate_wsr
,
4821 .test_ill
= test_ill_sr
,
4822 .par
= (const uint32_t[]){
4824 XTENSA_OPTION_CACHEATTR
,
4826 .op_flags
= XTENSA_OP_PRIVILEGED
,
4828 .name
= "wsr.ccompare0",
4829 .translate
= translate_wsr_ccompare
,
4830 .test_ill
= test_ill_ccompare
,
4831 .par
= (const uint32_t[]){
4833 XTENSA_OPTION_TIMER_INTERRUPT
,
4835 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4837 .name
= "wsr.ccompare1",
4838 .translate
= translate_wsr_ccompare
,
4839 .test_ill
= test_ill_ccompare
,
4840 .par
= (const uint32_t[]){
4842 XTENSA_OPTION_TIMER_INTERRUPT
,
4844 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4846 .name
= "wsr.ccompare2",
4847 .translate
= translate_wsr_ccompare
,
4848 .test_ill
= test_ill_ccompare
,
4849 .par
= (const uint32_t[]){
4851 XTENSA_OPTION_TIMER_INTERRUPT
,
4853 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4855 .name
= "wsr.ccount",
4856 .translate
= translate_wsr_ccount
,
4857 .test_ill
= test_ill_sr
,
4858 .par
= (const uint32_t[]){
4860 XTENSA_OPTION_TIMER_INTERRUPT
,
4862 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4864 .name
= "wsr.configid0",
4865 .op_flags
= XTENSA_OP_ILL
,
4867 .name
= "wsr.configid1",
4868 .op_flags
= XTENSA_OP_ILL
,
4870 .name
= "wsr.cpenable",
4871 .translate
= translate_wsr_mask
,
4872 .test_ill
= test_ill_sr
,
4873 .par
= (const uint32_t[]){
4875 XTENSA_OPTION_COPROCESSOR
,
4878 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
4880 .name
= "wsr.dbreaka0",
4881 .translate
= translate_wsr_dbreaka
,
4882 .test_ill
= test_ill_dbreak
,
4883 .par
= (const uint32_t[]){
4885 XTENSA_OPTION_DEBUG
,
4887 .op_flags
= XTENSA_OP_PRIVILEGED
,
4889 .name
= "wsr.dbreaka1",
4890 .translate
= translate_wsr_dbreaka
,
4891 .test_ill
= test_ill_dbreak
,
4892 .par
= (const uint32_t[]){
4894 XTENSA_OPTION_DEBUG
,
4896 .op_flags
= XTENSA_OP_PRIVILEGED
,
4898 .name
= "wsr.dbreakc0",
4899 .translate
= translate_wsr_dbreakc
,
4900 .test_ill
= test_ill_dbreak
,
4901 .par
= (const uint32_t[]){
4903 XTENSA_OPTION_DEBUG
,
4905 .op_flags
= XTENSA_OP_PRIVILEGED
,
4907 .name
= "wsr.dbreakc1",
4908 .translate
= translate_wsr_dbreakc
,
4909 .test_ill
= test_ill_dbreak
,
4910 .par
= (const uint32_t[]){
4912 XTENSA_OPTION_DEBUG
,
4914 .op_flags
= XTENSA_OP_PRIVILEGED
,
4917 .translate
= translate_wsr
,
4918 .test_ill
= test_ill_sr
,
4919 .par
= (const uint32_t[]){
4921 XTENSA_OPTION_DEBUG
,
4923 .op_flags
= XTENSA_OP_PRIVILEGED
,
4925 .name
= "wsr.debugcause",
4926 .op_flags
= XTENSA_OP_ILL
,
4929 .translate
= translate_wsr
,
4930 .test_ill
= test_ill_sr
,
4931 .par
= (const uint32_t[]){
4933 XTENSA_OPTION_EXCEPTION
,
4935 .op_flags
= XTENSA_OP_PRIVILEGED
,
4937 .name
= "wsr.dtlbcfg",
4938 .translate
= translate_wsr_mask
,
4939 .test_ill
= test_ill_sr
,
4940 .par
= (const uint32_t[]){
4945 .op_flags
= XTENSA_OP_PRIVILEGED
,
4948 .translate
= translate_wsr
,
4949 .test_ill
= test_ill_sr
,
4950 .par
= (const uint32_t[]){
4952 XTENSA_OPTION_EXCEPTION
,
4954 .op_flags
= XTENSA_OP_PRIVILEGED
,
4957 .translate
= translate_wsr
,
4958 .test_ill
= test_ill_hpi
,
4959 .par
= (const uint32_t[]){
4961 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4963 .op_flags
= XTENSA_OP_PRIVILEGED
,
4966 .translate
= translate_wsr
,
4967 .test_ill
= test_ill_hpi
,
4968 .par
= (const uint32_t[]){
4970 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4972 .op_flags
= XTENSA_OP_PRIVILEGED
,
4975 .translate
= translate_wsr
,
4976 .test_ill
= test_ill_hpi
,
4977 .par
= (const uint32_t[]){
4979 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4981 .op_flags
= XTENSA_OP_PRIVILEGED
,
4984 .translate
= translate_wsr
,
4985 .test_ill
= test_ill_hpi
,
4986 .par
= (const uint32_t[]){
4988 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4990 .op_flags
= XTENSA_OP_PRIVILEGED
,
4993 .translate
= translate_wsr
,
4994 .test_ill
= test_ill_hpi
,
4995 .par
= (const uint32_t[]){
4997 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4999 .op_flags
= XTENSA_OP_PRIVILEGED
,
5002 .translate
= translate_wsr
,
5003 .test_ill
= test_ill_hpi
,
5004 .par
= (const uint32_t[]){
5006 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5008 .op_flags
= XTENSA_OP_PRIVILEGED
,
5011 .translate
= translate_wsr
,
5012 .test_ill
= test_ill_hpi
,
5013 .par
= (const uint32_t[]){
5015 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5017 .op_flags
= XTENSA_OP_PRIVILEGED
,
5020 .translate
= translate_wsr
,
5021 .test_ill
= test_ill_hpi
,
5022 .par
= (const uint32_t[]){
5024 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5026 .op_flags
= XTENSA_OP_PRIVILEGED
,
5029 .translate
= translate_wsr
,
5030 .test_ill
= test_ill_hpi
,
5031 .par
= (const uint32_t[]){
5033 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5035 .op_flags
= XTENSA_OP_PRIVILEGED
,
5038 .translate
= translate_wsr
,
5039 .test_ill
= test_ill_hpi
,
5040 .par
= (const uint32_t[]){
5042 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5044 .op_flags
= XTENSA_OP_PRIVILEGED
,
5047 .translate
= translate_wsr
,
5048 .test_ill
= test_ill_hpi
,
5049 .par
= (const uint32_t[]){
5051 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5053 .op_flags
= XTENSA_OP_PRIVILEGED
,
5056 .translate
= translate_wsr
,
5057 .test_ill
= test_ill_hpi
,
5058 .par
= (const uint32_t[]){
5060 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5062 .op_flags
= XTENSA_OP_PRIVILEGED
,
5064 .name
= "wsr.eraccess",
5065 .translate
= translate_wsr_mask
,
5066 .par
= (const uint32_t[]){
5071 .op_flags
= XTENSA_OP_PRIVILEGED
,
5073 .name
= "wsr.exccause",
5074 .translate
= translate_wsr
,
5075 .test_ill
= test_ill_sr
,
5076 .par
= (const uint32_t[]){
5078 XTENSA_OPTION_EXCEPTION
,
5080 .op_flags
= XTENSA_OP_PRIVILEGED
,
5082 .name
= "wsr.excsave1",
5083 .translate
= translate_wsr
,
5084 .test_ill
= test_ill_sr
,
5085 .par
= (const uint32_t[]){
5087 XTENSA_OPTION_EXCEPTION
,
5089 .op_flags
= XTENSA_OP_PRIVILEGED
,
5091 .name
= "wsr.excsave2",
5092 .translate
= translate_wsr
,
5093 .test_ill
= test_ill_hpi
,
5094 .par
= (const uint32_t[]){
5096 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5098 .op_flags
= XTENSA_OP_PRIVILEGED
,
5100 .name
= "wsr.excsave3",
5101 .translate
= translate_wsr
,
5102 .test_ill
= test_ill_hpi
,
5103 .par
= (const uint32_t[]){
5105 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5107 .op_flags
= XTENSA_OP_PRIVILEGED
,
5109 .name
= "wsr.excsave4",
5110 .translate
= translate_wsr
,
5111 .test_ill
= test_ill_hpi
,
5112 .par
= (const uint32_t[]){
5114 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5116 .op_flags
= XTENSA_OP_PRIVILEGED
,
5118 .name
= "wsr.excsave5",
5119 .translate
= translate_wsr
,
5120 .test_ill
= test_ill_hpi
,
5121 .par
= (const uint32_t[]){
5123 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5125 .op_flags
= XTENSA_OP_PRIVILEGED
,
5127 .name
= "wsr.excsave6",
5128 .translate
= translate_wsr
,
5129 .test_ill
= test_ill_hpi
,
5130 .par
= (const uint32_t[]){
5132 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5134 .op_flags
= XTENSA_OP_PRIVILEGED
,
5136 .name
= "wsr.excsave7",
5137 .translate
= translate_wsr
,
5138 .test_ill
= test_ill_hpi
,
5139 .par
= (const uint32_t[]){
5141 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5143 .op_flags
= XTENSA_OP_PRIVILEGED
,
5145 .name
= "wsr.excvaddr",
5146 .translate
= translate_wsr
,
5147 .test_ill
= test_ill_sr
,
5148 .par
= (const uint32_t[]){
5150 XTENSA_OPTION_EXCEPTION
,
5152 .op_flags
= XTENSA_OP_PRIVILEGED
,
5154 .name
= "wsr.ibreaka0",
5155 .translate
= translate_wsr_ibreaka
,
5156 .test_ill
= test_ill_ibreak
,
5157 .par
= (const uint32_t[]){
5159 XTENSA_OPTION_DEBUG
,
5161 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5163 .name
= "wsr.ibreaka1",
5164 .translate
= translate_wsr_ibreaka
,
5165 .test_ill
= test_ill_ibreak
,
5166 .par
= (const uint32_t[]){
5168 XTENSA_OPTION_DEBUG
,
5170 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5172 .name
= "wsr.ibreakenable",
5173 .translate
= translate_wsr_ibreakenable
,
5174 .test_ill
= test_ill_sr
,
5175 .par
= (const uint32_t[]){
5177 XTENSA_OPTION_DEBUG
,
5179 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5181 .name
= "wsr.icount",
5182 .translate
= translate_wsr_icount
,
5183 .test_ill
= test_ill_sr
,
5184 .par
= (const uint32_t[]){
5186 XTENSA_OPTION_DEBUG
,
5188 .op_flags
= XTENSA_OP_PRIVILEGED
,
5190 .name
= "wsr.icountlevel",
5191 .translate
= translate_wsr_mask
,
5192 .test_ill
= test_ill_sr
,
5193 .par
= (const uint32_t[]){
5195 XTENSA_OPTION_DEBUG
,
5198 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5200 .name
= "wsr.intclear",
5201 .translate
= translate_wsr_intclear
,
5202 .test_ill
= test_ill_sr
,
5203 .par
= (const uint32_t[]){
5205 XTENSA_OPTION_INTERRUPT
,
5208 XTENSA_OP_PRIVILEGED
|
5209 XTENSA_OP_EXIT_TB_0
|
5210 XTENSA_OP_CHECK_INTERRUPTS
,
5212 .name
= "wsr.intenable",
5213 .translate
= translate_wsr
,
5214 .test_ill
= test_ill_sr
,
5215 .par
= (const uint32_t[]){
5217 XTENSA_OPTION_INTERRUPT
,
5220 XTENSA_OP_PRIVILEGED
|
5221 XTENSA_OP_EXIT_TB_0
|
5222 XTENSA_OP_CHECK_INTERRUPTS
,
5224 .name
= "wsr.interrupt",
5225 .translate
= translate_wsr
,
5226 .test_ill
= test_ill_sr
,
5227 .par
= (const uint32_t[]){
5229 XTENSA_OPTION_INTERRUPT
,
5232 XTENSA_OP_PRIVILEGED
|
5233 XTENSA_OP_EXIT_TB_0
|
5234 XTENSA_OP_CHECK_INTERRUPTS
,
5236 .name
= "wsr.intset",
5237 .translate
= translate_wsr_intset
,
5238 .test_ill
= test_ill_sr
,
5239 .par
= (const uint32_t[]){
5241 XTENSA_OPTION_INTERRUPT
,
5244 XTENSA_OP_PRIVILEGED
|
5245 XTENSA_OP_EXIT_TB_0
|
5246 XTENSA_OP_CHECK_INTERRUPTS
,
5248 .name
= "wsr.itlbcfg",
5249 .translate
= translate_wsr_mask
,
5250 .test_ill
= test_ill_sr
,
5251 .par
= (const uint32_t[]){
5256 .op_flags
= XTENSA_OP_PRIVILEGED
,
5259 .translate
= translate_wsr
,
5260 .test_ill
= test_ill_sr
,
5261 .par
= (const uint32_t[]){
5265 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
5267 .name
= "wsr.lcount",
5268 .translate
= translate_wsr
,
5269 .test_ill
= test_ill_sr
,
5270 .par
= (const uint32_t[]){
5276 .translate
= translate_wsr
,
5277 .test_ill
= test_ill_sr
,
5278 .par
= (const uint32_t[]){
5282 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
5284 .name
= "wsr.litbase",
5285 .translate
= translate_wsr_mask
,
5286 .test_ill
= test_ill_sr
,
5287 .par
= (const uint32_t[]){
5289 XTENSA_OPTION_EXTENDED_L32R
,
5292 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
5295 .translate
= translate_wsr
,
5296 .test_ill
= test_ill_sr
,
5297 .par
= (const uint32_t[]){
5299 XTENSA_OPTION_MAC16
,
5303 .translate
= translate_wsr
,
5304 .test_ill
= test_ill_sr
,
5305 .par
= (const uint32_t[]){
5307 XTENSA_OPTION_MAC16
,
5311 .translate
= translate_wsr
,
5312 .test_ill
= test_ill_sr
,
5313 .par
= (const uint32_t[]){
5315 XTENSA_OPTION_MAC16
,
5319 .translate
= translate_wsr
,
5320 .test_ill
= test_ill_sr
,
5321 .par
= (const uint32_t[]){
5323 XTENSA_OPTION_MAC16
,
5326 .name
= "wsr.memctl",
5327 .translate
= translate_wsr_memctl
,
5328 .par
= (const uint32_t[]){MEMCTL
},
5329 .op_flags
= XTENSA_OP_PRIVILEGED
,
5332 .translate
= translate_wsr
,
5333 .test_ill
= test_ill_sr
,
5334 .par
= (const uint32_t[]){
5336 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5338 .op_flags
= XTENSA_OP_PRIVILEGED
,
5341 .translate
= translate_wsr
,
5342 .test_ill
= test_ill_sr
,
5343 .par
= (const uint32_t[]){
5345 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5347 .op_flags
= XTENSA_OP_PRIVILEGED
,
5350 .translate
= translate_wsr
,
5351 .test_ill
= test_ill_sr
,
5352 .par
= (const uint32_t[]){
5354 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5356 .op_flags
= XTENSA_OP_PRIVILEGED
,
5358 .name
= "wsr.mesave",
5359 .translate
= translate_wsr
,
5360 .test_ill
= test_ill_sr
,
5361 .par
= (const uint32_t[]){
5363 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5365 .op_flags
= XTENSA_OP_PRIVILEGED
,
5368 .translate
= translate_wsr
,
5369 .test_ill
= test_ill_sr
,
5370 .par
= (const uint32_t[]){
5372 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5374 .op_flags
= XTENSA_OP_PRIVILEGED
,
5376 .name
= "wsr.mevaddr",
5377 .translate
= translate_wsr
,
5378 .test_ill
= test_ill_sr
,
5379 .par
= (const uint32_t[]){
5381 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5383 .op_flags
= XTENSA_OP_PRIVILEGED
,
5385 .name
= "wsr.misc0",
5386 .translate
= translate_wsr
,
5387 .test_ill
= test_ill_sr
,
5388 .par
= (const uint32_t[]){
5390 XTENSA_OPTION_MISC_SR
,
5392 .op_flags
= XTENSA_OP_PRIVILEGED
,
5394 .name
= "wsr.misc1",
5395 .translate
= translate_wsr
,
5396 .test_ill
= test_ill_sr
,
5397 .par
= (const uint32_t[]){
5399 XTENSA_OPTION_MISC_SR
,
5401 .op_flags
= XTENSA_OP_PRIVILEGED
,
5403 .name
= "wsr.misc2",
5404 .translate
= translate_wsr
,
5405 .test_ill
= test_ill_sr
,
5406 .par
= (const uint32_t[]){
5408 XTENSA_OPTION_MISC_SR
,
5410 .op_flags
= XTENSA_OP_PRIVILEGED
,
5412 .name
= "wsr.misc3",
5413 .translate
= translate_wsr
,
5414 .test_ill
= test_ill_sr
,
5415 .par
= (const uint32_t[]){
5417 XTENSA_OPTION_MISC_SR
,
5419 .op_flags
= XTENSA_OP_PRIVILEGED
,
5422 .translate
= translate_wsr
,
5423 .test_ill
= test_ill_sr
,
5424 .par
= (const uint32_t[]){
5426 XTENSA_OPTION_TRACE_PORT
,
5428 .op_flags
= XTENSA_OP_PRIVILEGED
,
5430 .name
= "wsr.mpuenb",
5431 .translate
= translate_wsr_mpuenb
,
5432 .test_ill
= test_ill_sr
,
5433 .par
= (const uint32_t[]){
5437 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5439 .name
= "wsr.prefctl",
5440 .translate
= translate_wsr
,
5441 .par
= (const uint32_t[]){PREFCTL
},
5444 .op_flags
= XTENSA_OP_ILL
,
5447 .translate
= translate_wsr_ps
,
5448 .test_ill
= test_ill_sr
,
5449 .par
= (const uint32_t[]){
5451 XTENSA_OPTION_EXCEPTION
,
5454 XTENSA_OP_PRIVILEGED
|
5455 XTENSA_OP_EXIT_TB_M1
|
5456 XTENSA_OP_CHECK_INTERRUPTS
,
5458 .name
= "wsr.ptevaddr",
5459 .translate
= translate_wsr_mask
,
5460 .test_ill
= test_ill_sr
,
5461 .par
= (const uint32_t[]){
5466 .op_flags
= XTENSA_OP_PRIVILEGED
,
5468 .name
= "wsr.rasid",
5469 .translate
= translate_wsr_rasid
,
5470 .test_ill
= test_ill_sr
,
5471 .par
= (const uint32_t[]){
5475 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5478 .translate
= translate_wsr_sar
,
5479 .par
= (const uint32_t[]){SAR
},
5481 .name
= "wsr.scompare1",
5482 .translate
= translate_wsr
,
5483 .test_ill
= test_ill_sr
,
5484 .par
= (const uint32_t[]){
5486 XTENSA_OPTION_CONDITIONAL_STORE
,
5489 .name
= "wsr.vecbase",
5490 .translate
= translate_wsr
,
5491 .test_ill
= test_ill_sr
,
5492 .par
= (const uint32_t[]){
5494 XTENSA_OPTION_RELOCATABLE_VECTOR
,
5496 .op_flags
= XTENSA_OP_PRIVILEGED
,
5498 .name
= "wsr.windowbase",
5499 .translate
= translate_wsr_windowbase
,
5500 .test_ill
= test_ill_sr
,
5501 .par
= (const uint32_t[]){
5503 XTENSA_OPTION_WINDOWED_REGISTER
,
5505 .op_flags
= XTENSA_OP_PRIVILEGED
|
5506 XTENSA_OP_EXIT_TB_M1
|
5507 XTENSA_OP_SYNC_REGISTER_WINDOW
,
5509 .name
= "wsr.windowstart",
5510 .translate
= translate_wsr_windowstart
,
5511 .test_ill
= test_ill_sr
,
5512 .par
= (const uint32_t[]){
5514 XTENSA_OPTION_WINDOWED_REGISTER
,
5516 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5518 .name
= "wur.expstate",
5519 .translate
= translate_wur
,
5520 .par
= (const uint32_t[]){EXPSTATE
},
5523 .translate
= translate_wur_fcr
,
5524 .par
= (const uint32_t[]){FCR
},
5528 .translate
= translate_wur_fsr
,
5529 .par
= (const uint32_t[]){FSR
},
5532 .name
= "wur.threadptr",
5533 .translate
= translate_wur
,
5534 .par
= (const uint32_t[]){THREADPTR
},
5537 .translate
= translate_xor
,
5540 .translate
= translate_boolean
,
5541 .par
= (const uint32_t[]){BOOLEAN_XOR
},
5544 .op_flags
= XTENSA_OP_ILL
,
5547 .op_flags
= XTENSA_OP_ILL
,
5549 .name
= "xsr.acchi",
5550 .translate
= translate_xsr_acchi
,
5551 .test_ill
= test_ill_sr
,
5552 .par
= (const uint32_t[]){
5554 XTENSA_OPTION_MAC16
,
5557 .name
= "xsr.acclo",
5558 .translate
= translate_xsr
,
5559 .test_ill
= test_ill_sr
,
5560 .par
= (const uint32_t[]){
5562 XTENSA_OPTION_MAC16
,
5565 .name
= "xsr.atomctl",
5566 .translate
= translate_xsr_mask
,
5567 .test_ill
= test_ill_sr
,
5568 .par
= (const uint32_t[]){
5570 XTENSA_OPTION_ATOMCTL
,
5573 .op_flags
= XTENSA_OP_PRIVILEGED
,
5576 .translate
= translate_xsr_mask
,
5577 .test_ill
= test_ill_sr
,
5578 .par
= (const uint32_t[]){
5580 XTENSA_OPTION_BOOLEAN
,
5584 .name
= "xsr.cacheadrdis",
5585 .translate
= translate_xsr_mask
,
5586 .test_ill
= test_ill_sr
,
5587 .par
= (const uint32_t[]){
5592 .op_flags
= XTENSA_OP_PRIVILEGED
,
5594 .name
= "xsr.cacheattr",
5595 .translate
= translate_xsr
,
5596 .test_ill
= test_ill_sr
,
5597 .par
= (const uint32_t[]){
5599 XTENSA_OPTION_CACHEATTR
,
5601 .op_flags
= XTENSA_OP_PRIVILEGED
,
5603 .name
= "xsr.ccompare0",
5604 .translate
= translate_xsr_ccompare
,
5605 .test_ill
= test_ill_ccompare
,
5606 .par
= (const uint32_t[]){
5608 XTENSA_OPTION_TIMER_INTERRUPT
,
5610 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5612 .name
= "xsr.ccompare1",
5613 .translate
= translate_xsr_ccompare
,
5614 .test_ill
= test_ill_ccompare
,
5615 .par
= (const uint32_t[]){
5617 XTENSA_OPTION_TIMER_INTERRUPT
,
5619 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5621 .name
= "xsr.ccompare2",
5622 .translate
= translate_xsr_ccompare
,
5623 .test_ill
= test_ill_ccompare
,
5624 .par
= (const uint32_t[]){
5626 XTENSA_OPTION_TIMER_INTERRUPT
,
5628 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5630 .name
= "xsr.ccount",
5631 .translate
= translate_xsr_ccount
,
5632 .test_ill
= test_ill_sr
,
5633 .par
= (const uint32_t[]){
5635 XTENSA_OPTION_TIMER_INTERRUPT
,
5637 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5639 .name
= "xsr.configid0",
5640 .op_flags
= XTENSA_OP_ILL
,
5642 .name
= "xsr.configid1",
5643 .op_flags
= XTENSA_OP_ILL
,
5645 .name
= "xsr.cpenable",
5646 .translate
= translate_xsr_mask
,
5647 .test_ill
= test_ill_sr
,
5648 .par
= (const uint32_t[]){
5650 XTENSA_OPTION_COPROCESSOR
,
5653 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5655 .name
= "xsr.dbreaka0",
5656 .translate
= translate_xsr_dbreaka
,
5657 .test_ill
= test_ill_dbreak
,
5658 .par
= (const uint32_t[]){
5660 XTENSA_OPTION_DEBUG
,
5662 .op_flags
= XTENSA_OP_PRIVILEGED
,
5664 .name
= "xsr.dbreaka1",
5665 .translate
= translate_xsr_dbreaka
,
5666 .test_ill
= test_ill_dbreak
,
5667 .par
= (const uint32_t[]){
5669 XTENSA_OPTION_DEBUG
,
5671 .op_flags
= XTENSA_OP_PRIVILEGED
,
5673 .name
= "xsr.dbreakc0",
5674 .translate
= translate_xsr_dbreakc
,
5675 .test_ill
= test_ill_dbreak
,
5676 .par
= (const uint32_t[]){
5678 XTENSA_OPTION_DEBUG
,
5680 .op_flags
= XTENSA_OP_PRIVILEGED
,
5682 .name
= "xsr.dbreakc1",
5683 .translate
= translate_xsr_dbreakc
,
5684 .test_ill
= test_ill_dbreak
,
5685 .par
= (const uint32_t[]){
5687 XTENSA_OPTION_DEBUG
,
5689 .op_flags
= XTENSA_OP_PRIVILEGED
,
5692 .translate
= translate_xsr
,
5693 .test_ill
= test_ill_sr
,
5694 .par
= (const uint32_t[]){
5696 XTENSA_OPTION_DEBUG
,
5698 .op_flags
= XTENSA_OP_PRIVILEGED
,
5700 .name
= "xsr.debugcause",
5701 .op_flags
= XTENSA_OP_ILL
,
5704 .translate
= translate_xsr
,
5705 .test_ill
= test_ill_sr
,
5706 .par
= (const uint32_t[]){
5708 XTENSA_OPTION_EXCEPTION
,
5710 .op_flags
= XTENSA_OP_PRIVILEGED
,
5712 .name
= "xsr.dtlbcfg",
5713 .translate
= translate_xsr_mask
,
5714 .test_ill
= test_ill_sr
,
5715 .par
= (const uint32_t[]){
5720 .op_flags
= XTENSA_OP_PRIVILEGED
,
5723 .translate
= translate_xsr
,
5724 .test_ill
= test_ill_sr
,
5725 .par
= (const uint32_t[]){
5727 XTENSA_OPTION_EXCEPTION
,
5729 .op_flags
= XTENSA_OP_PRIVILEGED
,
5732 .translate
= translate_xsr
,
5733 .test_ill
= test_ill_hpi
,
5734 .par
= (const uint32_t[]){
5736 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5738 .op_flags
= XTENSA_OP_PRIVILEGED
,
5741 .translate
= translate_xsr
,
5742 .test_ill
= test_ill_hpi
,
5743 .par
= (const uint32_t[]){
5745 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5747 .op_flags
= XTENSA_OP_PRIVILEGED
,
5750 .translate
= translate_xsr
,
5751 .test_ill
= test_ill_hpi
,
5752 .par
= (const uint32_t[]){
5754 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5756 .op_flags
= XTENSA_OP_PRIVILEGED
,
5759 .translate
= translate_xsr
,
5760 .test_ill
= test_ill_hpi
,
5761 .par
= (const uint32_t[]){
5763 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5765 .op_flags
= XTENSA_OP_PRIVILEGED
,
5768 .translate
= translate_xsr
,
5769 .test_ill
= test_ill_hpi
,
5770 .par
= (const uint32_t[]){
5772 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5774 .op_flags
= XTENSA_OP_PRIVILEGED
,
5777 .translate
= translate_xsr
,
5778 .test_ill
= test_ill_hpi
,
5779 .par
= (const uint32_t[]){
5781 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5783 .op_flags
= XTENSA_OP_PRIVILEGED
,
5786 .translate
= translate_xsr
,
5787 .test_ill
= test_ill_hpi
,
5788 .par
= (const uint32_t[]){
5790 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5792 .op_flags
= XTENSA_OP_PRIVILEGED
,
5795 .translate
= translate_xsr
,
5796 .test_ill
= test_ill_hpi
,
5797 .par
= (const uint32_t[]){
5799 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5801 .op_flags
= XTENSA_OP_PRIVILEGED
,
5804 .translate
= translate_xsr
,
5805 .test_ill
= test_ill_hpi
,
5806 .par
= (const uint32_t[]){
5808 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5810 .op_flags
= XTENSA_OP_PRIVILEGED
,
5813 .translate
= translate_xsr
,
5814 .test_ill
= test_ill_hpi
,
5815 .par
= (const uint32_t[]){
5817 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5819 .op_flags
= XTENSA_OP_PRIVILEGED
,
5822 .translate
= translate_xsr
,
5823 .test_ill
= test_ill_hpi
,
5824 .par
= (const uint32_t[]){
5826 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5828 .op_flags
= XTENSA_OP_PRIVILEGED
,
5831 .translate
= translate_xsr
,
5832 .test_ill
= test_ill_hpi
,
5833 .par
= (const uint32_t[]){
5835 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5837 .op_flags
= XTENSA_OP_PRIVILEGED
,
5839 .name
= "xsr.eraccess",
5840 .translate
= translate_xsr_mask
,
5841 .par
= (const uint32_t[]){
5846 .op_flags
= XTENSA_OP_PRIVILEGED
,
5848 .name
= "xsr.exccause",
5849 .translate
= translate_xsr
,
5850 .test_ill
= test_ill_sr
,
5851 .par
= (const uint32_t[]){
5853 XTENSA_OPTION_EXCEPTION
,
5855 .op_flags
= XTENSA_OP_PRIVILEGED
,
5857 .name
= "xsr.excsave1",
5858 .translate
= translate_xsr
,
5859 .test_ill
= test_ill_sr
,
5860 .par
= (const uint32_t[]){
5862 XTENSA_OPTION_EXCEPTION
,
5864 .op_flags
= XTENSA_OP_PRIVILEGED
,
5866 .name
= "xsr.excsave2",
5867 .translate
= translate_xsr
,
5868 .test_ill
= test_ill_hpi
,
5869 .par
= (const uint32_t[]){
5871 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5873 .op_flags
= XTENSA_OP_PRIVILEGED
,
5875 .name
= "xsr.excsave3",
5876 .translate
= translate_xsr
,
5877 .test_ill
= test_ill_hpi
,
5878 .par
= (const uint32_t[]){
5880 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5882 .op_flags
= XTENSA_OP_PRIVILEGED
,
5884 .name
= "xsr.excsave4",
5885 .translate
= translate_xsr
,
5886 .test_ill
= test_ill_hpi
,
5887 .par
= (const uint32_t[]){
5889 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5891 .op_flags
= XTENSA_OP_PRIVILEGED
,
5893 .name
= "xsr.excsave5",
5894 .translate
= translate_xsr
,
5895 .test_ill
= test_ill_hpi
,
5896 .par
= (const uint32_t[]){
5898 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5900 .op_flags
= XTENSA_OP_PRIVILEGED
,
5902 .name
= "xsr.excsave6",
5903 .translate
= translate_xsr
,
5904 .test_ill
= test_ill_hpi
,
5905 .par
= (const uint32_t[]){
5907 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5909 .op_flags
= XTENSA_OP_PRIVILEGED
,
5911 .name
= "xsr.excsave7",
5912 .translate
= translate_xsr
,
5913 .test_ill
= test_ill_hpi
,
5914 .par
= (const uint32_t[]){
5916 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5918 .op_flags
= XTENSA_OP_PRIVILEGED
,
5920 .name
= "xsr.excvaddr",
5921 .translate
= translate_xsr
,
5922 .test_ill
= test_ill_sr
,
5923 .par
= (const uint32_t[]){
5925 XTENSA_OPTION_EXCEPTION
,
5927 .op_flags
= XTENSA_OP_PRIVILEGED
,
5929 .name
= "xsr.ibreaka0",
5930 .translate
= translate_xsr_ibreaka
,
5931 .test_ill
= test_ill_ibreak
,
5932 .par
= (const uint32_t[]){
5934 XTENSA_OPTION_DEBUG
,
5936 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5938 .name
= "xsr.ibreaka1",
5939 .translate
= translate_xsr_ibreaka
,
5940 .test_ill
= test_ill_ibreak
,
5941 .par
= (const uint32_t[]){
5943 XTENSA_OPTION_DEBUG
,
5945 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5947 .name
= "xsr.ibreakenable",
5948 .translate
= translate_xsr_ibreakenable
,
5949 .test_ill
= test_ill_sr
,
5950 .par
= (const uint32_t[]){
5952 XTENSA_OPTION_DEBUG
,
5954 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5956 .name
= "xsr.icount",
5957 .translate
= translate_xsr_icount
,
5958 .test_ill
= test_ill_sr
,
5959 .par
= (const uint32_t[]){
5961 XTENSA_OPTION_DEBUG
,
5963 .op_flags
= XTENSA_OP_PRIVILEGED
,
5965 .name
= "xsr.icountlevel",
5966 .translate
= translate_xsr_mask
,
5967 .test_ill
= test_ill_sr
,
5968 .par
= (const uint32_t[]){
5970 XTENSA_OPTION_DEBUG
,
5973 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5975 .name
= "xsr.intclear",
5976 .op_flags
= XTENSA_OP_ILL
,
5978 .name
= "xsr.intenable",
5979 .translate
= translate_xsr
,
5980 .test_ill
= test_ill_sr
,
5981 .par
= (const uint32_t[]){
5983 XTENSA_OPTION_INTERRUPT
,
5986 XTENSA_OP_PRIVILEGED
|
5987 XTENSA_OP_EXIT_TB_0
|
5988 XTENSA_OP_CHECK_INTERRUPTS
,
5990 .name
= "xsr.interrupt",
5991 .op_flags
= XTENSA_OP_ILL
,
5993 .name
= "xsr.intset",
5994 .op_flags
= XTENSA_OP_ILL
,
5996 .name
= "xsr.itlbcfg",
5997 .translate
= translate_xsr_mask
,
5998 .test_ill
= test_ill_sr
,
5999 .par
= (const uint32_t[]){
6004 .op_flags
= XTENSA_OP_PRIVILEGED
,
6007 .translate
= translate_xsr
,
6008 .test_ill
= test_ill_sr
,
6009 .par
= (const uint32_t[]){
6013 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
6015 .name
= "xsr.lcount",
6016 .translate
= translate_xsr
,
6017 .test_ill
= test_ill_sr
,
6018 .par
= (const uint32_t[]){
6024 .translate
= translate_xsr
,
6025 .test_ill
= test_ill_sr
,
6026 .par
= (const uint32_t[]){
6030 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
6032 .name
= "xsr.litbase",
6033 .translate
= translate_xsr_mask
,
6034 .test_ill
= test_ill_sr
,
6035 .par
= (const uint32_t[]){
6037 XTENSA_OPTION_EXTENDED_L32R
,
6040 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
6043 .translate
= translate_xsr
,
6044 .test_ill
= test_ill_sr
,
6045 .par
= (const uint32_t[]){
6047 XTENSA_OPTION_MAC16
,
6051 .translate
= translate_xsr
,
6052 .test_ill
= test_ill_sr
,
6053 .par
= (const uint32_t[]){
6055 XTENSA_OPTION_MAC16
,
6059 .translate
= translate_xsr
,
6060 .test_ill
= test_ill_sr
,
6061 .par
= (const uint32_t[]){
6063 XTENSA_OPTION_MAC16
,
6067 .translate
= translate_xsr
,
6068 .test_ill
= test_ill_sr
,
6069 .par
= (const uint32_t[]){
6071 XTENSA_OPTION_MAC16
,
6074 .name
= "xsr.memctl",
6075 .translate
= translate_xsr_memctl
,
6076 .par
= (const uint32_t[]){MEMCTL
},
6077 .op_flags
= XTENSA_OP_PRIVILEGED
,
6080 .translate
= translate_xsr
,
6081 .test_ill
= test_ill_sr
,
6082 .par
= (const uint32_t[]){
6084 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6086 .op_flags
= XTENSA_OP_PRIVILEGED
,
6089 .translate
= translate_xsr
,
6090 .test_ill
= test_ill_sr
,
6091 .par
= (const uint32_t[]){
6093 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6095 .op_flags
= XTENSA_OP_PRIVILEGED
,
6098 .translate
= translate_xsr
,
6099 .test_ill
= test_ill_sr
,
6100 .par
= (const uint32_t[]){
6102 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6104 .op_flags
= XTENSA_OP_PRIVILEGED
,
6106 .name
= "xsr.mesave",
6107 .translate
= translate_xsr
,
6108 .test_ill
= test_ill_sr
,
6109 .par
= (const uint32_t[]){
6111 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6113 .op_flags
= XTENSA_OP_PRIVILEGED
,
6116 .translate
= translate_xsr
,
6117 .test_ill
= test_ill_sr
,
6118 .par
= (const uint32_t[]){
6120 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6122 .op_flags
= XTENSA_OP_PRIVILEGED
,
6124 .name
= "xsr.mevaddr",
6125 .translate
= translate_xsr
,
6126 .test_ill
= test_ill_sr
,
6127 .par
= (const uint32_t[]){
6129 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6131 .op_flags
= XTENSA_OP_PRIVILEGED
,
6133 .name
= "xsr.misc0",
6134 .translate
= translate_xsr
,
6135 .test_ill
= test_ill_sr
,
6136 .par
= (const uint32_t[]){
6138 XTENSA_OPTION_MISC_SR
,
6140 .op_flags
= XTENSA_OP_PRIVILEGED
,
6142 .name
= "xsr.misc1",
6143 .translate
= translate_xsr
,
6144 .test_ill
= test_ill_sr
,
6145 .par
= (const uint32_t[]){
6147 XTENSA_OPTION_MISC_SR
,
6149 .op_flags
= XTENSA_OP_PRIVILEGED
,
6151 .name
= "xsr.misc2",
6152 .translate
= translate_xsr
,
6153 .test_ill
= test_ill_sr
,
6154 .par
= (const uint32_t[]){
6156 XTENSA_OPTION_MISC_SR
,
6158 .op_flags
= XTENSA_OP_PRIVILEGED
,
6160 .name
= "xsr.misc3",
6161 .translate
= translate_xsr
,
6162 .test_ill
= test_ill_sr
,
6163 .par
= (const uint32_t[]){
6165 XTENSA_OPTION_MISC_SR
,
6167 .op_flags
= XTENSA_OP_PRIVILEGED
,
6169 .name
= "xsr.mpuenb",
6170 .translate
= translate_xsr_mpuenb
,
6171 .test_ill
= test_ill_sr
,
6172 .par
= (const uint32_t[]){
6176 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
6178 .name
= "xsr.prefctl",
6179 .translate
= translate_xsr
,
6180 .par
= (const uint32_t[]){PREFCTL
},
6183 .op_flags
= XTENSA_OP_ILL
,
6186 .translate
= translate_xsr_ps
,
6187 .test_ill
= test_ill_sr
,
6188 .par
= (const uint32_t[]){
6190 XTENSA_OPTION_EXCEPTION
,
6193 XTENSA_OP_PRIVILEGED
|
6194 XTENSA_OP_EXIT_TB_M1
|
6195 XTENSA_OP_CHECK_INTERRUPTS
,
6197 .name
= "xsr.ptevaddr",
6198 .translate
= translate_xsr_mask
,
6199 .test_ill
= test_ill_sr
,
6200 .par
= (const uint32_t[]){
6205 .op_flags
= XTENSA_OP_PRIVILEGED
,
6207 .name
= "xsr.rasid",
6208 .translate
= translate_xsr_rasid
,
6209 .test_ill
= test_ill_sr
,
6210 .par
= (const uint32_t[]){
6214 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
6217 .translate
= translate_xsr_sar
,
6218 .par
= (const uint32_t[]){SAR
},
6220 .name
= "xsr.scompare1",
6221 .translate
= translate_xsr
,
6222 .test_ill
= test_ill_sr
,
6223 .par
= (const uint32_t[]){
6225 XTENSA_OPTION_CONDITIONAL_STORE
,
6228 .name
= "xsr.vecbase",
6229 .translate
= translate_xsr
,
6230 .test_ill
= test_ill_sr
,
6231 .par
= (const uint32_t[]){
6233 XTENSA_OPTION_RELOCATABLE_VECTOR
,
6235 .op_flags
= XTENSA_OP_PRIVILEGED
,
6237 .name
= "xsr.windowbase",
6238 .translate
= translate_xsr_windowbase
,
6239 .test_ill
= test_ill_sr
,
6240 .par
= (const uint32_t[]){
6242 XTENSA_OPTION_WINDOWED_REGISTER
,
6244 .op_flags
= XTENSA_OP_PRIVILEGED
|
6245 XTENSA_OP_EXIT_TB_M1
|
6246 XTENSA_OP_SYNC_REGISTER_WINDOW
,
6248 .name
= "xsr.windowstart",
6249 .translate
= translate_xsr_windowstart
,
6250 .test_ill
= test_ill_sr
,
6251 .par
= (const uint32_t[]){
6253 XTENSA_OPTION_WINDOWED_REGISTER
,
6255 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
6259 const XtensaOpcodeTranslators xtensa_core_opcodes
= {
6260 .num_opcodes
= ARRAY_SIZE(core_ops
),
6265 static void translate_abs_s(DisasContext
*dc
, const OpcodeArg arg
[],
6266 const uint32_t par
[])
6268 gen_helper_abs_s(arg
[0].out
, arg
[1].in
);
6271 static void translate_add_s(DisasContext
*dc
, const OpcodeArg arg
[],
6272 const uint32_t par
[])
6274 gen_helper_add_s(arg
[0].out
, cpu_env
,
6275 arg
[1].in
, arg
[2].in
);
6288 static void translate_compare_s(DisasContext
*dc
, const OpcodeArg arg
[],
6289 const uint32_t par
[])
6291 static void (* const helper
[])(TCGv_env env
, TCGv_i32 bit
,
6292 TCGv_i32 s
, TCGv_i32 t
) = {
6293 [COMPARE_UN
] = gen_helper_un_s
,
6294 [COMPARE_OEQ
] = gen_helper_oeq_s
,
6295 [COMPARE_UEQ
] = gen_helper_ueq_s
,
6296 [COMPARE_OLT
] = gen_helper_olt_s
,
6297 [COMPARE_ULT
] = gen_helper_ult_s
,
6298 [COMPARE_OLE
] = gen_helper_ole_s
,
6299 [COMPARE_ULE
] = gen_helper_ule_s
,
6301 TCGv_i32 bit
= tcg_const_i32(1 << arg
[0].imm
);
6303 helper
[par
[0]](cpu_env
, bit
, arg
[1].in
, arg
[2].in
);
6307 static void translate_float_s(DisasContext
*dc
, const OpcodeArg arg
[],
6308 const uint32_t par
[])
6310 TCGv_i32 scale
= tcg_const_i32(-arg
[2].imm
);
6313 gen_helper_uitof(arg
[0].out
, cpu_env
, arg
[1].in
, scale
);
6315 gen_helper_itof(arg
[0].out
, cpu_env
, arg
[1].in
, scale
);
6317 tcg_temp_free(scale
);
6320 static void translate_ftoi_s(DisasContext
*dc
, const OpcodeArg arg
[],
6321 const uint32_t par
[])
6323 TCGv_i32 rounding_mode
= tcg_const_i32(par
[0]);
6324 TCGv_i32 scale
= tcg_const_i32(arg
[2].imm
);
6327 gen_helper_ftoui(arg
[0].out
, arg
[1].in
,
6328 rounding_mode
, scale
);
6330 gen_helper_ftoi(arg
[0].out
, arg
[1].in
,
6331 rounding_mode
, scale
);
6333 tcg_temp_free(rounding_mode
);
6334 tcg_temp_free(scale
);
6337 static void translate_ldsti(DisasContext
*dc
, const OpcodeArg arg
[],
6338 const uint32_t par
[])
6340 TCGv_i32 addr
= tcg_temp_new_i32();
6342 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
6343 gen_load_store_alignment(dc
, 2, addr
, false);
6345 tcg_gen_qemu_st32(arg
[0].in
, addr
, dc
->cring
);
6347 tcg_gen_qemu_ld32u(arg
[0].out
, addr
, dc
->cring
);
6350 tcg_gen_mov_i32(arg
[1].out
, addr
);
6352 tcg_temp_free(addr
);
6355 static void translate_ldstx(DisasContext
*dc
, const OpcodeArg arg
[],
6356 const uint32_t par
[])
6358 TCGv_i32 addr
= tcg_temp_new_i32();
6360 tcg_gen_add_i32(addr
, arg
[1].in
, arg
[2].in
);
6361 gen_load_store_alignment(dc
, 2, addr
, false);
6363 tcg_gen_qemu_st32(arg
[0].in
, addr
, dc
->cring
);
6365 tcg_gen_qemu_ld32u(arg
[0].out
, addr
, dc
->cring
);
6368 tcg_gen_mov_i32(arg
[1].out
, addr
);
6370 tcg_temp_free(addr
);
6373 static void translate_madd_s(DisasContext
*dc
, const OpcodeArg arg
[],
6374 const uint32_t par
[])
6376 gen_helper_madd_s(arg
[0].out
, cpu_env
,
6377 arg
[0].in
, arg
[1].in
, arg
[2].in
);
6380 static void translate_mov_s(DisasContext
*dc
, const OpcodeArg arg
[],
6381 const uint32_t par
[])
6383 tcg_gen_mov_i32(arg
[0].out
, arg
[1].in
);
6386 static void translate_movcond_s(DisasContext
*dc
, const OpcodeArg arg
[],
6387 const uint32_t par
[])
6389 TCGv_i32 zero
= tcg_const_i32(0);
6391 tcg_gen_movcond_i32(par
[0], arg
[0].out
,
6393 arg
[1].in
, arg
[0].in
);
6394 tcg_temp_free(zero
);
6397 static void translate_movp_s(DisasContext
*dc
, const OpcodeArg arg
[],
6398 const uint32_t par
[])
6400 TCGv_i32 zero
= tcg_const_i32(0);
6401 TCGv_i32 tmp
= tcg_temp_new_i32();
6403 tcg_gen_andi_i32(tmp
, arg
[2].in
, 1 << arg
[2].imm
);
6404 tcg_gen_movcond_i32(par
[0],
6405 arg
[0].out
, tmp
, zero
,
6406 arg
[1].in
, arg
[0].in
);
6408 tcg_temp_free(zero
);
6411 static void translate_mul_s(DisasContext
*dc
, const OpcodeArg arg
[],
6412 const uint32_t par
[])
6414 gen_helper_mul_s(arg
[0].out
, cpu_env
,
6415 arg
[1].in
, arg
[2].in
);
6418 static void translate_msub_s(DisasContext
*dc
, const OpcodeArg arg
[],
6419 const uint32_t par
[])
6421 gen_helper_msub_s(arg
[0].out
, cpu_env
,
6422 arg
[0].in
, arg
[1].in
, arg
[2].in
);
6425 static void translate_neg_s(DisasContext
*dc
, const OpcodeArg arg
[],
6426 const uint32_t par
[])
6428 gen_helper_neg_s(arg
[0].out
, arg
[1].in
);
6431 static void translate_rfr_s(DisasContext
*dc
, const OpcodeArg arg
[],
6432 const uint32_t par
[])
6434 tcg_gen_mov_i32(arg
[0].out
, arg
[1].in
);
6437 static void translate_sub_s(DisasContext
*dc
, const OpcodeArg arg
[],
6438 const uint32_t par
[])
6440 gen_helper_sub_s(arg
[0].out
, cpu_env
,
6441 arg
[1].in
, arg
[2].in
);
6444 static void translate_wfr_s(DisasContext
*dc
, const OpcodeArg arg
[],
6445 const uint32_t par
[])
6447 tcg_gen_mov_i32(arg
[0].out
, arg
[1].in
);
6450 static const XtensaOpcodeOps fpu2000_ops
[] = {
6453 .translate
= translate_abs_s
,
6457 .translate
= translate_add_s
,
6461 .translate
= translate_ftoi_s
,
6462 .par
= (const uint32_t[]){float_round_up
, false},
6466 .translate
= translate_float_s
,
6467 .par
= (const uint32_t[]){false},
6471 .translate
= translate_ftoi_s
,
6472 .par
= (const uint32_t[]){float_round_down
, false},
6476 .translate
= translate_ldsti
,
6477 .par
= (const uint32_t[]){false, false},
6478 .op_flags
= XTENSA_OP_LOAD
,
6482 .translate
= translate_ldsti
,
6483 .par
= (const uint32_t[]){false, true},
6484 .op_flags
= XTENSA_OP_LOAD
,
6488 .translate
= translate_ldstx
,
6489 .par
= (const uint32_t[]){false, false},
6490 .op_flags
= XTENSA_OP_LOAD
,
6494 .translate
= translate_ldstx
,
6495 .par
= (const uint32_t[]){false, true},
6496 .op_flags
= XTENSA_OP_LOAD
,
6500 .translate
= translate_madd_s
,
6504 .translate
= translate_mov_s
,
6508 .translate
= translate_movcond_s
,
6509 .par
= (const uint32_t[]){TCG_COND_EQ
},
6513 .translate
= translate_movp_s
,
6514 .par
= (const uint32_t[]){TCG_COND_EQ
},
6518 .translate
= translate_movcond_s
,
6519 .par
= (const uint32_t[]){TCG_COND_GE
},
6523 .translate
= translate_movcond_s
,
6524 .par
= (const uint32_t[]){TCG_COND_LT
},
6528 .translate
= translate_movcond_s
,
6529 .par
= (const uint32_t[]){TCG_COND_NE
},
6533 .translate
= translate_movp_s
,
6534 .par
= (const uint32_t[]){TCG_COND_NE
},
6538 .translate
= translate_msub_s
,
6542 .translate
= translate_mul_s
,
6546 .translate
= translate_neg_s
,
6550 .translate
= translate_compare_s
,
6551 .par
= (const uint32_t[]){COMPARE_OEQ
},
6555 .translate
= translate_compare_s
,
6556 .par
= (const uint32_t[]){COMPARE_OLE
},
6560 .translate
= translate_compare_s
,
6561 .par
= (const uint32_t[]){COMPARE_OLT
},
6565 .translate
= translate_rfr_s
,
6569 .translate
= translate_ftoi_s
,
6570 .par
= (const uint32_t[]){float_round_nearest_even
, false},
6574 .translate
= translate_ldsti
,
6575 .par
= (const uint32_t[]){true, false},
6576 .op_flags
= XTENSA_OP_STORE
,
6580 .translate
= translate_ldsti
,
6581 .par
= (const uint32_t[]){true, true},
6582 .op_flags
= XTENSA_OP_STORE
,
6586 .translate
= translate_ldstx
,
6587 .par
= (const uint32_t[]){true, false},
6588 .op_flags
= XTENSA_OP_STORE
,
6592 .translate
= translate_ldstx
,
6593 .par
= (const uint32_t[]){true, true},
6594 .op_flags
= XTENSA_OP_STORE
,
6598 .translate
= translate_sub_s
,
6602 .translate
= translate_ftoi_s
,
6603 .par
= (const uint32_t[]){float_round_to_zero
, false},
6607 .translate
= translate_compare_s
,
6608 .par
= (const uint32_t[]){COMPARE_UEQ
},
6612 .translate
= translate_float_s
,
6613 .par
= (const uint32_t[]){true},
6617 .translate
= translate_compare_s
,
6618 .par
= (const uint32_t[]){COMPARE_ULE
},
6622 .translate
= translate_compare_s
,
6623 .par
= (const uint32_t[]){COMPARE_ULT
},
6627 .translate
= translate_compare_s
,
6628 .par
= (const uint32_t[]){COMPARE_UN
},
6632 .translate
= translate_ftoi_s
,
6633 .par
= (const uint32_t[]){float_round_to_zero
, true},
6637 .translate
= translate_wfr_s
,
6642 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes
= {
6643 .num_opcodes
= ARRAY_SIZE(fpu2000_ops
),
6644 .opcode
= fpu2000_ops
,