target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 /* QEMU addressing/paging config */
  24 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
  25 #if defined(TARGET_RISCV64)
  26 #define TARGET_LONG_BITS 64
  27 #define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
  28 #define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
  29 #elif defined(TARGET_RISCV32)
  30 #define TARGET_LONG_BITS 32
  31 #define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
  32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
  33 #endif
  34
  35 #define TCG_GUEST_DEFAULT_MO 0
  36
  37 #define CPUArchState struct CPURISCVState
  38
  39 #include "qemu-common.h"
  40 #include "qom/cpu.h"
  41 #include "exec/cpu-defs.h"
  42 #include "fpu/softfloat.h"
  43
  44 #define TYPE_RISCV_CPU "riscv-cpu"
  45
  46 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  47 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  48 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  49
  50 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  51 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
  52 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
  53 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
  54 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
  55 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
  56 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
  57 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  58 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  59 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  60 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  61
  62 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
  63 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
  64
  65 #if defined(TARGET_RISCV32)
  66 #define RVXLEN RV32
  67 #elif defined(TARGET_RISCV64)
  68 #define RVXLEN RV64
  69 #endif
  70
  71 #define RV(x) ((target_ulong)1 << (x - 'A'))
  72
  73 #define RVI RV('I')
  74 #define RVE RV('E') /* E and I are mutually exclusive */
  75 #define RVM RV('M')
  76 #define RVA RV('A')
  77 #define RVF RV('F')
  78 #define RVD RV('D')
  79 #define RVC RV('C')
  80 #define RVS RV('S')
  81 #define RVU RV('U')
  82
  83 /* S extension denotes that Supervisor mode exists, however it is possible
  84    to have a core that support S mode but does not have an MMU and there
  85    is currently no bit in misa to indicate whether an MMU exists or not
  86    so a cpu features bitfield is required, likewise for optional PMP support */
  87 enum {
  88     RISCV_FEATURE_MMU,
  89     RISCV_FEATURE_PMP,
  90     RISCV_FEATURE_MISA
  91 };
  92
  93 #define USER_VERSION_2_02_0 0x00020200
  94 #define PRIV_VERSION_1_09_1 0x00010901
  95 #define PRIV_VERSION_1_10_0 0x00011000
  96
  97 #define TRANSLATE_FAIL 1
  98 #define TRANSLATE_SUCCESS 0
  99 #define NB_MMU_MODES 4
 100 #define MMU_USER_IDX 3
 101
 102 #define MAX_RISCV_PMPS (16)
 103
 104 typedef struct CPURISCVState CPURISCVState;
 105
 106 #include "pmp.h"
 107
 108 struct CPURISCVState {
 109     target_ulong gpr[32];
 110     uint64_t fpr[32]; /* assume both F and D extensions */
 111     target_ulong pc;
 112     target_ulong load_res;
 113     target_ulong load_val;
 114
 115     target_ulong frm;
 116
 117     target_ulong badaddr;
 118
 119     target_ulong user_ver;
 120     target_ulong priv_ver;
 121     target_ulong misa;
 122     target_ulong misa_mask;
 123
 124     uint32_t features;
 125
 126 #ifdef CONFIG_USER_ONLY
 127     uint32_t elf_flags;
 128 #endif
 129
 130 #ifndef CONFIG_USER_ONLY
 131     target_ulong priv;
 132     target_ulong resetvec;
 133
 134     target_ulong mhartid;
 135     target_ulong mstatus;
 136
 137     /*
 138      * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
 139      * by I/O threads. It should be read with atomic_read. It should be updated
 140      * using riscv_cpu_update_mip with the iothread mutex held. The iothread
 141      * mutex must be held because mip must be consistent with the CPU inturrept
 142      * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt
 143      * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
 144      * mip is 32-bits to allow atomic_read on 32-bit hosts.
 145      */
 146     uint32_t mip;
 147     uint32_t miclaim;
 148
 149     target_ulong mie;
 150     target_ulong mideleg;
 151
 152     target_ulong sptbr;  /* until: priv-1.9.1 */
 153     target_ulong satp;   /* since: priv-1.10.0 */
 154     target_ulong sbadaddr;
 155     target_ulong mbadaddr;
 156     target_ulong medeleg;
 157
 158     target_ulong stvec;
 159     target_ulong sepc;
 160     target_ulong scause;
 161
 162     target_ulong mtvec;
 163     target_ulong mepc;
 164     target_ulong mcause;
 165     target_ulong mtval;  /* since: priv-1.10.0 */
 166
 167     target_ulong scounteren;
 168     target_ulong mcounteren;
 169
 170     target_ulong sscratch;
 171     target_ulong mscratch;
 172
 173     /* temporary htif regs */
 174     uint64_t mfromhost;
 175     uint64_t mtohost;
 176     uint64_t timecmp;
 177
 178     /* physical memory protection */
 179     pmp_table_t pmp_state;
 180
 181     /* True if in debugger mode.  */
 182     bool debugger;
 183 #endif
 184
 185     float_status fp_status;
 186
 187     /* QEMU */
 188     CPU_COMMON
 189
 190     /* Fields from here on are preserved across CPU reset. */
 191     QEMUTimer *timer; /* Internal timer */
 192 };
 193
 194 #define RISCV_CPU_CLASS(klass) \
 195     OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
 196 #define RISCV_CPU(obj) \
 197     OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
 198 #define RISCV_CPU_GET_CLASS(obj) \
 199     OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
 200
 201 /**
 202  * RISCVCPUClass:
 203  * @parent_realize: The parent class' realize handler.
 204  * @parent_reset: The parent class' reset handler.
 205  *
 206  * A RISCV CPU model.
 207  */
 208 typedef struct RISCVCPUClass {
 209     /*< private >*/
 210     CPUClass parent_class;
 211     /*< public >*/
 212     DeviceRealize parent_realize;
 213     void (*parent_reset)(CPUState *cpu);
 214 } RISCVCPUClass;
 215
 216 /**
 217  * RISCVCPU:
 218  * @env: #CPURISCVState
 219  *
 220  * A RISCV CPU.
 221  */
 222 typedef struct RISCVCPU {
 223     /*< private >*/
 224     CPUState parent_obj;
 225     /*< public >*/
 226     CPURISCVState env;
 227 } RISCVCPU;
 228
 229 static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env)
 230 {
 231     return container_of(env, RISCVCPU, env);
 232 }
 233
 234 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 235 {
 236     return (env->misa & ext) != 0;
 237 }
 238
 239 static inline bool riscv_feature(CPURISCVState *env, int feature)
 240 {
 241     return env->features & (1ULL << feature);
 242 }
 243
 244 #include "cpu_user.h"
 245 #include "cpu_bits.h"
 246
 247 extern const char * const riscv_int_regnames[];
 248 extern const char * const riscv_fpr_regnames[];
 249 extern const char * const riscv_excp_names[];
 250 extern const char * const riscv_intr_names[];
 251
 252 #define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e))
 253 #define ENV_OFFSET offsetof(RISCVCPU, env)
 254
 255 void riscv_cpu_do_interrupt(CPUState *cpu);
 256 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 257 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 258 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 259 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 260 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 261 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 262                                     MMUAccessType access_type, int mmu_idx,
 263                                     uintptr_t retaddr);
 264 int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
 265                               int rw, int mmu_idx);
 266 char *riscv_isa_string(RISCVCPU *cpu);
 267 void riscv_cpu_list(void);
 268
 269 #define cpu_signal_handler riscv_cpu_signal_handler
 270 #define cpu_list riscv_cpu_list
 271 #define cpu_mmu_index riscv_cpu_mmu_index
 272
 273 #ifndef CONFIG_USER_ONLY
 274 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 275 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 276 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 277 #endif
 278 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 279
 280 void riscv_translate_init(void);
 281 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 282 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 283                                          uint32_t exception, uintptr_t pc);
 284
 285 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 286 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 287
 288 #define TB_FLAGS_MMU_MASK   3
 289 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 290
 291 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 292                                         target_ulong *cs_base, uint32_t *flags)
 293 {
 294     *pc = env->pc;
 295     *cs_base = 0;
 296 #ifdef CONFIG_USER_ONLY
 297     *flags = TB_FLAGS_MSTATUS_FS;
 298 #else
 299     *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
 300 #endif
 301 }
 302
 303 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 304                 target_ulong new_value, target_ulong write_mask);
 305 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
 306                       target_ulong new_value, target_ulong write_mask);
 307
 308 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 309                                    target_ulong val)
 310 {
 311     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 312 }
 313
 314 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 315 {
 316     target_ulong val = 0;
 317     riscv_csrrw(env, csrno, &val, 0, 0);
 318     return val;
 319 }
 320
 321 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
 322 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 323     target_ulong *ret_value);
 324 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 325     target_ulong new_value);
 326 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 327     target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
 328
 329 typedef struct {
 330     riscv_csr_predicate_fn predicate;
 331     riscv_csr_read_fn read;
 332     riscv_csr_write_fn write;
 333     riscv_csr_op_fn op;
 334 } riscv_csr_operations;
 335
 336 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 337 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 338
 339 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 340
 341 #include "exec/cpu-all.h"
 342
 343 #endif /* RISCV_CPU_H */