2 * ARM VFP floating-point operations
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "exec/helper-proto.h"
24 #include "fpu/softfloat.h"
25 #include "internals.h"
28 /* VFP support. We follow the convention used for VFP instructions:
29 Single precision routines have a "s" suffix, double precision a
32 /* Convert host exception flags to vfp form. */
33 static inline int vfp_exceptbits_from_host(int host_bits
)
37 if (host_bits
& float_flag_invalid
) {
40 if (host_bits
& float_flag_divbyzero
) {
43 if (host_bits
& float_flag_overflow
) {
46 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
)) {
49 if (host_bits
& float_flag_inexact
) {
52 if (host_bits
& float_flag_input_denormal
) {
58 /* Convert vfp exception flags to target form. */
59 static inline int vfp_exceptbits_to_host(int target_bits
)
63 if (target_bits
& 1) {
64 host_bits
|= float_flag_invalid
;
66 if (target_bits
& 2) {
67 host_bits
|= float_flag_divbyzero
;
69 if (target_bits
& 4) {
70 host_bits
|= float_flag_overflow
;
72 if (target_bits
& 8) {
73 host_bits
|= float_flag_underflow
;
75 if (target_bits
& 0x10) {
76 host_bits
|= float_flag_inexact
;
78 if (target_bits
& 0x80) {
79 host_bits
|= float_flag_input_denormal
;
84 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
88 fpscr
= env
->vfp
.xregs
[ARM_VFP_FPSCR
]
89 | (env
->vfp
.vec_len
<< 16)
90 | (env
->vfp
.vec_stride
<< 20);
92 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
93 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
94 /* FZ16 does not generate an input denormal exception. */
95 i
|= (get_float_exception_flags(&env
->vfp
.fp_status_f16
)
96 & ~float_flag_input_denormal
);
97 fpscr
|= vfp_exceptbits_from_host(i
);
99 i
= env
->vfp
.qc
[0] | env
->vfp
.qc
[1] | env
->vfp
.qc
[2] | env
->vfp
.qc
[3];
100 fpscr
|= i
? FPCR_QC
: 0;
105 uint32_t vfp_get_fpscr(CPUARMState
*env
)
107 return HELPER(vfp_get_fpscr
)(env
);
110 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
113 uint32_t changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
115 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
116 if (!cpu_isar_feature(aa64_fp16
, env_archcpu(env
))) {
120 if (arm_feature(env
, ARM_FEATURE_M
)) {
122 * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
123 * and also for the trapped-exception-handling bits IxE.
129 * We don't implement trapped exception handling, so the
130 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
132 * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
133 * (which are stored in fp_status), and the other RES0 bits
134 * in between, then we clear all of the low 16 bits.
136 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = val
& 0xf7c80000;
137 env
->vfp
.vec_len
= (val
>> 16) & 7;
138 env
->vfp
.vec_stride
= (val
>> 20) & 3;
141 * The bit we set within fpscr_q is arbitrary; the register as a
142 * whole being zero/non-zero is what counts.
144 env
->vfp
.qc
[0] = val
& FPCR_QC
;
150 if (changed
& (3 << 22)) {
153 case FPROUNDING_TIEEVEN
:
154 i
= float_round_nearest_even
;
156 case FPROUNDING_POSINF
:
159 case FPROUNDING_NEGINF
:
160 i
= float_round_down
;
162 case FPROUNDING_ZERO
:
163 i
= float_round_to_zero
;
166 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
167 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
169 if (changed
& FPCR_FZ16
) {
170 bool ftz_enabled
= val
& FPCR_FZ16
;
171 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
172 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
174 if (changed
& FPCR_FZ
) {
175 bool ftz_enabled
= val
& FPCR_FZ
;
176 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
177 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
179 if (changed
& FPCR_DN
) {
180 bool dnan_enabled
= val
& FPCR_DN
;
181 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
182 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
186 * The exception flags are ORed together when we read fpscr so we
187 * only need to preserve the current state in one of our
188 * float_status values.
190 i
= vfp_exceptbits_to_host(val
);
191 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
192 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
193 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
196 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
198 HELPER(vfp_set_fpscr
)(env
, val
);
201 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
203 #define VFP_BINOP(name) \
204 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
206 float_status *fpst = fpstp; \
207 return float32_ ## name(a, b, fpst); \
209 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
211 float_status *fpst = fpstp; \
212 return float64_ ## name(a, b, fpst); \
224 float32
VFP_HELPER(neg
, s
)(float32 a
)
226 return float32_chs(a
);
229 float64
VFP_HELPER(neg
, d
)(float64 a
)
231 return float64_chs(a
);
234 float32
VFP_HELPER(abs
, s
)(float32 a
)
236 return float32_abs(a
);
239 float64
VFP_HELPER(abs
, d
)(float64 a
)
241 return float64_abs(a
);
244 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
246 return float32_sqrt(a
, &env
->vfp
.fp_status
);
249 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
251 return float64_sqrt(a
, &env
->vfp
.fp_status
);
254 static void softfloat_to_vfp_compare(CPUARMState
*env
, int cmp
)
258 case float_relation_equal
:
261 case float_relation_less
:
264 case float_relation_greater
:
267 case float_relation_unordered
:
271 g_assert_not_reached();
273 env
->vfp
.xregs
[ARM_VFP_FPSCR
] =
274 deposit32(env
->vfp
.xregs
[ARM_VFP_FPSCR
], 28, 4, flags
);
277 /* XXX: check quiet/signaling case */
278 #define DO_VFP_cmp(p, type) \
279 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
281 softfloat_to_vfp_compare(env, \
282 type ## _compare_quiet(a, b, &env->vfp.fp_status)); \
284 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
286 softfloat_to_vfp_compare(env, \
287 type ## _compare(a, b, &env->vfp.fp_status)); \
289 DO_VFP_cmp(s
, float32
)
290 DO_VFP_cmp(d
, float64
)
293 /* Integer to float and float to integer conversions */
295 #define CONV_ITOF(name, ftype, fsz, sign) \
296 ftype HELPER(name)(uint32_t x, void *fpstp) \
298 float_status *fpst = fpstp; \
299 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
302 #define CONV_FTOI(name, ftype, fsz, sign, round) \
303 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
305 float_status *fpst = fpstp; \
306 if (float##fsz##_is_any_nan(x)) { \
307 float_raise(float_flag_invalid, fpst); \
310 return float##fsz##_to_##sign##int32##round(x, fpst); \
313 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
314 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
315 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
316 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
318 FLOAT_CONVS(si
, h
, uint32_t, 16, )
319 FLOAT_CONVS(si
, s
, float32
, 32, )
320 FLOAT_CONVS(si
, d
, float64
, 64, )
321 FLOAT_CONVS(ui
, h
, uint32_t, 16, u
)
322 FLOAT_CONVS(ui
, s
, float32
, 32, u
)
323 FLOAT_CONVS(ui
, d
, float64
, 64, u
)
329 /* floating point conversion */
330 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
332 return float32_to_float64(x
, &env
->vfp
.fp_status
);
335 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
337 return float64_to_float32(x
, &env
->vfp
.fp_status
);
340 /* VFP3 fixed point conversion. */
341 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
342 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
344 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
346 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \
347 uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \
350 if (unlikely(float##fsz##_is_any_nan(x))) { \
351 float_raise(float_flag_invalid, fpst); \
354 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
357 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
358 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
359 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
360 float_round_to_zero, _round_to_zero) \
361 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
362 get_float_rounding_mode(fpst), )
364 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
365 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
366 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
367 get_float_rounding_mode(fpst), )
369 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
370 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
371 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
372 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
373 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
374 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
375 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
376 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
377 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
378 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
379 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
380 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
383 #undef VFP_CONV_FIX_FLOAT
384 #undef VFP_CONV_FLOAT_FIX_ROUND
385 #undef VFP_CONV_FIX_A64
387 uint32_t HELPER(vfp_sltoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
389 return int32_to_float16_scalbn(x
, -shift
, fpst
);
392 uint32_t HELPER(vfp_ultoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
394 return uint32_to_float16_scalbn(x
, -shift
, fpst
);
397 uint32_t HELPER(vfp_sqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
399 return int64_to_float16_scalbn(x
, -shift
, fpst
);
402 uint32_t HELPER(vfp_uqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
404 return uint64_to_float16_scalbn(x
, -shift
, fpst
);
407 uint32_t HELPER(vfp_toshh
)(uint32_t x
, uint32_t shift
, void *fpst
)
409 if (unlikely(float16_is_any_nan(x
))) {
410 float_raise(float_flag_invalid
, fpst
);
413 return float16_to_int16_scalbn(x
, get_float_rounding_mode(fpst
),
417 uint32_t HELPER(vfp_touhh
)(uint32_t x
, uint32_t shift
, void *fpst
)
419 if (unlikely(float16_is_any_nan(x
))) {
420 float_raise(float_flag_invalid
, fpst
);
423 return float16_to_uint16_scalbn(x
, get_float_rounding_mode(fpst
),
427 uint32_t HELPER(vfp_toslh
)(uint32_t x
, uint32_t shift
, void *fpst
)
429 if (unlikely(float16_is_any_nan(x
))) {
430 float_raise(float_flag_invalid
, fpst
);
433 return float16_to_int32_scalbn(x
, get_float_rounding_mode(fpst
),
437 uint32_t HELPER(vfp_toulh
)(uint32_t x
, uint32_t shift
, void *fpst
)
439 if (unlikely(float16_is_any_nan(x
))) {
440 float_raise(float_flag_invalid
, fpst
);
443 return float16_to_uint32_scalbn(x
, get_float_rounding_mode(fpst
),
447 uint64_t HELPER(vfp_tosqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
449 if (unlikely(float16_is_any_nan(x
))) {
450 float_raise(float_flag_invalid
, fpst
);
453 return float16_to_int64_scalbn(x
, get_float_rounding_mode(fpst
),
457 uint64_t HELPER(vfp_touqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
459 if (unlikely(float16_is_any_nan(x
))) {
460 float_raise(float_flag_invalid
, fpst
);
463 return float16_to_uint64_scalbn(x
, get_float_rounding_mode(fpst
),
467 /* Set the current fp rounding mode and return the old one.
468 * The argument is a softfloat float_round_ value.
470 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
472 float_status
*fp_status
= fpstp
;
474 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
475 set_float_rounding_mode(rmode
, fp_status
);
480 /* Set the current fp rounding mode in the standard fp status and return
481 * the old one. This is for NEON instructions that need to change the
482 * rounding mode but wish to use the standard FPSCR values for everything
483 * else. Always set the rounding mode back to the correct value after
485 * The argument is a softfloat float_round_ value.
487 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
489 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
491 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
492 set_float_rounding_mode(rmode
, fp_status
);
497 /* Half precision conversions. */
498 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
500 /* Squash FZ16 to 0 for the duration of conversion. In this case,
501 * it would affect flushing input denormals.
503 float_status
*fpst
= fpstp
;
504 flag save
= get_flush_inputs_to_zero(fpst
);
505 set_flush_inputs_to_zero(false, fpst
);
506 float32 r
= float16_to_float32(a
, !ahp_mode
, fpst
);
507 set_flush_inputs_to_zero(save
, fpst
);
511 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, void *fpstp
, uint32_t ahp_mode
)
513 /* Squash FZ16 to 0 for the duration of conversion. In this case,
514 * it would affect flushing output denormals.
516 float_status
*fpst
= fpstp
;
517 flag save
= get_flush_to_zero(fpst
);
518 set_flush_to_zero(false, fpst
);
519 float16 r
= float32_to_float16(a
, !ahp_mode
, fpst
);
520 set_flush_to_zero(save
, fpst
);
524 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
526 /* Squash FZ16 to 0 for the duration of conversion. In this case,
527 * it would affect flushing input denormals.
529 float_status
*fpst
= fpstp
;
530 flag save
= get_flush_inputs_to_zero(fpst
);
531 set_flush_inputs_to_zero(false, fpst
);
532 float64 r
= float16_to_float64(a
, !ahp_mode
, fpst
);
533 set_flush_inputs_to_zero(save
, fpst
);
537 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, void *fpstp
, uint32_t ahp_mode
)
539 /* Squash FZ16 to 0 for the duration of conversion. In this case,
540 * it would affect flushing output denormals.
542 float_status
*fpst
= fpstp
;
543 flag save
= get_flush_to_zero(fpst
);
544 set_flush_to_zero(false, fpst
);
545 float16 r
= float64_to_float16(a
, !ahp_mode
, fpst
);
546 set_flush_to_zero(save
, fpst
);
550 #define float32_two make_float32(0x40000000)
551 #define float32_three make_float32(0x40400000)
552 #define float32_one_point_five make_float32(0x3fc00000)
554 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
556 float_status
*s
= &env
->vfp
.standard_fp_status
;
557 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
558 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
559 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
560 float_raise(float_flag_input_denormal
, s
);
564 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
567 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
569 float_status
*s
= &env
->vfp
.standard_fp_status
;
571 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
572 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
573 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
574 float_raise(float_flag_input_denormal
, s
);
576 return float32_one_point_five
;
578 product
= float32_mul(a
, b
, s
);
579 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
584 /* Constants 256 and 512 are used in some helpers; we avoid relying on
585 * int->float conversions at run-time. */
586 #define float64_256 make_float64(0x4070000000000000LL)
587 #define float64_512 make_float64(0x4080000000000000LL)
588 #define float16_maxnorm make_float16(0x7bff)
589 #define float32_maxnorm make_float32(0x7f7fffff)
590 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
592 /* Reciprocal functions
594 * The algorithm that must be used to calculate the estimate
595 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
598 /* See RecipEstimate()
600 * input is a 9 bit fixed point number
601 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
602 * result range 256 .. 511 for a number from 1.0 to 511/256.
605 static int recip_estimate(int input
)
608 assert(256 <= input
&& input
< 512);
612 assert(256 <= r
&& r
< 512);
617 * Common wrapper to call recip_estimate
619 * The parameters are exponent and 64 bit fraction (without implicit
620 * bit) where the binary point is nominally at bit 52. Returns a
621 * float64 which can then be rounded to the appropriate size by the
625 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
627 uint32_t scaled
, estimate
;
628 uint64_t result_frac
;
631 /* Handle sub-normals */
633 if (extract64(frac
, 51, 1) == 0) {
641 /* scaled = UInt('1':fraction<51:44>) */
642 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
643 estimate
= recip_estimate(scaled
);
645 result_exp
= exp_off
- *exp
;
646 result_frac
= deposit64(0, 44, 8, estimate
);
647 if (result_exp
== 0) {
648 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
649 } else if (result_exp
== -1) {
650 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
659 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
661 switch (fpst
->float_rounding_mode
) {
662 case float_round_nearest_even
: /* Round to Nearest */
664 case float_round_up
: /* Round to +Inf */
666 case float_round_down
: /* Round to -Inf */
668 case float_round_to_zero
: /* Round to Zero */
672 g_assert_not_reached();
675 uint32_t HELPER(recpe_f16
)(uint32_t input
, void *fpstp
)
677 float_status
*fpst
= fpstp
;
678 float16 f16
= float16_squash_input_denormal(input
, fpst
);
679 uint32_t f16_val
= float16_val(f16
);
680 uint32_t f16_sign
= float16_is_neg(f16
);
681 int f16_exp
= extract32(f16_val
, 10, 5);
682 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
685 if (float16_is_any_nan(f16
)) {
687 if (float16_is_signaling_nan(f16
, fpst
)) {
688 float_raise(float_flag_invalid
, fpst
);
689 nan
= float16_silence_nan(f16
, fpst
);
691 if (fpst
->default_nan_mode
) {
692 nan
= float16_default_nan(fpst
);
695 } else if (float16_is_infinity(f16
)) {
696 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
697 } else if (float16_is_zero(f16
)) {
698 float_raise(float_flag_divbyzero
, fpst
);
699 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
700 } else if (float16_abs(f16
) < (1 << 8)) {
701 /* Abs(value) < 2.0^-16 */
702 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
703 if (round_to_inf(fpst
, f16_sign
)) {
704 return float16_set_sign(float16_infinity
, f16_sign
);
706 return float16_set_sign(float16_maxnorm
, f16_sign
);
708 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
709 float_raise(float_flag_underflow
, fpst
);
710 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
713 f64_frac
= call_recip_estimate(&f16_exp
, 29,
714 ((uint64_t) f16_frac
) << (52 - 10));
716 /* result = sign : result_exp<4:0> : fraction<51:42> */
717 f16_val
= deposit32(0, 15, 1, f16_sign
);
718 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
719 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
720 return make_float16(f16_val
);
723 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
725 float_status
*fpst
= fpstp
;
726 float32 f32
= float32_squash_input_denormal(input
, fpst
);
727 uint32_t f32_val
= float32_val(f32
);
728 bool f32_sign
= float32_is_neg(f32
);
729 int f32_exp
= extract32(f32_val
, 23, 8);
730 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
733 if (float32_is_any_nan(f32
)) {
735 if (float32_is_signaling_nan(f32
, fpst
)) {
736 float_raise(float_flag_invalid
, fpst
);
737 nan
= float32_silence_nan(f32
, fpst
);
739 if (fpst
->default_nan_mode
) {
740 nan
= float32_default_nan(fpst
);
743 } else if (float32_is_infinity(f32
)) {
744 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
745 } else if (float32_is_zero(f32
)) {
746 float_raise(float_flag_divbyzero
, fpst
);
747 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
748 } else if (float32_abs(f32
) < (1ULL << 21)) {
749 /* Abs(value) < 2.0^-128 */
750 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
751 if (round_to_inf(fpst
, f32_sign
)) {
752 return float32_set_sign(float32_infinity
, f32_sign
);
754 return float32_set_sign(float32_maxnorm
, f32_sign
);
756 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
757 float_raise(float_flag_underflow
, fpst
);
758 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
761 f64_frac
= call_recip_estimate(&f32_exp
, 253,
762 ((uint64_t) f32_frac
) << (52 - 23));
764 /* result = sign : result_exp<7:0> : fraction<51:29> */
765 f32_val
= deposit32(0, 31, 1, f32_sign
);
766 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
767 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
768 return make_float32(f32_val
);
771 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
773 float_status
*fpst
= fpstp
;
774 float64 f64
= float64_squash_input_denormal(input
, fpst
);
775 uint64_t f64_val
= float64_val(f64
);
776 bool f64_sign
= float64_is_neg(f64
);
777 int f64_exp
= extract64(f64_val
, 52, 11);
778 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
780 /* Deal with any special cases */
781 if (float64_is_any_nan(f64
)) {
783 if (float64_is_signaling_nan(f64
, fpst
)) {
784 float_raise(float_flag_invalid
, fpst
);
785 nan
= float64_silence_nan(f64
, fpst
);
787 if (fpst
->default_nan_mode
) {
788 nan
= float64_default_nan(fpst
);
791 } else if (float64_is_infinity(f64
)) {
792 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
793 } else if (float64_is_zero(f64
)) {
794 float_raise(float_flag_divbyzero
, fpst
);
795 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
796 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
797 /* Abs(value) < 2.0^-1024 */
798 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
799 if (round_to_inf(fpst
, f64_sign
)) {
800 return float64_set_sign(float64_infinity
, f64_sign
);
802 return float64_set_sign(float64_maxnorm
, f64_sign
);
804 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
805 float_raise(float_flag_underflow
, fpst
);
806 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
809 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
811 /* result = sign : result_exp<10:0> : fraction<51:0>; */
812 f64_val
= deposit64(0, 63, 1, f64_sign
);
813 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
814 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
815 return make_float64(f64_val
);
818 /* The algorithm that must be used to calculate the estimate
819 * is specified by the ARM ARM.
822 static int do_recip_sqrt_estimate(int a
)
826 assert(128 <= a
&& a
< 512);
834 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
837 estimate
= (b
+ 1) / 2;
838 assert(256 <= estimate
&& estimate
< 512);
844 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
850 while (extract64(frac
, 51, 1) == 0) {
854 frac
= extract64(frac
, 0, 51) << 1;
858 /* scaled = UInt('01':fraction<51:45>) */
859 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
861 /* scaled = UInt('1':fraction<51:44>) */
862 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
864 estimate
= do_recip_sqrt_estimate(scaled
);
866 *exp
= (exp_off
- *exp
) / 2;
867 return extract64(estimate
, 0, 8) << 44;
870 uint32_t HELPER(rsqrte_f16
)(uint32_t input
, void *fpstp
)
872 float_status
*s
= fpstp
;
873 float16 f16
= float16_squash_input_denormal(input
, s
);
874 uint16_t val
= float16_val(f16
);
875 bool f16_sign
= float16_is_neg(f16
);
876 int f16_exp
= extract32(val
, 10, 5);
877 uint16_t f16_frac
= extract32(val
, 0, 10);
880 if (float16_is_any_nan(f16
)) {
882 if (float16_is_signaling_nan(f16
, s
)) {
883 float_raise(float_flag_invalid
, s
);
884 nan
= float16_silence_nan(f16
, s
);
886 if (s
->default_nan_mode
) {
887 nan
= float16_default_nan(s
);
890 } else if (float16_is_zero(f16
)) {
891 float_raise(float_flag_divbyzero
, s
);
892 return float16_set_sign(float16_infinity
, f16_sign
);
893 } else if (f16_sign
) {
894 float_raise(float_flag_invalid
, s
);
895 return float16_default_nan(s
);
896 } else if (float16_is_infinity(f16
)) {
900 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
901 * preserving the parity of the exponent. */
903 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
905 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
907 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
908 val
= deposit32(0, 15, 1, f16_sign
);
909 val
= deposit32(val
, 10, 5, f16_exp
);
910 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
911 return make_float16(val
);
914 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
916 float_status
*s
= fpstp
;
917 float32 f32
= float32_squash_input_denormal(input
, s
);
918 uint32_t val
= float32_val(f32
);
919 uint32_t f32_sign
= float32_is_neg(f32
);
920 int f32_exp
= extract32(val
, 23, 8);
921 uint32_t f32_frac
= extract32(val
, 0, 23);
924 if (float32_is_any_nan(f32
)) {
926 if (float32_is_signaling_nan(f32
, s
)) {
927 float_raise(float_flag_invalid
, s
);
928 nan
= float32_silence_nan(f32
, s
);
930 if (s
->default_nan_mode
) {
931 nan
= float32_default_nan(s
);
934 } else if (float32_is_zero(f32
)) {
935 float_raise(float_flag_divbyzero
, s
);
936 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
937 } else if (float32_is_neg(f32
)) {
938 float_raise(float_flag_invalid
, s
);
939 return float32_default_nan(s
);
940 } else if (float32_is_infinity(f32
)) {
944 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
945 * preserving the parity of the exponent. */
947 f64_frac
= ((uint64_t) f32_frac
) << 29;
949 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
951 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
952 val
= deposit32(0, 31, 1, f32_sign
);
953 val
= deposit32(val
, 23, 8, f32_exp
);
954 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
955 return make_float32(val
);
958 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
960 float_status
*s
= fpstp
;
961 float64 f64
= float64_squash_input_denormal(input
, s
);
962 uint64_t val
= float64_val(f64
);
963 bool f64_sign
= float64_is_neg(f64
);
964 int f64_exp
= extract64(val
, 52, 11);
965 uint64_t f64_frac
= extract64(val
, 0, 52);
967 if (float64_is_any_nan(f64
)) {
969 if (float64_is_signaling_nan(f64
, s
)) {
970 float_raise(float_flag_invalid
, s
);
971 nan
= float64_silence_nan(f64
, s
);
973 if (s
->default_nan_mode
) {
974 nan
= float64_default_nan(s
);
977 } else if (float64_is_zero(f64
)) {
978 float_raise(float_flag_divbyzero
, s
);
979 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
980 } else if (float64_is_neg(f64
)) {
981 float_raise(float_flag_invalid
, s
);
982 return float64_default_nan(s
);
983 } else if (float64_is_infinity(f64
)) {
987 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
989 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
990 val
= deposit64(0, 61, 1, f64_sign
);
991 val
= deposit64(val
, 52, 11, f64_exp
);
992 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
993 return make_float64(val
);
996 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
998 /* float_status *s = fpstp; */
1001 if ((a
& 0x80000000) == 0) {
1005 input
= extract32(a
, 23, 9);
1006 estimate
= recip_estimate(input
);
1008 return deposit32(0, (32 - 9), 9, estimate
);
1011 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
1015 if ((a
& 0xc0000000) == 0) {
1019 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
1021 return deposit32(0, 23, 9, estimate
);
1024 /* VFPv4 fused multiply-accumulate */
1025 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
1027 float_status
*fpst
= fpstp
;
1028 return float32_muladd(a
, b
, c
, 0, fpst
);
1031 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
1033 float_status
*fpst
= fpstp
;
1034 return float64_muladd(a
, b
, c
, 0, fpst
);
1037 /* ARMv8 round to integral */
1038 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
1040 return float32_round_to_int(x
, fp_status
);
1043 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
1045 return float64_round_to_int(x
, fp_status
);
1048 float32
HELPER(rints
)(float32 x
, void *fp_status
)
1050 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1053 ret
= float32_round_to_int(x
, fp_status
);
1055 /* Suppress any inexact exceptions the conversion produced */
1056 if (!(old_flags
& float_flag_inexact
)) {
1057 new_flags
= get_float_exception_flags(fp_status
);
1058 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1064 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
1066 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1069 ret
= float64_round_to_int(x
, fp_status
);
1071 new_flags
= get_float_exception_flags(fp_status
);
1073 /* Suppress any inexact exceptions the conversion produced */
1074 if (!(old_flags
& float_flag_inexact
)) {
1075 new_flags
= get_float_exception_flags(fp_status
);
1076 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1082 /* Convert ARM rounding mode to softfloat */
1083 int arm_rmode_to_sf(int rmode
)
1086 case FPROUNDING_TIEAWAY
:
1087 rmode
= float_round_ties_away
;
1089 case FPROUNDING_ODD
:
1090 /* FIXME: add support for TIEAWAY and ODD */
1091 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
1093 /* fall through for now */
1094 case FPROUNDING_TIEEVEN
:
1096 rmode
= float_round_nearest_even
;
1098 case FPROUNDING_POSINF
:
1099 rmode
= float_round_up
;
1101 case FPROUNDING_NEGINF
:
1102 rmode
= float_round_down
;
1104 case FPROUNDING_ZERO
:
1105 rmode
= float_round_to_zero
;
1112 * Implement float64 to int32_t conversion without saturation;
1113 * the result is supplied modulo 2^32.
1115 uint64_t HELPER(fjcvtzs
)(float64 value
, void *vstatus
)
1117 float_status
*status
= vstatus
;
1120 uint32_t inexact
= 1; /* !Z */
1122 sign
= extract64(value
, 63, 1);
1123 exp
= extract64(value
, 52, 11);
1124 frac
= extract64(value
, 0, 52);
1127 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1130 if (status
->flush_inputs_to_zero
) {
1131 float_raise(float_flag_input_denormal
, status
);
1133 float_raise(float_flag_inexact
, status
);
1138 } else if (exp
== 0x7ff) {
1139 /* This operation raises Invalid for both NaN and overflow (Inf). */
1140 float_raise(float_flag_invalid
, status
);
1143 int true_exp
= exp
- 1023;
1144 int shift
= true_exp
- 52;
1146 /* Restore implicit bit. */
1149 /* Shift the fraction into place. */
1151 /* The number is so large we must shift the fraction left. */
1153 /* The fraction is shifted out entirely. */
1158 } else if (shift
> -64) {
1159 /* Normal case -- shift right and notice if bits shift out. */
1160 inexact
= (frac
<< (64 + shift
)) != 0;
1163 /* The fraction is shifted out entirely. */
1167 /* Notice overflow or inexact exceptions. */
1168 if (true_exp
> 31 || frac
> (sign
? 0x80000000ull
: 0x7fffffff)) {
1169 /* Overflow, for which this operation raises invalid. */
1170 float_raise(float_flag_invalid
, status
);
1172 } else if (inexact
) {
1173 float_raise(float_flag_inexact
, status
);
1176 /* Honor the sign. */
1182 /* Pack the result and the env->ZF representation of Z together. */
1183 return deposit64(frac
, 32, 32, inexact
);
1186 uint32_t HELPER(vjcvt
)(float64 value
, CPUARMState
*env
)
1188 uint64_t pair
= HELPER(fjcvtzs
)(value
, &env
->vfp
.fp_status
);
1189 uint32_t result
= pair
;
1190 uint32_t z
= (pair
>> 32) == 0;
1192 /* Store Z, clear NCV, in FPSCR.NZCV. */
1193 env
->vfp
.xregs
[ARM_VFP_FPSCR
]
1194 = (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & ~CPSR_NZCV
) | (z
* CPSR_Z
);
1199 /* Round a float32 to an integer that fits in int32_t or int64_t. */
1200 static float32
frint_s(float32 f
, float_status
*fpst
, int intsize
)
1202 int old_flags
= get_float_exception_flags(fpst
);
1203 uint32_t exp
= extract32(f
, 23, 8);
1205 if (unlikely(exp
== 0xff)) {
1210 /* Round and re-extract the exponent. */
1211 f
= float32_round_to_int(f
, fpst
);
1212 exp
= extract32(f
, 23, 8);
1214 /* Validate the range of the result. */
1215 if (exp
< 126 + intsize
) {
1216 /* abs(F) <= INT{N}_MAX */
1219 if (exp
== 126 + intsize
) {
1220 uint32_t sign
= extract32(f
, 31, 1);
1221 uint32_t frac
= extract32(f
, 0, 23);
1222 if (sign
&& frac
== 0) {
1223 /* F == INT{N}_MIN */
1230 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1231 * inexact exception float32_round_to_int may have raised.
1233 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1234 return (0x100u
+ 126u + intsize
) << 23;
1237 float32
HELPER(frint32_s
)(float32 f
, void *fpst
)
1239 return frint_s(f
, fpst
, 32);
1242 float32
HELPER(frint64_s
)(float32 f
, void *fpst
)
1244 return frint_s(f
, fpst
, 64);
1247 /* Round a float64 to an integer that fits in int32_t or int64_t. */
1248 static float64
frint_d(float64 f
, float_status
*fpst
, int intsize
)
1250 int old_flags
= get_float_exception_flags(fpst
);
1251 uint32_t exp
= extract64(f
, 52, 11);
1253 if (unlikely(exp
== 0x7ff)) {
1258 /* Round and re-extract the exponent. */
1259 f
= float64_round_to_int(f
, fpst
);
1260 exp
= extract64(f
, 52, 11);
1262 /* Validate the range of the result. */
1263 if (exp
< 1022 + intsize
) {
1264 /* abs(F) <= INT{N}_MAX */
1267 if (exp
== 1022 + intsize
) {
1268 uint64_t sign
= extract64(f
, 63, 1);
1269 uint64_t frac
= extract64(f
, 0, 52);
1270 if (sign
&& frac
== 0) {
1271 /* F == INT{N}_MIN */
1278 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1279 * inexact exception float64_round_to_int may have raised.
1281 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1282 return (uint64_t)(0x800 + 1022 + intsize
) << 52;
1285 float64
HELPER(frint32_d
)(float64 f
, void *fpst
)
1287 return frint_d(f
, fpst
, 32);
1290 float64
HELPER(frint64_d
)(float64 f
, void *fpst
)
1292 return frint_d(f
, fpst
, 64);