2 * SD Association Host Standard Specification v2.0 controller emulation
4 * Datasheet: PartA2_SD_Host_Controller_Simplified_Specification_Ver2.00.pdf
6 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
7 * Mitsyanko Igor <i.mitsyanko@samsung.com>
8 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
10 * Based on MMC controller for Samsung S5PC1xx-based board emulation
11 * by Alexey Merkulov and Vladimir Monakhov.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
21 * See the GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 #include "qemu/osdep.h"
28 #include "qemu/units.h"
29 #include "qemu/error-report.h"
30 #include "qapi/error.h"
32 #include "hw/qdev-properties.h"
33 #include "sysemu/dma.h"
34 #include "qemu/timer.h"
35 #include "qemu/bitops.h"
36 #include "hw/sd/sdhci.h"
37 #include "migration/vmstate.h"
38 #include "sdhci-internal.h"
40 #include "qemu/module.h"
42 #include "qom/object.h"
44 #define TYPE_SDHCI_BUS "sdhci-bus"
45 /* This is reusing the SDBus typedef from SD_BUS */
46 DECLARE_INSTANCE_CHECKER(SDBus
, SDHCI_BUS
,
49 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
51 static inline unsigned int sdhci_get_fifolen(SDHCIState
*s
)
53 return 1 << (9 + FIELD_EX32(s
->capareg
, SDHC_CAPAB
, MAXBLOCKLENGTH
));
56 /* return true on error */
57 static bool sdhci_check_capab_freq_range(SDHCIState
*s
, const char *desc
,
58 uint8_t freq
, Error
**errp
)
60 if (s
->sd_spec_version
>= 3) {
68 error_setg(errp
, "SD %s clock frequency can have value"
69 "in range 0-63 only", desc
);
75 static void sdhci_check_capareg(SDHCIState
*s
, Error
**errp
)
77 uint64_t msk
= s
->capareg
;
81 switch (s
->sd_spec_version
) {
83 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS64BIT_V4
);
84 trace_sdhci_capareg("64-bit system bus (v4)", val
);
85 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS64BIT_V4
, 0);
87 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, UHS_II
);
88 trace_sdhci_capareg("UHS-II", val
);
89 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, UHS_II
, 0);
91 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA3
);
92 trace_sdhci_capareg("ADMA3", val
);
93 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA3
, 0);
97 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ASYNC_INT
);
98 trace_sdhci_capareg("async interrupt", val
);
99 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ASYNC_INT
, 0);
101 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SLOT_TYPE
);
103 error_setg(errp
, "slot-type not supported");
106 trace_sdhci_capareg("slot type", val
);
107 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SLOT_TYPE
, 0);
110 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, EMBEDDED_8BIT
);
111 trace_sdhci_capareg("8-bit bus", val
);
113 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, EMBEDDED_8BIT
, 0);
115 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS_SPEED
);
116 trace_sdhci_capareg("bus speed mask", val
);
117 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS_SPEED
, 0);
119 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, DRIVER_STRENGTH
);
120 trace_sdhci_capareg("driver strength mask", val
);
121 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, DRIVER_STRENGTH
, 0);
123 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TIMER_RETUNING
);
124 trace_sdhci_capareg("timer re-tuning", val
);
125 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TIMER_RETUNING
, 0);
127 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SDR50_TUNING
);
128 trace_sdhci_capareg("use SDR50 tuning", val
);
129 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SDR50_TUNING
, 0);
131 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, RETUNING_MODE
);
132 trace_sdhci_capareg("re-tuning mode", val
);
133 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, RETUNING_MODE
, 0);
135 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, CLOCK_MULT
);
136 trace_sdhci_capareg("clock multiplier", val
);
137 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, CLOCK_MULT
, 0);
140 case 2: /* default version */
141 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA2
);
142 trace_sdhci_capareg("ADMA2", val
);
143 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA2
, 0);
145 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA1
);
146 trace_sdhci_capareg("ADMA1", val
);
147 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA1
, 0);
149 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS64BIT
);
150 trace_sdhci_capareg("64-bit system bus (v3)", val
);
151 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS64BIT
, 0);
155 y
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TOUNIT
);
156 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TOUNIT
, 0);
158 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TOCLKFREQ
);
159 trace_sdhci_capareg(y
? "timeout (MHz)" : "Timeout (KHz)", val
);
160 if (sdhci_check_capab_freq_range(s
, "timeout", val
, errp
)) {
163 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TOCLKFREQ
, 0);
165 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BASECLKFREQ
);
166 trace_sdhci_capareg(y
? "base (MHz)" : "Base (KHz)", val
);
167 if (sdhci_check_capab_freq_range(s
, "base", val
, errp
)) {
170 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BASECLKFREQ
, 0);
172 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, MAXBLOCKLENGTH
);
174 error_setg(errp
, "block size can be 512, 1024 or 2048 only");
177 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s
));
178 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, MAXBLOCKLENGTH
, 0);
180 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, HIGHSPEED
);
181 trace_sdhci_capareg("high speed", val
);
182 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, HIGHSPEED
, 0);
184 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SDMA
);
185 trace_sdhci_capareg("SDMA", val
);
186 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SDMA
, 0);
188 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SUSPRESUME
);
189 trace_sdhci_capareg("suspend/resume", val
);
190 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SUSPRESUME
, 0);
192 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V33
);
193 trace_sdhci_capareg("3.3v", val
);
194 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V33
, 0);
196 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V30
);
197 trace_sdhci_capareg("3.0v", val
);
198 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V30
, 0);
200 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V18
);
201 trace_sdhci_capareg("1.8v", val
);
202 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V18
, 0);
206 error_setg(errp
, "Unsupported spec version: %u", s
->sd_spec_version
);
209 qemu_log_mask(LOG_UNIMP
,
210 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64
"\n", msk
);
214 static uint8_t sdhci_slotint(SDHCIState
*s
)
216 return (s
->norintsts
& s
->norintsigen
) || (s
->errintsts
& s
->errintsigen
) ||
217 ((s
->norintsts
& SDHC_NIS_INSERT
) && (s
->wakcon
& SDHC_WKUP_ON_INS
)) ||
218 ((s
->norintsts
& SDHC_NIS_REMOVE
) && (s
->wakcon
& SDHC_WKUP_ON_RMV
));
221 /* Return true if IRQ was pending and delivered */
222 static bool sdhci_update_irq(SDHCIState
*s
)
224 bool pending
= sdhci_slotint(s
);
226 qemu_set_irq(s
->irq
, pending
);
231 static void sdhci_raise_insertion_irq(void *opaque
)
233 SDHCIState
*s
= (SDHCIState
*)opaque
;
235 if (s
->norintsts
& SDHC_NIS_REMOVE
) {
236 timer_mod(s
->insert_timer
,
237 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
239 s
->prnsts
= 0x1ff0000;
240 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
241 s
->norintsts
|= SDHC_NIS_INSERT
;
247 static void sdhci_set_inserted(DeviceState
*dev
, bool level
)
249 SDHCIState
*s
= (SDHCIState
*)dev
;
251 trace_sdhci_set_inserted(level
? "insert" : "eject");
252 if ((s
->norintsts
& SDHC_NIS_REMOVE
) && level
) {
253 /* Give target some time to notice card ejection */
254 timer_mod(s
->insert_timer
,
255 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
258 s
->prnsts
= 0x1ff0000;
259 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
260 s
->norintsts
|= SDHC_NIS_INSERT
;
263 s
->prnsts
= 0x1fa0000;
264 s
->pwrcon
&= ~SDHC_POWER_ON
;
265 s
->clkcon
&= ~SDHC_CLOCK_SDCLK_EN
;
266 if (s
->norintstsen
& SDHC_NISEN_REMOVE
) {
267 s
->norintsts
|= SDHC_NIS_REMOVE
;
274 static void sdhci_set_readonly(DeviceState
*dev
, bool level
)
276 SDHCIState
*s
= (SDHCIState
*)dev
;
279 s
->prnsts
&= ~SDHC_WRITE_PROTECT
;
282 s
->prnsts
|= SDHC_WRITE_PROTECT
;
286 static void sdhci_reset(SDHCIState
*s
)
288 DeviceState
*dev
= DEVICE(s
);
290 timer_del(s
->insert_timer
);
291 timer_del(s
->transfer_timer
);
293 /* Set all registers to 0. Capabilities/Version registers are not cleared
294 * and assumed to always preserve their value, given to them during
296 memset(&s
->sdmasysad
, 0, (uintptr_t)&s
->capareg
- (uintptr_t)&s
->sdmasysad
);
298 /* Reset other state based on current card insertion/readonly status */
299 sdhci_set_inserted(dev
, sdbus_get_inserted(&s
->sdbus
));
300 sdhci_set_readonly(dev
, sdbus_get_readonly(&s
->sdbus
));
303 s
->stopped_state
= sdhc_not_stopped
;
304 s
->pending_insert_state
= false;
307 static void sdhci_poweron_reset(DeviceState
*dev
)
309 /* QOM (ie power-on) reset. This is identical to reset
310 * commanded via device register apart from handling of the
311 * 'pending insert on powerup' quirk.
313 SDHCIState
*s
= (SDHCIState
*)dev
;
317 if (s
->pending_insert_quirk
) {
318 s
->pending_insert_state
= true;
322 static void sdhci_data_transfer(void *opaque
);
324 static void sdhci_send_command(SDHCIState
*s
)
327 uint8_t response
[16];
332 request
.cmd
= s
->cmdreg
>> 8;
333 request
.arg
= s
->argument
;
335 trace_sdhci_send_command(request
.cmd
, request
.arg
);
336 rlen
= sdbus_do_command(&s
->sdbus
, &request
, response
);
338 if (s
->cmdreg
& SDHC_CMD_RESPONSE
) {
340 s
->rspreg
[0] = ldl_be_p(response
);
341 s
->rspreg
[1] = s
->rspreg
[2] = s
->rspreg
[3] = 0;
342 trace_sdhci_response4(s
->rspreg
[0]);
343 } else if (rlen
== 16) {
344 s
->rspreg
[0] = ldl_be_p(&response
[11]);
345 s
->rspreg
[1] = ldl_be_p(&response
[7]);
346 s
->rspreg
[2] = ldl_be_p(&response
[3]);
347 s
->rspreg
[3] = (response
[0] << 16) | (response
[1] << 8) |
349 trace_sdhci_response16(s
->rspreg
[3], s
->rspreg
[2],
350 s
->rspreg
[1], s
->rspreg
[0]);
352 trace_sdhci_error("timeout waiting for command response");
353 if (s
->errintstsen
& SDHC_EISEN_CMDTIMEOUT
) {
354 s
->errintsts
|= SDHC_EIS_CMDTIMEOUT
;
355 s
->norintsts
|= SDHC_NIS_ERR
;
359 if (!(s
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
) &&
360 (s
->norintstsen
& SDHC_NISEN_TRSCMP
) &&
361 (s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
) {
362 s
->norintsts
|= SDHC_NIS_TRSCMP
;
366 if (s
->norintstsen
& SDHC_NISEN_CMDCMP
) {
367 s
->norintsts
|= SDHC_NIS_CMDCMP
;
372 if (s
->blksize
&& (s
->cmdreg
& SDHC_CMD_DATA_PRESENT
)) {
374 sdhci_data_transfer(s
);
378 static void sdhci_end_transfer(SDHCIState
*s
)
380 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
381 if ((s
->trnmod
& SDHC_TRNS_ACMD12
) != 0) {
383 uint8_t response
[16];
387 trace_sdhci_end_transfer(request
.cmd
, request
.arg
);
388 sdbus_do_command(&s
->sdbus
, &request
, response
);
389 /* Auto CMD12 response goes to the upper Response register */
390 s
->rspreg
[3] = ldl_be_p(response
);
393 s
->prnsts
&= ~(SDHC_DOING_READ
| SDHC_DOING_WRITE
|
394 SDHC_DAT_LINE_ACTIVE
| SDHC_DATA_INHIBIT
|
395 SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
);
397 if (s
->norintstsen
& SDHC_NISEN_TRSCMP
) {
398 s
->norintsts
|= SDHC_NIS_TRSCMP
;
405 * Programmed i/o data transfer
407 #define BLOCK_SIZE_MASK (4 * KiB - 1)
409 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
410 static void sdhci_read_block_from_card(SDHCIState
*s
)
412 const uint16_t blk_size
= s
->blksize
& BLOCK_SIZE_MASK
;
414 if ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
415 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) {
419 if (!FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, EXECUTE_TUNING
)) {
420 /* Device is not in tuning */
421 sdbus_read_data(&s
->sdbus
, s
->fifo_buffer
, blk_size
);
424 if (FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, EXECUTE_TUNING
)) {
425 /* Device is in tuning */
426 s
->hostctl2
&= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK
;
427 s
->hostctl2
|= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK
;
428 s
->prnsts
&= ~(SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
|
433 /* New data now available for READ through Buffer Port Register */
434 s
->prnsts
|= SDHC_DATA_AVAILABLE
;
435 if (s
->norintstsen
& SDHC_NISEN_RBUFRDY
) {
436 s
->norintsts
|= SDHC_NIS_RBUFRDY
;
439 /* Clear DAT line active status if that was the last block */
440 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
441 ((s
->trnmod
& SDHC_TRNS_MULTI
) && s
->blkcnt
== 1)) {
442 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
445 /* If stop at block gap request was set and it's not the last block of
446 * data - generate Block Event interrupt */
447 if (s
->stopped_state
== sdhc_gap_read
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
449 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
450 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
451 s
->norintsts
|= SDHC_EIS_BLKGAP
;
459 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
460 static uint32_t sdhci_read_dataport(SDHCIState
*s
, unsigned size
)
465 /* first check that a valid data exists in host controller input buffer */
466 if ((s
->prnsts
& SDHC_DATA_AVAILABLE
) == 0) {
467 trace_sdhci_error("read from empty buffer");
471 for (i
= 0; i
< size
; i
++) {
472 value
|= s
->fifo_buffer
[s
->data_count
] << i
* 8;
474 /* check if we've read all valid data (blksize bytes) from buffer */
475 if ((s
->data_count
) >= (s
->blksize
& BLOCK_SIZE_MASK
)) {
476 trace_sdhci_read_dataport(s
->data_count
);
477 s
->prnsts
&= ~SDHC_DATA_AVAILABLE
; /* no more data in a buffer */
478 s
->data_count
= 0; /* next buff read must start at position [0] */
480 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
484 /* if that was the last block of data */
485 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
486 ((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) ||
487 /* stop at gap request */
488 (s
->stopped_state
== sdhc_gap_read
&&
489 !(s
->prnsts
& SDHC_DAT_LINE_ACTIVE
))) {
490 sdhci_end_transfer(s
);
491 } else { /* if there are more data, read next block from card */
492 sdhci_read_block_from_card(s
);
501 /* Write data from host controller FIFO to card */
502 static void sdhci_write_block_to_card(SDHCIState
*s
)
504 if (s
->prnsts
& SDHC_SPACE_AVAILABLE
) {
505 if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
506 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
512 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
513 if (s
->blkcnt
== 0) {
520 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
, s
->blksize
& BLOCK_SIZE_MASK
);
522 /* Next data can be written through BUFFER DATORT register */
523 s
->prnsts
|= SDHC_SPACE_AVAILABLE
;
525 /* Finish transfer if that was the last block of data */
526 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
527 ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
528 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0))) {
529 sdhci_end_transfer(s
);
530 } else if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
531 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
534 /* Generate Block Gap Event if requested and if not the last block */
535 if (s
->stopped_state
== sdhc_gap_write
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
537 s
->prnsts
&= ~SDHC_DOING_WRITE
;
538 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
539 s
->norintsts
|= SDHC_EIS_BLKGAP
;
541 sdhci_end_transfer(s
);
547 /* Write @size bytes of @value data to host controller @s Buffer Data Port
549 static void sdhci_write_dataport(SDHCIState
*s
, uint32_t value
, unsigned size
)
553 /* Check that there is free space left in a buffer */
554 if (!(s
->prnsts
& SDHC_SPACE_AVAILABLE
)) {
555 trace_sdhci_error("Can't write to data buffer: buffer full");
559 for (i
= 0; i
< size
; i
++) {
560 s
->fifo_buffer
[s
->data_count
] = value
& 0xFF;
563 if (s
->data_count
>= (s
->blksize
& BLOCK_SIZE_MASK
)) {
564 trace_sdhci_write_dataport(s
->data_count
);
566 s
->prnsts
&= ~SDHC_SPACE_AVAILABLE
;
567 if (s
->prnsts
& SDHC_DOING_WRITE
) {
568 sdhci_write_block_to_card(s
);
575 * Single DMA data transfer
578 /* Multi block SDMA transfer */
579 static void sdhci_sdma_transfer_multi_blocks(SDHCIState
*s
)
581 bool page_aligned
= false;
583 const uint16_t block_size
= s
->blksize
& BLOCK_SIZE_MASK
;
584 uint32_t boundary_chk
= 1 << (((s
->blksize
& ~BLOCK_SIZE_MASK
) >> 12) + 12);
585 uint32_t boundary_count
= boundary_chk
- (s
->sdmasysad
% boundary_chk
);
587 if (!(s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) || !s
->blkcnt
) {
588 qemu_log_mask(LOG_UNIMP
, "infinite transfer is not supported\n");
592 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
593 * possible stop at page boundary if initial address is not page aligned,
594 * allow them to work properly */
595 if ((s
->sdmasysad
% boundary_chk
) == 0) {
599 s
->prnsts
|= SDHC_DATA_INHIBIT
| SDHC_DAT_LINE_ACTIVE
;
600 if (s
->trnmod
& SDHC_TRNS_READ
) {
601 s
->prnsts
|= SDHC_DOING_READ
;
603 if (s
->data_count
== 0) {
604 sdbus_read_data(&s
->sdbus
, s
->fifo_buffer
, block_size
);
606 begin
= s
->data_count
;
607 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
608 s
->data_count
= boundary_count
+ begin
;
611 s
->data_count
= block_size
;
612 boundary_count
-= block_size
- begin
;
613 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
617 dma_memory_write(s
->dma_as
, s
->sdmasysad
,
618 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
619 s
->sdmasysad
+= s
->data_count
- begin
;
620 if (s
->data_count
== block_size
) {
623 if (page_aligned
&& boundary_count
== 0) {
628 s
->prnsts
|= SDHC_DOING_WRITE
;
630 begin
= s
->data_count
;
631 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
632 s
->data_count
= boundary_count
+ begin
;
635 s
->data_count
= block_size
;
636 boundary_count
-= block_size
- begin
;
638 dma_memory_read(s
->dma_as
, s
->sdmasysad
,
639 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
640 s
->sdmasysad
+= s
->data_count
- begin
;
641 if (s
->data_count
== block_size
) {
642 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
, block_size
);
644 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
648 if (page_aligned
&& boundary_count
== 0) {
654 if (s
->blkcnt
== 0) {
655 sdhci_end_transfer(s
);
657 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
658 s
->norintsts
|= SDHC_NIS_DMA
;
664 /* single block SDMA transfer */
665 static void sdhci_sdma_transfer_single_block(SDHCIState
*s
)
667 uint32_t datacnt
= s
->blksize
& BLOCK_SIZE_MASK
;
669 if (s
->trnmod
& SDHC_TRNS_READ
) {
670 sdbus_read_data(&s
->sdbus
, s
->fifo_buffer
, datacnt
);
671 dma_memory_write(s
->dma_as
, s
->sdmasysad
, s
->fifo_buffer
, datacnt
);
673 dma_memory_read(s
->dma_as
, s
->sdmasysad
, s
->fifo_buffer
, datacnt
);
674 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
, datacnt
);
678 sdhci_end_transfer(s
);
681 typedef struct ADMADescr
{
688 static void get_adma_description(SDHCIState
*s
, ADMADescr
*dscr
)
692 hwaddr entry_addr
= (hwaddr
)s
->admasysaddr
;
693 switch (SDHC_DMA_TYPE(s
->hostctl1
)) {
694 case SDHC_CTRL_ADMA2_32
:
695 dma_memory_read(s
->dma_as
, entry_addr
, &adma2
, sizeof(adma2
));
696 adma2
= le64_to_cpu(adma2
);
697 /* The spec does not specify endianness of descriptor table.
698 * We currently assume that it is LE.
700 dscr
->addr
= (hwaddr
)extract64(adma2
, 32, 32) & ~0x3ull
;
701 dscr
->length
= (uint16_t)extract64(adma2
, 16, 16);
702 dscr
->attr
= (uint8_t)extract64(adma2
, 0, 7);
705 case SDHC_CTRL_ADMA1_32
:
706 dma_memory_read(s
->dma_as
, entry_addr
, &adma1
, sizeof(adma1
));
707 adma1
= le32_to_cpu(adma1
);
708 dscr
->addr
= (hwaddr
)(adma1
& 0xFFFFF000);
709 dscr
->attr
= (uint8_t)extract32(adma1
, 0, 7);
711 if ((dscr
->attr
& SDHC_ADMA_ATTR_ACT_MASK
) == SDHC_ADMA_ATTR_SET_LEN
) {
712 dscr
->length
= (uint16_t)extract32(adma1
, 12, 16);
714 dscr
->length
= 4 * KiB
;
717 case SDHC_CTRL_ADMA2_64
:
718 dma_memory_read(s
->dma_as
, entry_addr
, &dscr
->attr
, 1);
719 dma_memory_read(s
->dma_as
, entry_addr
+ 2, &dscr
->length
, 2);
720 dscr
->length
= le16_to_cpu(dscr
->length
);
721 dma_memory_read(s
->dma_as
, entry_addr
+ 4, &dscr
->addr
, 8);
722 dscr
->addr
= le64_to_cpu(dscr
->addr
);
723 dscr
->attr
&= (uint8_t) ~0xC0;
729 /* Advanced DMA data transfer */
731 static void sdhci_do_adma(SDHCIState
*s
)
733 unsigned int begin
, length
;
734 const uint16_t block_size
= s
->blksize
& BLOCK_SIZE_MASK
;
738 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
&& !s
->blkcnt
) {
739 /* Stop Multiple Transfer */
740 sdhci_end_transfer(s
);
744 for (i
= 0; i
< SDHC_ADMA_DESCS_PER_DELAY
; ++i
) {
745 s
->admaerr
&= ~SDHC_ADMAERR_LENGTH_MISMATCH
;
747 get_adma_description(s
, &dscr
);
748 trace_sdhci_adma_loop(dscr
.addr
, dscr
.length
, dscr
.attr
);
750 if ((dscr
.attr
& SDHC_ADMA_ATTR_VALID
) == 0) {
751 /* Indicate that error occurred in ST_FDS state */
752 s
->admaerr
&= ~SDHC_ADMAERR_STATE_MASK
;
753 s
->admaerr
|= SDHC_ADMAERR_STATE_ST_FDS
;
755 /* Generate ADMA error interrupt */
756 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
757 s
->errintsts
|= SDHC_EIS_ADMAERR
;
758 s
->norintsts
|= SDHC_NIS_ERR
;
765 length
= dscr
.length
? dscr
.length
: 64 * KiB
;
767 switch (dscr
.attr
& SDHC_ADMA_ATTR_ACT_MASK
) {
768 case SDHC_ADMA_ATTR_ACT_TRAN
: /* data transfer */
769 if (s
->trnmod
& SDHC_TRNS_READ
) {
771 if (s
->data_count
== 0) {
772 sdbus_read_data(&s
->sdbus
, s
->fifo_buffer
, block_size
);
774 begin
= s
->data_count
;
775 if ((length
+ begin
) < block_size
) {
776 s
->data_count
= length
+ begin
;
779 s
->data_count
= block_size
;
780 length
-= block_size
- begin
;
782 dma_memory_write(s
->dma_as
, dscr
.addr
,
783 &s
->fifo_buffer
[begin
],
784 s
->data_count
- begin
);
785 dscr
.addr
+= s
->data_count
- begin
;
786 if (s
->data_count
== block_size
) {
788 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
790 if (s
->blkcnt
== 0) {
798 begin
= s
->data_count
;
799 if ((length
+ begin
) < block_size
) {
800 s
->data_count
= length
+ begin
;
803 s
->data_count
= block_size
;
804 length
-= block_size
- begin
;
806 dma_memory_read(s
->dma_as
, dscr
.addr
,
807 &s
->fifo_buffer
[begin
],
808 s
->data_count
- begin
);
809 dscr
.addr
+= s
->data_count
- begin
;
810 if (s
->data_count
== block_size
) {
811 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
, block_size
);
813 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
815 if (s
->blkcnt
== 0) {
822 s
->admasysaddr
+= dscr
.incr
;
824 case SDHC_ADMA_ATTR_ACT_LINK
: /* link to next descriptor table */
825 s
->admasysaddr
= dscr
.addr
;
826 trace_sdhci_adma("link", s
->admasysaddr
);
829 s
->admasysaddr
+= dscr
.incr
;
833 if (dscr
.attr
& SDHC_ADMA_ATTR_INT
) {
834 trace_sdhci_adma("interrupt", s
->admasysaddr
);
835 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
836 s
->norintsts
|= SDHC_NIS_DMA
;
839 if (sdhci_update_irq(s
) && !(dscr
.attr
& SDHC_ADMA_ATTR_END
)) {
840 /* IRQ delivered, reschedule current transfer */
845 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
846 if (((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
847 (s
->blkcnt
== 0)) || (dscr
.attr
& SDHC_ADMA_ATTR_END
)) {
848 trace_sdhci_adma_transfer_completed();
849 if (length
|| ((dscr
.attr
& SDHC_ADMA_ATTR_END
) &&
850 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
852 trace_sdhci_error("SD/MMC host ADMA length mismatch");
853 s
->admaerr
|= SDHC_ADMAERR_LENGTH_MISMATCH
|
854 SDHC_ADMAERR_STATE_ST_TFR
;
855 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
856 trace_sdhci_error("Set ADMA error flag");
857 s
->errintsts
|= SDHC_EIS_ADMAERR
;
858 s
->norintsts
|= SDHC_NIS_ERR
;
863 sdhci_end_transfer(s
);
869 /* we have unfinished business - reschedule to continue ADMA */
870 timer_mod(s
->transfer_timer
,
871 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_TRANSFER_DELAY
);
874 /* Perform data transfer according to controller configuration */
876 static void sdhci_data_transfer(void *opaque
)
878 SDHCIState
*s
= (SDHCIState
*)opaque
;
880 if (s
->trnmod
& SDHC_TRNS_DMA
) {
881 switch (SDHC_DMA_TYPE(s
->hostctl1
)) {
883 if ((s
->blkcnt
== 1) || !(s
->trnmod
& SDHC_TRNS_MULTI
)) {
884 sdhci_sdma_transfer_single_block(s
);
886 sdhci_sdma_transfer_multi_blocks(s
);
890 case SDHC_CTRL_ADMA1_32
:
891 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA1_MASK
)) {
892 trace_sdhci_error("ADMA1 not supported");
898 case SDHC_CTRL_ADMA2_32
:
899 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA2_MASK
)) {
900 trace_sdhci_error("ADMA2 not supported");
906 case SDHC_CTRL_ADMA2_64
:
907 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA2_MASK
) ||
908 !(s
->capareg
& R_SDHC_CAPAB_BUS64BIT_MASK
)) {
909 trace_sdhci_error("64 bit ADMA not supported");
916 trace_sdhci_error("Unsupported DMA type");
920 if ((s
->trnmod
& SDHC_TRNS_READ
) && sdbus_data_ready(&s
->sdbus
)) {
921 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
922 SDHC_DAT_LINE_ACTIVE
;
923 sdhci_read_block_from_card(s
);
925 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DAT_LINE_ACTIVE
|
926 SDHC_SPACE_AVAILABLE
| SDHC_DATA_INHIBIT
;
927 sdhci_write_block_to_card(s
);
932 static bool sdhci_can_issue_command(SDHCIState
*s
)
934 if (!SDHC_CLOCK_IS_ON(s
->clkcon
) ||
935 (((s
->prnsts
& SDHC_DATA_INHIBIT
) || s
->stopped_state
) &&
936 ((s
->cmdreg
& SDHC_CMD_DATA_PRESENT
) ||
937 ((s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
&&
938 !(SDHC_COMMAND_TYPE(s
->cmdreg
) == SDHC_CMD_ABORT
))))) {
945 /* The Buffer Data Port register must be accessed in sequential and
946 * continuous manner */
948 sdhci_buff_access_is_sequential(SDHCIState
*s
, unsigned byte_num
)
950 if ((s
->data_count
& 0x3) != byte_num
) {
951 trace_sdhci_error("Non-sequential access to Buffer Data Port register"
958 static void sdhci_resume_pending_transfer(SDHCIState
*s
)
960 timer_del(s
->transfer_timer
);
961 sdhci_data_transfer(s
);
964 static uint64_t sdhci_read(void *opaque
, hwaddr offset
, unsigned size
)
966 SDHCIState
*s
= (SDHCIState
*)opaque
;
969 if (timer_pending(s
->transfer_timer
)) {
970 sdhci_resume_pending_transfer(s
);
973 switch (offset
& ~0x3) {
978 ret
= s
->blksize
| (s
->blkcnt
<< 16);
984 ret
= s
->trnmod
| (s
->cmdreg
<< 16);
986 case SDHC_RSPREG0
... SDHC_RSPREG3
:
987 ret
= s
->rspreg
[((offset
& ~0x3) - SDHC_RSPREG0
) >> 2];
990 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
991 ret
= sdhci_read_dataport(s
, size
);
992 trace_sdhci_access("rd", size
<< 3, offset
, "->", ret
, ret
);
998 ret
= FIELD_DP32(ret
, SDHC_PRNSTS
, DAT_LVL
,
999 sdbus_get_dat_lines(&s
->sdbus
));
1000 ret
= FIELD_DP32(ret
, SDHC_PRNSTS
, CMD_LVL
,
1001 sdbus_get_cmd_line(&s
->sdbus
));
1004 ret
= s
->hostctl1
| (s
->pwrcon
<< 8) | (s
->blkgap
<< 16) |
1008 ret
= s
->clkcon
| (s
->timeoutcon
<< 16);
1010 case SDHC_NORINTSTS
:
1011 ret
= s
->norintsts
| (s
->errintsts
<< 16);
1013 case SDHC_NORINTSTSEN
:
1014 ret
= s
->norintstsen
| (s
->errintstsen
<< 16);
1016 case SDHC_NORINTSIGEN
:
1017 ret
= s
->norintsigen
| (s
->errintsigen
<< 16);
1019 case SDHC_ACMD12ERRSTS
:
1020 ret
= s
->acmd12errsts
| (s
->hostctl2
<< 16);
1023 ret
= (uint32_t)s
->capareg
;
1025 case SDHC_CAPAB
+ 4:
1026 ret
= (uint32_t)(s
->capareg
>> 32);
1029 ret
= (uint32_t)s
->maxcurr
;
1031 case SDHC_MAXCURR
+ 4:
1032 ret
= (uint32_t)(s
->maxcurr
>> 32);
1037 case SDHC_ADMASYSADDR
:
1038 ret
= (uint32_t)s
->admasysaddr
;
1040 case SDHC_ADMASYSADDR
+ 4:
1041 ret
= (uint32_t)(s
->admasysaddr
>> 32);
1043 case SDHC_SLOT_INT_STATUS
:
1044 ret
= (s
->version
<< 16) | sdhci_slotint(s
);
1047 qemu_log_mask(LOG_UNIMP
, "SDHC rd_%ub @0x%02" HWADDR_PRIx
" "
1048 "not implemented\n", size
, offset
);
1052 ret
>>= (offset
& 0x3) * 8;
1053 ret
&= (1ULL << (size
* 8)) - 1;
1054 trace_sdhci_access("rd", size
<< 3, offset
, "->", ret
, ret
);
1058 static inline void sdhci_blkgap_write(SDHCIState
*s
, uint8_t value
)
1060 if ((value
& SDHC_STOP_AT_GAP_REQ
) && (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
)) {
1063 s
->blkgap
= value
& SDHC_STOP_AT_GAP_REQ
;
1065 if ((value
& SDHC_CONTINUE_REQ
) && s
->stopped_state
&&
1066 (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
) == 0) {
1067 if (s
->stopped_state
== sdhc_gap_read
) {
1068 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
;
1069 sdhci_read_block_from_card(s
);
1071 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_WRITE
;
1072 sdhci_write_block_to_card(s
);
1074 s
->stopped_state
= sdhc_not_stopped
;
1075 } else if (!s
->stopped_state
&& (value
& SDHC_STOP_AT_GAP_REQ
)) {
1076 if (s
->prnsts
& SDHC_DOING_READ
) {
1077 s
->stopped_state
= sdhc_gap_read
;
1078 } else if (s
->prnsts
& SDHC_DOING_WRITE
) {
1079 s
->stopped_state
= sdhc_gap_write
;
1084 static inline void sdhci_reset_write(SDHCIState
*s
, uint8_t value
)
1087 case SDHC_RESET_ALL
:
1090 case SDHC_RESET_CMD
:
1091 s
->prnsts
&= ~SDHC_CMD_INHIBIT
;
1092 s
->norintsts
&= ~SDHC_NIS_CMDCMP
;
1094 case SDHC_RESET_DATA
:
1096 s
->prnsts
&= ~(SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
|
1097 SDHC_DOING_READ
| SDHC_DOING_WRITE
|
1098 SDHC_DATA_INHIBIT
| SDHC_DAT_LINE_ACTIVE
);
1099 s
->blkgap
&= ~(SDHC_STOP_AT_GAP_REQ
| SDHC_CONTINUE_REQ
);
1100 s
->stopped_state
= sdhc_not_stopped
;
1101 s
->norintsts
&= ~(SDHC_NIS_WBUFRDY
| SDHC_NIS_RBUFRDY
|
1102 SDHC_NIS_DMA
| SDHC_NIS_TRSCMP
| SDHC_NIS_BLKGAP
);
1108 sdhci_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
1110 SDHCIState
*s
= (SDHCIState
*)opaque
;
1111 unsigned shift
= 8 * (offset
& 0x3);
1112 uint32_t mask
= ~(((1ULL << (size
* 8)) - 1) << shift
);
1113 uint32_t value
= val
;
1116 if (timer_pending(s
->transfer_timer
)) {
1117 sdhci_resume_pending_transfer(s
);
1120 switch (offset
& ~0x3) {
1122 s
->sdmasysad
= (s
->sdmasysad
& mask
) | value
;
1123 MASKED_WRITE(s
->sdmasysad
, mask
, value
);
1124 /* Writing to last byte of sdmasysad might trigger transfer */
1125 if (!(mask
& 0xFF000000) && TRANSFERRING_DATA(s
->prnsts
) && s
->blkcnt
&&
1126 s
->blksize
&& SDHC_DMA_TYPE(s
->hostctl1
) == SDHC_CTRL_SDMA
) {
1127 if (s
->trnmod
& SDHC_TRNS_MULTI
) {
1128 sdhci_sdma_transfer_multi_blocks(s
);
1130 sdhci_sdma_transfer_single_block(s
);
1135 if (!TRANSFERRING_DATA(s
->prnsts
)) {
1136 MASKED_WRITE(s
->blksize
, mask
, extract32(value
, 0, 12));
1137 MASKED_WRITE(s
->blkcnt
, mask
>> 16, value
>> 16);
1140 /* Limit block size to the maximum buffer size */
1141 if (extract32(s
->blksize
, 0, 12) > s
->buf_maxsz
) {
1142 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Size 0x%x is larger than "
1143 "the maximum buffer 0x%x\n", __func__
, s
->blksize
,
1146 s
->blksize
= deposit32(s
->blksize
, 0, 12, s
->buf_maxsz
);
1151 MASKED_WRITE(s
->argument
, mask
, value
);
1154 /* DMA can be enabled only if it is supported as indicated by
1155 * capabilities register */
1156 if (!(s
->capareg
& R_SDHC_CAPAB_SDMA_MASK
)) {
1157 value
&= ~SDHC_TRNS_DMA
;
1159 MASKED_WRITE(s
->trnmod
, mask
, value
& SDHC_TRNMOD_MASK
);
1160 MASKED_WRITE(s
->cmdreg
, mask
>> 16, value
>> 16);
1162 /* Writing to the upper byte of CMDREG triggers SD command generation */
1163 if ((mask
& 0xFF000000) || !sdhci_can_issue_command(s
)) {
1167 sdhci_send_command(s
);
1170 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
1171 sdhci_write_dataport(s
, value
>> shift
, size
);
1175 if (!(mask
& 0xFF0000)) {
1176 sdhci_blkgap_write(s
, value
>> 16);
1178 MASKED_WRITE(s
->hostctl1
, mask
, value
);
1179 MASKED_WRITE(s
->pwrcon
, mask
>> 8, value
>> 8);
1180 MASKED_WRITE(s
->wakcon
, mask
>> 24, value
>> 24);
1181 if (!(s
->prnsts
& SDHC_CARD_PRESENT
) || ((s
->pwrcon
>> 1) & 0x7) < 5 ||
1182 !(s
->capareg
& (1 << (31 - ((s
->pwrcon
>> 1) & 0x7))))) {
1183 s
->pwrcon
&= ~SDHC_POWER_ON
;
1187 if (!(mask
& 0xFF000000)) {
1188 sdhci_reset_write(s
, value
>> 24);
1190 MASKED_WRITE(s
->clkcon
, mask
, value
);
1191 MASKED_WRITE(s
->timeoutcon
, mask
>> 16, value
>> 16);
1192 if (s
->clkcon
& SDHC_CLOCK_INT_EN
) {
1193 s
->clkcon
|= SDHC_CLOCK_INT_STABLE
;
1195 s
->clkcon
&= ~SDHC_CLOCK_INT_STABLE
;
1198 case SDHC_NORINTSTS
:
1199 if (s
->norintstsen
& SDHC_NISEN_CARDINT
) {
1200 value
&= ~SDHC_NIS_CARDINT
;
1202 s
->norintsts
&= mask
| ~value
;
1203 s
->errintsts
&= (mask
>> 16) | ~(value
>> 16);
1205 s
->norintsts
|= SDHC_NIS_ERR
;
1207 s
->norintsts
&= ~SDHC_NIS_ERR
;
1209 sdhci_update_irq(s
);
1211 case SDHC_NORINTSTSEN
:
1212 MASKED_WRITE(s
->norintstsen
, mask
, value
);
1213 MASKED_WRITE(s
->errintstsen
, mask
>> 16, value
>> 16);
1214 s
->norintsts
&= s
->norintstsen
;
1215 s
->errintsts
&= s
->errintstsen
;
1217 s
->norintsts
|= SDHC_NIS_ERR
;
1219 s
->norintsts
&= ~SDHC_NIS_ERR
;
1221 /* Quirk for Raspberry Pi: pending card insert interrupt
1222 * appears when first enabled after power on */
1223 if ((s
->norintstsen
& SDHC_NISEN_INSERT
) && s
->pending_insert_state
) {
1224 assert(s
->pending_insert_quirk
);
1225 s
->norintsts
|= SDHC_NIS_INSERT
;
1226 s
->pending_insert_state
= false;
1228 sdhci_update_irq(s
);
1230 case SDHC_NORINTSIGEN
:
1231 MASKED_WRITE(s
->norintsigen
, mask
, value
);
1232 MASKED_WRITE(s
->errintsigen
, mask
>> 16, value
>> 16);
1233 sdhci_update_irq(s
);
1236 MASKED_WRITE(s
->admaerr
, mask
, value
);
1238 case SDHC_ADMASYSADDR
:
1239 s
->admasysaddr
= (s
->admasysaddr
& (0xFFFFFFFF00000000ULL
|
1240 (uint64_t)mask
)) | (uint64_t)value
;
1242 case SDHC_ADMASYSADDR
+ 4:
1243 s
->admasysaddr
= (s
->admasysaddr
& (0x00000000FFFFFFFFULL
|
1244 ((uint64_t)mask
<< 32))) | ((uint64_t)value
<< 32);
1247 s
->acmd12errsts
|= value
;
1248 s
->errintsts
|= (value
>> 16) & s
->errintstsen
;
1249 if (s
->acmd12errsts
) {
1250 s
->errintsts
|= SDHC_EIS_CMD12ERR
;
1253 s
->norintsts
|= SDHC_NIS_ERR
;
1255 sdhci_update_irq(s
);
1257 case SDHC_ACMD12ERRSTS
:
1258 MASKED_WRITE(s
->acmd12errsts
, mask
, value
& UINT16_MAX
);
1259 if (s
->uhs_mode
>= UHS_I
) {
1260 MASKED_WRITE(s
->hostctl2
, mask
>> 16, value
>> 16);
1262 if (FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, V18_ENA
)) {
1263 sdbus_set_voltage(&s
->sdbus
, SD_VOLTAGE_1_8V
);
1265 sdbus_set_voltage(&s
->sdbus
, SD_VOLTAGE_3_3V
);
1271 case SDHC_CAPAB
+ 4:
1273 case SDHC_MAXCURR
+ 4:
1274 qemu_log_mask(LOG_GUEST_ERROR
, "SDHC wr_%ub @0x%02" HWADDR_PRIx
1275 " <- 0x%08x read-only\n", size
, offset
, value
>> shift
);
1279 qemu_log_mask(LOG_UNIMP
, "SDHC wr_%ub @0x%02" HWADDR_PRIx
" <- 0x%08x "
1280 "not implemented\n", size
, offset
, value
>> shift
);
1283 trace_sdhci_access("wr", size
<< 3, offset
, "<-",
1284 value
>> shift
, value
>> shift
);
1287 static const MemoryRegionOps sdhci_mmio_ops
= {
1289 .write
= sdhci_write
,
1291 .min_access_size
= 1,
1292 .max_access_size
= 4,
1295 .endianness
= DEVICE_LITTLE_ENDIAN
,
1298 static void sdhci_init_readonly_registers(SDHCIState
*s
, Error
**errp
)
1302 switch (s
->sd_spec_version
) {
1306 error_setg(errp
, "Only Spec v2/v3 are supported");
1309 s
->version
= (SDHC_HCVER_VENDOR
<< 8) | (s
->sd_spec_version
- 1);
1311 sdhci_check_capareg(s
, errp
);
1317 /* --- qdev common --- */
1319 void sdhci_initfn(SDHCIState
*s
)
1321 qbus_create_inplace(&s
->sdbus
, sizeof(s
->sdbus
),
1322 TYPE_SDHCI_BUS
, DEVICE(s
), "sd-bus");
1324 s
->insert_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_raise_insertion_irq
, s
);
1325 s
->transfer_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_data_transfer
, s
);
1327 s
->io_ops
= &sdhci_mmio_ops
;
1330 void sdhci_uninitfn(SDHCIState
*s
)
1332 timer_free(s
->insert_timer
);
1333 timer_free(s
->transfer_timer
);
1335 g_free(s
->fifo_buffer
);
1336 s
->fifo_buffer
= NULL
;
1339 void sdhci_common_realize(SDHCIState
*s
, Error
**errp
)
1343 sdhci_init_readonly_registers(s
, errp
);
1347 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1348 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1350 memory_region_init_io(&s
->iomem
, OBJECT(s
), s
->io_ops
, s
, "sdhci",
1351 SDHC_REGISTERS_MAP_SIZE
);
1354 void sdhci_common_unrealize(SDHCIState
*s
)
1356 /* This function is expected to be called only once for each class:
1357 * - SysBus: via DeviceClass->unrealize(),
1358 * - PCI: via PCIDeviceClass->exit().
1359 * However to avoid double-free and/or use-after-free we still nullify
1360 * this variable (better safe than sorry!). */
1361 g_free(s
->fifo_buffer
);
1362 s
->fifo_buffer
= NULL
;
1365 static bool sdhci_pending_insert_vmstate_needed(void *opaque
)
1367 SDHCIState
*s
= opaque
;
1369 return s
->pending_insert_state
;
1372 static const VMStateDescription sdhci_pending_insert_vmstate
= {
1373 .name
= "sdhci/pending-insert",
1375 .minimum_version_id
= 1,
1376 .needed
= sdhci_pending_insert_vmstate_needed
,
1377 .fields
= (VMStateField
[]) {
1378 VMSTATE_BOOL(pending_insert_state
, SDHCIState
),
1379 VMSTATE_END_OF_LIST()
1383 const VMStateDescription sdhci_vmstate
= {
1386 .minimum_version_id
= 1,
1387 .fields
= (VMStateField
[]) {
1388 VMSTATE_UINT32(sdmasysad
, SDHCIState
),
1389 VMSTATE_UINT16(blksize
, SDHCIState
),
1390 VMSTATE_UINT16(blkcnt
, SDHCIState
),
1391 VMSTATE_UINT32(argument
, SDHCIState
),
1392 VMSTATE_UINT16(trnmod
, SDHCIState
),
1393 VMSTATE_UINT16(cmdreg
, SDHCIState
),
1394 VMSTATE_UINT32_ARRAY(rspreg
, SDHCIState
, 4),
1395 VMSTATE_UINT32(prnsts
, SDHCIState
),
1396 VMSTATE_UINT8(hostctl1
, SDHCIState
),
1397 VMSTATE_UINT8(pwrcon
, SDHCIState
),
1398 VMSTATE_UINT8(blkgap
, SDHCIState
),
1399 VMSTATE_UINT8(wakcon
, SDHCIState
),
1400 VMSTATE_UINT16(clkcon
, SDHCIState
),
1401 VMSTATE_UINT8(timeoutcon
, SDHCIState
),
1402 VMSTATE_UINT8(admaerr
, SDHCIState
),
1403 VMSTATE_UINT16(norintsts
, SDHCIState
),
1404 VMSTATE_UINT16(errintsts
, SDHCIState
),
1405 VMSTATE_UINT16(norintstsen
, SDHCIState
),
1406 VMSTATE_UINT16(errintstsen
, SDHCIState
),
1407 VMSTATE_UINT16(norintsigen
, SDHCIState
),
1408 VMSTATE_UINT16(errintsigen
, SDHCIState
),
1409 VMSTATE_UINT16(acmd12errsts
, SDHCIState
),
1410 VMSTATE_UINT16(data_count
, SDHCIState
),
1411 VMSTATE_UINT64(admasysaddr
, SDHCIState
),
1412 VMSTATE_UINT8(stopped_state
, SDHCIState
),
1413 VMSTATE_VBUFFER_UINT32(fifo_buffer
, SDHCIState
, 1, NULL
, buf_maxsz
),
1414 VMSTATE_TIMER_PTR(insert_timer
, SDHCIState
),
1415 VMSTATE_TIMER_PTR(transfer_timer
, SDHCIState
),
1416 VMSTATE_END_OF_LIST()
1418 .subsections
= (const VMStateDescription
*[]) {
1419 &sdhci_pending_insert_vmstate
,
1424 void sdhci_common_class_init(ObjectClass
*klass
, void *data
)
1426 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1428 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1429 dc
->vmsd
= &sdhci_vmstate
;
1430 dc
->reset
= sdhci_poweron_reset
;
1433 /* --- qdev SysBus --- */
1435 static Property sdhci_sysbus_properties
[] = {
1436 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState
),
1437 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState
, pending_insert_quirk
,
1439 DEFINE_PROP_LINK("dma", SDHCIState
,
1440 dma_mr
, TYPE_MEMORY_REGION
, MemoryRegion
*),
1441 DEFINE_PROP_END_OF_LIST(),
1444 static void sdhci_sysbus_init(Object
*obj
)
1446 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1451 static void sdhci_sysbus_finalize(Object
*obj
)
1453 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1456 object_unparent(OBJECT(s
->dma_mr
));
1462 static void sdhci_sysbus_realize(DeviceState
*dev
, Error
**errp
)
1465 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1466 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1468 sdhci_common_realize(s
, errp
);
1474 s
->dma_as
= &s
->sysbus_dma_as
;
1475 address_space_init(s
->dma_as
, s
->dma_mr
, "sdhci-dma");
1477 /* use system_memory() if property "dma" not set */
1478 s
->dma_as
= &address_space_memory
;
1481 sysbus_init_irq(sbd
, &s
->irq
);
1483 sysbus_init_mmio(sbd
, &s
->iomem
);
1486 static void sdhci_sysbus_unrealize(DeviceState
*dev
)
1488 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1490 sdhci_common_unrealize(s
);
1493 address_space_destroy(s
->dma_as
);
1497 static void sdhci_sysbus_class_init(ObjectClass
*klass
, void *data
)
1499 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1501 device_class_set_props(dc
, sdhci_sysbus_properties
);
1502 dc
->realize
= sdhci_sysbus_realize
;
1503 dc
->unrealize
= sdhci_sysbus_unrealize
;
1505 sdhci_common_class_init(klass
, data
);
1508 static const TypeInfo sdhci_sysbus_info
= {
1509 .name
= TYPE_SYSBUS_SDHCI
,
1510 .parent
= TYPE_SYS_BUS_DEVICE
,
1511 .instance_size
= sizeof(SDHCIState
),
1512 .instance_init
= sdhci_sysbus_init
,
1513 .instance_finalize
= sdhci_sysbus_finalize
,
1514 .class_init
= sdhci_sysbus_class_init
,
1517 /* --- qdev bus master --- */
1519 static void sdhci_bus_class_init(ObjectClass
*klass
, void *data
)
1521 SDBusClass
*sbc
= SD_BUS_CLASS(klass
);
1523 sbc
->set_inserted
= sdhci_set_inserted
;
1524 sbc
->set_readonly
= sdhci_set_readonly
;
1527 static const TypeInfo sdhci_bus_info
= {
1528 .name
= TYPE_SDHCI_BUS
,
1529 .parent
= TYPE_SD_BUS
,
1530 .instance_size
= sizeof(SDBus
),
1531 .class_init
= sdhci_bus_class_init
,
1534 /* --- qdev i.MX eSDHC --- */
1536 static uint64_t usdhc_read(void *opaque
, hwaddr offset
, unsigned size
)
1538 SDHCIState
*s
= SYSBUS_SDHCI(opaque
);
1544 return sdhci_read(opaque
, offset
, size
);
1548 * For a detailed explanation on the following bit
1549 * manipulation code see comments in a similar part of
1552 hostctl1
= SDHC_DMA_TYPE(s
->hostctl1
) << (8 - 3);
1554 if (s
->hostctl1
& SDHC_CTRL_8BITBUS
) {
1555 hostctl1
|= ESDHC_CTRL_8BITBUS
;
1558 if (s
->hostctl1
& SDHC_CTRL_4BITBUS
) {
1559 hostctl1
|= ESDHC_CTRL_4BITBUS
;
1563 ret
|= (uint32_t)s
->blkgap
<< 16;
1564 ret
|= (uint32_t)s
->wakcon
<< 24;
1569 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
1570 ret
= sdhci_read(opaque
, offset
, size
) & ~ESDHC_PRNSTS_SDSTB
;
1571 if (s
->clkcon
& SDHC_CLOCK_INT_STABLE
) {
1572 ret
|= ESDHC_PRNSTS_SDSTB
;
1576 case ESDHC_VENDOR_SPEC
:
1577 ret
= s
->vendor_spec
;
1579 case ESDHC_DLL_CTRL
:
1580 case ESDHC_TUNE_CTRL_STATUS
:
1581 case ESDHC_UNDOCUMENTED_REG27
:
1582 case ESDHC_TUNING_CTRL
:
1583 case ESDHC_MIX_CTRL
:
1584 case ESDHC_WTMK_LVL
:
1593 usdhc_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
1595 SDHCIState
*s
= SYSBUS_SDHCI(opaque
);
1597 uint32_t value
= (uint32_t)val
;
1600 case ESDHC_DLL_CTRL
:
1601 case ESDHC_TUNE_CTRL_STATUS
:
1602 case ESDHC_UNDOCUMENTED_REG27
:
1603 case ESDHC_TUNING_CTRL
:
1604 case ESDHC_WTMK_LVL
:
1607 case ESDHC_VENDOR_SPEC
:
1608 s
->vendor_spec
= value
;
1609 switch (s
->vendor
) {
1610 case SDHCI_VENDOR_IMX
:
1611 if (value
& ESDHC_IMX_FRC_SDCLK_ON
) {
1612 s
->prnsts
&= ~SDHC_IMX_CLOCK_GATE_OFF
;
1614 s
->prnsts
|= SDHC_IMX_CLOCK_GATE_OFF
;
1624 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
1627 * |-----------+--------+--------+-----------+----------+---------|
1628 * | Card | Card | Endian | DATA3 | Data | Led |
1629 * | Detect | Detect | Mode | as Card | Transfer | Control |
1630 * | Signal | Test | | Detection | Width | |
1631 * | Selection | Level | | Pin | | |
1632 * |-----------+--------+--------+-----------+----------+---------|
1637 * |----------+------|
1638 * | Reserved | DMA |
1641 * |----------+------|
1643 * and here's what SDCHI spec expects those offsets to be:
1645 * 0x28 (Host Control Register)
1648 * |--------+--------+----------+------+--------+----------+---------|
1649 * | Card | Card | Extended | DMA | High | Data | LED |
1650 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
1651 * | Signal | Test | Transfer | | Enable | Width | |
1652 * | Sel. | Level | Width | | | | |
1653 * |--------+--------+----------+------+--------+----------+---------|
1655 * and 0x29 (Power Control Register)
1657 * |----------------------------------|
1658 * | Power Control Register |
1660 * | Description omitted, |
1661 * | since it has no analog in ESDHCI |
1663 * |----------------------------------|
1665 * Since offsets 0x2A and 0x2B should be compatible between
1666 * both IP specs we only need to reconcile least 16-bit of the
1667 * word we've been given.
1671 * First, save bits 7 6 and 0 since they are identical
1673 hostctl1
= value
& (SDHC_CTRL_LED
|
1674 SDHC_CTRL_CDTEST_INS
|
1675 SDHC_CTRL_CDTEST_EN
);
1677 * Second, split "Data Transfer Width" from bits 2 and 1 in to
1680 if (value
& ESDHC_CTRL_8BITBUS
) {
1681 hostctl1
|= SDHC_CTRL_8BITBUS
;
1684 if (value
& ESDHC_CTRL_4BITBUS
) {
1685 hostctl1
|= ESDHC_CTRL_4BITBUS
;
1689 * Third, move DMA select from bits 9 and 8 to bits 4 and 3
1691 hostctl1
|= SDHC_DMA_TYPE(value
>> (8 - 3));
1694 * Now place the corrected value into low 16-bit of the value
1695 * we are going to give standard SDHCI write function
1697 * NOTE: This transformation should be the inverse of what can
1698 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
1701 value
&= ~UINT16_MAX
;
1703 value
|= (uint16_t)s
->pwrcon
<< 8;
1705 sdhci_write(opaque
, offset
, value
, size
);
1708 case ESDHC_MIX_CTRL
:
1710 * So, when SD/MMC stack in Linux tries to write to "Transfer
1711 * Mode Register", ESDHC i.MX quirk code will translate it
1712 * into a write to ESDHC_MIX_CTRL, so we do the opposite in
1713 * order to get where we started
1715 * Note that Auto CMD23 Enable bit is located in a wrong place
1716 * on i.MX, but since it is not used by QEMU we do not care.
1718 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
1719 * here becuase it will result in a call to
1720 * sdhci_send_command(s) which we don't want.
1723 s
->trnmod
= value
& UINT16_MAX
;
1727 * Similar to above, but this time a write to "Command
1728 * Register" will be translated into a 4-byte write to
1729 * "Transfer Mode register" where lower 16-bit of value would
1730 * be set to zero. So what we do is fill those bits with
1731 * cached value from s->trnmod and let the SDHCI
1732 * infrastructure handle the rest
1734 sdhci_write(opaque
, offset
, val
| s
->trnmod
, size
);
1738 * ESDHCI does not implement "Host SDMA Buffer Boundary", and
1739 * Linux driver will try to zero this field out which will
1740 * break the rest of SDHCI emulation.
1742 * Linux defaults to maximum possible setting (512K boundary)
1743 * and it seems to be the only option that i.MX IP implements,
1744 * so we artificially set it to that value.
1749 sdhci_write(opaque
, offset
, val
, size
);
1754 static const MemoryRegionOps usdhc_mmio_ops
= {
1756 .write
= usdhc_write
,
1758 .min_access_size
= 1,
1759 .max_access_size
= 4,
1762 .endianness
= DEVICE_LITTLE_ENDIAN
,
1765 static void imx_usdhc_init(Object
*obj
)
1767 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1769 s
->io_ops
= &usdhc_mmio_ops
;
1770 s
->quirks
= SDHCI_QUIRK_NO_BUSY_IRQ
;
1773 static const TypeInfo imx_usdhc_info
= {
1774 .name
= TYPE_IMX_USDHC
,
1775 .parent
= TYPE_SYSBUS_SDHCI
,
1776 .instance_init
= imx_usdhc_init
,
1779 /* --- qdev Samsung s3c --- */
1781 #define S3C_SDHCI_CONTROL2 0x80
1782 #define S3C_SDHCI_CONTROL3 0x84
1783 #define S3C_SDHCI_CONTROL4 0x8c
1785 static uint64_t sdhci_s3c_read(void *opaque
, hwaddr offset
, unsigned size
)
1790 case S3C_SDHCI_CONTROL2
:
1791 case S3C_SDHCI_CONTROL3
:
1792 case S3C_SDHCI_CONTROL4
:
1797 ret
= sdhci_read(opaque
, offset
, size
);
1804 static void sdhci_s3c_write(void *opaque
, hwaddr offset
, uint64_t val
,
1808 case S3C_SDHCI_CONTROL2
:
1809 case S3C_SDHCI_CONTROL3
:
1810 case S3C_SDHCI_CONTROL4
:
1814 sdhci_write(opaque
, offset
, val
, size
);
1819 static const MemoryRegionOps sdhci_s3c_mmio_ops
= {
1820 .read
= sdhci_s3c_read
,
1821 .write
= sdhci_s3c_write
,
1823 .min_access_size
= 1,
1824 .max_access_size
= 4,
1827 .endianness
= DEVICE_LITTLE_ENDIAN
,
1830 static void sdhci_s3c_init(Object
*obj
)
1832 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1834 s
->io_ops
= &sdhci_s3c_mmio_ops
;
1837 static const TypeInfo sdhci_s3c_info
= {
1838 .name
= TYPE_S3C_SDHCI
,
1839 .parent
= TYPE_SYSBUS_SDHCI
,
1840 .instance_init
= sdhci_s3c_init
,
1843 static void sdhci_register_types(void)
1845 type_register_static(&sdhci_sysbus_info
);
1846 type_register_static(&sdhci_bus_info
);
1847 type_register_static(&imx_usdhc_info
);
1848 type_register_static(&sdhci_s3c_info
);
1851 type_init(sdhci_register_types
)