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target/mips: Remove XBurst Media eXtension Unit dead code
[qemu/ar7.git] / hw / ppc / ppc4xx_devs.c
blobfe9d4f7155e1f700e7f97eb3c2748dacdc219516
1 /*
2 * QEMU PowerPC 4xx embedded processors shared devices emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "sysemu/reset.h"
28 #include "cpu.h"
29 #include "hw/irq.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/ppc/ppc4xx.h"
32 #include "hw/boards.h"
33 #include "hw/intc/ppc-uic.h"
34 #include "hw/qdev-properties.h"
35 #include "qemu/log.h"
36 #include "exec/address-spaces.h"
37 #include "qemu/error-report.h"
38 #include "qapi/error.h"
39
40 /*#define DEBUG_UIC*/
41
42 #ifdef DEBUG_UIC
43 # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
44 #else
45 # define LOG_UIC(...) do { } while (0)
46 #endif
47
48 static void ppc4xx_reset(void *opaque)
49 {
50 PowerPCCPU *cpu = opaque;
51
52 cpu_reset(CPU(cpu));
53 }
54
55 /*****************************************************************************/
56 /* Generic PowerPC 4xx processor instantiation */
57 PowerPCCPU *ppc4xx_init(const char *cpu_type,
58 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
59 uint32_t sysclk)
60 {
61 PowerPCCPU *cpu;
62 CPUPPCState *env;
63
64 /* init CPUs */
65 cpu = POWERPC_CPU(cpu_create(cpu_type));
66 env = &cpu->env;
67
68 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
69 cpu_clk->opaque = env;
70 /* Set time-base frequency to sysclk */
71 tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT);
72 tb_clk->opaque = env;
73 ppc_dcr_init(env, NULL, NULL);
74 /* Register qemu callbacks */
75 qemu_register_reset(ppc4xx_reset, cpu);
76
77 return cpu;
78 }
79
80 /*****************************************************************************/
81 /* SDRAM controller */
82 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
83 struct ppc4xx_sdram_t {
84 uint32_t addr;
85 int nbanks;
86 MemoryRegion containers[4]; /* used for clipping */
87 MemoryRegion *ram_memories;
88 hwaddr ram_bases[4];
89 hwaddr ram_sizes[4];
90 uint32_t besr0;
91 uint32_t besr1;
92 uint32_t bear;
93 uint32_t cfg;
94 uint32_t status;
95 uint32_t rtr;
96 uint32_t pmit;
97 uint32_t bcr[4];
98 uint32_t tr;
99 uint32_t ecccfg;
100 uint32_t eccesr;
101 qemu_irq irq;
102 };
103
104 enum {
105 SDRAM0_CFGADDR = 0x010,
106 SDRAM0_CFGDATA = 0x011,
107 };
108
109 /* XXX: TOFIX: some patches have made this code become inconsistent:
110 * there are type inconsistencies, mixing hwaddr, target_ulong
111 * and uint32_t
112 */
113 static uint32_t sdram_bcr (hwaddr ram_base,
114 hwaddr ram_size)
115 {
116 uint32_t bcr;
117
118 switch (ram_size) {
119 case 4 * MiB:
120 bcr = 0x00000000;
121 break;
122 case 8 * MiB:
123 bcr = 0x00020000;
124 break;
125 case 16 * MiB:
126 bcr = 0x00040000;
127 break;
128 case 32 * MiB:
129 bcr = 0x00060000;
130 break;
131 case 64 * MiB:
132 bcr = 0x00080000;
133 break;
134 case 128 * MiB:
135 bcr = 0x000A0000;
136 break;
137 case 256 * MiB:
138 bcr = 0x000C0000;
139 break;
140 default:
141 printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
142 ram_size);
143 return 0x00000000;
144 }
145 bcr |= ram_base & 0xFF800000;
146 bcr |= 1;
147
148 return bcr;
149 }
150
151 static inline hwaddr sdram_base(uint32_t bcr)
152 {
153 return bcr & 0xFF800000;
154 }
155
156 static target_ulong sdram_size (uint32_t bcr)
157 {
158 target_ulong size;
159 int sh;
160
161 sh = (bcr >> 17) & 0x7;
162 if (sh == 7)
163 size = -1;
164 else
165 size = (4 * MiB) << sh;
166
167 return size;
168 }
169
170 static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
171 uint32_t bcr, int enabled)
172 {
173 if (sdram->bcr[i] & 0x00000001) {
174 /* Unmap RAM */
175 #ifdef DEBUG_SDRAM
176 printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
177 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
178 #endif
179 memory_region_del_subregion(get_system_memory(),
180 &sdram->containers[i]);
181 memory_region_del_subregion(&sdram->containers[i],
182 &sdram->ram_memories[i]);
183 object_unparent(OBJECT(&sdram->containers[i]));
184 }
185 sdram->bcr[i] = bcr & 0xFFDEE001;
186 if (enabled && (bcr & 0x00000001)) {
187 #ifdef DEBUG_SDRAM
188 printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
189 __func__, sdram_base(bcr), sdram_size(bcr));
190 #endif
191 memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
192 sdram_size(bcr));
193 memory_region_add_subregion(&sdram->containers[i], 0,
194 &sdram->ram_memories[i]);
195 memory_region_add_subregion(get_system_memory(),
196 sdram_base(bcr),
197 &sdram->containers[i]);
198 }
199 }
200
201 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
202 {
203 int i;
204
205 for (i = 0; i < sdram->nbanks; i++) {
206 if (sdram->ram_sizes[i] != 0) {
207 sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i],
208 sdram->ram_sizes[i]), 1);
209 } else {
210 sdram_set_bcr(sdram, i, 0x00000000, 0);
211 }
212 }
213 }
214
215 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
216 {
217 int i;
218
219 for (i = 0; i < sdram->nbanks; i++) {
220 #ifdef DEBUG_SDRAM
221 printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
222 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
223 #endif
224 memory_region_del_subregion(get_system_memory(),
225 &sdram->ram_memories[i]);
226 }
227 }
228
229 static uint32_t dcr_read_sdram (void *opaque, int dcrn)
230 {
231 ppc4xx_sdram_t *sdram;
232 uint32_t ret;
233
234 sdram = opaque;
235 switch (dcrn) {
236 case SDRAM0_CFGADDR:
237 ret = sdram->addr;
238 break;
239 case SDRAM0_CFGDATA:
240 switch (sdram->addr) {
241 case 0x00: /* SDRAM_BESR0 */
242 ret = sdram->besr0;
243 break;
244 case 0x08: /* SDRAM_BESR1 */
245 ret = sdram->besr1;
246 break;
247 case 0x10: /* SDRAM_BEAR */
248 ret = sdram->bear;
249 break;
250 case 0x20: /* SDRAM_CFG */
251 ret = sdram->cfg;
252 break;
253 case 0x24: /* SDRAM_STATUS */
254 ret = sdram->status;
255 break;
256 case 0x30: /* SDRAM_RTR */
257 ret = sdram->rtr;
258 break;
259 case 0x34: /* SDRAM_PMIT */
260 ret = sdram->pmit;
261 break;
262 case 0x40: /* SDRAM_B0CR */
263 ret = sdram->bcr[0];
264 break;
265 case 0x44: /* SDRAM_B1CR */
266 ret = sdram->bcr[1];
267 break;
268 case 0x48: /* SDRAM_B2CR */
269 ret = sdram->bcr[2];
270 break;
271 case 0x4C: /* SDRAM_B3CR */
272 ret = sdram->bcr[3];
273 break;
274 case 0x80: /* SDRAM_TR */
275 ret = -1; /* ? */
276 break;
277 case 0x94: /* SDRAM_ECCCFG */
278 ret = sdram->ecccfg;
279 break;
280 case 0x98: /* SDRAM_ECCESR */
281 ret = sdram->eccesr;
282 break;
283 default: /* Error */
284 ret = -1;
285 break;
286 }
287 break;
288 default:
289 /* Avoid gcc warning */
290 ret = 0x00000000;
291 break;
292 }
293
294 return ret;
295 }
296
297 static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
298 {
299 ppc4xx_sdram_t *sdram;
300
301 sdram = opaque;
302 switch (dcrn) {
303 case SDRAM0_CFGADDR:
304 sdram->addr = val;
305 break;
306 case SDRAM0_CFGDATA:
307 switch (sdram->addr) {
308 case 0x00: /* SDRAM_BESR0 */
309 sdram->besr0 &= ~val;
310 break;
311 case 0x08: /* SDRAM_BESR1 */
312 sdram->besr1 &= ~val;
313 break;
314 case 0x10: /* SDRAM_BEAR */
315 sdram->bear = val;
316 break;
317 case 0x20: /* SDRAM_CFG */
318 val &= 0xFFE00000;
319 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
320 #ifdef DEBUG_SDRAM
321 printf("%s: enable SDRAM controller\n", __func__);
322 #endif
323 /* validate all RAM mappings */
324 sdram_map_bcr(sdram);
325 sdram->status &= ~0x80000000;
326 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
327 #ifdef DEBUG_SDRAM
328 printf("%s: disable SDRAM controller\n", __func__);
329 #endif
330 /* invalidate all RAM mappings */
331 sdram_unmap_bcr(sdram);
332 sdram->status |= 0x80000000;
333 }
334 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
335 sdram->status |= 0x40000000;
336 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
337 sdram->status &= ~0x40000000;
338 sdram->cfg = val;
339 break;
340 case 0x24: /* SDRAM_STATUS */
341 /* Read-only register */
342 break;
343 case 0x30: /* SDRAM_RTR */
344 sdram->rtr = val & 0x3FF80000;
345 break;
346 case 0x34: /* SDRAM_PMIT */
347 sdram->pmit = (val & 0xF8000000) | 0x07C00000;
348 break;
349 case 0x40: /* SDRAM_B0CR */
350 sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
351 break;
352 case 0x44: /* SDRAM_B1CR */
353 sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
354 break;
355 case 0x48: /* SDRAM_B2CR */
356 sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
357 break;
358 case 0x4C: /* SDRAM_B3CR */
359 sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
360 break;
361 case 0x80: /* SDRAM_TR */
362 sdram->tr = val & 0x018FC01F;
363 break;
364 case 0x94: /* SDRAM_ECCCFG */
365 sdram->ecccfg = val & 0x00F00000;
366 break;
367 case 0x98: /* SDRAM_ECCESR */
368 val &= 0xFFF0F000;
369 if (sdram->eccesr == 0 && val != 0)
370 qemu_irq_raise(sdram->irq);
371 else if (sdram->eccesr != 0 && val == 0)
372 qemu_irq_lower(sdram->irq);
373 sdram->eccesr = val;
374 break;
375 default: /* Error */
376 break;
377 }
378 break;
379 }
380 }
381
382 static void sdram_reset (void *opaque)
383 {
384 ppc4xx_sdram_t *sdram;
385
386 sdram = opaque;
387 sdram->addr = 0x00000000;
388 sdram->bear = 0x00000000;
389 sdram->besr0 = 0x00000000; /* No error */
390 sdram->besr1 = 0x00000000; /* No error */
391 sdram->cfg = 0x00000000;
392 sdram->ecccfg = 0x00000000; /* No ECC */
393 sdram->eccesr = 0x00000000; /* No error */
394 sdram->pmit = 0x07C00000;
395 sdram->rtr = 0x05F00000;
396 sdram->tr = 0x00854009;
397 /* We pre-initialize RAM banks */
398 sdram->status = 0x00000000;
399 sdram->cfg = 0x00800000;
400 }
401
402 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
403 MemoryRegion *ram_memories,
404 hwaddr *ram_bases,
405 hwaddr *ram_sizes,
406 int do_init)
407 {
408 ppc4xx_sdram_t *sdram;
409
410 sdram = g_malloc0(sizeof(ppc4xx_sdram_t));
411 sdram->irq = irq;
412 sdram->nbanks = nbanks;
413 sdram->ram_memories = ram_memories;
414 memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
415 memcpy(sdram->ram_bases, ram_bases,
416 nbanks * sizeof(hwaddr));
417 memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
418 memcpy(sdram->ram_sizes, ram_sizes,
419 nbanks * sizeof(hwaddr));
420 qemu_register_reset(&sdram_reset, sdram);
421 ppc_dcr_register(env, SDRAM0_CFGADDR,
422 sdram, &dcr_read_sdram, &dcr_write_sdram);
423 ppc_dcr_register(env, SDRAM0_CFGDATA,
424 sdram, &dcr_read_sdram, &dcr_write_sdram);
425 if (do_init)
426 sdram_map_bcr(sdram);
427 }
428
429 /*
430 * Split RAM between SDRAM banks.
431 *
432 * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
433 * and must be 0-terminated.
434 *
435 * The 4xx SDRAM controller supports a small number of banks, and each bank
436 * must be one of a small set of sizes. The number of banks and the supported
437 * sizes varies by SoC.
438 */
439 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
440 MemoryRegion ram_memories[],
441 hwaddr ram_bases[], hwaddr ram_sizes[],
442 const ram_addr_t sdram_bank_sizes[])
443 {
444 ram_addr_t size_left = memory_region_size(ram);
445 ram_addr_t base = 0;
446 ram_addr_t bank_size;
447 int i;
448 int j;
449
450 for (i = 0; i < nr_banks; i++) {
451 for (j = 0; sdram_bank_sizes[j] != 0; j++) {
452 bank_size = sdram_bank_sizes[j];
453 if (bank_size <= size_left) {
454 char name[32];
455
456 ram_bases[i] = base;
457 ram_sizes[i] = bank_size;
458 base += bank_size;
459 size_left -= bank_size;
460 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
461 memory_region_init_alias(&ram_memories[i], NULL, name, ram,
462 ram_bases[i], ram_sizes[i]);
463 break;
464 }
465 }
466 if (!size_left) {
467 /* No need to use the remaining banks. */
468 break;
469 }
470 }
471
472 if (size_left) {
473 ram_addr_t used_size = memory_region_size(ram) - size_left;
474 GString *s = g_string_new(NULL);
475
476 for (i = 0; sdram_bank_sizes[i]; i++) {
477 g_string_append_printf(s, "%" PRIi64 "%s",
478 sdram_bank_sizes[i] / MiB,
479 sdram_bank_sizes[i + 1] ? ", " : "");
480 }
481 error_report("at most %d bank%s of %s MiB each supported",
482 nr_banks, nr_banks == 1 ? "" : "s", s->str);
483 error_printf("Possible valid RAM size: %" PRIi64 " MiB \n",
484 used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
485
486 g_string_free(s, true);
487 exit(EXIT_FAILURE);
488 }
489 }
490
491 /*****************************************************************************/
492 /* MAL */
493
494 enum {
495 MAL0_CFG = 0x180,
496 MAL0_ESR = 0x181,
497 MAL0_IER = 0x182,
498 MAL0_TXCASR = 0x184,
499 MAL0_TXCARR = 0x185,
500 MAL0_TXEOBISR = 0x186,
501 MAL0_TXDEIR = 0x187,
502 MAL0_RXCASR = 0x190,
503 MAL0_RXCARR = 0x191,
504 MAL0_RXEOBISR = 0x192,
505 MAL0_RXDEIR = 0x193,
506 MAL0_TXCTP0R = 0x1A0,
507 MAL0_RXCTP0R = 0x1C0,
508 MAL0_RCBS0 = 0x1E0,
509 MAL0_RCBS1 = 0x1E1,
510 };
511
512 typedef struct ppc4xx_mal_t ppc4xx_mal_t;
513 struct ppc4xx_mal_t {
514 qemu_irq irqs[4];
515 uint32_t cfg;
516 uint32_t esr;
517 uint32_t ier;
518 uint32_t txcasr;
519 uint32_t txcarr;
520 uint32_t txeobisr;
521 uint32_t txdeir;
522 uint32_t rxcasr;
523 uint32_t rxcarr;
524 uint32_t rxeobisr;
525 uint32_t rxdeir;
526 uint32_t *txctpr;
527 uint32_t *rxctpr;
528 uint32_t *rcbs;
529 uint8_t txcnum;
530 uint8_t rxcnum;
531 };
532
533 static void ppc4xx_mal_reset(void *opaque)
534 {
535 ppc4xx_mal_t *mal;
536
537 mal = opaque;
538 mal->cfg = 0x0007C000;
539 mal->esr = 0x00000000;
540 mal->ier = 0x00000000;
541 mal->rxcasr = 0x00000000;
542 mal->rxdeir = 0x00000000;
543 mal->rxeobisr = 0x00000000;
544 mal->txcasr = 0x00000000;
545 mal->txdeir = 0x00000000;
546 mal->txeobisr = 0x00000000;
547 }
548
549 static uint32_t dcr_read_mal(void *opaque, int dcrn)
550 {
551 ppc4xx_mal_t *mal;
552 uint32_t ret;
553
554 mal = opaque;
555 switch (dcrn) {
556 case MAL0_CFG:
557 ret = mal->cfg;
558 break;
559 case MAL0_ESR:
560 ret = mal->esr;
561 break;
562 case MAL0_IER:
563 ret = mal->ier;
564 break;
565 case MAL0_TXCASR:
566 ret = mal->txcasr;
567 break;
568 case MAL0_TXCARR:
569 ret = mal->txcarr;
570 break;
571 case MAL0_TXEOBISR:
572 ret = mal->txeobisr;
573 break;
574 case MAL0_TXDEIR:
575 ret = mal->txdeir;
576 break;
577 case MAL0_RXCASR:
578 ret = mal->rxcasr;
579 break;
580 case MAL0_RXCARR:
581 ret = mal->rxcarr;
582 break;
583 case MAL0_RXEOBISR:
584 ret = mal->rxeobisr;
585 break;
586 case MAL0_RXDEIR:
587 ret = mal->rxdeir;
588 break;
589 default:
590 ret = 0;
591 break;
592 }
593 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
594 ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
595 }
596 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
597 ret = mal->rxctpr[dcrn - MAL0_RXCTP0R];
598 }
599 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
600 ret = mal->rcbs[dcrn - MAL0_RCBS0];
601 }
602
603 return ret;
604 }
605
606 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
607 {
608 ppc4xx_mal_t *mal;
609
610 mal = opaque;
611 switch (dcrn) {
612 case MAL0_CFG:
613 if (val & 0x80000000) {
614 ppc4xx_mal_reset(mal);
615 }
616 mal->cfg = val & 0x00FFC087;
617 break;
618 case MAL0_ESR:
619 /* Read/clear */
620 mal->esr &= ~val;
621 break;
622 case MAL0_IER:
623 mal->ier = val & 0x0000001F;
624 break;
625 case MAL0_TXCASR:
626 mal->txcasr = val & 0xF0000000;
627 break;
628 case MAL0_TXCARR:
629 mal->txcarr = val & 0xF0000000;
630 break;
631 case MAL0_TXEOBISR:
632 /* Read/clear */
633 mal->txeobisr &= ~val;
634 break;
635 case MAL0_TXDEIR:
636 /* Read/clear */
637 mal->txdeir &= ~val;
638 break;
639 case MAL0_RXCASR:
640 mal->rxcasr = val & 0xC0000000;
641 break;
642 case MAL0_RXCARR:
643 mal->rxcarr = val & 0xC0000000;
644 break;
645 case MAL0_RXEOBISR:
646 /* Read/clear */
647 mal->rxeobisr &= ~val;
648 break;
649 case MAL0_RXDEIR:
650 /* Read/clear */
651 mal->rxdeir &= ~val;
652 break;
653 }
654 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
655 mal->txctpr[dcrn - MAL0_TXCTP0R] = val;
656 }
657 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
658 mal->rxctpr[dcrn - MAL0_RXCTP0R] = val;
659 }
660 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
661 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;
662 }
663 }
664
665 void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
666 qemu_irq irqs[4])
667 {
668 ppc4xx_mal_t *mal;
669 int i;
670
671 assert(txcnum <= 32 && rxcnum <= 32);
672 mal = g_malloc0(sizeof(*mal));
673 mal->txcnum = txcnum;
674 mal->rxcnum = rxcnum;
675 mal->txctpr = g_new0(uint32_t, txcnum);
676 mal->rxctpr = g_new0(uint32_t, rxcnum);
677 mal->rcbs = g_new0(uint32_t, rxcnum);
678 for (i = 0; i < 4; i++) {
679 mal->irqs[i] = irqs[i];
680 }
681 qemu_register_reset(&ppc4xx_mal_reset, mal);
682 ppc_dcr_register(env, MAL0_CFG,
683 mal, &dcr_read_mal, &dcr_write_mal);
684 ppc_dcr_register(env, MAL0_ESR,
685 mal, &dcr_read_mal, &dcr_write_mal);
686 ppc_dcr_register(env, MAL0_IER,
687 mal, &dcr_read_mal, &dcr_write_mal);
688 ppc_dcr_register(env, MAL0_TXCASR,
689 mal, &dcr_read_mal, &dcr_write_mal);
690 ppc_dcr_register(env, MAL0_TXCARR,
691 mal, &dcr_read_mal, &dcr_write_mal);
692 ppc_dcr_register(env, MAL0_TXEOBISR,
693 mal, &dcr_read_mal, &dcr_write_mal);
694 ppc_dcr_register(env, MAL0_TXDEIR,
695 mal, &dcr_read_mal, &dcr_write_mal);
696 ppc_dcr_register(env, MAL0_RXCASR,
697 mal, &dcr_read_mal, &dcr_write_mal);
698 ppc_dcr_register(env, MAL0_RXCARR,
699 mal, &dcr_read_mal, &dcr_write_mal);
700 ppc_dcr_register(env, MAL0_RXEOBISR,
701 mal, &dcr_read_mal, &dcr_write_mal);
702 ppc_dcr_register(env, MAL0_RXDEIR,
703 mal, &dcr_read_mal, &dcr_write_mal);
704 for (i = 0; i < txcnum; i++) {
705 ppc_dcr_register(env, MAL0_TXCTP0R + i,
706 mal, &dcr_read_mal, &dcr_write_mal);
707 }
708 for (i = 0; i < rxcnum; i++) {
709 ppc_dcr_register(env, MAL0_RXCTP0R + i,
710 mal, &dcr_read_mal, &dcr_write_mal);
711 }
712 for (i = 0; i < rxcnum; i++) {
713 ppc_dcr_register(env, MAL0_RCBS0 + i,
714 mal, &dcr_read_mal, &dcr_write_mal);
715 }
716 }
AR7 emulation for QEMU