2 * QEMU model of the LatticeMico32 UART block.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 * Specification available at:
21 * http://www.latticesemi.com/documents/mico32uart.pdf
25 #include "qemu/osdep.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/qdev-properties-system.h"
29 #include "hw/sysbus.h"
30 #include "migration/vmstate.h"
32 #include "chardev/char-fe.h"
33 #include "qemu/error-report.h"
34 #include "qemu/module.h"
35 #include "qom/object.h"
98 #define TYPE_LM32_UART "lm32-uart"
99 OBJECT_DECLARE_SIMPLE_TYPE(LM32UartState
, LM32_UART
)
101 struct LM32UartState
{
102 SysBusDevice parent_obj
;
108 uint32_t regs
[R_MAX
];
111 static void uart_update_irq(LM32UartState
*s
)
115 if ((s
->regs
[R_LSR
] & (LSR_OE
| LSR_PE
| LSR_FE
| LSR_BI
))
116 && (s
->regs
[R_IER
] & IER_RLSI
)) {
118 s
->regs
[R_IIR
] = IIR_ID1
| IIR_ID0
;
119 } else if ((s
->regs
[R_LSR
] & LSR_DR
) && (s
->regs
[R_IER
] & IER_RBRI
)) {
121 s
->regs
[R_IIR
] = IIR_ID1
;
122 } else if ((s
->regs
[R_LSR
] & LSR_THRE
) && (s
->regs
[R_IER
] & IER_THRI
)) {
124 s
->regs
[R_IIR
] = IIR_ID0
;
125 } else if ((s
->regs
[R_MSR
] & 0x0f) && (s
->regs
[R_IER
] & IER_MSI
)) {
130 s
->regs
[R_IIR
] = IIR_STAT
;
133 trace_lm32_uart_irq_state(irq
);
134 qemu_set_irq(s
->irq
, irq
);
137 static uint64_t uart_read(void *opaque
, hwaddr addr
,
140 LM32UartState
*s
= opaque
;
147 s
->regs
[R_LSR
] &= ~LSR_DR
;
149 qemu_chr_fe_accept_input(&s
->chr
);
160 error_report("lm32_uart: read access to write only register 0x"
161 TARGET_FMT_plx
, addr
<< 2);
164 error_report("lm32_uart: read access to unknown register 0x"
165 TARGET_FMT_plx
, addr
<< 2);
169 trace_lm32_uart_memory_read(addr
<< 2, r
);
173 static void uart_write(void *opaque
, hwaddr addr
,
174 uint64_t value
, unsigned size
)
176 LM32UartState
*s
= opaque
;
177 unsigned char ch
= value
;
179 trace_lm32_uart_memory_write(addr
, value
);
184 /* XXX this blocks entire thread. Rewrite to use
185 * qemu_chr_fe_write and background I/O callbacks */
186 qemu_chr_fe_write_all(&s
->chr
, &ch
, 1);
192 s
->regs
[addr
] = value
;
197 error_report("lm32_uart: write access to read only register 0x"
198 TARGET_FMT_plx
, addr
<< 2);
201 error_report("lm32_uart: write access to unknown register 0x"
202 TARGET_FMT_plx
, addr
<< 2);
208 static const MemoryRegionOps uart_ops
= {
211 .endianness
= DEVICE_NATIVE_ENDIAN
,
213 .min_access_size
= 4,
214 .max_access_size
= 4,
218 static void uart_rx(void *opaque
, const uint8_t *buf
, int size
)
220 LM32UartState
*s
= opaque
;
222 if (s
->regs
[R_LSR
] & LSR_DR
) {
223 s
->regs
[R_LSR
] |= LSR_OE
;
226 s
->regs
[R_LSR
] |= LSR_DR
;
227 s
->regs
[R_RXTX
] = *buf
;
232 static int uart_can_rx(void *opaque
)
234 LM32UartState
*s
= opaque
;
236 return !(s
->regs
[R_LSR
] & LSR_DR
);
239 static void uart_event(void *opaque
, QEMUChrEvent event
)
243 static void uart_reset(DeviceState
*d
)
245 LM32UartState
*s
= LM32_UART(d
);
248 for (i
= 0; i
< R_MAX
; i
++) {
253 s
->regs
[R_LSR
] = LSR_THRE
| LSR_TEMT
;
256 static void lm32_uart_init(Object
*obj
)
258 LM32UartState
*s
= LM32_UART(obj
);
259 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
261 sysbus_init_irq(dev
, &s
->irq
);
263 memory_region_init_io(&s
->iomem
, obj
, &uart_ops
, s
,
265 sysbus_init_mmio(dev
, &s
->iomem
);
268 static void lm32_uart_realize(DeviceState
*dev
, Error
**errp
)
270 LM32UartState
*s
= LM32_UART(dev
);
272 qemu_chr_fe_set_handlers(&s
->chr
, uart_can_rx
, uart_rx
,
273 uart_event
, NULL
, s
, NULL
, true);
276 static const VMStateDescription vmstate_lm32_uart
= {
279 .minimum_version_id
= 1,
280 .fields
= (VMStateField
[]) {
281 VMSTATE_UINT32_ARRAY(regs
, LM32UartState
, R_MAX
),
282 VMSTATE_END_OF_LIST()
286 static Property lm32_uart_properties
[] = {
287 DEFINE_PROP_CHR("chardev", LM32UartState
, chr
),
288 DEFINE_PROP_END_OF_LIST(),
291 static void lm32_uart_class_init(ObjectClass
*klass
, void *data
)
293 DeviceClass
*dc
= DEVICE_CLASS(klass
);
295 dc
->reset
= uart_reset
;
296 dc
->vmsd
= &vmstate_lm32_uart
;
297 device_class_set_props(dc
, lm32_uart_properties
);
298 dc
->realize
= lm32_uart_realize
;
301 static const TypeInfo lm32_uart_info
= {
302 .name
= TYPE_LM32_UART
,
303 .parent
= TYPE_SYS_BUS_DEVICE
,
304 .instance_size
= sizeof(LM32UartState
),
305 .instance_init
= lm32_uart_init
,
306 .class_init
= lm32_uart_class_init
,
309 static void lm32_uart_register_types(void)
311 type_register_static(&lm32_uart_info
);
314 type_init(lm32_uart_register_types
)