hw/ppc/prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  * Copyright (c) 2017 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/rtc/m48t59.h"
  28 #include "hw/char/serial.h"
  29 #include "hw/block/fdc.h"
  30 #include "net/net.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/pci/pci.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/ppc/ppc.h"
  35 #include "hw/boards.h"
  36 #include "qapi/error.h"
  37 #include "qemu/error-report.h"
  38 #include "qemu/log.h"
  39 #include "hw/loader.h"
  40 #include "hw/rtc/mc146818rtc.h"
  41 #include "hw/isa/pc87312.h"
  42 #include "hw/qdev-properties.h"
  43 #include "sysemu/arch_init.h"
  44 #include "sysemu/kvm.h"
  45 #include "sysemu/reset.h"
  46 #include "exec/address-spaces.h"
  47 #include "trace.h"
  48 #include "elf.h"
  49 #include "qemu/units.h"
  50 #include "kvm_ppc.h"
  51
  52 /* SMP is not enabled, for now */
  53 #define MAX_CPUS 1
  54
  55 #define MAX_IDE_BUS 2
  56
  57 #define CFG_ADDR 0xf0000510
  58
  59 #define KERNEL_LOAD_ADDR 0x01000000
  60 #define INITRD_LOAD_ADDR 0x01800000
  61
  62 #define NVRAM_SIZE        0x2000
  63
  64 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  65                             Error **errp)
  66 {
  67     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  68 }
  69
  70 static void ppc_prep_reset(void *opaque)
  71 {
  72     PowerPCCPU *cpu = opaque;
  73
  74     cpu_reset(CPU(cpu));
  75 }
  76
  77
  78 /*****************************************************************************/
  79 /* NVRAM helpers */
  80 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
  81 {
  82     NvramClass *k = NVRAM_GET_CLASS(nvram);
  83     return (k->read)(nvram, addr);
  84 }
  85
  86 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
  87 {
  88     NvramClass *k = NVRAM_GET_CLASS(nvram);
  89     (k->write)(nvram, addr, val);
  90 }
  91
  92 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
  93 {
  94     nvram_write(nvram, addr, value);
  95 }
  96
  97 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
  98 {
  99     return nvram_read(nvram, addr);
 100 }
 101
 102 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
 103 {
 104     nvram_write(nvram, addr, value >> 8);
 105     nvram_write(nvram, addr + 1, value & 0xFF);
 106 }
 107
 108 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
 109 {
 110     uint16_t tmp;
 111
 112     tmp = nvram_read(nvram, addr) << 8;
 113     tmp |= nvram_read(nvram, addr + 1);
 114
 115     return tmp;
 116 }
 117
 118 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
 119 {
 120     nvram_write(nvram, addr, value >> 24);
 121     nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
 122     nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
 123     nvram_write(nvram, addr + 3, value & 0xFF);
 124 }
 125
 126 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
 127                              uint32_t max)
 128 {
 129     int i;
 130
 131     for (i = 0; i < max && str[i] != '\0'; i++) {
 132         nvram_write(nvram, addr + i, str[i]);
 133     }
 134     nvram_write(nvram, addr + i, str[i]);
 135     nvram_write(nvram, addr + max - 1, '\0');
 136 }
 137
 138 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 139 {
 140     uint16_t tmp;
 141     uint16_t pd, pd1, pd2;
 142
 143     tmp = prev >> 8;
 144     pd = prev ^ value;
 145     pd1 = pd & 0x000F;
 146     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 147     tmp ^= (pd1 << 3) | (pd1 << 8);
 148     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 149
 150     return tmp;
 151 }
 152
 153 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
 154 {
 155     uint32_t i;
 156     uint16_t crc = 0xFFFF;
 157     int odd;
 158
 159     odd = count & 1;
 160     count &= ~1;
 161     for (i = 0; i != count; i++) {
 162         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 163     }
 164     if (odd) {
 165         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 166     }
 167
 168     return crc;
 169 }
 170
 171 #define CMDLINE_ADDR 0x017ff000
 172
 173 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
 174                           const char *arch,
 175                           uint32_t RAM_size, int boot_device,
 176                           uint32_t kernel_image, uint32_t kernel_size,
 177                           const char *cmdline,
 178                           uint32_t initrd_image, uint32_t initrd_size,
 179                           uint32_t NVRAM_image,
 180                           int width, int height, int depth)
 181 {
 182     uint16_t crc;
 183
 184     /* Set parameters for Open Hack'Ware BIOS */
 185     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 186     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 187     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 188     NVRAM_set_string(nvram, 0x20, arch, 16);
 189     NVRAM_set_lword(nvram,  0x30, RAM_size);
 190     NVRAM_set_byte(nvram,   0x34, boot_device);
 191     NVRAM_set_lword(nvram,  0x38, kernel_image);
 192     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 193     if (cmdline) {
 194         /* XXX: put the cmdline in NVRAM too ? */
 195         pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
 196                          cmdline);
 197         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 198         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 199     } else {
 200         NVRAM_set_lword(nvram,  0x40, 0);
 201         NVRAM_set_lword(nvram,  0x44, 0);
 202     }
 203     NVRAM_set_lword(nvram,  0x48, initrd_image);
 204     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 205     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 206
 207     NVRAM_set_word(nvram,   0x54, width);
 208     NVRAM_set_word(nvram,   0x56, height);
 209     NVRAM_set_word(nvram,   0x58, depth);
 210     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 211     NVRAM_set_word(nvram,   0xFC, crc);
 212
 213     return 0;
 214 }
 215
 216 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
 217 {
 218     uint16_t checksum = *(uint16_t *)opaque;
 219     ISADevice *rtc;
 220
 221     if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
 222         rtc = ISA_DEVICE(dev);
 223         rtc_set_memory(rtc, 0x2e, checksum & 0xff);
 224         rtc_set_memory(rtc, 0x3e, checksum & 0xff);
 225         rtc_set_memory(rtc, 0x2f, checksum >> 8);
 226         rtc_set_memory(rtc, 0x3f, checksum >> 8);
 227
 228         object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
 229                                   "date");
 230     }
 231     return 0;
 232 }
 233
 234 static void ibm_40p_init(MachineState *machine)
 235 {
 236     const char *bios_name = machine->firmware ?: "openbios-ppc";
 237     CPUPPCState *env = NULL;
 238     uint16_t cmos_checksum;
 239     PowerPCCPU *cpu;
 240     DeviceState *dev, *i82378_dev;
 241     SysBusDevice *pcihost, *s;
 242     Nvram *m48t59 = NULL;
 243     PCIBus *pci_bus;
 244     ISADevice *isa_dev;
 245     ISABus *isa_bus;
 246     void *fw_cfg;
 247     int i;
 248     uint32_t kernel_base = 0, initrd_base = 0;
 249     long kernel_size = 0, initrd_size = 0;
 250     char boot_device;
 251
 252     /* init CPU */
 253     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 254     env = &cpu->env;
 255     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 256         error_report("only 6xx bus is supported on this machine");
 257         exit(1);
 258     }
 259
 260     if (env->flags & POWERPC_FLAG_RTC_CLK) {
 261         /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 262         cpu_ppc_tb_init(env, 7812500UL);
 263     } else {
 264         /* Set time-base frequency to 100 Mhz */
 265         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 266     }
 267     qemu_register_reset(ppc_prep_reset, cpu);
 268
 269     /* PCI host */
 270     dev = qdev_new("raven-pcihost");
 271     qdev_prop_set_string(dev, "bios-name", bios_name);
 272     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
 273     pcihost = SYS_BUS_DEVICE(dev);
 274     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
 275     sysbus_realize_and_unref(pcihost, &error_fatal);
 276     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
 277     if (!pci_bus) {
 278         error_report("could not create PCI host controller");
 279         exit(1);
 280     }
 281
 282     /* PCI -> ISA bridge */
 283     i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
 284     qdev_connect_gpio_out(i82378_dev, 0,
 285                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
 286     sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
 287     isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
 288
 289     /* Memory controller */
 290     isa_dev = isa_new("rs6000-mc");
 291     dev = DEVICE(isa_dev);
 292     qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
 293     isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 294
 295     /* RTC */
 296     isa_dev = isa_new(TYPE_MC146818_RTC);
 297     dev = DEVICE(isa_dev);
 298     qdev_prop_set_int32(dev, "base_year", 1900);
 299     isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 300
 301     /* initialize CMOS checksums */
 302     cmos_checksum = 0x6aa9;
 303     qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
 304                        &cmos_checksum);
 305
 306     /* add some more devices */
 307     if (defaults_enabled()) {
 308         m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
 309
 310         isa_dev = isa_new("cs4231a");
 311         dev = DEVICE(isa_dev);
 312         qdev_prop_set_uint32(dev, "iobase", 0x830);
 313         qdev_prop_set_uint32(dev, "irq", 10);
 314         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 315
 316         isa_dev = isa_new("pc87312");
 317         dev = DEVICE(isa_dev);
 318         qdev_prop_set_uint32(dev, "config", 12);
 319         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 320
 321         isa_dev = isa_new("prep-systemio");
 322         dev = DEVICE(isa_dev);
 323         qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
 324         qdev_prop_set_uint32(dev, "equipment", 0xc0);
 325         isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
 326
 327         dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
 328                                        "lsi53c810"));
 329         lsi53c8xx_handle_legacy_cmdline(dev);
 330         qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
 331
 332         /* XXX: s3-trio at PCI_DEVFN(2, 0) */
 333         pci_vga_init(pci_bus);
 334
 335         for (i = 0; i < nb_nics; i++) {
 336             pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
 337                                 i == 0 ? "3" : NULL);
 338         }
 339     }
 340
 341     /* Prepare firmware configuration for OpenBIOS */
 342     dev = qdev_new(TYPE_FW_CFG_MEM);
 343     fw_cfg = FW_CFG(dev);
 344     qdev_prop_set_uint32(dev, "data_width", 1);
 345     qdev_prop_set_bit(dev, "dma_enabled", false);
 346     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
 347                               OBJECT(fw_cfg));
 348     s = SYS_BUS_DEVICE(dev);
 349     sysbus_realize_and_unref(s, &error_fatal);
 350     sysbus_mmio_map(s, 0, CFG_ADDR);
 351     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
 352
 353     if (machine->kernel_filename) {
 354         /* load kernel */
 355         kernel_base = KERNEL_LOAD_ADDR;
 356         kernel_size = load_image_targphys(machine->kernel_filename,
 357                                           kernel_base,
 358                                           machine->ram_size - kernel_base);
 359         if (kernel_size < 0) {
 360             error_report("could not load kernel '%s'",
 361                          machine->kernel_filename);
 362             exit(1);
 363         }
 364         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 365         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 366         /* load initrd */
 367         if (machine->initrd_filename) {
 368             initrd_base = INITRD_LOAD_ADDR;
 369             initrd_size = load_image_targphys(machine->initrd_filename,
 370                                               initrd_base,
 371                                               machine->ram_size - initrd_base);
 372             if (initrd_size < 0) {
 373                 error_report("could not load initial ram disk '%s'",
 374                              machine->initrd_filename);
 375                 exit(1);
 376             }
 377             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 378             fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 379         }
 380         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
 381             fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 382             pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
 383                              machine->kernel_cmdline);
 384             fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
 385                               machine->kernel_cmdline);
 386             fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 387                            strlen(machine->kernel_cmdline) + 1);
 388         }
 389         boot_device = 'm';
 390     } else {
 391         boot_device = machine->boot_order[0];
 392     }
 393
 394     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
 395     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
 396     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
 397
 398     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 399     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 400     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 401
 402     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 403     if (kvm_enabled()) {
 404         uint8_t *hypercall;
 405
 406         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 407         hypercall = g_malloc(16);
 408         kvmppc_get_hypercall(env, hypercall, 16);
 409         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 410         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 411     } else {
 412         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
 413     }
 414     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
 415     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 416
 417     /* Prepare firmware configuration for Open Hack'Ware */
 418     if (m48t59) {
 419         PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size,
 420                              boot_device,
 421                              kernel_base, kernel_size,
 422                              machine->kernel_cmdline,
 423                              initrd_base, initrd_size,
 424                              /* XXX: need an option to load a NVRAM image */
 425                              0,
 426                              graphic_width, graphic_height, graphic_depth);
 427     }
 428 }
 429
 430 static void ibm_40p_machine_init(MachineClass *mc)
 431 {
 432     mc->desc = "IBM RS/6000 7020 (40p)",
 433     mc->init = ibm_40p_init;
 434     mc->max_cpus = 1;
 435     mc->default_ram_size = 128 * MiB;
 436     mc->block_default_type = IF_SCSI;
 437     mc->default_boot_order = "c";
 438     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
 439     mc->default_display = "std";
 440 }
 441
 442 DEFINE_MACHINE("40p", ibm_40p_machine_init)