hw/hppa/dino.c

   1 /*
   2  * HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines
   3  *
   4  * (C) 2017-2019 by Helge Deller <deller@gmx.de>
   5  *
   6  * This work is licensed under the GNU GPL license version 2 or later.
   7  *
   8  * Documentation available at:
   9  * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf
  10  * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qemu/module.h"
  15 #include "qemu/units.h"
  16 #include "qapi/error.h"
  17 #include "hw/irq.h"
  18 #include "hw/pci/pci.h"
  19 #include "hw/pci/pci_bus.h"
  20 #include "migration/vmstate.h"
  21 #include "hppa_sys.h"
  22 #include "exec/address-spaces.h"
  23 #include "trace.h"
  24 #include "qom/object.h"
  25
  26
  27 #define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
  28
  29 #define DINO_IAR0               0x004
  30 #define DINO_IODC               0x008
  31 #define DINO_IRR0               0x00C  /* RO */
  32 #define DINO_IAR1               0x010
  33 #define DINO_IRR1               0x014  /* RO */
  34 #define DINO_IMR                0x018
  35 #define DINO_IPR                0x01C
  36 #define DINO_TOC_ADDR           0x020
  37 #define DINO_ICR                0x024
  38 #define DINO_ILR                0x028  /* RO */
  39 #define DINO_IO_COMMAND         0x030  /* WO */
  40 #define DINO_IO_STATUS          0x034  /* RO */
  41 #define DINO_IO_CONTROL         0x038
  42 #define DINO_IO_GSC_ERR_RESP    0x040  /* RO */
  43 #define DINO_IO_ERR_INFO        0x044  /* RO */
  44 #define DINO_IO_PCI_ERR_RESP    0x048  /* RO */
  45 #define DINO_IO_FBB_EN          0x05c
  46 #define DINO_IO_ADDR_EN         0x060
  47 #define DINO_PCI_CONFIG_ADDR    0x064
  48 #define DINO_PCI_CONFIG_DATA    0x068
  49 #define DINO_PCI_IO_DATA        0x06c
  50 #define DINO_PCI_MEM_DATA       0x070  /* Dino 3.x only */
  51 #define DINO_GSC2X_CONFIG       0x7b4  /* RO */
  52 #define DINO_GMASK              0x800
  53 #define DINO_PAMR               0x804
  54 #define DINO_PAPR               0x808
  55 #define DINO_DAMODE             0x80c
  56 #define DINO_PCICMD             0x810
  57 #define DINO_PCISTS             0x814  /* R/WC */
  58 #define DINO_MLTIM              0x81c
  59 #define DINO_BRDG_FEAT          0x820
  60 #define DINO_PCIROR             0x824
  61 #define DINO_PCIWOR             0x828
  62 #define DINO_TLTIM              0x830
  63
  64 #define DINO_IRQS         11      /* bits 0-10 are architected */
  65 #define DINO_IRR_MASK     0x5ff   /* only 10 bits are implemented */
  66 #define DINO_LOCAL_IRQS   (DINO_IRQS + 1)
  67 #define DINO_MASK_IRQ(x)  (1 << (x))
  68
  69 #define PCIINTA   0x001
  70 #define PCIINTB   0x002
  71 #define PCIINTC   0x004
  72 #define PCIINTD   0x008
  73 #define PCIINTE   0x010
  74 #define PCIINTF   0x020
  75 #define GSCEXTINT 0x040
  76 /* #define xxx       0x080 - bit 7 is "default" */
  77 /* #define xxx    0x100 - bit 8 not used */
  78 /* #define xxx    0x200 - bit 9 not used */
  79 #define RS232INT  0x400
  80
  81 #define DINO_MEM_CHUNK_SIZE (8 * MiB)
  82
  83 OBJECT_DECLARE_SIMPLE_TYPE(DinoState, DINO_PCI_HOST_BRIDGE)
  84
  85 #define DINO800_REGS (1 + (DINO_TLTIM - DINO_GMASK) / 4)
  86 static const uint32_t reg800_keep_bits[DINO800_REGS] = {
  87     MAKE_64BIT_MASK(0, 1),  /* GMASK */
  88     MAKE_64BIT_MASK(0, 7),  /* PAMR */
  89     MAKE_64BIT_MASK(0, 7),  /* PAPR */
  90     MAKE_64BIT_MASK(0, 8),  /* DAMODE */
  91     MAKE_64BIT_MASK(0, 7),  /* PCICMD */
  92     MAKE_64BIT_MASK(0, 9),  /* PCISTS */
  93     MAKE_64BIT_MASK(0, 32), /* Undefined */
  94     MAKE_64BIT_MASK(0, 8),  /* MLTIM */
  95     MAKE_64BIT_MASK(0, 30), /* BRDG_FEAT */
  96     MAKE_64BIT_MASK(0, 24), /* PCIROR */
  97     MAKE_64BIT_MASK(0, 22), /* PCIWOR */
  98     MAKE_64BIT_MASK(0, 32), /* Undocumented */
  99     MAKE_64BIT_MASK(0, 9),  /* TLTIM */
 100 };
 101
 102 struct DinoState {
 103     PCIHostState parent_obj;
 104
 105     /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
 106        so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops.  */
 107     uint32_t config_reg_dino; /* keep original copy, including 2 lowest bits */
 108
 109     uint32_t iar0;
 110     uint32_t iar1;
 111     uint32_t imr;
 112     uint32_t ipr;
 113     uint32_t icr;
 114     uint32_t ilr;
 115     uint32_t io_fbb_en;
 116     uint32_t io_addr_en;
 117     uint32_t io_control;
 118     uint32_t toc_addr;
 119
 120     uint32_t reg800[DINO800_REGS];
 121
 122     MemoryRegion this_mem;
 123     MemoryRegion pci_mem;
 124     MemoryRegion pci_mem_alias[32];
 125
 126     AddressSpace bm_as;
 127     MemoryRegion bm;
 128     MemoryRegion bm_ram_alias;
 129     MemoryRegion bm_pci_alias;
 130     MemoryRegion bm_cpu_alias;
 131 };
 132
 133 /*
 134  * Dino can forward memory accesses from the CPU in the range between
 135  * 0xf0800000 and 0xff000000 to the PCI bus.
 136  */
 137 static void gsc_to_pci_forwarding(DinoState *s)
 138 {
 139     uint32_t io_addr_en, tmp;
 140     int enabled, i;
 141
 142     tmp = extract32(s->io_control, 7, 2);
 143     enabled = (tmp == 0x01);
 144     io_addr_en = s->io_addr_en;
 145     /* Mask out first (=firmware) and last (=Dino) areas. */
 146     io_addr_en &= ~(BIT(31) | BIT(0));
 147
 148     memory_region_transaction_begin();
 149     for (i = 1; i < 31; i++) {
 150         MemoryRegion *mem = &s->pci_mem_alias[i];
 151         if (enabled && (io_addr_en & (1U << i))) {
 152             if (!memory_region_is_mapped(mem)) {
 153                 uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
 154                 memory_region_add_subregion(get_system_memory(), addr, mem);
 155             }
 156         } else if (memory_region_is_mapped(mem)) {
 157             memory_region_del_subregion(get_system_memory(), mem);
 158         }
 159     }
 160     memory_region_transaction_commit();
 161 }
 162
 163 static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
 164                                 unsigned size, bool is_write,
 165                                 MemTxAttrs attrs)
 166 {
 167     bool ret = false;
 168
 169     switch (addr) {
 170     case DINO_IAR0:
 171     case DINO_IAR1:
 172     case DINO_IRR0:
 173     case DINO_IRR1:
 174     case DINO_IMR:
 175     case DINO_IPR:
 176     case DINO_ICR:
 177     case DINO_ILR:
 178     case DINO_IO_CONTROL:
 179     case DINO_IO_FBB_EN:
 180     case DINO_IO_ADDR_EN:
 181     case DINO_PCI_IO_DATA:
 182     case DINO_TOC_ADDR:
 183     case DINO_GMASK ... DINO_PCISTS:
 184     case DINO_MLTIM ... DINO_PCIWOR:
 185     case DINO_TLTIM:
 186         ret = true;
 187         break;
 188     case DINO_PCI_IO_DATA + 2:
 189         ret = (size <= 2);
 190         break;
 191     case DINO_PCI_IO_DATA + 1:
 192     case DINO_PCI_IO_DATA + 3:
 193         ret = (size == 1);
 194     }
 195     trace_dino_chip_mem_valid(addr, ret);
 196     return ret;
 197 }
 198
 199 static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
 200                                              uint64_t *data, unsigned size,
 201                                              MemTxAttrs attrs)
 202 {
 203     DinoState *s = opaque;
 204     MemTxResult ret = MEMTX_OK;
 205     AddressSpace *io;
 206     uint16_t ioaddr;
 207     uint32_t val;
 208
 209     switch (addr) {
 210     case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
 211         /* Read from PCI IO space. */
 212         io = &address_space_io;
 213         ioaddr = s->parent_obj.config_reg + (addr & 3);
 214         switch (size) {
 215         case 1:
 216             val = address_space_ldub(io, ioaddr, attrs, &ret);
 217             break;
 218         case 2:
 219             val = address_space_lduw_be(io, ioaddr, attrs, &ret);
 220             break;
 221         case 4:
 222             val = address_space_ldl_be(io, ioaddr, attrs, &ret);
 223             break;
 224         default:
 225             g_assert_not_reached();
 226         }
 227         break;
 228
 229     case DINO_IO_FBB_EN:
 230         val = s->io_fbb_en;
 231         break;
 232     case DINO_IO_ADDR_EN:
 233         val = s->io_addr_en;
 234         break;
 235     case DINO_IO_CONTROL:
 236         val = s->io_control;
 237         break;
 238
 239     case DINO_IAR0:
 240         val = s->iar0;
 241         break;
 242     case DINO_IAR1:
 243         val = s->iar1;
 244         break;
 245     case DINO_IMR:
 246         val = s->imr;
 247         break;
 248     case DINO_ICR:
 249         val = s->icr;
 250         break;
 251     case DINO_IPR:
 252         val = s->ipr;
 253         /* Any read to IPR clears the register.  */
 254         s->ipr = 0;
 255         break;
 256     case DINO_ILR:
 257         val = s->ilr;
 258         break;
 259     case DINO_IRR0:
 260         val = s->ilr & s->imr & ~s->icr;
 261         break;
 262     case DINO_IRR1:
 263         val = s->ilr & s->imr & s->icr;
 264         break;
 265     case DINO_TOC_ADDR:
 266         val = s->toc_addr;
 267         break;
 268     case DINO_GMASK ... DINO_TLTIM:
 269         val = s->reg800[(addr - DINO_GMASK) / 4];
 270         if (addr == DINO_PAMR) {
 271             val &= ~0x01;  /* LSB is hardwired to 0 */
 272         }
 273         if (addr == DINO_MLTIM) {
 274             val &= ~0x07;  /* 3 LSB are hardwired to 0 */
 275         }
 276         if (addr == DINO_BRDG_FEAT) {
 277             val &= ~(0x10710E0ul | 8); /* bits 5-7, 24 & 15 reserved */
 278         }
 279         break;
 280
 281     default:
 282         /* Controlled by dino_chip_mem_valid above.  */
 283         g_assert_not_reached();
 284     }
 285
 286     trace_dino_chip_read(addr, val);
 287     *data = val;
 288     return ret;
 289 }
 290
 291 static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
 292                                               uint64_t val, unsigned size,
 293                                               MemTxAttrs attrs)
 294 {
 295     DinoState *s = opaque;
 296     AddressSpace *io;
 297     MemTxResult ret;
 298     uint16_t ioaddr;
 299     int i;
 300
 301     trace_dino_chip_write(addr, val);
 302
 303     switch (addr) {
 304     case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
 305         /* Write into PCI IO space.  */
 306         io = &address_space_io;
 307         ioaddr = s->parent_obj.config_reg + (addr & 3);
 308         switch (size) {
 309         case 1:
 310             address_space_stb(io, ioaddr, val, attrs, &ret);
 311             break;
 312         case 2:
 313             address_space_stw_be(io, ioaddr, val, attrs, &ret);
 314             break;
 315         case 4:
 316             address_space_stl_be(io, ioaddr, val, attrs, &ret);
 317             break;
 318         default:
 319             g_assert_not_reached();
 320         }
 321         return ret;
 322
 323     case DINO_IO_FBB_EN:
 324         s->io_fbb_en = val & 0x03;
 325         break;
 326     case DINO_IO_ADDR_EN:
 327         s->io_addr_en = val;
 328         gsc_to_pci_forwarding(s);
 329         break;
 330     case DINO_IO_CONTROL:
 331         s->io_control = val;
 332         gsc_to_pci_forwarding(s);
 333         break;
 334
 335     case DINO_IAR0:
 336         s->iar0 = val;
 337         break;
 338     case DINO_IAR1:
 339         s->iar1 = val;
 340         break;
 341     case DINO_IMR:
 342         s->imr = val;
 343         break;
 344     case DINO_ICR:
 345         s->icr = val;
 346         break;
 347     case DINO_IPR:
 348         /* Any write to IPR clears the register.  */
 349         s->ipr = 0;
 350         break;
 351     case DINO_TOC_ADDR:
 352         /* IO_COMMAND of CPU with client_id bits */
 353         s->toc_addr = 0xFFFA0030 | (val & 0x1e000);
 354         break;
 355
 356     case DINO_ILR:
 357     case DINO_IRR0:
 358     case DINO_IRR1:
 359         /* These registers are read-only.  */
 360         break;
 361
 362     case DINO_GMASK ... DINO_TLTIM:
 363         i = (addr - DINO_GMASK) / 4;
 364         val &= reg800_keep_bits[i];
 365         s->reg800[i] = val;
 366         break;
 367
 368     default:
 369         /* Controlled by dino_chip_mem_valid above.  */
 370         g_assert_not_reached();
 371     }
 372     return MEMTX_OK;
 373 }
 374
 375 static const MemoryRegionOps dino_chip_ops = {
 376     .read_with_attrs = dino_chip_read_with_attrs,
 377     .write_with_attrs = dino_chip_write_with_attrs,
 378     .endianness = DEVICE_BIG_ENDIAN,
 379     .valid = {
 380         .min_access_size = 1,
 381         .max_access_size = 4,
 382         .accepts = dino_chip_mem_valid,
 383     },
 384     .impl = {
 385         .min_access_size = 1,
 386         .max_access_size = 4,
 387     },
 388 };
 389
 390 static const VMStateDescription vmstate_dino = {
 391     .name = "Dino",
 392     .version_id = 2,
 393     .minimum_version_id = 1,
 394     .fields = (VMStateField[]) {
 395         VMSTATE_UINT32(iar0, DinoState),
 396         VMSTATE_UINT32(iar1, DinoState),
 397         VMSTATE_UINT32(imr, DinoState),
 398         VMSTATE_UINT32(ipr, DinoState),
 399         VMSTATE_UINT32(icr, DinoState),
 400         VMSTATE_UINT32(ilr, DinoState),
 401         VMSTATE_UINT32(io_fbb_en, DinoState),
 402         VMSTATE_UINT32(io_addr_en, DinoState),
 403         VMSTATE_UINT32(io_control, DinoState),
 404         VMSTATE_UINT32(toc_addr, DinoState),
 405         VMSTATE_END_OF_LIST()
 406     }
 407 };
 408
 409 /* Unlike pci_config_data_le_ops, no check of high bit set in config_reg.  */
 410
 411 static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
 412 {
 413     PCIHostState *s = opaque;
 414     return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
 415 }
 416
 417 static void dino_config_data_write(void *opaque, hwaddr addr,
 418                                    uint64_t val, unsigned len)
 419 {
 420     PCIHostState *s = opaque;
 421     pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
 422 }
 423
 424 static const MemoryRegionOps dino_config_data_ops = {
 425     .read = dino_config_data_read,
 426     .write = dino_config_data_write,
 427     .endianness = DEVICE_LITTLE_ENDIAN,
 428 };
 429
 430 static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
 431 {
 432     DinoState *s = opaque;
 433     return s->config_reg_dino;
 434 }
 435
 436 static void dino_config_addr_write(void *opaque, hwaddr addr,
 437                                    uint64_t val, unsigned len)
 438 {
 439     PCIHostState *s = opaque;
 440     DinoState *ds = opaque;
 441     ds->config_reg_dino = val; /* keep a copy of original value */
 442     s->config_reg = val & ~3U;
 443 }
 444
 445 static const MemoryRegionOps dino_config_addr_ops = {
 446     .read = dino_config_addr_read,
 447     .write = dino_config_addr_write,
 448     .valid.min_access_size = 4,
 449     .valid.max_access_size = 4,
 450     .endianness = DEVICE_BIG_ENDIAN,
 451 };
 452
 453 static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque,
 454                                             int devfn)
 455 {
 456     DinoState *s = opaque;
 457
 458     return &s->bm_as;
 459 }
 460
 461 /*
 462  * Dino interrupts are connected as shown on Page 78, Table 23
 463  * (Little-endian bit numbers)
 464  *    0   PCI INTA
 465  *    1   PCI INTB
 466  *    2   PCI INTC
 467  *    3   PCI INTD
 468  *    4   PCI INTE
 469  *    5   PCI INTF
 470  *    6   GSC External Interrupt
 471  *    7   Bus Error for "less than fatal" mode
 472  *    8   PS2
 473  *    9   Unused
 474  *    10  RS232
 475  */
 476
 477 static void dino_set_irq(void *opaque, int irq, int level)
 478 {
 479     DinoState *s = opaque;
 480     uint32_t bit = 1u << irq;
 481     uint32_t old_ilr = s->ilr;
 482
 483     if (level) {
 484         uint32_t ena = bit & ~old_ilr;
 485         s->ipr |= ena;
 486         s->ilr = old_ilr | bit;
 487         if (ena & s->imr) {
 488             uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0);
 489             stl_be_phys(&address_space_memory, iar & -32, iar & 31);
 490         }
 491     } else {
 492         s->ilr = old_ilr & ~bit;
 493     }
 494 }
 495
 496 static int dino_pci_map_irq(PCIDevice *d, int irq_num)
 497 {
 498     int slot = PCI_SLOT(d->devfn);
 499
 500     assert(irq_num >= 0 && irq_num <= 3);
 501
 502     return slot & 0x03;
 503 }
 504
 505 static void dino_set_timer_irq(void *opaque, int irq, int level)
 506 {
 507     /* ??? Not connected.  */
 508 }
 509
 510 static void dino_set_serial_irq(void *opaque, int irq, int level)
 511 {
 512     dino_set_irq(opaque, 10, level);
 513 }
 514
 515 PCIBus *dino_init(MemoryRegion *addr_space,
 516                   qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq)
 517 {
 518     DeviceState *dev;
 519     DinoState *s;
 520     PCIBus *b;
 521     int i;
 522
 523     dev = qdev_new(TYPE_DINO_PCI_HOST_BRIDGE);
 524     s = DINO_PCI_HOST_BRIDGE(dev);
 525     s->iar0 = s->iar1 = CPU_HPA + 3;
 526     s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */
 527
 528     /* Dino PCI access from main memory.  */
 529     memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
 530                           s, "dino", 4096);
 531     memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem);
 532
 533     /* Dino PCI config. */
 534     memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj),
 535                           &dino_config_addr_ops, dev, "pci-conf-idx", 4);
 536     memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj),
 537                           &dino_config_data_ops, dev, "pci-conf-data", 4);
 538     memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
 539                                 &s->parent_obj.conf_mem);
 540     memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA,
 541                                 &s->parent_obj.data_mem);
 542
 543     /* Dino PCI bus memory.  */
 544     memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 4 * GiB);
 545
 546     b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s,
 547                               &s->pci_mem, get_system_io(),
 548                               PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
 549     s->parent_obj.bus = b;
 550     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 551
 552     /* Set up windows into PCI bus memory.  */
 553     for (i = 1; i < 31; i++) {
 554         uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
 555         char *name = g_strdup_printf("PCI Outbound Window %d", i);
 556         memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s),
 557                                  name, &s->pci_mem, addr,
 558                                  DINO_MEM_CHUNK_SIZE);
 559         g_free(name);
 560     }
 561
 562     /* Set up PCI view of memory: Bus master address space.  */
 563     memory_region_init(&s->bm, OBJECT(s), "bm-dino", 4 * GiB);
 564     memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
 565                              "bm-system", addr_space, 0,
 566                              0xf0000000 + DINO_MEM_CHUNK_SIZE);
 567     memory_region_init_alias(&s->bm_pci_alias, OBJECT(s),
 568                              "bm-pci", &s->pci_mem,
 569                              0xf0000000 + DINO_MEM_CHUNK_SIZE,
 570                              30 * DINO_MEM_CHUNK_SIZE);
 571     memory_region_init_alias(&s->bm_cpu_alias, OBJECT(s),
 572                              "bm-cpu", addr_space, 0xfff00000,
 573                              0xfffff);
 574     memory_region_add_subregion(&s->bm, 0,
 575                                 &s->bm_ram_alias);
 576     memory_region_add_subregion(&s->bm,
 577                                 0xf0000000 + DINO_MEM_CHUNK_SIZE,
 578                                 &s->bm_pci_alias);
 579     memory_region_add_subregion(&s->bm, 0xfff00000,
 580                                 &s->bm_cpu_alias);
 581     address_space_init(&s->bm_as, &s->bm, "pci-bm");
 582     pci_setup_iommu(b, dino_pcihost_set_iommu, s);
 583
 584     *p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0);
 585     *p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0);
 586
 587     return b;
 588 }
 589
 590 static void dino_pcihost_class_init(ObjectClass *klass, void *data)
 591 {
 592     DeviceClass *dc = DEVICE_CLASS(klass);
 593
 594     dc->vmsd = &vmstate_dino;
 595 }
 596
 597 static const TypeInfo dino_pcihost_info = {
 598     .name          = TYPE_DINO_PCI_HOST_BRIDGE,
 599     .parent        = TYPE_PCI_HOST_BRIDGE,
 600     .instance_size = sizeof(DinoState),
 601     .class_init    = dino_pcihost_class_init,
 602 };
 603
 604 static void dino_register_types(void)
 605 {
 606     type_register_static(&dino_pcihost_info);
 607 }
 608
 609 type_init(dino_register_types)