4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
7 * Copyright 2016 IBM Corp.
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "exec/address-spaces.h"
16 #include "hw/misc/unimp.h"
17 #include "hw/arm/aspeed_soc.h"
18 #include "hw/char/serial.h"
19 #include "qemu/module.h"
20 #include "qemu/error-report.h"
21 #include "hw/i2c/aspeed_i2c.h"
23 #include "sysemu/sysemu.h"
25 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
27 static const hwaddr aspeed_soc_ast2400_memmap
[] = {
28 [ASPEED_DEV_IOMEM
] = 0x1E600000,
29 [ASPEED_DEV_FMC
] = 0x1E620000,
30 [ASPEED_DEV_SPI1
] = 0x1E630000,
31 [ASPEED_DEV_EHCI1
] = 0x1E6A1000,
32 [ASPEED_DEV_VIC
] = 0x1E6C0000,
33 [ASPEED_DEV_SDMC
] = 0x1E6E0000,
34 [ASPEED_DEV_SCU
] = 0x1E6E2000,
35 [ASPEED_DEV_XDMA
] = 0x1E6E7000,
36 [ASPEED_DEV_VIDEO
] = 0x1E700000,
37 [ASPEED_DEV_ADC
] = 0x1E6E9000,
38 [ASPEED_DEV_SRAM
] = 0x1E720000,
39 [ASPEED_DEV_SDHCI
] = 0x1E740000,
40 [ASPEED_DEV_GPIO
] = 0x1E780000,
41 [ASPEED_DEV_RTC
] = 0x1E781000,
42 [ASPEED_DEV_TIMER1
] = 0x1E782000,
43 [ASPEED_DEV_WDT
] = 0x1E785000,
44 [ASPEED_DEV_PWM
] = 0x1E786000,
45 [ASPEED_DEV_LPC
] = 0x1E789000,
46 [ASPEED_DEV_IBT
] = 0x1E789140,
47 [ASPEED_DEV_I2C
] = 0x1E78A000,
48 [ASPEED_DEV_ETH1
] = 0x1E660000,
49 [ASPEED_DEV_ETH2
] = 0x1E680000,
50 [ASPEED_DEV_UART1
] = 0x1E783000,
51 [ASPEED_DEV_UART5
] = 0x1E784000,
52 [ASPEED_DEV_VUART
] = 0x1E787000,
53 [ASPEED_DEV_SDRAM
] = 0x40000000,
56 static const hwaddr aspeed_soc_ast2500_memmap
[] = {
57 [ASPEED_DEV_IOMEM
] = 0x1E600000,
58 [ASPEED_DEV_FMC
] = 0x1E620000,
59 [ASPEED_DEV_SPI1
] = 0x1E630000,
60 [ASPEED_DEV_SPI2
] = 0x1E631000,
61 [ASPEED_DEV_EHCI1
] = 0x1E6A1000,
62 [ASPEED_DEV_EHCI2
] = 0x1E6A3000,
63 [ASPEED_DEV_VIC
] = 0x1E6C0000,
64 [ASPEED_DEV_SDMC
] = 0x1E6E0000,
65 [ASPEED_DEV_SCU
] = 0x1E6E2000,
66 [ASPEED_DEV_XDMA
] = 0x1E6E7000,
67 [ASPEED_DEV_ADC
] = 0x1E6E9000,
68 [ASPEED_DEV_VIDEO
] = 0x1E700000,
69 [ASPEED_DEV_SRAM
] = 0x1E720000,
70 [ASPEED_DEV_SDHCI
] = 0x1E740000,
71 [ASPEED_DEV_GPIO
] = 0x1E780000,
72 [ASPEED_DEV_RTC
] = 0x1E781000,
73 [ASPEED_DEV_TIMER1
] = 0x1E782000,
74 [ASPEED_DEV_WDT
] = 0x1E785000,
75 [ASPEED_DEV_PWM
] = 0x1E786000,
76 [ASPEED_DEV_LPC
] = 0x1E789000,
77 [ASPEED_DEV_IBT
] = 0x1E789140,
78 [ASPEED_DEV_I2C
] = 0x1E78A000,
79 [ASPEED_DEV_ETH1
] = 0x1E660000,
80 [ASPEED_DEV_ETH2
] = 0x1E680000,
81 [ASPEED_DEV_UART1
] = 0x1E783000,
82 [ASPEED_DEV_UART5
] = 0x1E784000,
83 [ASPEED_DEV_VUART
] = 0x1E787000,
84 [ASPEED_DEV_SDRAM
] = 0x80000000,
87 static const int aspeed_soc_ast2400_irqmap
[] = {
88 [ASPEED_DEV_UART1
] = 9,
89 [ASPEED_DEV_UART2
] = 32,
90 [ASPEED_DEV_UART3
] = 33,
91 [ASPEED_DEV_UART4
] = 34,
92 [ASPEED_DEV_UART5
] = 10,
93 [ASPEED_DEV_VUART
] = 8,
94 [ASPEED_DEV_FMC
] = 19,
95 [ASPEED_DEV_EHCI1
] = 5,
96 [ASPEED_DEV_EHCI2
] = 13,
97 [ASPEED_DEV_SDMC
] = 0,
98 [ASPEED_DEV_SCU
] = 21,
99 [ASPEED_DEV_ADC
] = 31,
100 [ASPEED_DEV_GPIO
] = 20,
101 [ASPEED_DEV_RTC
] = 22,
102 [ASPEED_DEV_TIMER1
] = 16,
103 [ASPEED_DEV_TIMER2
] = 17,
104 [ASPEED_DEV_TIMER3
] = 18,
105 [ASPEED_DEV_TIMER4
] = 35,
106 [ASPEED_DEV_TIMER5
] = 36,
107 [ASPEED_DEV_TIMER6
] = 37,
108 [ASPEED_DEV_TIMER7
] = 38,
109 [ASPEED_DEV_TIMER8
] = 39,
110 [ASPEED_DEV_WDT
] = 27,
111 [ASPEED_DEV_PWM
] = 28,
112 [ASPEED_DEV_LPC
] = 8,
113 [ASPEED_DEV_I2C
] = 12,
114 [ASPEED_DEV_ETH1
] = 2,
115 [ASPEED_DEV_ETH2
] = 3,
116 [ASPEED_DEV_XDMA
] = 6,
117 [ASPEED_DEV_SDHCI
] = 26,
120 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
122 static qemu_irq
aspeed_soc_get_irq(AspeedSoCState
*s
, int ctrl
)
124 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
126 return qdev_get_gpio_in(DEVICE(&s
->vic
), sc
->irqmap
[ctrl
]);
129 static void aspeed_soc_init(Object
*obj
)
131 AspeedSoCState
*s
= ASPEED_SOC(obj
);
132 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
137 if (sscanf(sc
->name
, "%7s", socname
) != 1) {
138 g_assert_not_reached();
141 for (i
= 0; i
< sc
->num_cpus
; i
++) {
142 object_initialize_child(obj
, "cpu[*]", &s
->cpu
[i
], sc
->cpu_type
);
145 snprintf(typename
, sizeof(typename
), "aspeed.scu-%s", socname
);
146 object_initialize_child(obj
, "scu", &s
->scu
, typename
);
147 qdev_prop_set_uint32(DEVICE(&s
->scu
), "silicon-rev",
149 object_property_add_alias(obj
, "hw-strap1", OBJECT(&s
->scu
),
151 object_property_add_alias(obj
, "hw-strap2", OBJECT(&s
->scu
),
153 object_property_add_alias(obj
, "hw-prot-key", OBJECT(&s
->scu
),
156 object_initialize_child(obj
, "vic", &s
->vic
, TYPE_ASPEED_VIC
);
158 object_initialize_child(obj
, "rtc", &s
->rtc
, TYPE_ASPEED_RTC
);
160 snprintf(typename
, sizeof(typename
), "aspeed.timer-%s", socname
);
161 object_initialize_child(obj
, "timerctrl", &s
->timerctrl
, typename
);
163 snprintf(typename
, sizeof(typename
), "aspeed.i2c-%s", socname
);
164 object_initialize_child(obj
, "i2c", &s
->i2c
, typename
);
166 snprintf(typename
, sizeof(typename
), "aspeed.fmc-%s", socname
);
167 object_initialize_child(obj
, "fmc", &s
->fmc
, typename
);
168 object_property_add_alias(obj
, "num-cs", OBJECT(&s
->fmc
), "num-cs");
170 for (i
= 0; i
< sc
->spis_num
; i
++) {
171 snprintf(typename
, sizeof(typename
), "aspeed.spi%d-%s", i
+ 1, socname
);
172 object_initialize_child(obj
, "spi[*]", &s
->spi
[i
], typename
);
175 for (i
= 0; i
< sc
->ehcis_num
; i
++) {
176 object_initialize_child(obj
, "ehci[*]", &s
->ehci
[i
],
180 snprintf(typename
, sizeof(typename
), "aspeed.sdmc-%s", socname
);
181 object_initialize_child(obj
, "sdmc", &s
->sdmc
, typename
);
182 object_property_add_alias(obj
, "ram-size", OBJECT(&s
->sdmc
),
184 object_property_add_alias(obj
, "max-ram-size", OBJECT(&s
->sdmc
),
187 for (i
= 0; i
< sc
->wdts_num
; i
++) {
188 snprintf(typename
, sizeof(typename
), "aspeed.wdt-%s", socname
);
189 object_initialize_child(obj
, "wdt[*]", &s
->wdt
[i
], typename
);
192 for (i
= 0; i
< sc
->macs_num
; i
++) {
193 object_initialize_child(obj
, "ftgmac100[*]", &s
->ftgmac100
[i
],
197 object_initialize_child(obj
, "xdma", &s
->xdma
, TYPE_ASPEED_XDMA
);
199 snprintf(typename
, sizeof(typename
), "aspeed.gpio-%s", socname
);
200 object_initialize_child(obj
, "gpio", &s
->gpio
, typename
);
202 object_initialize_child(obj
, "sdc", &s
->sdhci
, TYPE_ASPEED_SDHCI
);
204 object_property_set_int(OBJECT(&s
->sdhci
), "num-slots", 2, &error_abort
);
206 /* Init sd card slot class here so that they're under the correct parent */
207 for (i
= 0; i
< ASPEED_SDHCI_NUM_SLOTS
; ++i
) {
208 object_initialize_child(obj
, "sdhci[*]", &s
->sdhci
.slots
[i
],
212 object_initialize_child(obj
, "lpc", &s
->lpc
, TYPE_ASPEED_LPC
);
215 static void aspeed_soc_realize(DeviceState
*dev
, Error
**errp
)
218 AspeedSoCState
*s
= ASPEED_SOC(dev
);
219 AspeedSoCClass
*sc
= ASPEED_SOC_GET_CLASS(s
);
223 create_unimplemented_device("aspeed_soc.io", sc
->memmap
[ASPEED_DEV_IOMEM
],
224 ASPEED_SOC_IOMEM_SIZE
);
226 /* Video engine stub */
227 create_unimplemented_device("aspeed.video", sc
->memmap
[ASPEED_DEV_VIDEO
],
231 for (i
= 0; i
< sc
->num_cpus
; i
++) {
232 if (!qdev_realize(DEVICE(&s
->cpu
[i
]), NULL
, errp
)) {
238 memory_region_init_ram(&s
->sram
, OBJECT(dev
), "aspeed.sram",
239 sc
->sram_size
, &err
);
241 error_propagate(errp
, err
);
244 memory_region_add_subregion(get_system_memory(),
245 sc
->memmap
[ASPEED_DEV_SRAM
], &s
->sram
);
248 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->scu
), errp
)) {
251 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->scu
), 0, sc
->memmap
[ASPEED_DEV_SCU
]);
254 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->vic
), errp
)) {
257 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->vic
), 0, sc
->memmap
[ASPEED_DEV_VIC
]);
258 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 0,
259 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
260 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->vic
), 1,
261 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
264 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->rtc
), errp
)) {
267 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->rtc
), 0, sc
->memmap
[ASPEED_DEV_RTC
]);
268 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->rtc
), 0,
269 aspeed_soc_get_irq(s
, ASPEED_DEV_RTC
));
272 object_property_set_link(OBJECT(&s
->timerctrl
), "scu", OBJECT(&s
->scu
),
274 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->timerctrl
), errp
)) {
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->timerctrl
), 0,
278 sc
->memmap
[ASPEED_DEV_TIMER1
]);
279 for (i
= 0; i
< ASPEED_TIMER_NR_TIMERS
; i
++) {
280 qemu_irq irq
= aspeed_soc_get_irq(s
, ASPEED_DEV_TIMER1
+ i
);
281 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->timerctrl
), i
, irq
);
284 /* UART - attach an 8250 to the IO space as our UART5 */
285 serial_mm_init(get_system_memory(), sc
->memmap
[ASPEED_DEV_UART5
], 2,
286 aspeed_soc_get_irq(s
, ASPEED_DEV_UART5
), 38400,
287 serial_hd(0), DEVICE_LITTLE_ENDIAN
);
290 object_property_set_link(OBJECT(&s
->i2c
), "dram", OBJECT(s
->dram_mr
),
292 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->i2c
), errp
)) {
295 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
), 0, sc
->memmap
[ASPEED_DEV_I2C
]);
296 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
), 0,
297 aspeed_soc_get_irq(s
, ASPEED_DEV_I2C
));
299 /* FMC, The number of CS is set at the board level */
300 object_property_set_link(OBJECT(&s
->fmc
), "dram", OBJECT(s
->dram_mr
),
302 if (!object_property_set_int(OBJECT(&s
->fmc
), "sdram-base",
303 sc
->memmap
[ASPEED_DEV_SDRAM
], errp
)) {
306 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->fmc
), errp
)) {
309 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 0, sc
->memmap
[ASPEED_DEV_FMC
]);
310 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fmc
), 1,
311 s
->fmc
.ctrl
->flash_window_base
);
312 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fmc
), 0,
313 aspeed_soc_get_irq(s
, ASPEED_DEV_FMC
));
316 for (i
= 0; i
< sc
->spis_num
; i
++) {
317 object_property_set_int(OBJECT(&s
->spi
[i
]), "num-cs", 1, &error_abort
);
318 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->spi
[i
]), errp
)) {
321 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 0,
322 sc
->memmap
[ASPEED_DEV_SPI1
+ i
]);
323 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->spi
[i
]), 1,
324 s
->spi
[i
].ctrl
->flash_window_base
);
328 for (i
= 0; i
< sc
->ehcis_num
; i
++) {
329 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ehci
[i
]), errp
)) {
332 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
333 sc
->memmap
[ASPEED_DEV_EHCI1
+ i
]);
334 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ehci
[i
]), 0,
335 aspeed_soc_get_irq(s
, ASPEED_DEV_EHCI1
+ i
));
338 /* SDMC - SDRAM Memory Controller */
339 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sdmc
), errp
)) {
342 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdmc
), 0, sc
->memmap
[ASPEED_DEV_SDMC
]);
345 for (i
= 0; i
< sc
->wdts_num
; i
++) {
346 AspeedWDTClass
*awc
= ASPEED_WDT_GET_CLASS(&s
->wdt
[i
]);
348 object_property_set_link(OBJECT(&s
->wdt
[i
]), "scu", OBJECT(&s
->scu
),
350 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->wdt
[i
]), errp
)) {
353 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->wdt
[i
]), 0,
354 sc
->memmap
[ASPEED_DEV_WDT
] + i
* awc
->offset
);
358 for (i
= 0; i
< sc
->macs_num
; i
++) {
359 object_property_set_bool(OBJECT(&s
->ftgmac100
[i
]), "aspeed", true,
361 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), errp
)) {
364 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
365 sc
->memmap
[ASPEED_DEV_ETH1
+ i
]);
366 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->ftgmac100
[i
]), 0,
367 aspeed_soc_get_irq(s
, ASPEED_DEV_ETH1
+ i
));
371 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->xdma
), errp
)) {
374 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->xdma
), 0,
375 sc
->memmap
[ASPEED_DEV_XDMA
]);
376 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->xdma
), 0,
377 aspeed_soc_get_irq(s
, ASPEED_DEV_XDMA
));
380 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->gpio
), errp
)) {
383 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
), 0, sc
->memmap
[ASPEED_DEV_GPIO
]);
384 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
), 0,
385 aspeed_soc_get_irq(s
, ASPEED_DEV_GPIO
));
388 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->sdhci
), errp
)) {
391 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->sdhci
), 0,
392 sc
->memmap
[ASPEED_DEV_SDHCI
]);
393 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->sdhci
), 0,
394 aspeed_soc_get_irq(s
, ASPEED_DEV_SDHCI
));
397 if (!sysbus_realize(SYS_BUS_DEVICE(&s
->lpc
), errp
)) {
400 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->lpc
), 0, sc
->memmap
[ASPEED_DEV_LPC
]);
402 /* Connect the LPC IRQ to the VIC */
403 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 0,
404 aspeed_soc_get_irq(s
, ASPEED_DEV_LPC
));
407 * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
408 * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
409 * contrast, on the AST2600, the subdevice IRQs are connected straight to
412 * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
413 * to the VIC is at offset 0.
415 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_1
,
416 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_1
));
418 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_2
,
419 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_2
));
421 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_3
,
422 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_3
));
424 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->lpc
), 1 + aspeed_lpc_kcs_4
,
425 qdev_get_gpio_in(DEVICE(&s
->lpc
), aspeed_lpc_kcs_4
));
427 static Property aspeed_soc_properties
[] = {
428 DEFINE_PROP_LINK("dram", AspeedSoCState
, dram_mr
, TYPE_MEMORY_REGION
,
430 DEFINE_PROP_END_OF_LIST(),
433 static void aspeed_soc_class_init(ObjectClass
*oc
, void *data
)
435 DeviceClass
*dc
= DEVICE_CLASS(oc
);
437 dc
->realize
= aspeed_soc_realize
;
438 /* Reason: Uses serial_hds and nd_table in realize() directly */
439 dc
->user_creatable
= false;
440 device_class_set_props(dc
, aspeed_soc_properties
);
443 static const TypeInfo aspeed_soc_type_info
= {
444 .name
= TYPE_ASPEED_SOC
,
445 .parent
= TYPE_DEVICE
,
446 .instance_size
= sizeof(AspeedSoCState
),
447 .class_size
= sizeof(AspeedSoCClass
),
448 .class_init
= aspeed_soc_class_init
,
452 static void aspeed_soc_ast2400_class_init(ObjectClass
*oc
, void *data
)
454 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
456 sc
->name
= "ast2400-a1";
457 sc
->cpu_type
= ARM_CPU_TYPE_NAME("arm926");
458 sc
->silicon_rev
= AST2400_A1_SILICON_REV
;
459 sc
->sram_size
= 0x8000;
464 sc
->irqmap
= aspeed_soc_ast2400_irqmap
;
465 sc
->memmap
= aspeed_soc_ast2400_memmap
;
469 static const TypeInfo aspeed_soc_ast2400_type_info
= {
470 .name
= "ast2400-a1",
471 .parent
= TYPE_ASPEED_SOC
,
472 .instance_init
= aspeed_soc_init
,
473 .instance_size
= sizeof(AspeedSoCState
),
474 .class_init
= aspeed_soc_ast2400_class_init
,
477 static void aspeed_soc_ast2500_class_init(ObjectClass
*oc
, void *data
)
479 AspeedSoCClass
*sc
= ASPEED_SOC_CLASS(oc
);
481 sc
->name
= "ast2500-a1";
482 sc
->cpu_type
= ARM_CPU_TYPE_NAME("arm1176");
483 sc
->silicon_rev
= AST2500_A1_SILICON_REV
;
484 sc
->sram_size
= 0x9000;
489 sc
->irqmap
= aspeed_soc_ast2500_irqmap
;
490 sc
->memmap
= aspeed_soc_ast2500_memmap
;
494 static const TypeInfo aspeed_soc_ast2500_type_info
= {
495 .name
= "ast2500-a1",
496 .parent
= TYPE_ASPEED_SOC
,
497 .instance_init
= aspeed_soc_init
,
498 .instance_size
= sizeof(AspeedSoCState
),
499 .class_init
= aspeed_soc_ast2500_class_init
,
501 static void aspeed_soc_register_types(void)
503 type_register_static(&aspeed_soc_type_info
);
504 type_register_static(&aspeed_soc_ast2400_type_info
);
505 type_register_static(&aspeed_soc_ast2500_type_info
);
508 type_init(aspeed_soc_register_types
)