s390x/sclp: clean up sclp masks
[qemu/ar7.git] / exec.c
blob604f03c535bc879afbb4ebe5536e2332f37ef585
1 /*
2 * Virtual page mapping
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
23 #include "cpu.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
26 #include "tcg.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
32 #endif
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
39 #include "qemu.h"
40 #else /* !CONFIG_USER_ONLY */
41 #include "hw/hw.h"
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <linux/falloc.h>
53 #endif
55 #endif
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "translate-all.h"
59 #include "sysemu/replay.h"
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
63 #include "exec/log.h"
65 #include "migration/vmstate.h"
67 #include "qemu/range.h"
68 #ifndef _WIN32
69 #include "qemu/mmap-alloc.h"
70 #endif
72 #include "monitor/monitor.h"
74 //#define DEBUG_SUBPAGE
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
80 RAMList ram_list = { .blocks = QLIST_HEAD_INITIALIZER(ram_list.blocks) };
82 static MemoryRegion *system_memory;
83 static MemoryRegion *system_io;
85 AddressSpace address_space_io;
86 AddressSpace address_space_memory;
88 MemoryRegion io_mem_rom, io_mem_notdirty;
89 static MemoryRegion io_mem_unassigned;
91 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
92 #define RAM_PREALLOC (1 << 0)
94 /* RAM is mmap-ed with MAP_SHARED */
95 #define RAM_SHARED (1 << 1)
97 /* Only a portion of RAM (used_length) is actually used, and migrated.
98 * This used_length size can change across reboots.
100 #define RAM_RESIZEABLE (1 << 2)
102 #endif
104 #ifdef TARGET_PAGE_BITS_VARY
105 int target_page_bits;
106 bool target_page_bits_decided;
107 #endif
109 struct CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus);
110 /* current CPU in the current thread. It is only valid inside
111 cpu_exec() */
112 __thread CPUState *current_cpu;
113 /* 0 = Do not count executed instructions.
114 1 = Precise instruction counting.
115 2 = Adaptive rate instruction counting. */
116 int use_icount;
118 uintptr_t qemu_host_page_size;
119 intptr_t qemu_host_page_mask;
121 bool set_preferred_target_page_bits(int bits)
123 /* The target page size is the lowest common denominator for all
124 * the CPUs in the system, so we can only make it smaller, never
125 * larger. And we can't make it smaller once we've committed to
126 * a particular size.
128 #ifdef TARGET_PAGE_BITS_VARY
129 assert(bits >= TARGET_PAGE_BITS_MIN);
130 if (target_page_bits == 0 || target_page_bits > bits) {
131 if (target_page_bits_decided) {
132 return false;
134 target_page_bits = bits;
136 #endif
137 return true;
140 #if !defined(CONFIG_USER_ONLY)
142 static void finalize_target_page_bits(void)
144 #ifdef TARGET_PAGE_BITS_VARY
145 if (target_page_bits == 0) {
146 target_page_bits = TARGET_PAGE_BITS_MIN;
148 target_page_bits_decided = true;
149 #endif
152 typedef struct PhysPageEntry PhysPageEntry;
154 struct PhysPageEntry {
155 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
156 uint32_t skip : 6;
157 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
158 uint32_t ptr : 26;
161 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
163 /* Size of the L2 (and L3, etc) page tables. */
164 #define ADDR_SPACE_BITS 64
166 #define P_L2_BITS 9
167 #define P_L2_SIZE (1 << P_L2_BITS)
169 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
171 typedef PhysPageEntry Node[P_L2_SIZE];
173 typedef struct PhysPageMap {
174 struct rcu_head rcu;
176 unsigned sections_nb;
177 unsigned sections_nb_alloc;
178 unsigned nodes_nb;
179 unsigned nodes_nb_alloc;
180 Node *nodes;
181 MemoryRegionSection *sections;
182 } PhysPageMap;
184 struct AddressSpaceDispatch {
185 MemoryRegionSection *mru_section;
186 /* This is a multi-level map on the physical address space.
187 * The bottom level has pointers to MemoryRegionSections.
189 PhysPageEntry phys_map;
190 PhysPageMap map;
193 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
194 typedef struct subpage_t {
195 MemoryRegion iomem;
196 FlatView *fv;
197 hwaddr base;
198 uint16_t sub_section[];
199 } subpage_t;
201 #define PHYS_SECTION_UNASSIGNED 0
202 #define PHYS_SECTION_NOTDIRTY 1
203 #define PHYS_SECTION_ROM 2
204 #define PHYS_SECTION_WATCH 3
206 static void io_mem_init(void);
207 static void memory_map_init(void);
208 static void tcg_commit(MemoryListener *listener);
210 static MemoryRegion io_mem_watch;
213 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
214 * @cpu: the CPU whose AddressSpace this is
215 * @as: the AddressSpace itself
216 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
217 * @tcg_as_listener: listener for tracking changes to the AddressSpace
219 struct CPUAddressSpace {
220 CPUState *cpu;
221 AddressSpace *as;
222 struct AddressSpaceDispatch *memory_dispatch;
223 MemoryListener tcg_as_listener;
226 struct DirtyBitmapSnapshot {
227 ram_addr_t start;
228 ram_addr_t end;
229 unsigned long dirty[];
232 #endif
234 #if !defined(CONFIG_USER_ONLY)
236 static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
238 static unsigned alloc_hint = 16;
239 if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
240 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint);
241 map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes);
242 map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc);
243 alloc_hint = map->nodes_nb_alloc;
247 static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf)
249 unsigned i;
250 uint32_t ret;
251 PhysPageEntry e;
252 PhysPageEntry *p;
254 ret = map->nodes_nb++;
255 p = map->nodes[ret];
256 assert(ret != PHYS_MAP_NODE_NIL);
257 assert(ret != map->nodes_nb_alloc);
259 e.skip = leaf ? 0 : 1;
260 e.ptr = leaf ? PHYS_SECTION_UNASSIGNED : PHYS_MAP_NODE_NIL;
261 for (i = 0; i < P_L2_SIZE; ++i) {
262 memcpy(&p[i], &e, sizeof(e));
264 return ret;
267 static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp,
268 hwaddr *index, hwaddr *nb, uint16_t leaf,
269 int level)
271 PhysPageEntry *p;
272 hwaddr step = (hwaddr)1 << (level * P_L2_BITS);
274 if (lp->skip && lp->ptr == PHYS_MAP_NODE_NIL) {
275 lp->ptr = phys_map_node_alloc(map, level == 0);
277 p = map->nodes[lp->ptr];
278 lp = &p[(*index >> (level * P_L2_BITS)) & (P_L2_SIZE - 1)];
280 while (*nb && lp < &p[P_L2_SIZE]) {
281 if ((*index & (step - 1)) == 0 && *nb >= step) {
282 lp->skip = 0;
283 lp->ptr = leaf;
284 *index += step;
285 *nb -= step;
286 } else {
287 phys_page_set_level(map, lp, index, nb, leaf, level - 1);
289 ++lp;
293 static void phys_page_set(AddressSpaceDispatch *d,
294 hwaddr index, hwaddr nb,
295 uint16_t leaf)
297 /* Wildly overreserve - it doesn't matter much. */
298 phys_map_node_reserve(&d->map, 3 * P_L2_LEVELS);
300 phys_page_set_level(&d->map, &d->phys_map, &index, &nb, leaf, P_L2_LEVELS - 1);
303 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
304 * and update our entry so we can skip it and go directly to the destination.
306 static void phys_page_compact(PhysPageEntry *lp, Node *nodes)
308 unsigned valid_ptr = P_L2_SIZE;
309 int valid = 0;
310 PhysPageEntry *p;
311 int i;
313 if (lp->ptr == PHYS_MAP_NODE_NIL) {
314 return;
317 p = nodes[lp->ptr];
318 for (i = 0; i < P_L2_SIZE; i++) {
319 if (p[i].ptr == PHYS_MAP_NODE_NIL) {
320 continue;
323 valid_ptr = i;
324 valid++;
325 if (p[i].skip) {
326 phys_page_compact(&p[i], nodes);
330 /* We can only compress if there's only one child. */
331 if (valid != 1) {
332 return;
335 assert(valid_ptr < P_L2_SIZE);
337 /* Don't compress if it won't fit in the # of bits we have. */
338 if (lp->skip + p[valid_ptr].skip >= (1 << 3)) {
339 return;
342 lp->ptr = p[valid_ptr].ptr;
343 if (!p[valid_ptr].skip) {
344 /* If our only child is a leaf, make this a leaf. */
345 /* By design, we should have made this node a leaf to begin with so we
346 * should never reach here.
347 * But since it's so simple to handle this, let's do it just in case we
348 * change this rule.
350 lp->skip = 0;
351 } else {
352 lp->skip += p[valid_ptr].skip;
356 void address_space_dispatch_compact(AddressSpaceDispatch *d)
358 if (d->phys_map.skip) {
359 phys_page_compact(&d->phys_map, d->map.nodes);
363 static inline bool section_covers_addr(const MemoryRegionSection *section,
364 hwaddr addr)
366 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
367 * the section must cover the entire address space.
369 return int128_gethi(section->size) ||
370 range_covers_byte(section->offset_within_address_space,
371 int128_getlo(section->size), addr);
374 static MemoryRegionSection *phys_page_find(AddressSpaceDispatch *d, hwaddr addr)
376 PhysPageEntry lp = d->phys_map, *p;
377 Node *nodes = d->map.nodes;
378 MemoryRegionSection *sections = d->map.sections;
379 hwaddr index = addr >> TARGET_PAGE_BITS;
380 int i;
382 for (i = P_L2_LEVELS; lp.skip && (i -= lp.skip) >= 0;) {
383 if (lp.ptr == PHYS_MAP_NODE_NIL) {
384 return &sections[PHYS_SECTION_UNASSIGNED];
386 p = nodes[lp.ptr];
387 lp = p[(index >> (i * P_L2_BITS)) & (P_L2_SIZE - 1)];
390 if (section_covers_addr(&sections[lp.ptr], addr)) {
391 return &sections[lp.ptr];
392 } else {
393 return &sections[PHYS_SECTION_UNASSIGNED];
397 bool memory_region_is_unassigned(MemoryRegion *mr)
399 return mr != &io_mem_rom && mr != &io_mem_notdirty && !mr->rom_device
400 && mr != &io_mem_watch;
403 /* Called from RCU critical section */
404 static MemoryRegionSection *address_space_lookup_region(AddressSpaceDispatch *d,
405 hwaddr addr,
406 bool resolve_subpage)
408 MemoryRegionSection *section = atomic_read(&d->mru_section);
409 subpage_t *subpage;
411 if (!section || section == &d->map.sections[PHYS_SECTION_UNASSIGNED] ||
412 !section_covers_addr(section, addr)) {
413 section = phys_page_find(d, addr);
414 atomic_set(&d->mru_section, section);
416 if (resolve_subpage && section->mr->subpage) {
417 subpage = container_of(section->mr, subpage_t, iomem);
418 section = &d->map.sections[subpage->sub_section[SUBPAGE_IDX(addr)]];
420 return section;
423 /* Called from RCU critical section */
424 static MemoryRegionSection *
425 address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *xlat,
426 hwaddr *plen, bool resolve_subpage)
428 MemoryRegionSection *section;
429 MemoryRegion *mr;
430 Int128 diff;
432 section = address_space_lookup_region(d, addr, resolve_subpage);
433 /* Compute offset within MemoryRegionSection */
434 addr -= section->offset_within_address_space;
436 /* Compute offset within MemoryRegion */
437 *xlat = addr + section->offset_within_region;
439 mr = section->mr;
441 /* MMIO registers can be expected to perform full-width accesses based only
442 * on their address, without considering adjacent registers that could
443 * decode to completely different MemoryRegions. When such registers
444 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
445 * regions overlap wildly. For this reason we cannot clamp the accesses
446 * here.
448 * If the length is small (as is the case for address_space_ldl/stl),
449 * everything works fine. If the incoming length is large, however,
450 * the caller really has to do the clamping through memory_access_size.
452 if (memory_region_is_ram(mr)) {
453 diff = int128_sub(section->size, int128_make64(addr));
454 *plen = int128_get64(int128_min(diff, int128_make64(*plen)));
456 return section;
460 * flatview_do_translate - translate an address in FlatView
462 * @fv: the flat view that we want to translate on
463 * @addr: the address to be translated in above address space
464 * @xlat: the translated address offset within memory region. It
465 * cannot be @NULL.
466 * @plen_out: valid read/write length of the translated address. It
467 * can be @NULL when we don't care about it.
468 * @page_mask_out: page mask for the translated address. This
469 * should only be meaningful for IOMMU translated
470 * addresses, since there may be huge pages that this bit
471 * would tell. It can be @NULL if we don't care about it.
472 * @is_write: whether the translation operation is for write
473 * @is_mmio: whether this can be MMIO, set true if it can
475 * This function is called from RCU critical section
477 static MemoryRegionSection flatview_do_translate(FlatView *fv,
478 hwaddr addr,
479 hwaddr *xlat,
480 hwaddr *plen_out,
481 hwaddr *page_mask_out,
482 bool is_write,
483 bool is_mmio,
484 AddressSpace **target_as)
486 IOMMUTLBEntry iotlb;
487 MemoryRegionSection *section;
488 IOMMUMemoryRegion *iommu_mr;
489 IOMMUMemoryRegionClass *imrc;
490 hwaddr page_mask = (hwaddr)(-1);
491 hwaddr plen = (hwaddr)(-1);
493 if (plen_out) {
494 plen = *plen_out;
497 for (;;) {
498 section = address_space_translate_internal(
499 flatview_to_dispatch(fv), addr, &addr,
500 &plen, is_mmio);
502 iommu_mr = memory_region_get_iommu(section->mr);
503 if (!iommu_mr) {
504 break;
506 imrc = memory_region_get_iommu_class_nocheck(iommu_mr);
508 iotlb = imrc->translate(iommu_mr, addr, is_write ?
509 IOMMU_WO : IOMMU_RO);
510 addr = ((iotlb.translated_addr & ~iotlb.addr_mask)
511 | (addr & iotlb.addr_mask));
512 page_mask &= iotlb.addr_mask;
513 plen = MIN(plen, (addr | iotlb.addr_mask) - addr + 1);
514 if (!(iotlb.perm & (1 << is_write))) {
515 goto translate_fail;
518 fv = address_space_to_flatview(iotlb.target_as);
519 *target_as = iotlb.target_as;
522 *xlat = addr;
524 if (page_mask == (hwaddr)(-1)) {
525 /* Not behind an IOMMU, use default page size. */
526 page_mask = ~TARGET_PAGE_MASK;
529 if (page_mask_out) {
530 *page_mask_out = page_mask;
533 if (plen_out) {
534 *plen_out = plen;
537 return *section;
539 translate_fail:
540 return (MemoryRegionSection) { .mr = &io_mem_unassigned };
543 /* Called from RCU critical section */
544 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
545 bool is_write)
547 MemoryRegionSection section;
548 hwaddr xlat, page_mask;
551 * This can never be MMIO, and we don't really care about plen,
552 * but page mask.
554 section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
555 NULL, &page_mask, is_write, false, &as);
557 /* Illegal translation */
558 if (section.mr == &io_mem_unassigned) {
559 goto iotlb_fail;
562 /* Convert memory region offset into address space offset */
563 xlat += section.offset_within_address_space -
564 section.offset_within_region;
566 return (IOMMUTLBEntry) {
567 .target_as = as,
568 .iova = addr & ~page_mask,
569 .translated_addr = xlat & ~page_mask,
570 .addr_mask = page_mask,
571 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
572 .perm = IOMMU_RW,
575 iotlb_fail:
576 return (IOMMUTLBEntry) {0};
579 /* Called from RCU critical section */
580 MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
581 hwaddr *plen, bool is_write)
583 MemoryRegion *mr;
584 MemoryRegionSection section;
585 AddressSpace *as = NULL;
587 /* This can be MMIO, so setup MMIO bit. */
588 section = flatview_do_translate(fv, addr, xlat, plen, NULL,
589 is_write, true, &as);
590 mr = section.mr;
592 if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
593 hwaddr page = ((addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE) - addr;
594 *plen = MIN(page, *plen);
597 return mr;
600 /* Called from RCU critical section */
601 MemoryRegionSection *
602 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
603 hwaddr *xlat, hwaddr *plen)
605 MemoryRegionSection *section;
606 AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch);
608 section = address_space_translate_internal(d, addr, xlat, plen, false);
610 assert(!memory_region_is_iommu(section->mr));
611 return section;
613 #endif
615 #if !defined(CONFIG_USER_ONLY)
617 static int cpu_common_post_load(void *opaque, int version_id)
619 CPUState *cpu = opaque;
621 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
622 version_id is increased. */
623 cpu->interrupt_request &= ~0x01;
624 tlb_flush(cpu);
626 /* loadvm has just updated the content of RAM, bypassing the
627 * usual mechanisms that ensure we flush TBs for writes to
628 * memory we've translated code from. So we must flush all TBs,
629 * which will now be stale.
631 tb_flush(cpu);
633 return 0;
636 static int cpu_common_pre_load(void *opaque)
638 CPUState *cpu = opaque;
640 cpu->exception_index = -1;
642 return 0;
645 static bool cpu_common_exception_index_needed(void *opaque)
647 CPUState *cpu = opaque;
649 return tcg_enabled() && cpu->exception_index != -1;
652 static const VMStateDescription vmstate_cpu_common_exception_index = {
653 .name = "cpu_common/exception_index",
654 .version_id = 1,
655 .minimum_version_id = 1,
656 .needed = cpu_common_exception_index_needed,
657 .fields = (VMStateField[]) {
658 VMSTATE_INT32(exception_index, CPUState),
659 VMSTATE_END_OF_LIST()
663 static bool cpu_common_crash_occurred_needed(void *opaque)
665 CPUState *cpu = opaque;
667 return cpu->crash_occurred;
670 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
671 .name = "cpu_common/crash_occurred",
672 .version_id = 1,
673 .minimum_version_id = 1,
674 .needed = cpu_common_crash_occurred_needed,
675 .fields = (VMStateField[]) {
676 VMSTATE_BOOL(crash_occurred, CPUState),
677 VMSTATE_END_OF_LIST()
681 const VMStateDescription vmstate_cpu_common = {
682 .name = "cpu_common",
683 .version_id = 1,
684 .minimum_version_id = 1,
685 .pre_load = cpu_common_pre_load,
686 .post_load = cpu_common_post_load,
687 .fields = (VMStateField[]) {
688 VMSTATE_UINT32(halted, CPUState),
689 VMSTATE_UINT32(interrupt_request, CPUState),
690 VMSTATE_END_OF_LIST()
692 .subsections = (const VMStateDescription*[]) {
693 &vmstate_cpu_common_exception_index,
694 &vmstate_cpu_common_crash_occurred,
695 NULL
699 #endif
701 CPUState *qemu_get_cpu(int index)
703 CPUState *cpu;
705 CPU_FOREACH(cpu) {
706 if (cpu->cpu_index == index) {
707 return cpu;
711 return NULL;
714 #if !defined(CONFIG_USER_ONLY)
715 void cpu_address_space_init(CPUState *cpu, int asidx,
716 const char *prefix, MemoryRegion *mr)
718 CPUAddressSpace *newas;
719 AddressSpace *as = g_new0(AddressSpace, 1);
720 char *as_name;
722 assert(mr);
723 as_name = g_strdup_printf("%s-%d", prefix, cpu->cpu_index);
724 address_space_init(as, mr, as_name);
725 g_free(as_name);
727 /* Target code should have set num_ases before calling us */
728 assert(asidx < cpu->num_ases);
730 if (asidx == 0) {
731 /* address space 0 gets the convenience alias */
732 cpu->as = as;
735 /* KVM cannot currently support multiple address spaces. */
736 assert(asidx == 0 || !kvm_enabled());
738 if (!cpu->cpu_ases) {
739 cpu->cpu_ases = g_new0(CPUAddressSpace, cpu->num_ases);
742 newas = &cpu->cpu_ases[asidx];
743 newas->cpu = cpu;
744 newas->as = as;
745 if (tcg_enabled()) {
746 newas->tcg_as_listener.commit = tcg_commit;
747 memory_listener_register(&newas->tcg_as_listener, as);
751 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx)
753 /* Return the AddressSpace corresponding to the specified index */
754 return cpu->cpu_ases[asidx].as;
756 #endif
758 void cpu_exec_unrealizefn(CPUState *cpu)
760 CPUClass *cc = CPU_GET_CLASS(cpu);
762 cpu_list_remove(cpu);
764 if (cc->vmsd != NULL) {
765 vmstate_unregister(NULL, cc->vmsd, cpu);
767 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
768 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
772 Property cpu_common_props[] = {
773 #ifndef CONFIG_USER_ONLY
774 /* Create a memory property for softmmu CPU object,
775 * so users can wire up its memory. (This can't go in qom/cpu.c
776 * because that file is compiled only once for both user-mode
777 * and system builds.) The default if no link is set up is to use
778 * the system address space.
780 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
781 MemoryRegion *),
782 #endif
783 DEFINE_PROP_END_OF_LIST(),
786 void cpu_exec_initfn(CPUState *cpu)
788 cpu->as = NULL;
789 cpu->num_ases = 0;
791 #ifndef CONFIG_USER_ONLY
792 cpu->thread_id = qemu_get_thread_id();
793 cpu->memory = system_memory;
794 object_ref(OBJECT(cpu->memory));
795 #endif
798 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
800 CPUClass *cc = CPU_GET_CLASS(cpu);
801 static bool tcg_target_initialized;
803 cpu_list_add(cpu);
805 if (tcg_enabled() && !tcg_target_initialized) {
806 tcg_target_initialized = true;
807 cc->tcg_initialize();
810 #ifndef CONFIG_USER_ONLY
811 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
812 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
814 if (cc->vmsd != NULL) {
815 vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
817 #endif
820 #if defined(CONFIG_USER_ONLY)
821 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
823 mmap_lock();
824 tb_lock();
825 tb_invalidate_phys_page_range(pc, pc + 1, 0);
826 tb_unlock();
827 mmap_unlock();
829 #else
830 static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
832 MemTxAttrs attrs;
833 hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
834 int asidx = cpu_asidx_from_attrs(cpu, attrs);
835 if (phys != -1) {
836 /* Locks grabbed by tb_invalidate_phys_addr */
837 tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
838 phys | (pc & ~TARGET_PAGE_MASK));
841 #endif
843 #if defined(CONFIG_USER_ONLY)
844 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
849 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
850 int flags)
852 return -ENOSYS;
855 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
859 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
860 int flags, CPUWatchpoint **watchpoint)
862 return -ENOSYS;
864 #else
865 /* Add a watchpoint. */
866 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
867 int flags, CPUWatchpoint **watchpoint)
869 CPUWatchpoint *wp;
871 /* forbid ranges which are empty or run off the end of the address space */
872 if (len == 0 || (addr + len - 1) < addr) {
873 error_report("tried to set invalid watchpoint at %"
874 VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
875 return -EINVAL;
877 wp = g_malloc(sizeof(*wp));
879 wp->vaddr = addr;
880 wp->len = len;
881 wp->flags = flags;
883 /* keep all GDB-injected watchpoints in front */
884 if (flags & BP_GDB) {
885 QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
886 } else {
887 QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
890 tlb_flush_page(cpu, addr);
892 if (watchpoint)
893 *watchpoint = wp;
894 return 0;
897 /* Remove a specific watchpoint. */
898 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
899 int flags)
901 CPUWatchpoint *wp;
903 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
904 if (addr == wp->vaddr && len == wp->len
905 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
906 cpu_watchpoint_remove_by_ref(cpu, wp);
907 return 0;
910 return -ENOENT;
913 /* Remove a specific watchpoint by reference. */
914 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
916 QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
918 tlb_flush_page(cpu, watchpoint->vaddr);
920 g_free(watchpoint);
923 /* Remove all matching watchpoints. */
924 void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
926 CPUWatchpoint *wp, *next;
928 QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
929 if (wp->flags & mask) {
930 cpu_watchpoint_remove_by_ref(cpu, wp);
935 /* Return true if this watchpoint address matches the specified
936 * access (ie the address range covered by the watchpoint overlaps
937 * partially or completely with the address range covered by the
938 * access).
940 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
941 vaddr addr,
942 vaddr len)
944 /* We know the lengths are non-zero, but a little caution is
945 * required to avoid errors in the case where the range ends
946 * exactly at the top of the address space and so addr + len
947 * wraps round to zero.
949 vaddr wpend = wp->vaddr + wp->len - 1;
950 vaddr addrend = addr + len - 1;
952 return !(addr > wpend || wp->vaddr > addrend);
955 #endif
957 /* Add a breakpoint. */
958 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
959 CPUBreakpoint **breakpoint)
961 CPUBreakpoint *bp;
963 bp = g_malloc(sizeof(*bp));
965 bp->pc = pc;
966 bp->flags = flags;
968 /* keep all GDB-injected breakpoints in front */
969 if (flags & BP_GDB) {
970 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
971 } else {
972 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
975 breakpoint_invalidate(cpu, pc);
977 if (breakpoint) {
978 *breakpoint = bp;
980 return 0;
983 /* Remove a specific breakpoint. */
984 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
986 CPUBreakpoint *bp;
988 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
989 if (bp->pc == pc && bp->flags == flags) {
990 cpu_breakpoint_remove_by_ref(cpu, bp);
991 return 0;
994 return -ENOENT;
997 /* Remove a specific breakpoint by reference. */
998 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
1000 QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
1002 breakpoint_invalidate(cpu, breakpoint->pc);
1004 g_free(breakpoint);
1007 /* Remove all matching breakpoints. */
1008 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
1010 CPUBreakpoint *bp, *next;
1012 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
1013 if (bp->flags & mask) {
1014 cpu_breakpoint_remove_by_ref(cpu, bp);
1019 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1020 CPU loop after each instruction */
1021 void cpu_single_step(CPUState *cpu, int enabled)
1023 if (cpu->singlestep_enabled != enabled) {
1024 cpu->singlestep_enabled = enabled;
1025 if (kvm_enabled()) {
1026 kvm_update_guest_debug(cpu, 0);
1027 } else {
1028 /* must flush all the translated code to avoid inconsistencies */
1029 /* XXX: only flush what is necessary */
1030 tb_flush(cpu);
1035 void cpu_abort(CPUState *cpu, const char *fmt, ...)
1037 va_list ap;
1038 va_list ap2;
1040 va_start(ap, fmt);
1041 va_copy(ap2, ap);
1042 fprintf(stderr, "qemu: fatal: ");
1043 vfprintf(stderr, fmt, ap);
1044 fprintf(stderr, "\n");
1045 cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1046 if (qemu_log_separate()) {
1047 qemu_log_lock();
1048 qemu_log("qemu: fatal: ");
1049 qemu_log_vprintf(fmt, ap2);
1050 qemu_log("\n");
1051 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1052 qemu_log_flush();
1053 qemu_log_unlock();
1054 qemu_log_close();
1056 va_end(ap2);
1057 va_end(ap);
1058 replay_finish();
1059 #if defined(CONFIG_USER_ONLY)
1061 struct sigaction act;
1062 sigfillset(&act.sa_mask);
1063 act.sa_handler = SIG_DFL;
1064 sigaction(SIGABRT, &act, NULL);
1066 #endif
1067 abort();
1070 #if !defined(CONFIG_USER_ONLY)
1071 /* Called from RCU critical section */
1072 static RAMBlock *qemu_get_ram_block(ram_addr_t addr)
1074 RAMBlock *block;
1076 block = atomic_rcu_read(&ram_list.mru_block);
1077 if (block && addr - block->offset < block->max_length) {
1078 return block;
1080 RAMBLOCK_FOREACH(block) {
1081 if (addr - block->offset < block->max_length) {
1082 goto found;
1086 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
1087 abort();
1089 found:
1090 /* It is safe to write mru_block outside the iothread lock. This
1091 * is what happens:
1093 * mru_block = xxx
1094 * rcu_read_unlock()
1095 * xxx removed from list
1096 * rcu_read_lock()
1097 * read mru_block
1098 * mru_block = NULL;
1099 * call_rcu(reclaim_ramblock, xxx);
1100 * rcu_read_unlock()
1102 * atomic_rcu_set is not needed here. The block was already published
1103 * when it was placed into the list. Here we're just making an extra
1104 * copy of the pointer.
1106 ram_list.mru_block = block;
1107 return block;
1110 static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
1112 CPUState *cpu;
1113 ram_addr_t start1;
1114 RAMBlock *block;
1115 ram_addr_t end;
1117 end = TARGET_PAGE_ALIGN(start + length);
1118 start &= TARGET_PAGE_MASK;
1120 rcu_read_lock();
1121 block = qemu_get_ram_block(start);
1122 assert(block == qemu_get_ram_block(end - 1));
1123 start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
1124 CPU_FOREACH(cpu) {
1125 tlb_reset_dirty(cpu, start1, length);
1127 rcu_read_unlock();
1130 /* Note: start and end must be within the same ram block. */
1131 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start,
1132 ram_addr_t length,
1133 unsigned client)
1135 DirtyMemoryBlocks *blocks;
1136 unsigned long end, page;
1137 bool dirty = false;
1139 if (length == 0) {
1140 return false;
1143 end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS;
1144 page = start >> TARGET_PAGE_BITS;
1146 rcu_read_lock();
1148 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1150 while (page < end) {
1151 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1152 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1153 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1155 dirty |= bitmap_test_and_clear_atomic(blocks->blocks[idx],
1156 offset, num);
1157 page += num;
1160 rcu_read_unlock();
1162 if (dirty && tcg_enabled()) {
1163 tlb_reset_dirty_range_all(start, length);
1166 return dirty;
1169 DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty
1170 (ram_addr_t start, ram_addr_t length, unsigned client)
1172 DirtyMemoryBlocks *blocks;
1173 unsigned long align = 1UL << (TARGET_PAGE_BITS + BITS_PER_LEVEL);
1174 ram_addr_t first = QEMU_ALIGN_DOWN(start, align);
1175 ram_addr_t last = QEMU_ALIGN_UP(start + length, align);
1176 DirtyBitmapSnapshot *snap;
1177 unsigned long page, end, dest;
1179 snap = g_malloc0(sizeof(*snap) +
1180 ((last - first) >> (TARGET_PAGE_BITS + 3)));
1181 snap->start = first;
1182 snap->end = last;
1184 page = first >> TARGET_PAGE_BITS;
1185 end = last >> TARGET_PAGE_BITS;
1186 dest = 0;
1188 rcu_read_lock();
1190 blocks = atomic_rcu_read(&ram_list.dirty_memory[client]);
1192 while (page < end) {
1193 unsigned long idx = page / DIRTY_MEMORY_BLOCK_SIZE;
1194 unsigned long offset = page % DIRTY_MEMORY_BLOCK_SIZE;
1195 unsigned long num = MIN(end - page, DIRTY_MEMORY_BLOCK_SIZE - offset);
1197 assert(QEMU_IS_ALIGNED(offset, (1 << BITS_PER_LEVEL)));
1198 assert(QEMU_IS_ALIGNED(num, (1 << BITS_PER_LEVEL)));
1199 offset >>= BITS_PER_LEVEL;
1201 bitmap_copy_and_clear_atomic(snap->dirty + dest,
1202 blocks->blocks[idx] + offset,
1203 num);
1204 page += num;
1205 dest += num >> BITS_PER_LEVEL;
1208 rcu_read_unlock();
1210 if (tcg_enabled()) {
1211 tlb_reset_dirty_range_all(start, length);
1214 return snap;
1217 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap,
1218 ram_addr_t start,
1219 ram_addr_t length)
1221 unsigned long page, end;
1223 assert(start >= snap->start);
1224 assert(start + length <= snap->end);
1226 end = TARGET_PAGE_ALIGN(start + length - snap->start) >> TARGET_PAGE_BITS;
1227 page = (start - snap->start) >> TARGET_PAGE_BITS;
1229 while (page < end) {
1230 if (test_bit(page, snap->dirty)) {
1231 return true;
1233 page++;
1235 return false;
1238 /* Called from RCU critical section */
1239 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
1240 MemoryRegionSection *section,
1241 target_ulong vaddr,
1242 hwaddr paddr, hwaddr xlat,
1243 int prot,
1244 target_ulong *address)
1246 hwaddr iotlb;
1247 CPUWatchpoint *wp;
1249 if (memory_region_is_ram(section->mr)) {
1250 /* Normal RAM. */
1251 iotlb = memory_region_get_ram_addr(section->mr) + xlat;
1252 if (!section->readonly) {
1253 iotlb |= PHYS_SECTION_NOTDIRTY;
1254 } else {
1255 iotlb |= PHYS_SECTION_ROM;
1257 } else {
1258 AddressSpaceDispatch *d;
1260 d = flatview_to_dispatch(section->fv);
1261 iotlb = section - d->map.sections;
1262 iotlb += xlat;
1265 /* Make accesses to pages with watchpoints go via the
1266 watchpoint trap routines. */
1267 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1268 if (cpu_watchpoint_address_matches(wp, vaddr, TARGET_PAGE_SIZE)) {
1269 /* Avoid trapping reads of pages with a write breakpoint. */
1270 if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
1271 iotlb = PHYS_SECTION_WATCH + paddr;
1272 *address |= TLB_MMIO;
1273 break;
1278 return iotlb;
1280 #endif /* defined(CONFIG_USER_ONLY) */
1282 #if !defined(CONFIG_USER_ONLY)
1284 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1285 uint16_t section);
1286 static subpage_t *subpage_init(FlatView *fv, hwaddr base);
1288 static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) =
1289 qemu_anon_ram_alloc;
1292 * Set a custom physical guest memory alloator.
1293 * Accelerators with unusual needs may need this. Hopefully, we can
1294 * get rid of it eventually.
1296 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align, bool shared))
1298 phys_mem_alloc = alloc;
1301 static uint16_t phys_section_add(PhysPageMap *map,
1302 MemoryRegionSection *section)
1304 /* The physical section number is ORed with a page-aligned
1305 * pointer to produce the iotlb entries. Thus it should
1306 * never overflow into the page-aligned value.
1308 assert(map->sections_nb < TARGET_PAGE_SIZE);
1310 if (map->sections_nb == map->sections_nb_alloc) {
1311 map->sections_nb_alloc = MAX(map->sections_nb_alloc * 2, 16);
1312 map->sections = g_renew(MemoryRegionSection, map->sections,
1313 map->sections_nb_alloc);
1315 map->sections[map->sections_nb] = *section;
1316 memory_region_ref(section->mr);
1317 return map->sections_nb++;
1320 static void phys_section_destroy(MemoryRegion *mr)
1322 bool have_sub_page = mr->subpage;
1324 memory_region_unref(mr);
1326 if (have_sub_page) {
1327 subpage_t *subpage = container_of(mr, subpage_t, iomem);
1328 object_unref(OBJECT(&subpage->iomem));
1329 g_free(subpage);
1333 static void phys_sections_free(PhysPageMap *map)
1335 while (map->sections_nb > 0) {
1336 MemoryRegionSection *section = &map->sections[--map->sections_nb];
1337 phys_section_destroy(section->mr);
1339 g_free(map->sections);
1340 g_free(map->nodes);
1343 static void register_subpage(FlatView *fv, MemoryRegionSection *section)
1345 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1346 subpage_t *subpage;
1347 hwaddr base = section->offset_within_address_space
1348 & TARGET_PAGE_MASK;
1349 MemoryRegionSection *existing = phys_page_find(d, base);
1350 MemoryRegionSection subsection = {
1351 .offset_within_address_space = base,
1352 .size = int128_make64(TARGET_PAGE_SIZE),
1354 hwaddr start, end;
1356 assert(existing->mr->subpage || existing->mr == &io_mem_unassigned);
1358 if (!(existing->mr->subpage)) {
1359 subpage = subpage_init(fv, base);
1360 subsection.fv = fv;
1361 subsection.mr = &subpage->iomem;
1362 phys_page_set(d, base >> TARGET_PAGE_BITS, 1,
1363 phys_section_add(&d->map, &subsection));
1364 } else {
1365 subpage = container_of(existing->mr, subpage_t, iomem);
1367 start = section->offset_within_address_space & ~TARGET_PAGE_MASK;
1368 end = start + int128_get64(section->size) - 1;
1369 subpage_register(subpage, start, end,
1370 phys_section_add(&d->map, section));
1374 static void register_multipage(FlatView *fv,
1375 MemoryRegionSection *section)
1377 AddressSpaceDispatch *d = flatview_to_dispatch(fv);
1378 hwaddr start_addr = section->offset_within_address_space;
1379 uint16_t section_index = phys_section_add(&d->map, section);
1380 uint64_t num_pages = int128_get64(int128_rshift(section->size,
1381 TARGET_PAGE_BITS));
1383 assert(num_pages);
1384 phys_page_set(d, start_addr >> TARGET_PAGE_BITS, num_pages, section_index);
1387 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section)
1389 MemoryRegionSection now = *section, remain = *section;
1390 Int128 page_size = int128_make64(TARGET_PAGE_SIZE);
1392 if (now.offset_within_address_space & ~TARGET_PAGE_MASK) {
1393 uint64_t left = TARGET_PAGE_ALIGN(now.offset_within_address_space)
1394 - now.offset_within_address_space;
1396 now.size = int128_min(int128_make64(left), now.size);
1397 register_subpage(fv, &now);
1398 } else {
1399 now.size = int128_zero();
1401 while (int128_ne(remain.size, now.size)) {
1402 remain.size = int128_sub(remain.size, now.size);
1403 remain.offset_within_address_space += int128_get64(now.size);
1404 remain.offset_within_region += int128_get64(now.size);
1405 now = remain;
1406 if (int128_lt(remain.size, page_size)) {
1407 register_subpage(fv, &now);
1408 } else if (remain.offset_within_address_space & ~TARGET_PAGE_MASK) {
1409 now.size = page_size;
1410 register_subpage(fv, &now);
1411 } else {
1412 now.size = int128_and(now.size, int128_neg(page_size));
1413 register_multipage(fv, &now);
1418 void qemu_flush_coalesced_mmio_buffer(void)
1420 if (kvm_enabled())
1421 kvm_flush_coalesced_mmio_buffer();
1424 void qemu_mutex_lock_ramlist(void)
1426 qemu_mutex_lock(&ram_list.mutex);
1429 void qemu_mutex_unlock_ramlist(void)
1431 qemu_mutex_unlock(&ram_list.mutex);
1434 void ram_block_dump(Monitor *mon)
1436 RAMBlock *block;
1437 char *psize;
1439 rcu_read_lock();
1440 monitor_printf(mon, "%24s %8s %18s %18s %18s\n",
1441 "Block Name", "PSize", "Offset", "Used", "Total");
1442 RAMBLOCK_FOREACH(block) {
1443 psize = size_to_str(block->page_size);
1444 monitor_printf(mon, "%24s %8s 0x%016" PRIx64 " 0x%016" PRIx64
1445 " 0x%016" PRIx64 "\n", block->idstr, psize,
1446 (uint64_t)block->offset,
1447 (uint64_t)block->used_length,
1448 (uint64_t)block->max_length);
1449 g_free(psize);
1451 rcu_read_unlock();
1454 #ifdef __linux__
1456 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1457 * may or may not name the same files / on the same filesystem now as
1458 * when we actually open and map them. Iterate over the file
1459 * descriptors instead, and use qemu_fd_getpagesize().
1461 static int find_max_supported_pagesize(Object *obj, void *opaque)
1463 char *mem_path;
1464 long *hpsize_min = opaque;
1466 if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
1467 mem_path = object_property_get_str(obj, "mem-path", NULL);
1468 if (mem_path) {
1469 long hpsize = qemu_mempath_getpagesize(mem_path);
1470 if (hpsize < *hpsize_min) {
1471 *hpsize_min = hpsize;
1473 } else {
1474 *hpsize_min = getpagesize();
1478 return 0;
1481 long qemu_getrampagesize(void)
1483 long hpsize = LONG_MAX;
1484 long mainrampagesize;
1485 Object *memdev_root;
1487 if (mem_path) {
1488 mainrampagesize = qemu_mempath_getpagesize(mem_path);
1489 } else {
1490 mainrampagesize = getpagesize();
1493 /* it's possible we have memory-backend objects with
1494 * hugepage-backed RAM. these may get mapped into system
1495 * address space via -numa parameters or memory hotplug
1496 * hooks. we want to take these into account, but we
1497 * also want to make sure these supported hugepage
1498 * sizes are applicable across the entire range of memory
1499 * we may boot from, so we take the min across all
1500 * backends, and assume normal pages in cases where a
1501 * backend isn't backed by hugepages.
1503 memdev_root = object_resolve_path("/objects", NULL);
1504 if (memdev_root) {
1505 object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize);
1507 if (hpsize == LONG_MAX) {
1508 /* No additional memory regions found ==> Report main RAM page size */
1509 return mainrampagesize;
1512 /* If NUMA is disabled or the NUMA nodes are not backed with a
1513 * memory-backend, then there is at least one node using "normal" RAM,
1514 * so if its page size is smaller we have got to report that size instead.
1516 if (hpsize > mainrampagesize &&
1517 (nb_numa_nodes == 0 || numa_info[0].node_memdev == NULL)) {
1518 static bool warned;
1519 if (!warned) {
1520 error_report("Huge page support disabled (n/a for main memory).");
1521 warned = true;
1523 return mainrampagesize;
1526 return hpsize;
1528 #else
1529 long qemu_getrampagesize(void)
1531 return getpagesize();
1533 #endif
1535 #ifdef __linux__
1536 static int64_t get_file_size(int fd)
1538 int64_t size = lseek(fd, 0, SEEK_END);
1539 if (size < 0) {
1540 return -errno;
1542 return size;
1545 static int file_ram_open(const char *path,
1546 const char *region_name,
1547 bool *created,
1548 Error **errp)
1550 char *filename;
1551 char *sanitized_name;
1552 char *c;
1553 int fd = -1;
1555 *created = false;
1556 for (;;) {
1557 fd = open(path, O_RDWR);
1558 if (fd >= 0) {
1559 /* @path names an existing file, use it */
1560 break;
1562 if (errno == ENOENT) {
1563 /* @path names a file that doesn't exist, create it */
1564 fd = open(path, O_RDWR | O_CREAT | O_EXCL, 0644);
1565 if (fd >= 0) {
1566 *created = true;
1567 break;
1569 } else if (errno == EISDIR) {
1570 /* @path names a directory, create a file there */
1571 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1572 sanitized_name = g_strdup(region_name);
1573 for (c = sanitized_name; *c != '\0'; c++) {
1574 if (*c == '/') {
1575 *c = '_';
1579 filename = g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path,
1580 sanitized_name);
1581 g_free(sanitized_name);
1583 fd = mkstemp(filename);
1584 if (fd >= 0) {
1585 unlink(filename);
1586 g_free(filename);
1587 break;
1589 g_free(filename);
1591 if (errno != EEXIST && errno != EINTR) {
1592 error_setg_errno(errp, errno,
1593 "can't open backing store %s for guest RAM",
1594 path);
1595 return -1;
1598 * Try again on EINTR and EEXIST. The latter happens when
1599 * something else creates the file between our two open().
1603 return fd;
1606 static void *file_ram_alloc(RAMBlock *block,
1607 ram_addr_t memory,
1608 int fd,
1609 bool truncate,
1610 Error **errp)
1612 void *area;
1614 block->page_size = qemu_fd_getpagesize(fd);
1615 if (block->mr->align % block->page_size) {
1616 error_setg(errp, "alignment 0x%" PRIx64
1617 " must be multiples of page size 0x%zx",
1618 block->mr->align, block->page_size);
1619 return NULL;
1621 block->mr->align = MAX(block->page_size, block->mr->align);
1622 #if defined(__s390x__)
1623 if (kvm_enabled()) {
1624 block->mr->align = MAX(block->mr->align, QEMU_VMALLOC_ALIGN);
1626 #endif
1628 if (memory < block->page_size) {
1629 error_setg(errp, "memory size 0x" RAM_ADDR_FMT " must be equal to "
1630 "or larger than page size 0x%zx",
1631 memory, block->page_size);
1632 return NULL;
1635 memory = ROUND_UP(memory, block->page_size);
1638 * ftruncate is not supported by hugetlbfs in older
1639 * hosts, so don't bother bailing out on errors.
1640 * If anything goes wrong with it under other filesystems,
1641 * mmap will fail.
1643 * Do not truncate the non-empty backend file to avoid corrupting
1644 * the existing data in the file. Disabling shrinking is not
1645 * enough. For example, the current vNVDIMM implementation stores
1646 * the guest NVDIMM labels at the end of the backend file. If the
1647 * backend file is later extended, QEMU will not be able to find
1648 * those labels. Therefore, extending the non-empty backend file
1649 * is disabled as well.
1651 if (truncate && ftruncate(fd, memory)) {
1652 perror("ftruncate");
1655 area = qemu_ram_mmap(fd, memory, block->mr->align,
1656 block->flags & RAM_SHARED);
1657 if (area == MAP_FAILED) {
1658 error_setg_errno(errp, errno,
1659 "unable to map backing store for guest RAM");
1660 return NULL;
1663 if (mem_prealloc) {
1664 os_mem_prealloc(fd, area, memory, smp_cpus, errp);
1665 if (errp && *errp) {
1666 qemu_ram_munmap(area, memory);
1667 return NULL;
1671 block->fd = fd;
1672 return area;
1674 #endif
1676 /* Allocate space within the ram_addr_t space that governs the
1677 * dirty bitmaps.
1678 * Called with the ramlist lock held.
1680 static ram_addr_t find_ram_offset(ram_addr_t size)
1682 RAMBlock *block, *next_block;
1683 ram_addr_t offset = RAM_ADDR_MAX, mingap = RAM_ADDR_MAX;
1685 assert(size != 0); /* it would hand out same offset multiple times */
1687 if (QLIST_EMPTY_RCU(&ram_list.blocks)) {
1688 return 0;
1691 RAMBLOCK_FOREACH(block) {
1692 ram_addr_t candidate, next = RAM_ADDR_MAX;
1694 /* Align blocks to start on a 'long' in the bitmap
1695 * which makes the bitmap sync'ing take the fast path.
1697 candidate = block->offset + block->max_length;
1698 candidate = ROUND_UP(candidate, BITS_PER_LONG << TARGET_PAGE_BITS);
1700 /* Search for the closest following block
1701 * and find the gap.
1703 RAMBLOCK_FOREACH(next_block) {
1704 if (next_block->offset >= candidate) {
1705 next = MIN(next, next_block->offset);
1709 /* If it fits remember our place and remember the size
1710 * of gap, but keep going so that we might find a smaller
1711 * gap to fill so avoiding fragmentation.
1713 if (next - candidate >= size && next - candidate < mingap) {
1714 offset = candidate;
1715 mingap = next - candidate;
1718 trace_find_ram_offset_loop(size, candidate, offset, next, mingap);
1721 if (offset == RAM_ADDR_MAX) {
1722 fprintf(stderr, "Failed to find gap of requested size: %" PRIu64 "\n",
1723 (uint64_t)size);
1724 abort();
1727 trace_find_ram_offset(size, offset);
1729 return offset;
1732 unsigned long last_ram_page(void)
1734 RAMBlock *block;
1735 ram_addr_t last = 0;
1737 rcu_read_lock();
1738 RAMBLOCK_FOREACH(block) {
1739 last = MAX(last, block->offset + block->max_length);
1741 rcu_read_unlock();
1742 return last >> TARGET_PAGE_BITS;
1745 static void qemu_ram_setup_dump(void *addr, ram_addr_t size)
1747 int ret;
1749 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1750 if (!machine_dump_guest_core(current_machine)) {
1751 ret = qemu_madvise(addr, size, QEMU_MADV_DONTDUMP);
1752 if (ret) {
1753 perror("qemu_madvise");
1754 fprintf(stderr, "madvise doesn't support MADV_DONTDUMP, "
1755 "but dump_guest_core=off specified\n");
1760 const char *qemu_ram_get_idstr(RAMBlock *rb)
1762 return rb->idstr;
1765 bool qemu_ram_is_shared(RAMBlock *rb)
1767 return rb->flags & RAM_SHARED;
1770 /* Called with iothread lock held. */
1771 void qemu_ram_set_idstr(RAMBlock *new_block, const char *name, DeviceState *dev)
1773 RAMBlock *block;
1775 assert(new_block);
1776 assert(!new_block->idstr[0]);
1778 if (dev) {
1779 char *id = qdev_get_dev_path(dev);
1780 if (id) {
1781 snprintf(new_block->idstr, sizeof(new_block->idstr), "%s/", id);
1782 g_free(id);
1785 pstrcat(new_block->idstr, sizeof(new_block->idstr), name);
1787 rcu_read_lock();
1788 RAMBLOCK_FOREACH(block) {
1789 if (block != new_block &&
1790 !strcmp(block->idstr, new_block->idstr)) {
1791 fprintf(stderr, "RAMBlock \"%s\" already registered, abort!\n",
1792 new_block->idstr);
1793 abort();
1796 rcu_read_unlock();
1799 /* Called with iothread lock held. */
1800 void qemu_ram_unset_idstr(RAMBlock *block)
1802 /* FIXME: arch_init.c assumes that this is not called throughout
1803 * migration. Ignore the problem since hot-unplug during migration
1804 * does not work anyway.
1806 if (block) {
1807 memset(block->idstr, 0, sizeof(block->idstr));
1811 size_t qemu_ram_pagesize(RAMBlock *rb)
1813 return rb->page_size;
1816 /* Returns the largest size of page in use */
1817 size_t qemu_ram_pagesize_largest(void)
1819 RAMBlock *block;
1820 size_t largest = 0;
1822 RAMBLOCK_FOREACH(block) {
1823 largest = MAX(largest, qemu_ram_pagesize(block));
1826 return largest;
1829 static int memory_try_enable_merging(void *addr, size_t len)
1831 if (!machine_mem_merge(current_machine)) {
1832 /* disabled by the user */
1833 return 0;
1836 return qemu_madvise(addr, len, QEMU_MADV_MERGEABLE);
1839 /* Only legal before guest might have detected the memory size: e.g. on
1840 * incoming migration, or right after reset.
1842 * As memory core doesn't know how is memory accessed, it is up to
1843 * resize callback to update device state and/or add assertions to detect
1844 * misuse, if necessary.
1846 int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp)
1848 assert(block);
1850 newsize = HOST_PAGE_ALIGN(newsize);
1852 if (block->used_length == newsize) {
1853 return 0;
1856 if (!(block->flags & RAM_RESIZEABLE)) {
1857 error_setg_errno(errp, EINVAL,
1858 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1859 " in != 0x" RAM_ADDR_FMT, block->idstr,
1860 newsize, block->used_length);
1861 return -EINVAL;
1864 if (block->max_length < newsize) {
1865 error_setg_errno(errp, EINVAL,
1866 "Length too large: %s: 0x" RAM_ADDR_FMT
1867 " > 0x" RAM_ADDR_FMT, block->idstr,
1868 newsize, block->max_length);
1869 return -EINVAL;
1872 cpu_physical_memory_clear_dirty_range(block->offset, block->used_length);
1873 block->used_length = newsize;
1874 cpu_physical_memory_set_dirty_range(block->offset, block->used_length,
1875 DIRTY_CLIENTS_ALL);
1876 memory_region_set_size(block->mr, newsize);
1877 if (block->resized) {
1878 block->resized(block->idstr, newsize, block->host);
1880 return 0;
1883 /* Called with ram_list.mutex held */
1884 static void dirty_memory_extend(ram_addr_t old_ram_size,
1885 ram_addr_t new_ram_size)
1887 ram_addr_t old_num_blocks = DIV_ROUND_UP(old_ram_size,
1888 DIRTY_MEMORY_BLOCK_SIZE);
1889 ram_addr_t new_num_blocks = DIV_ROUND_UP(new_ram_size,
1890 DIRTY_MEMORY_BLOCK_SIZE);
1891 int i;
1893 /* Only need to extend if block count increased */
1894 if (new_num_blocks <= old_num_blocks) {
1895 return;
1898 for (i = 0; i < DIRTY_MEMORY_NUM; i++) {
1899 DirtyMemoryBlocks *old_blocks;
1900 DirtyMemoryBlocks *new_blocks;
1901 int j;
1903 old_blocks = atomic_rcu_read(&ram_list.dirty_memory[i]);
1904 new_blocks = g_malloc(sizeof(*new_blocks) +
1905 sizeof(new_blocks->blocks[0]) * new_num_blocks);
1907 if (old_num_blocks) {
1908 memcpy(new_blocks->blocks, old_blocks->blocks,
1909 old_num_blocks * sizeof(old_blocks->blocks[0]));
1912 for (j = old_num_blocks; j < new_num_blocks; j++) {
1913 new_blocks->blocks[j] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE);
1916 atomic_rcu_set(&ram_list.dirty_memory[i], new_blocks);
1918 if (old_blocks) {
1919 g_free_rcu(old_blocks, rcu);
1924 static void ram_block_add(RAMBlock *new_block, Error **errp, bool shared)
1926 RAMBlock *block;
1927 RAMBlock *last_block = NULL;
1928 ram_addr_t old_ram_size, new_ram_size;
1929 Error *err = NULL;
1931 old_ram_size = last_ram_page();
1933 qemu_mutex_lock_ramlist();
1934 new_block->offset = find_ram_offset(new_block->max_length);
1936 if (!new_block->host) {
1937 if (xen_enabled()) {
1938 xen_ram_alloc(new_block->offset, new_block->max_length,
1939 new_block->mr, &err);
1940 if (err) {
1941 error_propagate(errp, err);
1942 qemu_mutex_unlock_ramlist();
1943 return;
1945 } else {
1946 new_block->host = phys_mem_alloc(new_block->max_length,
1947 &new_block->mr->align, shared);
1948 if (!new_block->host) {
1949 error_setg_errno(errp, errno,
1950 "cannot set up guest memory '%s'",
1951 memory_region_name(new_block->mr));
1952 qemu_mutex_unlock_ramlist();
1953 return;
1955 memory_try_enable_merging(new_block->host, new_block->max_length);
1959 new_ram_size = MAX(old_ram_size,
1960 (new_block->offset + new_block->max_length) >> TARGET_PAGE_BITS);
1961 if (new_ram_size > old_ram_size) {
1962 dirty_memory_extend(old_ram_size, new_ram_size);
1964 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1965 * QLIST (which has an RCU-friendly variant) does not have insertion at
1966 * tail, so save the last element in last_block.
1968 RAMBLOCK_FOREACH(block) {
1969 last_block = block;
1970 if (block->max_length < new_block->max_length) {
1971 break;
1974 if (block) {
1975 QLIST_INSERT_BEFORE_RCU(block, new_block, next);
1976 } else if (last_block) {
1977 QLIST_INSERT_AFTER_RCU(last_block, new_block, next);
1978 } else { /* list is empty */
1979 QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
1981 ram_list.mru_block = NULL;
1983 /* Write list before version */
1984 smp_wmb();
1985 ram_list.version++;
1986 qemu_mutex_unlock_ramlist();
1988 cpu_physical_memory_set_dirty_range(new_block->offset,
1989 new_block->used_length,
1990 DIRTY_CLIENTS_ALL);
1992 if (new_block->host) {
1993 qemu_ram_setup_dump(new_block->host, new_block->max_length);
1994 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_HUGEPAGE);
1995 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1996 qemu_madvise(new_block->host, new_block->max_length, QEMU_MADV_DONTFORK);
1997 ram_block_notify_add(new_block->host, new_block->max_length);
2001 #ifdef __linux__
2002 RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
2003 bool share, int fd,
2004 Error **errp)
2006 RAMBlock *new_block;
2007 Error *local_err = NULL;
2008 int64_t file_size;
2010 if (xen_enabled()) {
2011 error_setg(errp, "-mem-path not supported with Xen");
2012 return NULL;
2015 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2016 error_setg(errp,
2017 "host lacks kvm mmu notifiers, -mem-path unsupported");
2018 return NULL;
2021 if (phys_mem_alloc != qemu_anon_ram_alloc) {
2023 * file_ram_alloc() needs to allocate just like
2024 * phys_mem_alloc, but we haven't bothered to provide
2025 * a hook there.
2027 error_setg(errp,
2028 "-mem-path not supported with this accelerator");
2029 return NULL;
2032 size = HOST_PAGE_ALIGN(size);
2033 file_size = get_file_size(fd);
2034 if (file_size > 0 && file_size < size) {
2035 error_setg(errp, "backing store %s size 0x%" PRIx64
2036 " does not match 'size' option 0x" RAM_ADDR_FMT,
2037 mem_path, file_size, size);
2038 return NULL;
2041 new_block = g_malloc0(sizeof(*new_block));
2042 new_block->mr = mr;
2043 new_block->used_length = size;
2044 new_block->max_length = size;
2045 new_block->flags = share ? RAM_SHARED : 0;
2046 new_block->host = file_ram_alloc(new_block, size, fd, !file_size, errp);
2047 if (!new_block->host) {
2048 g_free(new_block);
2049 return NULL;
2052 ram_block_add(new_block, &local_err, share);
2053 if (local_err) {
2054 g_free(new_block);
2055 error_propagate(errp, local_err);
2056 return NULL;
2058 return new_block;
2063 RAMBlock *qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
2064 bool share, const char *mem_path,
2065 Error **errp)
2067 int fd;
2068 bool created;
2069 RAMBlock *block;
2071 fd = file_ram_open(mem_path, memory_region_name(mr), &created, errp);
2072 if (fd < 0) {
2073 return NULL;
2076 block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
2077 if (!block) {
2078 if (created) {
2079 unlink(mem_path);
2081 close(fd);
2082 return NULL;
2085 return block;
2087 #endif
2089 static
2090 RAMBlock *qemu_ram_alloc_internal(ram_addr_t size, ram_addr_t max_size,
2091 void (*resized)(const char*,
2092 uint64_t length,
2093 void *host),
2094 void *host, bool resizeable, bool share,
2095 MemoryRegion *mr, Error **errp)
2097 RAMBlock *new_block;
2098 Error *local_err = NULL;
2100 size = HOST_PAGE_ALIGN(size);
2101 max_size = HOST_PAGE_ALIGN(max_size);
2102 new_block = g_malloc0(sizeof(*new_block));
2103 new_block->mr = mr;
2104 new_block->resized = resized;
2105 new_block->used_length = size;
2106 new_block->max_length = max_size;
2107 assert(max_size >= size);
2108 new_block->fd = -1;
2109 new_block->page_size = getpagesize();
2110 new_block->host = host;
2111 if (host) {
2112 new_block->flags |= RAM_PREALLOC;
2114 if (resizeable) {
2115 new_block->flags |= RAM_RESIZEABLE;
2117 ram_block_add(new_block, &local_err, share);
2118 if (local_err) {
2119 g_free(new_block);
2120 error_propagate(errp, local_err);
2121 return NULL;
2123 return new_block;
2126 RAMBlock *qemu_ram_alloc_from_ptr(ram_addr_t size, void *host,
2127 MemoryRegion *mr, Error **errp)
2129 return qemu_ram_alloc_internal(size, size, NULL, host, false,
2130 false, mr, errp);
2133 RAMBlock *qemu_ram_alloc(ram_addr_t size, bool share,
2134 MemoryRegion *mr, Error **errp)
2136 return qemu_ram_alloc_internal(size, size, NULL, NULL, false,
2137 share, mr, errp);
2140 RAMBlock *qemu_ram_alloc_resizeable(ram_addr_t size, ram_addr_t maxsz,
2141 void (*resized)(const char*,
2142 uint64_t length,
2143 void *host),
2144 MemoryRegion *mr, Error **errp)
2146 return qemu_ram_alloc_internal(size, maxsz, resized, NULL, true,
2147 false, mr, errp);
2150 static void reclaim_ramblock(RAMBlock *block)
2152 if (block->flags & RAM_PREALLOC) {
2154 } else if (xen_enabled()) {
2155 xen_invalidate_map_cache_entry(block->host);
2156 #ifndef _WIN32
2157 } else if (block->fd >= 0) {
2158 qemu_ram_munmap(block->host, block->max_length);
2159 close(block->fd);
2160 #endif
2161 } else {
2162 qemu_anon_ram_free(block->host, block->max_length);
2164 g_free(block);
2167 void qemu_ram_free(RAMBlock *block)
2169 if (!block) {
2170 return;
2173 if (block->host) {
2174 ram_block_notify_remove(block->host, block->max_length);
2177 qemu_mutex_lock_ramlist();
2178 QLIST_REMOVE_RCU(block, next);
2179 ram_list.mru_block = NULL;
2180 /* Write list before version */
2181 smp_wmb();
2182 ram_list.version++;
2183 call_rcu(block, reclaim_ramblock, rcu);
2184 qemu_mutex_unlock_ramlist();
2187 #ifndef _WIN32
2188 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length)
2190 RAMBlock *block;
2191 ram_addr_t offset;
2192 int flags;
2193 void *area, *vaddr;
2195 RAMBLOCK_FOREACH(block) {
2196 offset = addr - block->offset;
2197 if (offset < block->max_length) {
2198 vaddr = ramblock_ptr(block, offset);
2199 if (block->flags & RAM_PREALLOC) {
2201 } else if (xen_enabled()) {
2202 abort();
2203 } else {
2204 flags = MAP_FIXED;
2205 if (block->fd >= 0) {
2206 flags |= (block->flags & RAM_SHARED ?
2207 MAP_SHARED : MAP_PRIVATE);
2208 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2209 flags, block->fd, offset);
2210 } else {
2212 * Remap needs to match alloc. Accelerators that
2213 * set phys_mem_alloc never remap. If they did,
2214 * we'd need a remap hook here.
2216 assert(phys_mem_alloc == qemu_anon_ram_alloc);
2218 flags |= MAP_PRIVATE | MAP_ANONYMOUS;
2219 area = mmap(vaddr, length, PROT_READ | PROT_WRITE,
2220 flags, -1, 0);
2222 if (area != vaddr) {
2223 error_report("Could not remap addr: "
2224 RAM_ADDR_FMT "@" RAM_ADDR_FMT "",
2225 length, addr);
2226 exit(1);
2228 memory_try_enable_merging(vaddr, length);
2229 qemu_ram_setup_dump(vaddr, length);
2234 #endif /* !_WIN32 */
2236 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2237 * This should not be used for general purpose DMA. Use address_space_map
2238 * or address_space_rw instead. For local memory (e.g. video ram) that the
2239 * device owns, use memory_region_get_ram_ptr.
2241 * Called within RCU critical section.
2243 void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr)
2245 RAMBlock *block = ram_block;
2247 if (block == NULL) {
2248 block = qemu_get_ram_block(addr);
2249 addr -= block->offset;
2252 if (xen_enabled() && block->host == NULL) {
2253 /* We need to check if the requested address is in the RAM
2254 * because we don't want to map the entire memory in QEMU.
2255 * In that case just map until the end of the page.
2257 if (block->offset == 0) {
2258 return xen_map_cache(addr, 0, 0, false);
2261 block->host = xen_map_cache(block->offset, block->max_length, 1, false);
2263 return ramblock_ptr(block, addr);
2266 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2267 * but takes a size argument.
2269 * Called within RCU critical section.
2271 static void *qemu_ram_ptr_length(RAMBlock *ram_block, ram_addr_t addr,
2272 hwaddr *size, bool lock)
2274 RAMBlock *block = ram_block;
2275 if (*size == 0) {
2276 return NULL;
2279 if (block == NULL) {
2280 block = qemu_get_ram_block(addr);
2281 addr -= block->offset;
2283 *size = MIN(*size, block->max_length - addr);
2285 if (xen_enabled() && block->host == NULL) {
2286 /* We need to check if the requested address is in the RAM
2287 * because we don't want to map the entire memory in QEMU.
2288 * In that case just map the requested area.
2290 if (block->offset == 0) {
2291 return xen_map_cache(addr, *size, lock, lock);
2294 block->host = xen_map_cache(block->offset, block->max_length, 1, lock);
2297 return ramblock_ptr(block, addr);
2301 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2302 * in that RAMBlock.
2304 * ptr: Host pointer to look up
2305 * round_offset: If true round the result offset down to a page boundary
2306 * *ram_addr: set to result ram_addr
2307 * *offset: set to result offset within the RAMBlock
2309 * Returns: RAMBlock (or NULL if not found)
2311 * By the time this function returns, the returned pointer is not protected
2312 * by RCU anymore. If the caller is not within an RCU critical section and
2313 * does not hold the iothread lock, it must have other means of protecting the
2314 * pointer, such as a reference to the region that includes the incoming
2315 * ram_addr_t.
2317 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
2318 ram_addr_t *offset)
2320 RAMBlock *block;
2321 uint8_t *host = ptr;
2323 if (xen_enabled()) {
2324 ram_addr_t ram_addr;
2325 rcu_read_lock();
2326 ram_addr = xen_ram_addr_from_mapcache(ptr);
2327 block = qemu_get_ram_block(ram_addr);
2328 if (block) {
2329 *offset = ram_addr - block->offset;
2331 rcu_read_unlock();
2332 return block;
2335 rcu_read_lock();
2336 block = atomic_rcu_read(&ram_list.mru_block);
2337 if (block && block->host && host - block->host < block->max_length) {
2338 goto found;
2341 RAMBLOCK_FOREACH(block) {
2342 /* This case append when the block is not mapped. */
2343 if (block->host == NULL) {
2344 continue;
2346 if (host - block->host < block->max_length) {
2347 goto found;
2351 rcu_read_unlock();
2352 return NULL;
2354 found:
2355 *offset = (host - block->host);
2356 if (round_offset) {
2357 *offset &= TARGET_PAGE_MASK;
2359 rcu_read_unlock();
2360 return block;
2364 * Finds the named RAMBlock
2366 * name: The name of RAMBlock to find
2368 * Returns: RAMBlock (or NULL if not found)
2370 RAMBlock *qemu_ram_block_by_name(const char *name)
2372 RAMBlock *block;
2374 RAMBLOCK_FOREACH(block) {
2375 if (!strcmp(name, block->idstr)) {
2376 return block;
2380 return NULL;
2383 /* Some of the softmmu routines need to translate from a host pointer
2384 (typically a TLB entry) back to a ram offset. */
2385 ram_addr_t qemu_ram_addr_from_host(void *ptr)
2387 RAMBlock *block;
2388 ram_addr_t offset;
2390 block = qemu_ram_block_from_host(ptr, false, &offset);
2391 if (!block) {
2392 return RAM_ADDR_INVALID;
2395 return block->offset + offset;
2398 /* Called within RCU critical section. */
2399 void memory_notdirty_write_prepare(NotDirtyInfo *ndi,
2400 CPUState *cpu,
2401 vaddr mem_vaddr,
2402 ram_addr_t ram_addr,
2403 unsigned size)
2405 ndi->cpu = cpu;
2406 ndi->ram_addr = ram_addr;
2407 ndi->mem_vaddr = mem_vaddr;
2408 ndi->size = size;
2409 ndi->locked = false;
2411 assert(tcg_enabled());
2412 if (!cpu_physical_memory_get_dirty_flag(ram_addr, DIRTY_MEMORY_CODE)) {
2413 ndi->locked = true;
2414 tb_lock();
2415 tb_invalidate_phys_page_fast(ram_addr, size);
2419 /* Called within RCU critical section. */
2420 void memory_notdirty_write_complete(NotDirtyInfo *ndi)
2422 if (ndi->locked) {
2423 tb_unlock();
2426 /* Set both VGA and migration bits for simplicity and to remove
2427 * the notdirty callback faster.
2429 cpu_physical_memory_set_dirty_range(ndi->ram_addr, ndi->size,
2430 DIRTY_CLIENTS_NOCODE);
2431 /* we remove the notdirty callback only if the code has been
2432 flushed */
2433 if (!cpu_physical_memory_is_clean(ndi->ram_addr)) {
2434 tlb_set_dirty(ndi->cpu, ndi->mem_vaddr);
2438 /* Called within RCU critical section. */
2439 static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
2440 uint64_t val, unsigned size)
2442 NotDirtyInfo ndi;
2444 memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr,
2445 ram_addr, size);
2447 switch (size) {
2448 case 1:
2449 stb_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2450 break;
2451 case 2:
2452 stw_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2453 break;
2454 case 4:
2455 stl_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2456 break;
2457 case 8:
2458 stq_p(qemu_map_ram_ptr(NULL, ram_addr), val);
2459 break;
2460 default:
2461 abort();
2463 memory_notdirty_write_complete(&ndi);
2466 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
2467 unsigned size, bool is_write)
2469 return is_write;
2472 static const MemoryRegionOps notdirty_mem_ops = {
2473 .write = notdirty_mem_write,
2474 .valid.accepts = notdirty_mem_accepts,
2475 .endianness = DEVICE_NATIVE_ENDIAN,
2476 .valid = {
2477 .min_access_size = 1,
2478 .max_access_size = 8,
2479 .unaligned = false,
2481 .impl = {
2482 .min_access_size = 1,
2483 .max_access_size = 8,
2484 .unaligned = false,
2488 /* Generate a debug exception if a watchpoint has been hit. */
2489 static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
2491 CPUState *cpu = current_cpu;
2492 CPUClass *cc = CPU_GET_CLASS(cpu);
2493 target_ulong vaddr;
2494 CPUWatchpoint *wp;
2496 assert(tcg_enabled());
2497 if (cpu->watchpoint_hit) {
2498 /* We re-entered the check after replacing the TB. Now raise
2499 * the debug interrupt so that is will trigger after the
2500 * current instruction. */
2501 cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
2502 return;
2504 vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
2505 vaddr = cc->adjust_watchpoint_address(cpu, vaddr, len);
2506 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
2507 if (cpu_watchpoint_address_matches(wp, vaddr, len)
2508 && (wp->flags & flags)) {
2509 if (flags == BP_MEM_READ) {
2510 wp->flags |= BP_WATCHPOINT_HIT_READ;
2511 } else {
2512 wp->flags |= BP_WATCHPOINT_HIT_WRITE;
2514 wp->hitaddr = vaddr;
2515 wp->hitattrs = attrs;
2516 if (!cpu->watchpoint_hit) {
2517 if (wp->flags & BP_CPU &&
2518 !cc->debug_check_watchpoint(cpu, wp)) {
2519 wp->flags &= ~BP_WATCHPOINT_HIT;
2520 continue;
2522 cpu->watchpoint_hit = wp;
2524 /* Both tb_lock and iothread_mutex will be reset when
2525 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2526 * back into the cpu_exec main loop.
2528 tb_lock();
2529 tb_check_watchpoint(cpu);
2530 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
2531 cpu->exception_index = EXCP_DEBUG;
2532 cpu_loop_exit(cpu);
2533 } else {
2534 /* Force execution of one insn next time. */
2535 cpu->cflags_next_tb = 1 | curr_cflags();
2536 cpu_loop_exit_noexc(cpu);
2539 } else {
2540 wp->flags &= ~BP_WATCHPOINT_HIT;
2545 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2546 so these check for a hit then pass through to the normal out-of-line
2547 phys routines. */
2548 static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
2549 unsigned size, MemTxAttrs attrs)
2551 MemTxResult res;
2552 uint64_t data;
2553 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2554 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2556 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
2557 switch (size) {
2558 case 1:
2559 data = address_space_ldub(as, addr, attrs, &res);
2560 break;
2561 case 2:
2562 data = address_space_lduw(as, addr, attrs, &res);
2563 break;
2564 case 4:
2565 data = address_space_ldl(as, addr, attrs, &res);
2566 break;
2567 case 8:
2568 data = address_space_ldq(as, addr, attrs, &res);
2569 break;
2570 default: abort();
2572 *pdata = data;
2573 return res;
2576 static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
2577 uint64_t val, unsigned size,
2578 MemTxAttrs attrs)
2580 MemTxResult res;
2581 int asidx = cpu_asidx_from_attrs(current_cpu, attrs);
2582 AddressSpace *as = current_cpu->cpu_ases[asidx].as;
2584 check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
2585 switch (size) {
2586 case 1:
2587 address_space_stb(as, addr, val, attrs, &res);
2588 break;
2589 case 2:
2590 address_space_stw(as, addr, val, attrs, &res);
2591 break;
2592 case 4:
2593 address_space_stl(as, addr, val, attrs, &res);
2594 break;
2595 case 8:
2596 address_space_stq(as, addr, val, attrs, &res);
2597 break;
2598 default: abort();
2600 return res;
2603 static const MemoryRegionOps watch_mem_ops = {
2604 .read_with_attrs = watch_mem_read,
2605 .write_with_attrs = watch_mem_write,
2606 .endianness = DEVICE_NATIVE_ENDIAN,
2607 .valid = {
2608 .min_access_size = 1,
2609 .max_access_size = 8,
2610 .unaligned = false,
2612 .impl = {
2613 .min_access_size = 1,
2614 .max_access_size = 8,
2615 .unaligned = false,
2619 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
2620 MemTxAttrs attrs, uint8_t *buf, int len);
2621 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
2622 const uint8_t *buf, int len);
2623 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
2624 bool is_write);
2626 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
2627 unsigned len, MemTxAttrs attrs)
2629 subpage_t *subpage = opaque;
2630 uint8_t buf[8];
2631 MemTxResult res;
2633 #if defined(DEBUG_SUBPAGE)
2634 printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
2635 subpage, len, addr);
2636 #endif
2637 res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len);
2638 if (res) {
2639 return res;
2641 switch (len) {
2642 case 1:
2643 *data = ldub_p(buf);
2644 return MEMTX_OK;
2645 case 2:
2646 *data = lduw_p(buf);
2647 return MEMTX_OK;
2648 case 4:
2649 *data = ldl_p(buf);
2650 return MEMTX_OK;
2651 case 8:
2652 *data = ldq_p(buf);
2653 return MEMTX_OK;
2654 default:
2655 abort();
2659 static MemTxResult subpage_write(void *opaque, hwaddr addr,
2660 uint64_t value, unsigned len, MemTxAttrs attrs)
2662 subpage_t *subpage = opaque;
2663 uint8_t buf[8];
2665 #if defined(DEBUG_SUBPAGE)
2666 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2667 " value %"PRIx64"\n",
2668 __func__, subpage, len, addr, value);
2669 #endif
2670 switch (len) {
2671 case 1:
2672 stb_p(buf, value);
2673 break;
2674 case 2:
2675 stw_p(buf, value);
2676 break;
2677 case 4:
2678 stl_p(buf, value);
2679 break;
2680 case 8:
2681 stq_p(buf, value);
2682 break;
2683 default:
2684 abort();
2686 return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len);
2689 static bool subpage_accepts(void *opaque, hwaddr addr,
2690 unsigned len, bool is_write)
2692 subpage_t *subpage = opaque;
2693 #if defined(DEBUG_SUBPAGE)
2694 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n",
2695 __func__, subpage, is_write ? 'w' : 'r', len, addr);
2696 #endif
2698 return flatview_access_valid(subpage->fv, addr + subpage->base,
2699 len, is_write);
2702 static const MemoryRegionOps subpage_ops = {
2703 .read_with_attrs = subpage_read,
2704 .write_with_attrs = subpage_write,
2705 .impl.min_access_size = 1,
2706 .impl.max_access_size = 8,
2707 .valid.min_access_size = 1,
2708 .valid.max_access_size = 8,
2709 .valid.accepts = subpage_accepts,
2710 .endianness = DEVICE_NATIVE_ENDIAN,
2713 static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
2714 uint16_t section)
2716 int idx, eidx;
2718 if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
2719 return -1;
2720 idx = SUBPAGE_IDX(start);
2721 eidx = SUBPAGE_IDX(end);
2722 #if defined(DEBUG_SUBPAGE)
2723 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2724 __func__, mmio, start, end, idx, eidx, section);
2725 #endif
2726 for (; idx <= eidx; idx++) {
2727 mmio->sub_section[idx] = section;
2730 return 0;
2733 static subpage_t *subpage_init(FlatView *fv, hwaddr base)
2735 subpage_t *mmio;
2737 mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t));
2738 mmio->fv = fv;
2739 mmio->base = base;
2740 memory_region_init_io(&mmio->iomem, NULL, &subpage_ops, mmio,
2741 NULL, TARGET_PAGE_SIZE);
2742 mmio->iomem.subpage = true;
2743 #if defined(DEBUG_SUBPAGE)
2744 printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__,
2745 mmio, base, TARGET_PAGE_SIZE);
2746 #endif
2747 subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED);
2749 return mmio;
2752 static uint16_t dummy_section(PhysPageMap *map, FlatView *fv, MemoryRegion *mr)
2754 assert(fv);
2755 MemoryRegionSection section = {
2756 .fv = fv,
2757 .mr = mr,
2758 .offset_within_address_space = 0,
2759 .offset_within_region = 0,
2760 .size = int128_2_64(),
2763 return phys_section_add(map, &section);
2766 static void readonly_mem_write(void *opaque, hwaddr addr,
2767 uint64_t val, unsigned size)
2769 /* Ignore any write to ROM. */
2772 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
2773 unsigned size, bool is_write)
2775 return is_write;
2778 /* This will only be used for writes, because reads are special cased
2779 * to directly access the underlying host ram.
2781 static const MemoryRegionOps readonly_mem_ops = {
2782 .write = readonly_mem_write,
2783 .valid.accepts = readonly_mem_accepts,
2784 .endianness = DEVICE_NATIVE_ENDIAN,
2785 .valid = {
2786 .min_access_size = 1,
2787 .max_access_size = 8,
2788 .unaligned = false,
2790 .impl = {
2791 .min_access_size = 1,
2792 .max_access_size = 8,
2793 .unaligned = false,
2797 MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs)
2799 int asidx = cpu_asidx_from_attrs(cpu, attrs);
2800 CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx];
2801 AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch);
2802 MemoryRegionSection *sections = d->map.sections;
2804 return sections[index & ~TARGET_PAGE_MASK].mr;
2807 static void io_mem_init(void)
2809 memory_region_init_io(&io_mem_rom, NULL, &readonly_mem_ops,
2810 NULL, NULL, UINT64_MAX);
2811 memory_region_init_io(&io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
2812 NULL, UINT64_MAX);
2814 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2815 * which can be called without the iothread mutex.
2817 memory_region_init_io(&io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
2818 NULL, UINT64_MAX);
2819 memory_region_clear_global_locking(&io_mem_notdirty);
2821 memory_region_init_io(&io_mem_watch, NULL, &watch_mem_ops, NULL,
2822 NULL, UINT64_MAX);
2825 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv)
2827 AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
2828 uint16_t n;
2830 n = dummy_section(&d->map, fv, &io_mem_unassigned);
2831 assert(n == PHYS_SECTION_UNASSIGNED);
2832 n = dummy_section(&d->map, fv, &io_mem_notdirty);
2833 assert(n == PHYS_SECTION_NOTDIRTY);
2834 n = dummy_section(&d->map, fv, &io_mem_rom);
2835 assert(n == PHYS_SECTION_ROM);
2836 n = dummy_section(&d->map, fv, &io_mem_watch);
2837 assert(n == PHYS_SECTION_WATCH);
2839 d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
2841 return d;
2844 void address_space_dispatch_free(AddressSpaceDispatch *d)
2846 phys_sections_free(&d->map);
2847 g_free(d);
2850 static void tcg_commit(MemoryListener *listener)
2852 CPUAddressSpace *cpuas;
2853 AddressSpaceDispatch *d;
2855 /* since each CPU stores ram addresses in its TLB cache, we must
2856 reset the modified entries */
2857 cpuas = container_of(listener, CPUAddressSpace, tcg_as_listener);
2858 cpu_reloading_memory_map();
2859 /* The CPU and TLB are protected by the iothread lock.
2860 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2861 * may have split the RCU critical section.
2863 d = address_space_to_dispatch(cpuas->as);
2864 atomic_rcu_set(&cpuas->memory_dispatch, d);
2865 tlb_flush(cpuas->cpu);
2868 static void memory_map_init(void)
2870 system_memory = g_malloc(sizeof(*system_memory));
2872 memory_region_init(system_memory, NULL, "system", UINT64_MAX);
2873 address_space_init(&address_space_memory, system_memory, "memory");
2875 system_io = g_malloc(sizeof(*system_io));
2876 memory_region_init_io(system_io, NULL, &unassigned_io_ops, NULL, "io",
2877 65536);
2878 address_space_init(&address_space_io, system_io, "I/O");
2881 MemoryRegion *get_system_memory(void)
2883 return system_memory;
2886 MemoryRegion *get_system_io(void)
2888 return system_io;
2891 #endif /* !defined(CONFIG_USER_ONLY) */
2893 /* physical memory access (slow version, mainly for debug) */
2894 #if defined(CONFIG_USER_ONLY)
2895 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
2896 uint8_t *buf, int len, int is_write)
2898 int l, flags;
2899 target_ulong page;
2900 void * p;
2902 while (len > 0) {
2903 page = addr & TARGET_PAGE_MASK;
2904 l = (page + TARGET_PAGE_SIZE) - addr;
2905 if (l > len)
2906 l = len;
2907 flags = page_get_flags(page);
2908 if (!(flags & PAGE_VALID))
2909 return -1;
2910 if (is_write) {
2911 if (!(flags & PAGE_WRITE))
2912 return -1;
2913 /* XXX: this code should not depend on lock_user */
2914 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
2915 return -1;
2916 memcpy(p, buf, l);
2917 unlock_user(p, addr, l);
2918 } else {
2919 if (!(flags & PAGE_READ))
2920 return -1;
2921 /* XXX: this code should not depend on lock_user */
2922 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
2923 return -1;
2924 memcpy(buf, p, l);
2925 unlock_user(p, addr, 0);
2927 len -= l;
2928 buf += l;
2929 addr += l;
2931 return 0;
2934 #else
2936 static void invalidate_and_set_dirty(MemoryRegion *mr, hwaddr addr,
2937 hwaddr length)
2939 uint8_t dirty_log_mask = memory_region_get_dirty_log_mask(mr);
2940 addr += memory_region_get_ram_addr(mr);
2942 /* No early return if dirty_log_mask is or becomes 0, because
2943 * cpu_physical_memory_set_dirty_range will still call
2944 * xen_modified_memory.
2946 if (dirty_log_mask) {
2947 dirty_log_mask =
2948 cpu_physical_memory_range_includes_clean(addr, length, dirty_log_mask);
2950 if (dirty_log_mask & (1 << DIRTY_MEMORY_CODE)) {
2951 assert(tcg_enabled());
2952 tb_lock();
2953 tb_invalidate_phys_range(addr, addr + length);
2954 tb_unlock();
2955 dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
2957 cpu_physical_memory_set_dirty_range(addr, length, dirty_log_mask);
2960 static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
2962 unsigned access_size_max = mr->ops->valid.max_access_size;
2964 /* Regions are assumed to support 1-4 byte accesses unless
2965 otherwise specified. */
2966 if (access_size_max == 0) {
2967 access_size_max = 4;
2970 /* Bound the maximum access by the alignment of the address. */
2971 if (!mr->ops->impl.unaligned) {
2972 unsigned align_size_max = addr & -addr;
2973 if (align_size_max != 0 && align_size_max < access_size_max) {
2974 access_size_max = align_size_max;
2978 /* Don't attempt accesses larger than the maximum. */
2979 if (l > access_size_max) {
2980 l = access_size_max;
2982 l = pow2floor(l);
2984 return l;
2987 static bool prepare_mmio_access(MemoryRegion *mr)
2989 bool unlocked = !qemu_mutex_iothread_locked();
2990 bool release_lock = false;
2992 if (unlocked && mr->global_locking) {
2993 qemu_mutex_lock_iothread();
2994 unlocked = false;
2995 release_lock = true;
2997 if (mr->flush_coalesced_mmio) {
2998 if (unlocked) {
2999 qemu_mutex_lock_iothread();
3001 qemu_flush_coalesced_mmio_buffer();
3002 if (unlocked) {
3003 qemu_mutex_unlock_iothread();
3007 return release_lock;
3010 /* Called within RCU critical section. */
3011 static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
3012 MemTxAttrs attrs,
3013 const uint8_t *buf,
3014 int len, hwaddr addr1,
3015 hwaddr l, MemoryRegion *mr)
3017 uint8_t *ptr;
3018 uint64_t val;
3019 MemTxResult result = MEMTX_OK;
3020 bool release_lock = false;
3022 for (;;) {
3023 if (!memory_access_is_direct(mr, true)) {
3024 release_lock |= prepare_mmio_access(mr);
3025 l = memory_access_size(mr, l, addr1);
3026 /* XXX: could force current_cpu to NULL to avoid
3027 potential bugs */
3028 switch (l) {
3029 case 8:
3030 /* 64 bit write access */
3031 val = ldq_p(buf);
3032 result |= memory_region_dispatch_write(mr, addr1, val, 8,
3033 attrs);
3034 break;
3035 case 4:
3036 /* 32 bit write access */
3037 val = (uint32_t)ldl_p(buf);
3038 result |= memory_region_dispatch_write(mr, addr1, val, 4,
3039 attrs);
3040 break;
3041 case 2:
3042 /* 16 bit write access */
3043 val = lduw_p(buf);
3044 result |= memory_region_dispatch_write(mr, addr1, val, 2,
3045 attrs);
3046 break;
3047 case 1:
3048 /* 8 bit write access */
3049 val = ldub_p(buf);
3050 result |= memory_region_dispatch_write(mr, addr1, val, 1,
3051 attrs);
3052 break;
3053 default:
3054 abort();
3056 } else {
3057 /* RAM case */
3058 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3059 memcpy(ptr, buf, l);
3060 invalidate_and_set_dirty(mr, addr1, l);
3063 if (release_lock) {
3064 qemu_mutex_unlock_iothread();
3065 release_lock = false;
3068 len -= l;
3069 buf += l;
3070 addr += l;
3072 if (!len) {
3073 break;
3076 l = len;
3077 mr = flatview_translate(fv, addr, &addr1, &l, true);
3080 return result;
3083 /* Called from RCU critical section. */
3084 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
3085 const uint8_t *buf, int len)
3087 hwaddr l;
3088 hwaddr addr1;
3089 MemoryRegion *mr;
3090 MemTxResult result = MEMTX_OK;
3092 l = len;
3093 mr = flatview_translate(fv, addr, &addr1, &l, true);
3094 result = flatview_write_continue(fv, addr, attrs, buf, len,
3095 addr1, l, mr);
3097 return result;
3100 /* Called within RCU critical section. */
3101 MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
3102 MemTxAttrs attrs, uint8_t *buf,
3103 int len, hwaddr addr1, hwaddr l,
3104 MemoryRegion *mr)
3106 uint8_t *ptr;
3107 uint64_t val;
3108 MemTxResult result = MEMTX_OK;
3109 bool release_lock = false;
3111 for (;;) {
3112 if (!memory_access_is_direct(mr, false)) {
3113 /* I/O case */
3114 release_lock |= prepare_mmio_access(mr);
3115 l = memory_access_size(mr, l, addr1);
3116 switch (l) {
3117 case 8:
3118 /* 64 bit read access */
3119 result |= memory_region_dispatch_read(mr, addr1, &val, 8,
3120 attrs);
3121 stq_p(buf, val);
3122 break;
3123 case 4:
3124 /* 32 bit read access */
3125 result |= memory_region_dispatch_read(mr, addr1, &val, 4,
3126 attrs);
3127 stl_p(buf, val);
3128 break;
3129 case 2:
3130 /* 16 bit read access */
3131 result |= memory_region_dispatch_read(mr, addr1, &val, 2,
3132 attrs);
3133 stw_p(buf, val);
3134 break;
3135 case 1:
3136 /* 8 bit read access */
3137 result |= memory_region_dispatch_read(mr, addr1, &val, 1,
3138 attrs);
3139 stb_p(buf, val);
3140 break;
3141 default:
3142 abort();
3144 } else {
3145 /* RAM case */
3146 ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
3147 memcpy(buf, ptr, l);
3150 if (release_lock) {
3151 qemu_mutex_unlock_iothread();
3152 release_lock = false;
3155 len -= l;
3156 buf += l;
3157 addr += l;
3159 if (!len) {
3160 break;
3163 l = len;
3164 mr = flatview_translate(fv, addr, &addr1, &l, false);
3167 return result;
3170 /* Called from RCU critical section. */
3171 static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
3172 MemTxAttrs attrs, uint8_t *buf, int len)
3174 hwaddr l;
3175 hwaddr addr1;
3176 MemoryRegion *mr;
3178 l = len;
3179 mr = flatview_translate(fv, addr, &addr1, &l, false);
3180 return flatview_read_continue(fv, addr, attrs, buf, len,
3181 addr1, l, mr);
3184 MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr,
3185 MemTxAttrs attrs, uint8_t *buf, int len)
3187 MemTxResult result = MEMTX_OK;
3188 FlatView *fv;
3190 if (len > 0) {
3191 rcu_read_lock();
3192 fv = address_space_to_flatview(as);
3193 result = flatview_read(fv, addr, attrs, buf, len);
3194 rcu_read_unlock();
3197 return result;
3200 MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
3201 MemTxAttrs attrs,
3202 const uint8_t *buf, int len)
3204 MemTxResult result = MEMTX_OK;
3205 FlatView *fv;
3207 if (len > 0) {
3208 rcu_read_lock();
3209 fv = address_space_to_flatview(as);
3210 result = flatview_write(fv, addr, attrs, buf, len);
3211 rcu_read_unlock();
3214 return result;
3217 MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
3218 uint8_t *buf, int len, bool is_write)
3220 if (is_write) {
3221 return address_space_write(as, addr, attrs, buf, len);
3222 } else {
3223 return address_space_read_full(as, addr, attrs, buf, len);
3227 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
3228 int len, int is_write)
3230 address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED,
3231 buf, len, is_write);
3234 enum write_rom_type {
3235 WRITE_DATA,
3236 FLUSH_CACHE,
3239 static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
3240 hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
3242 hwaddr l;
3243 uint8_t *ptr;
3244 hwaddr addr1;
3245 MemoryRegion *mr;
3247 rcu_read_lock();
3248 while (len > 0) {
3249 l = len;
3250 mr = address_space_translate(as, addr, &addr1, &l, true);
3252 if (!(memory_region_is_ram(mr) ||
3253 memory_region_is_romd(mr))) {
3254 l = memory_access_size(mr, l, addr1);
3255 } else {
3256 /* ROM/RAM case */
3257 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
3258 switch (type) {
3259 case WRITE_DATA:
3260 memcpy(ptr, buf, l);
3261 invalidate_and_set_dirty(mr, addr1, l);
3262 break;
3263 case FLUSH_CACHE:
3264 flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l);
3265 break;
3268 len -= l;
3269 buf += l;
3270 addr += l;
3272 rcu_read_unlock();
3275 /* used for ROM loading : can write in RAM and ROM */
3276 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
3277 const uint8_t *buf, int len)
3279 cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
3282 void cpu_flush_icache_range(hwaddr start, int len)
3285 * This function should do the same thing as an icache flush that was
3286 * triggered from within the guest. For TCG we are always cache coherent,
3287 * so there is no need to flush anything. For KVM / Xen we need to flush
3288 * the host's instruction cache at least.
3290 if (tcg_enabled()) {
3291 return;
3294 cpu_physical_memory_write_rom_internal(&address_space_memory,
3295 start, NULL, len, FLUSH_CACHE);
3298 typedef struct {
3299 MemoryRegion *mr;
3300 void *buffer;
3301 hwaddr addr;
3302 hwaddr len;
3303 bool in_use;
3304 } BounceBuffer;
3306 static BounceBuffer bounce;
3308 typedef struct MapClient {
3309 QEMUBH *bh;
3310 QLIST_ENTRY(MapClient) link;
3311 } MapClient;
3313 QemuMutex map_client_list_lock;
3314 static QLIST_HEAD(map_client_list, MapClient) map_client_list
3315 = QLIST_HEAD_INITIALIZER(map_client_list);
3317 static void cpu_unregister_map_client_do(MapClient *client)
3319 QLIST_REMOVE(client, link);
3320 g_free(client);
3323 static void cpu_notify_map_clients_locked(void)
3325 MapClient *client;
3327 while (!QLIST_EMPTY(&map_client_list)) {
3328 client = QLIST_FIRST(&map_client_list);
3329 qemu_bh_schedule(client->bh);
3330 cpu_unregister_map_client_do(client);
3334 void cpu_register_map_client(QEMUBH *bh)
3336 MapClient *client = g_malloc(sizeof(*client));
3338 qemu_mutex_lock(&map_client_list_lock);
3339 client->bh = bh;
3340 QLIST_INSERT_HEAD(&map_client_list, client, link);
3341 if (!atomic_read(&bounce.in_use)) {
3342 cpu_notify_map_clients_locked();
3344 qemu_mutex_unlock(&map_client_list_lock);
3347 void cpu_exec_init_all(void)
3349 qemu_mutex_init(&ram_list.mutex);
3350 /* The data structures we set up here depend on knowing the page size,
3351 * so no more changes can be made after this point.
3352 * In an ideal world, nothing we did before we had finished the
3353 * machine setup would care about the target page size, and we could
3354 * do this much later, rather than requiring board models to state
3355 * up front what their requirements are.
3357 finalize_target_page_bits();
3358 io_mem_init();
3359 memory_map_init();
3360 qemu_mutex_init(&map_client_list_lock);
3363 void cpu_unregister_map_client(QEMUBH *bh)
3365 MapClient *client;
3367 qemu_mutex_lock(&map_client_list_lock);
3368 QLIST_FOREACH(client, &map_client_list, link) {
3369 if (client->bh == bh) {
3370 cpu_unregister_map_client_do(client);
3371 break;
3374 qemu_mutex_unlock(&map_client_list_lock);
3377 static void cpu_notify_map_clients(void)
3379 qemu_mutex_lock(&map_client_list_lock);
3380 cpu_notify_map_clients_locked();
3381 qemu_mutex_unlock(&map_client_list_lock);
3384 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
3385 bool is_write)
3387 MemoryRegion *mr;
3388 hwaddr l, xlat;
3390 while (len > 0) {
3391 l = len;
3392 mr = flatview_translate(fv, addr, &xlat, &l, is_write);
3393 if (!memory_access_is_direct(mr, is_write)) {
3394 l = memory_access_size(mr, l, addr);
3395 if (!memory_region_access_valid(mr, xlat, l, is_write)) {
3396 rcu_read_unlock();
3397 return false;
3401 len -= l;
3402 addr += l;
3404 return true;
3407 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
3408 int len, bool is_write)
3410 FlatView *fv;
3411 bool result;
3413 rcu_read_lock();
3414 fv = address_space_to_flatview(as);
3415 result = flatview_access_valid(fv, addr, len, is_write);
3416 rcu_read_unlock();
3417 return result;
3420 static hwaddr
3421 flatview_extend_translation(FlatView *fv, hwaddr addr,
3422 hwaddr target_len,
3423 MemoryRegion *mr, hwaddr base, hwaddr len,
3424 bool is_write)
3426 hwaddr done = 0;
3427 hwaddr xlat;
3428 MemoryRegion *this_mr;
3430 for (;;) {
3431 target_len -= len;
3432 addr += len;
3433 done += len;
3434 if (target_len == 0) {
3435 return done;
3438 len = target_len;
3439 this_mr = flatview_translate(fv, addr, &xlat,
3440 &len, is_write);
3441 if (this_mr != mr || xlat != base + done) {
3442 return done;
3447 /* Map a physical memory region into a host virtual address.
3448 * May map a subset of the requested range, given by and returned in *plen.
3449 * May return NULL if resources needed to perform the mapping are exhausted.
3450 * Use only for reads OR writes - not for read-modify-write operations.
3451 * Use cpu_register_map_client() to know when retrying the map operation is
3452 * likely to succeed.
3454 void *address_space_map(AddressSpace *as,
3455 hwaddr addr,
3456 hwaddr *plen,
3457 bool is_write)
3459 hwaddr len = *plen;
3460 hwaddr l, xlat;
3461 MemoryRegion *mr;
3462 void *ptr;
3463 FlatView *fv;
3465 if (len == 0) {
3466 return NULL;
3469 l = len;
3470 rcu_read_lock();
3471 fv = address_space_to_flatview(as);
3472 mr = flatview_translate(fv, addr, &xlat, &l, is_write);
3474 if (!memory_access_is_direct(mr, is_write)) {
3475 if (atomic_xchg(&bounce.in_use, true)) {
3476 rcu_read_unlock();
3477 return NULL;
3479 /* Avoid unbounded allocations */
3480 l = MIN(l, TARGET_PAGE_SIZE);
3481 bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, l);
3482 bounce.addr = addr;
3483 bounce.len = l;
3485 memory_region_ref(mr);
3486 bounce.mr = mr;
3487 if (!is_write) {
3488 flatview_read(fv, addr, MEMTXATTRS_UNSPECIFIED,
3489 bounce.buffer, l);
3492 rcu_read_unlock();
3493 *plen = l;
3494 return bounce.buffer;
3498 memory_region_ref(mr);
3499 *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
3500 l, is_write);
3501 ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
3502 rcu_read_unlock();
3504 return ptr;
3507 /* Unmaps a memory region previously mapped by address_space_map().
3508 * Will also mark the memory as dirty if is_write == 1. access_len gives
3509 * the amount of memory that was actually read or written by the caller.
3511 void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
3512 int is_write, hwaddr access_len)
3514 if (buffer != bounce.buffer) {
3515 MemoryRegion *mr;
3516 ram_addr_t addr1;
3518 mr = memory_region_from_host(buffer, &addr1);
3519 assert(mr != NULL);
3520 if (is_write) {
3521 invalidate_and_set_dirty(mr, addr1, access_len);
3523 if (xen_enabled()) {
3524 xen_invalidate_map_cache_entry(buffer);
3526 memory_region_unref(mr);
3527 return;
3529 if (is_write) {
3530 address_space_write(as, bounce.addr, MEMTXATTRS_UNSPECIFIED,
3531 bounce.buffer, access_len);
3533 qemu_vfree(bounce.buffer);
3534 bounce.buffer = NULL;
3535 memory_region_unref(bounce.mr);
3536 atomic_mb_set(&bounce.in_use, false);
3537 cpu_notify_map_clients();
3540 void *cpu_physical_memory_map(hwaddr addr,
3541 hwaddr *plen,
3542 int is_write)
3544 return address_space_map(&address_space_memory, addr, plen, is_write);
3547 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
3548 int is_write, hwaddr access_len)
3550 return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len);
3553 #define ARG1_DECL AddressSpace *as
3554 #define ARG1 as
3555 #define SUFFIX
3556 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3557 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3558 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3559 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3560 #define RCU_READ_LOCK(...) rcu_read_lock()
3561 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3562 #include "memory_ldst.inc.c"
3564 int64_t address_space_cache_init(MemoryRegionCache *cache,
3565 AddressSpace *as,
3566 hwaddr addr,
3567 hwaddr len,
3568 bool is_write)
3570 cache->len = len;
3571 cache->as = as;
3572 cache->xlat = addr;
3573 return len;
3576 void address_space_cache_invalidate(MemoryRegionCache *cache,
3577 hwaddr addr,
3578 hwaddr access_len)
3582 void address_space_cache_destroy(MemoryRegionCache *cache)
3584 cache->as = NULL;
3587 #define ARG1_DECL MemoryRegionCache *cache
3588 #define ARG1 cache
3589 #define SUFFIX _cached
3590 #define TRANSLATE(addr, ...) \
3591 address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__)
3592 #define IS_DIRECT(mr, is_write) true
3593 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3594 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3595 #define RCU_READ_LOCK() rcu_read_lock()
3596 #define RCU_READ_UNLOCK() rcu_read_unlock()
3597 #include "memory_ldst.inc.c"
3599 /* virtual memory access for debug (includes writing to ROM) */
3600 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
3601 uint8_t *buf, int len, int is_write)
3603 int l;
3604 hwaddr phys_addr;
3605 target_ulong page;
3607 cpu_synchronize_state(cpu);
3608 while (len > 0) {
3609 int asidx;
3610 MemTxAttrs attrs;
3612 page = addr & TARGET_PAGE_MASK;
3613 phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
3614 asidx = cpu_asidx_from_attrs(cpu, attrs);
3615 /* if no physical page mapped, return an error */
3616 if (phys_addr == -1)
3617 return -1;
3618 l = (page + TARGET_PAGE_SIZE) - addr;
3619 if (l > len)
3620 l = len;
3621 phys_addr += (addr & ~TARGET_PAGE_MASK);
3622 if (is_write) {
3623 cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
3624 phys_addr, buf, l);
3625 } else {
3626 address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
3627 MEMTXATTRS_UNSPECIFIED,
3628 buf, l, 0);
3630 len -= l;
3631 buf += l;
3632 addr += l;
3634 return 0;
3638 * Allows code that needs to deal with migration bitmaps etc to still be built
3639 * target independent.
3641 size_t qemu_target_page_size(void)
3643 return TARGET_PAGE_SIZE;
3646 int qemu_target_page_bits(void)
3648 return TARGET_PAGE_BITS;
3651 int qemu_target_page_bits_min(void)
3653 return TARGET_PAGE_BITS_MIN;
3655 #endif
3658 * A helper function for the _utterly broken_ virtio device model to find out if
3659 * it's running on a big endian machine. Don't do this at home kids!
3661 bool target_words_bigendian(void);
3662 bool target_words_bigendian(void)
3664 #if defined(TARGET_WORDS_BIGENDIAN)
3665 return true;
3666 #else
3667 return false;
3668 #endif
3671 #ifndef CONFIG_USER_ONLY
3672 bool cpu_physical_memory_is_io(hwaddr phys_addr)
3674 MemoryRegion*mr;
3675 hwaddr l = 1;
3676 bool res;
3678 rcu_read_lock();
3679 mr = address_space_translate(&address_space_memory,
3680 phys_addr, &phys_addr, &l, false);
3682 res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
3683 rcu_read_unlock();
3684 return res;
3687 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque)
3689 RAMBlock *block;
3690 int ret = 0;
3692 rcu_read_lock();
3693 RAMBLOCK_FOREACH(block) {
3694 ret = func(block->idstr, block->host, block->offset,
3695 block->used_length, opaque);
3696 if (ret) {
3697 break;
3700 rcu_read_unlock();
3701 return ret;
3705 * Unmap pages of memory from start to start+length such that
3706 * they a) read as 0, b) Trigger whatever fault mechanism
3707 * the OS provides for postcopy.
3708 * The pages must be unmapped by the end of the function.
3709 * Returns: 0 on success, none-0 on failure
3712 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length)
3714 int ret = -1;
3716 uint8_t *host_startaddr = rb->host + start;
3718 if ((uintptr_t)host_startaddr & (rb->page_size - 1)) {
3719 error_report("ram_block_discard_range: Unaligned start address: %p",
3720 host_startaddr);
3721 goto err;
3724 if ((start + length) <= rb->used_length) {
3725 uint8_t *host_endaddr = host_startaddr + length;
3726 if ((uintptr_t)host_endaddr & (rb->page_size - 1)) {
3727 error_report("ram_block_discard_range: Unaligned end address: %p",
3728 host_endaddr);
3729 goto err;
3732 errno = ENOTSUP; /* If we are missing MADVISE etc */
3734 if (rb->page_size == qemu_host_page_size) {
3735 #if defined(CONFIG_MADVISE)
3736 /* Note: We need the madvise MADV_DONTNEED behaviour of definitely
3737 * freeing the page.
3739 ret = madvise(host_startaddr, length, MADV_DONTNEED);
3740 #endif
3741 } else {
3742 /* Huge page case - unfortunately it can't do DONTNEED, but
3743 * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the
3744 * huge page file.
3746 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3747 ret = fallocate(rb->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE,
3748 start, length);
3749 #endif
3751 if (ret) {
3752 ret = -errno;
3753 error_report("ram_block_discard_range: Failed to discard range "
3754 "%s:%" PRIx64 " +%zx (%d)",
3755 rb->idstr, start, length, ret);
3757 } else {
3758 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3759 "/%zx/" RAM_ADDR_FMT")",
3760 rb->idstr, start, length, rb->used_length);
3763 err:
3764 return ret;
3767 #endif
3769 void page_size_init(void)
3771 /* NOTE: we can always suppose that qemu_host_page_size >=
3772 TARGET_PAGE_SIZE */
3773 if (qemu_host_page_size == 0) {
3774 qemu_host_page_size = qemu_real_host_page_size;
3776 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
3777 qemu_host_page_size = TARGET_PAGE_SIZE;
3779 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
3782 #if !defined(CONFIG_USER_ONLY)
3784 static void mtree_print_phys_entries(fprintf_function mon, void *f,
3785 int start, int end, int skip, int ptr)
3787 if (start == end - 1) {
3788 mon(f, "\t%3d ", start);
3789 } else {
3790 mon(f, "\t%3d..%-3d ", start, end - 1);
3792 mon(f, " skip=%d ", skip);
3793 if (ptr == PHYS_MAP_NODE_NIL) {
3794 mon(f, " ptr=NIL");
3795 } else if (!skip) {
3796 mon(f, " ptr=#%d", ptr);
3797 } else {
3798 mon(f, " ptr=[%d]", ptr);
3800 mon(f, "\n");
3803 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
3804 int128_sub((size), int128_one())) : 0)
3806 void mtree_print_dispatch(fprintf_function mon, void *f,
3807 AddressSpaceDispatch *d, MemoryRegion *root)
3809 int i;
3811 mon(f, " Dispatch\n");
3812 mon(f, " Physical sections\n");
3814 for (i = 0; i < d->map.sections_nb; ++i) {
3815 MemoryRegionSection *s = d->map.sections + i;
3816 const char *names[] = { " [unassigned]", " [not dirty]",
3817 " [ROM]", " [watch]" };
3819 mon(f, " #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx " %s%s%s%s%s",
3821 s->offset_within_address_space,
3822 s->offset_within_address_space + MR_SIZE(s->mr->size),
3823 s->mr->name ? s->mr->name : "(noname)",
3824 i < ARRAY_SIZE(names) ? names[i] : "",
3825 s->mr == root ? " [ROOT]" : "",
3826 s == d->mru_section ? " [MRU]" : "",
3827 s->mr->is_iommu ? " [iommu]" : "");
3829 if (s->mr->alias) {
3830 mon(f, " alias=%s", s->mr->alias->name ?
3831 s->mr->alias->name : "noname");
3833 mon(f, "\n");
3836 mon(f, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
3837 P_L2_BITS, P_L2_LEVELS, d->phys_map.ptr, d->phys_map.skip);
3838 for (i = 0; i < d->map.nodes_nb; ++i) {
3839 int j, jprev;
3840 PhysPageEntry prev;
3841 Node *n = d->map.nodes + i;
3843 mon(f, " [%d]\n", i);
3845 for (j = 0, jprev = 0, prev = *n[0]; j < ARRAY_SIZE(*n); ++j) {
3846 PhysPageEntry *pe = *n + j;
3848 if (pe->ptr == prev.ptr && pe->skip == prev.skip) {
3849 continue;
3852 mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr);
3854 jprev = j;
3855 prev = *pe;
3858 if (jprev != ARRAY_SIZE(*n)) {
3859 mtree_print_phys_entries(mon, f, jprev, j, prev.skip, prev.ptr);
3864 #endif