4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
29 #include "translate.h"
30 #include "internals.h"
31 #include "qemu/host-utils.h"
33 #include "exec/gen-icount.h"
35 #include "exec/helper-proto.h"
36 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
40 static TCGv_i64 cpu_X
[32];
41 static TCGv_i64 cpu_pc
;
42 static TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
44 /* Load/store exclusive handling */
45 static TCGv_i64 cpu_exclusive_addr
;
46 static TCGv_i64 cpu_exclusive_val
;
47 static TCGv_i64 cpu_exclusive_high
;
48 #ifdef CONFIG_USER_ONLY
49 static TCGv_i64 cpu_exclusive_test
;
50 static TCGv_i32 cpu_exclusive_info
;
53 static const char *regnames
[] = {
54 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
55 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
56 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
57 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
61 A64_SHIFT_TYPE_LSL
= 0,
62 A64_SHIFT_TYPE_LSR
= 1,
63 A64_SHIFT_TYPE_ASR
= 2,
64 A64_SHIFT_TYPE_ROR
= 3
67 /* Table based decoder typedefs - used when the relevant bits for decode
68 * are too awkwardly scattered across the instruction (eg SIMD).
70 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
72 typedef struct AArch64DecodeTable
{
75 AArch64DecodeFn
*disas_fn
;
78 /* Function prototype for gen_ functions for calling Neon helpers */
79 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
80 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
81 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
82 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
83 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
84 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
85 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
86 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
87 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
88 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
89 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
90 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
91 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
93 /* initialize TCG globals. */
94 void a64_translate_init(void)
98 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
99 offsetof(CPUARMState
, pc
),
101 for (i
= 0; i
< 32; i
++) {
102 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
103 offsetof(CPUARMState
, xregs
[i
]),
107 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
108 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
109 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
110 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
112 cpu_exclusive_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
113 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
114 cpu_exclusive_val
= tcg_global_mem_new_i64(TCG_AREG0
,
115 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
116 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
117 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
118 #ifdef CONFIG_USER_ONLY
119 cpu_exclusive_test
= tcg_global_mem_new_i64(TCG_AREG0
,
120 offsetof(CPUARMState
, exclusive_test
), "exclusive_test");
121 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
122 offsetof(CPUARMState
, exclusive_info
), "exclusive_info");
126 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
127 fprintf_function cpu_fprintf
, int flags
)
129 ARMCPU
*cpu
= ARM_CPU(cs
);
130 CPUARMState
*env
= &cpu
->env
;
131 uint32_t psr
= pstate_read(env
);
134 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
135 env
->pc
, env
->xregs
[31]);
136 for (i
= 0; i
< 31; i
++) {
137 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
139 cpu_fprintf(f
, "\n");
144 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
146 psr
& PSTATE_N
? 'N' : '-',
147 psr
& PSTATE_Z
? 'Z' : '-',
148 psr
& PSTATE_C
? 'C' : '-',
149 psr
& PSTATE_V
? 'V' : '-');
150 cpu_fprintf(f
, "\n");
152 if (flags
& CPU_DUMP_FPU
) {
154 for (i
= 0; i
< numvfpregs
; i
+= 2) {
155 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
156 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
157 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
159 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
160 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
161 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
164 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
165 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
169 void gen_a64_set_pc_im(uint64_t val
)
171 tcg_gen_movi_i64(cpu_pc
, val
);
174 static void gen_exception_internal(int excp
)
176 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
178 assert(excp_is_internal(excp
));
179 gen_helper_exception_internal(cpu_env
, tcg_excp
);
180 tcg_temp_free_i32(tcg_excp
);
183 static void gen_exception(int excp
, uint32_t syndrome
)
185 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
186 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
188 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
, tcg_syn
);
189 tcg_temp_free_i32(tcg_syn
);
190 tcg_temp_free_i32(tcg_excp
);
193 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
195 gen_a64_set_pc_im(s
->pc
- offset
);
196 gen_exception_internal(excp
);
197 s
->is_jmp
= DISAS_EXC
;
200 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
203 gen_a64_set_pc_im(s
->pc
- offset
);
204 gen_exception(excp
, syndrome
);
205 s
->is_jmp
= DISAS_EXC
;
208 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
210 /* No direct tb linking with singlestep or deterministic io */
211 if (s
->singlestep_enabled
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
215 /* Only link tbs from inside the same guest page */
216 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
223 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
225 TranslationBlock
*tb
;
228 if (use_goto_tb(s
, n
, dest
)) {
230 gen_a64_set_pc_im(dest
);
231 tcg_gen_exit_tb((intptr_t)tb
+ n
);
232 s
->is_jmp
= DISAS_TB_JUMP
;
234 gen_a64_set_pc_im(dest
);
235 if (s
->singlestep_enabled
) {
236 gen_exception_internal(EXCP_DEBUG
);
239 s
->is_jmp
= DISAS_JUMP
;
243 static void unallocated_encoding(DisasContext
*s
)
245 /* Unallocated and reserved encodings are uncategorized */
246 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized());
249 #define unsupported_encoding(s, insn) \
251 qemu_log_mask(LOG_UNIMP, \
252 "%s:%d: unsupported instruction encoding 0x%08x " \
253 "at pc=%016" PRIx64 "\n", \
254 __FILE__, __LINE__, insn, s->pc - 4); \
255 unallocated_encoding(s); \
258 static void init_tmp_a64_array(DisasContext
*s
)
260 #ifdef CONFIG_DEBUG_TCG
262 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
263 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
266 s
->tmp_a64_count
= 0;
269 static void free_tmp_a64(DisasContext
*s
)
272 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
273 tcg_temp_free_i64(s
->tmp_a64
[i
]);
275 init_tmp_a64_array(s
);
278 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
280 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
281 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
284 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
286 TCGv_i64 t
= new_tmp_a64(s
);
287 tcg_gen_movi_i64(t
, 0);
292 * Register access functions
294 * These functions are used for directly accessing a register in where
295 * changes to the final register value are likely to be made. If you
296 * need to use a register for temporary calculation (e.g. index type
297 * operations) use the read_* form.
299 * B1.2.1 Register mappings
301 * In instruction register encoding 31 can refer to ZR (zero register) or
302 * the SP (stack pointer) depending on context. In QEMU's case we map SP
303 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
304 * This is the point of the _sp forms.
306 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
309 return new_tmp_a64_zero(s
);
315 /* register access for when 31 == SP */
316 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
321 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
322 * representing the register contents. This TCGv is an auto-freed
323 * temporary so it need not be explicitly freed, and may be modified.
325 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
327 TCGv_i64 v
= new_tmp_a64(s
);
330 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
332 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
335 tcg_gen_movi_i64(v
, 0);
340 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
342 TCGv_i64 v
= new_tmp_a64(s
);
344 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
346 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
351 /* We should have at some point before trying to access an FP register
352 * done the necessary access check, so assert that
353 * (a) we did the check and
354 * (b) we didn't then just plough ahead anyway if it failed.
355 * Print the instruction pattern in the abort message so we can figure
356 * out what we need to fix if a user encounters this problem in the wild.
358 static inline void assert_fp_access_checked(DisasContext
*s
)
360 #ifdef CONFIG_DEBUG_TCG
361 if (unlikely(!s
->fp_access_checked
|| !s
->cpacr_fpen
)) {
362 fprintf(stderr
, "target-arm: FP access check missing for "
363 "instruction 0x%08x\n", s
->insn
);
369 /* Return the offset into CPUARMState of an element of specified
370 * size, 'element' places in from the least significant end of
371 * the FP/vector register Qn.
373 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
374 int element
, TCGMemOp size
)
376 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
377 #ifdef HOST_WORDS_BIGENDIAN
378 /* This is complicated slightly because vfp.regs[2n] is
379 * still the low half and vfp.regs[2n+1] the high half
380 * of the 128 bit vector, even on big endian systems.
381 * Calculate the offset assuming a fully bigendian 128 bits,
382 * then XOR to account for the order of the two 64 bit halves.
384 offs
+= (16 - ((element
+ 1) * (1 << size
)));
387 offs
+= element
* (1 << size
);
389 assert_fp_access_checked(s
);
393 /* Return the offset into CPUARMState of a slice (from
394 * the least significant end) of FP register Qn (ie
396 * (Note that this is not the same mapping as for A32; see cpu.h)
398 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
400 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
401 #ifdef HOST_WORDS_BIGENDIAN
402 offs
+= (8 - (1 << size
));
404 assert_fp_access_checked(s
);
408 /* Offset of the high half of the 128 bit vector Qn */
409 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
411 assert_fp_access_checked(s
);
412 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
415 /* Convenience accessors for reading and writing single and double
416 * FP registers. Writing clears the upper parts of the associated
417 * 128 bit vector register, as required by the architecture.
418 * Note that unlike the GP register accessors, the values returned
419 * by the read functions must be manually freed.
421 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
423 TCGv_i64 v
= tcg_temp_new_i64();
425 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
429 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
431 TCGv_i32 v
= tcg_temp_new_i32();
433 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
437 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
439 TCGv_i64 tcg_zero
= tcg_const_i64(0);
441 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
442 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
443 tcg_temp_free_i64(tcg_zero
);
446 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
448 TCGv_i64 tmp
= tcg_temp_new_i64();
450 tcg_gen_extu_i32_i64(tmp
, v
);
451 write_fp_dreg(s
, reg
, tmp
);
452 tcg_temp_free_i64(tmp
);
455 static TCGv_ptr
get_fpstatus_ptr(void)
457 TCGv_ptr statusptr
= tcg_temp_new_ptr();
460 /* In A64 all instructions (both FP and Neon) use the FPCR;
461 * there is no equivalent of the A32 Neon "standard FPSCR value"
462 * and all operations use vfp.fp_status.
464 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
465 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
469 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
470 * than the 32 bit equivalent.
472 static inline void gen_set_NZ64(TCGv_i64 result
)
474 TCGv_i64 flag
= tcg_temp_new_i64();
476 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
477 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
478 tcg_gen_shri_i64(flag
, result
, 32);
479 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
480 tcg_temp_free_i64(flag
);
483 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
484 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
487 gen_set_NZ64(result
);
489 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
490 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
492 tcg_gen_movi_i32(cpu_CF
, 0);
493 tcg_gen_movi_i32(cpu_VF
, 0);
496 /* dest = T0 + T1; compute C, N, V and Z flags */
497 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
500 TCGv_i64 result
, flag
, tmp
;
501 result
= tcg_temp_new_i64();
502 flag
= tcg_temp_new_i64();
503 tmp
= tcg_temp_new_i64();
505 tcg_gen_movi_i64(tmp
, 0);
506 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
508 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
510 gen_set_NZ64(result
);
512 tcg_gen_xor_i64(flag
, result
, t0
);
513 tcg_gen_xor_i64(tmp
, t0
, t1
);
514 tcg_gen_andc_i64(flag
, flag
, tmp
);
515 tcg_temp_free_i64(tmp
);
516 tcg_gen_shri_i64(flag
, flag
, 32);
517 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
519 tcg_gen_mov_i64(dest
, result
);
520 tcg_temp_free_i64(result
);
521 tcg_temp_free_i64(flag
);
523 /* 32 bit arithmetic */
524 TCGv_i32 t0_32
= tcg_temp_new_i32();
525 TCGv_i32 t1_32
= tcg_temp_new_i32();
526 TCGv_i32 tmp
= tcg_temp_new_i32();
528 tcg_gen_movi_i32(tmp
, 0);
529 tcg_gen_trunc_i64_i32(t0_32
, t0
);
530 tcg_gen_trunc_i64_i32(t1_32
, t1
);
531 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
532 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
533 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
534 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
535 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
536 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
538 tcg_temp_free_i32(tmp
);
539 tcg_temp_free_i32(t0_32
);
540 tcg_temp_free_i32(t1_32
);
544 /* dest = T0 - T1; compute C, N, V and Z flags */
545 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
548 /* 64 bit arithmetic */
549 TCGv_i64 result
, flag
, tmp
;
551 result
= tcg_temp_new_i64();
552 flag
= tcg_temp_new_i64();
553 tcg_gen_sub_i64(result
, t0
, t1
);
555 gen_set_NZ64(result
);
557 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
558 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
560 tcg_gen_xor_i64(flag
, result
, t0
);
561 tmp
= tcg_temp_new_i64();
562 tcg_gen_xor_i64(tmp
, t0
, t1
);
563 tcg_gen_and_i64(flag
, flag
, tmp
);
564 tcg_temp_free_i64(tmp
);
565 tcg_gen_shri_i64(flag
, flag
, 32);
566 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
567 tcg_gen_mov_i64(dest
, result
);
568 tcg_temp_free_i64(flag
);
569 tcg_temp_free_i64(result
);
571 /* 32 bit arithmetic */
572 TCGv_i32 t0_32
= tcg_temp_new_i32();
573 TCGv_i32 t1_32
= tcg_temp_new_i32();
576 tcg_gen_trunc_i64_i32(t0_32
, t0
);
577 tcg_gen_trunc_i64_i32(t1_32
, t1
);
578 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
579 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
580 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
581 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
582 tmp
= tcg_temp_new_i32();
583 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
584 tcg_temp_free_i32(t0_32
);
585 tcg_temp_free_i32(t1_32
);
586 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
587 tcg_temp_free_i32(tmp
);
588 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
592 /* dest = T0 + T1 + CF; do not compute flags. */
593 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
595 TCGv_i64 flag
= tcg_temp_new_i64();
596 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
597 tcg_gen_add_i64(dest
, t0
, t1
);
598 tcg_gen_add_i64(dest
, dest
, flag
);
599 tcg_temp_free_i64(flag
);
602 tcg_gen_ext32u_i64(dest
, dest
);
606 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
607 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
610 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
611 result
= tcg_temp_new_i64();
612 cf_64
= tcg_temp_new_i64();
613 vf_64
= tcg_temp_new_i64();
614 tmp
= tcg_const_i64(0);
616 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
617 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
618 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
619 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
620 gen_set_NZ64(result
);
622 tcg_gen_xor_i64(vf_64
, result
, t0
);
623 tcg_gen_xor_i64(tmp
, t0
, t1
);
624 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
625 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
626 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
628 tcg_gen_mov_i64(dest
, result
);
630 tcg_temp_free_i64(tmp
);
631 tcg_temp_free_i64(vf_64
);
632 tcg_temp_free_i64(cf_64
);
633 tcg_temp_free_i64(result
);
635 TCGv_i32 t0_32
, t1_32
, tmp
;
636 t0_32
= tcg_temp_new_i32();
637 t1_32
= tcg_temp_new_i32();
638 tmp
= tcg_const_i32(0);
640 tcg_gen_trunc_i64_i32(t0_32
, t0
);
641 tcg_gen_trunc_i64_i32(t1_32
, t1
);
642 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
643 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
645 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
646 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
647 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
648 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
649 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
651 tcg_temp_free_i32(tmp
);
652 tcg_temp_free_i32(t1_32
);
653 tcg_temp_free_i32(t0_32
);
658 * Load/Store generators
662 * Store from GPR register to memory.
664 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
665 TCGv_i64 tcg_addr
, int size
, int memidx
)
668 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
671 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
672 TCGv_i64 tcg_addr
, int size
)
674 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
678 * Load from memory to GPR register
680 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
681 int size
, bool is_signed
, bool extend
, int memidx
)
683 TCGMemOp memop
= MO_TE
+ size
;
691 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
693 if (extend
&& is_signed
) {
695 tcg_gen_ext32u_i64(dest
, dest
);
699 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
700 int size
, bool is_signed
, bool extend
)
702 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
707 * Store from FP register to memory
709 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
711 /* This writes the bottom N bits of a 128 bit wide vector to memory */
712 TCGv_i64 tmp
= tcg_temp_new_i64();
713 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
715 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
717 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
718 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
719 tcg_gen_qemu_st64(tmp
, tcg_addr
, get_mem_index(s
));
720 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
721 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
722 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
723 tcg_temp_free_i64(tcg_hiaddr
);
726 tcg_temp_free_i64(tmp
);
730 * Load from memory to FP register
732 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
734 /* This always zero-extends and writes to a full 128 bit wide vector */
735 TCGv_i64 tmplo
= tcg_temp_new_i64();
739 TCGMemOp memop
= MO_TE
+ size
;
740 tmphi
= tcg_const_i64(0);
741 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
744 tmphi
= tcg_temp_new_i64();
745 tcg_hiaddr
= tcg_temp_new_i64();
747 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
748 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
749 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
750 tcg_temp_free_i64(tcg_hiaddr
);
753 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
754 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
756 tcg_temp_free_i64(tmplo
);
757 tcg_temp_free_i64(tmphi
);
761 * Vector load/store helpers.
763 * The principal difference between this and a FP load is that we don't
764 * zero extend as we are filling a partial chunk of the vector register.
765 * These functions don't support 128 bit loads/stores, which would be
766 * normal load/store operations.
768 * The _i32 versions are useful when operating on 32 bit quantities
769 * (eg for floating point single or using Neon helper functions).
772 /* Get value of an element within a vector register */
773 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
774 int element
, TCGMemOp memop
)
776 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
779 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
782 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
785 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
788 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
791 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
794 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
798 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
801 g_assert_not_reached();
805 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
806 int element
, TCGMemOp memop
)
808 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
811 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
814 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
817 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
820 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
824 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
827 g_assert_not_reached();
831 /* Set value of an element within a vector register */
832 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
833 int element
, TCGMemOp memop
)
835 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
838 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
841 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
844 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
847 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
850 g_assert_not_reached();
854 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
855 int destidx
, int element
, TCGMemOp memop
)
857 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
860 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
863 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
866 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
869 g_assert_not_reached();
873 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
874 * vector ops all need to do this).
876 static void clear_vec_high(DisasContext
*s
, int rd
)
878 TCGv_i64 tcg_zero
= tcg_const_i64(0);
880 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
881 tcg_temp_free_i64(tcg_zero
);
884 /* Store from vector register to memory */
885 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
886 TCGv_i64 tcg_addr
, int size
)
888 TCGMemOp memop
= MO_TE
+ size
;
889 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
891 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
892 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
894 tcg_temp_free_i64(tcg_tmp
);
897 /* Load from memory to vector register */
898 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
899 TCGv_i64 tcg_addr
, int size
)
901 TCGMemOp memop
= MO_TE
+ size
;
902 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
904 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
905 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
907 tcg_temp_free_i64(tcg_tmp
);
910 /* Check that FP/Neon access is enabled. If it is, return
911 * true. If not, emit code to generate an appropriate exception,
912 * and return false; the caller should not emit any code for
913 * the instruction. Note that this check must happen after all
914 * unallocated-encoding checks (otherwise the syndrome information
915 * for the resulting exception will be incorrect).
917 static inline bool fp_access_check(DisasContext
*s
)
919 assert(!s
->fp_access_checked
);
920 s
->fp_access_checked
= true;
926 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false));
931 * This utility function is for doing register extension with an
932 * optional shift. You will likely want to pass a temporary for the
933 * destination register. See DecodeRegExtend() in the ARM ARM.
935 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
936 int option
, unsigned int shift
)
938 int extsize
= extract32(option
, 0, 2);
939 bool is_signed
= extract32(option
, 2, 1);
944 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
947 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
950 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
953 tcg_gen_mov_i64(tcg_out
, tcg_in
);
959 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
962 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
965 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
968 tcg_gen_mov_i64(tcg_out
, tcg_in
);
974 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
978 static inline void gen_check_sp_alignment(DisasContext
*s
)
980 /* The AArch64 architecture mandates that (if enabled via PSTATE
981 * or SCTLR bits) there is a check that SP is 16-aligned on every
982 * SP-relative load or store (with an exception generated if it is not).
983 * In line with general QEMU practice regarding misaligned accesses,
984 * we omit these checks for the sake of guest program performance.
985 * This function is provided as a hook so we can more easily add these
986 * checks in future (possibly as a "favour catching guest program bugs
987 * over speed" user selectable option).
992 * This provides a simple table based table lookup decoder. It is
993 * intended to be used when the relevant bits for decode are too
994 * awkwardly placed and switch/if based logic would be confusing and
995 * deeply nested. Since it's a linear search through the table, tables
996 * should be kept small.
998 * It returns the first handler where insn & mask == pattern, or
999 * NULL if there is no match.
1000 * The table is terminated by an empty mask (i.e. 0)
1002 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1005 const AArch64DecodeTable
*tptr
= table
;
1007 while (tptr
->mask
) {
1008 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1009 return tptr
->disas_fn
;
1017 * the instruction disassembly implemented here matches
1018 * the instruction encoding classifications in chapter 3 (C3)
1019 * of the ARM Architecture Reference Manual (DDI0487A_a)
1022 /* C3.2.7 Unconditional branch (immediate)
1024 * +----+-----------+-------------------------------------+
1025 * | op | 0 0 1 0 1 | imm26 |
1026 * +----+-----------+-------------------------------------+
1028 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1030 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1032 if (insn
& (1 << 31)) {
1033 /* C5.6.26 BL Branch with link */
1034 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1037 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1038 gen_goto_tb(s
, 0, addr
);
1041 /* C3.2.1 Compare & branch (immediate)
1042 * 31 30 25 24 23 5 4 0
1043 * +----+-------------+----+---------------------+--------+
1044 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1045 * +----+-------------+----+---------------------+--------+
1047 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1049 unsigned int sf
, op
, rt
;
1054 sf
= extract32(insn
, 31, 1);
1055 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1056 rt
= extract32(insn
, 0, 5);
1057 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1059 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1060 label_match
= gen_new_label();
1062 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1063 tcg_cmp
, 0, label_match
);
1065 gen_goto_tb(s
, 0, s
->pc
);
1066 gen_set_label(label_match
);
1067 gen_goto_tb(s
, 1, addr
);
1070 /* C3.2.5 Test & branch (immediate)
1071 * 31 30 25 24 23 19 18 5 4 0
1072 * +----+-------------+----+-------+-------------+------+
1073 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1074 * +----+-------------+----+-------+-------------+------+
1076 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1078 unsigned int bit_pos
, op
, rt
;
1083 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1084 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1085 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1086 rt
= extract32(insn
, 0, 5);
1088 tcg_cmp
= tcg_temp_new_i64();
1089 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1090 label_match
= gen_new_label();
1091 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1092 tcg_cmp
, 0, label_match
);
1093 tcg_temp_free_i64(tcg_cmp
);
1094 gen_goto_tb(s
, 0, s
->pc
);
1095 gen_set_label(label_match
);
1096 gen_goto_tb(s
, 1, addr
);
1099 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1100 * 31 25 24 23 5 4 3 0
1101 * +---------------+----+---------------------+----+------+
1102 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1103 * +---------------+----+---------------------+----+------+
1105 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1110 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1111 unallocated_encoding(s
);
1114 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1115 cond
= extract32(insn
, 0, 4);
1118 /* genuinely conditional branches */
1119 int label_match
= gen_new_label();
1120 arm_gen_test_cc(cond
, label_match
);
1121 gen_goto_tb(s
, 0, s
->pc
);
1122 gen_set_label(label_match
);
1123 gen_goto_tb(s
, 1, addr
);
1125 /* 0xe and 0xf are both "always" conditions */
1126 gen_goto_tb(s
, 0, addr
);
1131 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1132 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1134 unsigned int selector
= crm
<< 3 | op2
;
1137 unallocated_encoding(s
);
1145 s
->is_jmp
= DISAS_WFI
;
1149 s
->is_jmp
= DISAS_WFE
;
1153 /* we treat all as NOP at least for now */
1156 /* default specified as NOP equivalent */
1161 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1163 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1166 /* CLREX, DSB, DMB, ISB */
1167 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1168 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1171 unallocated_encoding(s
);
1182 /* We don't emulate caches so barriers are no-ops */
1185 unallocated_encoding(s
);
1190 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1191 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1192 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1194 int op
= op1
<< 3 | op2
;
1196 case 0x05: /* SPSel */
1197 if (s
->current_pl
== 0) {
1198 unallocated_encoding(s
);
1202 case 0x1e: /* DAIFSet */
1203 case 0x1f: /* DAIFClear */
1205 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1206 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1207 gen_a64_set_pc_im(s
->pc
- 4);
1208 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1209 tcg_temp_free_i32(tcg_imm
);
1210 tcg_temp_free_i32(tcg_op
);
1211 s
->is_jmp
= DISAS_UPDATE
;
1215 unallocated_encoding(s
);
1220 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1222 TCGv_i32 tmp
= tcg_temp_new_i32();
1223 TCGv_i32 nzcv
= tcg_temp_new_i32();
1225 /* build bit 31, N */
1226 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1 << 31));
1227 /* build bit 30, Z */
1228 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1229 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1230 /* build bit 29, C */
1231 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1232 /* build bit 28, V */
1233 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1234 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1235 /* generate result */
1236 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1238 tcg_temp_free_i32(nzcv
);
1239 tcg_temp_free_i32(tmp
);
1242 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1245 TCGv_i32 nzcv
= tcg_temp_new_i32();
1247 /* take NZCV from R[t] */
1248 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
1251 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1 << 31));
1253 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1254 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1256 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1257 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1259 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1260 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1261 tcg_temp_free_i32(nzcv
);
1264 /* C5.6.129 MRS - move from system register
1265 * C5.6.131 MSR (register) - move to system register
1268 * These are all essentially the same insn in 'read' and 'write'
1269 * versions, with varying op0 fields.
1271 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1272 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1273 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1275 const ARMCPRegInfo
*ri
;
1278 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1279 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1280 crn
, crm
, op0
, op1
, op2
));
1283 /* Unknown register; this might be a guest error or a QEMU
1284 * unimplemented feature.
1286 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1287 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1288 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1289 unallocated_encoding(s
);
1293 /* Check access permissions */
1294 if (!cp_access_ok(s
->current_pl
, ri
, isread
)) {
1295 unallocated_encoding(s
);
1300 /* Emit code to perform further access permissions checks at
1301 * runtime; this may result in an exception.
1307 gen_a64_set_pc_im(s
->pc
- 4);
1308 tmpptr
= tcg_const_ptr(ri
);
1309 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1310 tcg_syn
= tcg_const_i32(syndrome
);
1311 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
);
1312 tcg_temp_free_ptr(tmpptr
);
1313 tcg_temp_free_i32(tcg_syn
);
1316 /* Handle special cases first */
1317 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1321 tcg_rt
= cpu_reg(s
, rt
);
1323 gen_get_nzcv(tcg_rt
);
1325 gen_set_nzcv(tcg_rt
);
1328 case ARM_CP_CURRENTEL
:
1329 /* Reads as current EL value from pstate, which is
1330 * guaranteed to be constant by the tb flags.
1332 tcg_rt
= cpu_reg(s
, rt
);
1333 tcg_gen_movi_i64(tcg_rt
, s
->current_pl
<< 2);
1336 /* Writes clear the aligned block of memory which rt points into. */
1337 tcg_rt
= cpu_reg(s
, rt
);
1338 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1344 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1348 tcg_rt
= cpu_reg(s
, rt
);
1351 if (ri
->type
& ARM_CP_CONST
) {
1352 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1353 } else if (ri
->readfn
) {
1355 tmpptr
= tcg_const_ptr(ri
);
1356 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1357 tcg_temp_free_ptr(tmpptr
);
1359 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1362 if (ri
->type
& ARM_CP_CONST
) {
1363 /* If not forbidden by access permissions, treat as WI */
1365 } else if (ri
->writefn
) {
1367 tmpptr
= tcg_const_ptr(ri
);
1368 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1369 tcg_temp_free_ptr(tmpptr
);
1371 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1375 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1376 /* I/O operations must end the TB here (whether read or write) */
1378 s
->is_jmp
= DISAS_UPDATE
;
1379 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1380 /* We default to ending the TB on a coprocessor register write,
1381 * but allow this to be suppressed by the register definition
1382 * (usually only necessary to work around guest bugs).
1384 s
->is_jmp
= DISAS_UPDATE
;
1389 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1390 * +---------------------+---+-----+-----+-------+-------+-----+------+
1391 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1392 * +---------------------+---+-----+-----+-------+-------+-----+------+
1394 static void disas_system(DisasContext
*s
, uint32_t insn
)
1396 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1397 l
= extract32(insn
, 21, 1);
1398 op0
= extract32(insn
, 19, 2);
1399 op1
= extract32(insn
, 16, 3);
1400 crn
= extract32(insn
, 12, 4);
1401 crm
= extract32(insn
, 8, 4);
1402 op2
= extract32(insn
, 5, 3);
1403 rt
= extract32(insn
, 0, 5);
1406 if (l
|| rt
!= 31) {
1407 unallocated_encoding(s
);
1411 case 2: /* C5.6.68 HINT */
1412 handle_hint(s
, insn
, op1
, op2
, crm
);
1414 case 3: /* CLREX, DSB, DMB, ISB */
1415 handle_sync(s
, insn
, op1
, op2
, crm
);
1417 case 4: /* C5.6.130 MSR (immediate) */
1418 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1421 unallocated_encoding(s
);
1426 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1429 /* C3.2.3 Exception generation
1431 * 31 24 23 21 20 5 4 2 1 0
1432 * +-----------------+-----+------------------------+-----+----+
1433 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1434 * +-----------------------+------------------------+----------+
1436 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1438 int opc
= extract32(insn
, 21, 3);
1439 int op2_ll
= extract32(insn
, 0, 5);
1440 int imm16
= extract32(insn
, 5, 16);
1444 /* SVC, HVC, SMC; since we don't support the Virtualization
1445 * or TrustZone extensions these all UNDEF except SVC.
1448 unallocated_encoding(s
);
1451 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
));
1455 unallocated_encoding(s
);
1459 gen_exception_insn(s
, 0, EXCP_BKPT
, syn_aa64_bkpt(imm16
));
1463 unallocated_encoding(s
);
1467 unsupported_encoding(s
, insn
);
1470 if (op2_ll
< 1 || op2_ll
> 3) {
1471 unallocated_encoding(s
);
1474 /* DCPS1, DCPS2, DCPS3 */
1475 unsupported_encoding(s
, insn
);
1478 unallocated_encoding(s
);
1483 /* C3.2.7 Unconditional branch (register)
1484 * 31 25 24 21 20 16 15 10 9 5 4 0
1485 * +---------------+-------+-------+-------+------+-------+
1486 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1487 * +---------------+-------+-------+-------+------+-------+
1489 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1491 unsigned int opc
, op2
, op3
, rn
, op4
;
1493 opc
= extract32(insn
, 21, 4);
1494 op2
= extract32(insn
, 16, 5);
1495 op3
= extract32(insn
, 10, 6);
1496 rn
= extract32(insn
, 5, 5);
1497 op4
= extract32(insn
, 0, 5);
1499 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1500 unallocated_encoding(s
);
1507 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1510 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1511 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1514 if (s
->current_pl
== 0) {
1515 unallocated_encoding(s
);
1518 gen_helper_exception_return(cpu_env
);
1519 s
->is_jmp
= DISAS_JUMP
;
1523 unallocated_encoding(s
);
1525 unsupported_encoding(s
, insn
);
1529 unallocated_encoding(s
);
1533 s
->is_jmp
= DISAS_JUMP
;
1536 /* C3.2 Branches, exception generating and system instructions */
1537 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1539 switch (extract32(insn
, 25, 7)) {
1540 case 0x0a: case 0x0b:
1541 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1542 disas_uncond_b_imm(s
, insn
);
1544 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1545 disas_comp_b_imm(s
, insn
);
1547 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1548 disas_test_b_imm(s
, insn
);
1550 case 0x2a: /* Conditional branch (immediate) */
1551 disas_cond_b_imm(s
, insn
);
1553 case 0x6a: /* Exception generation / System */
1554 if (insn
& (1 << 24)) {
1555 disas_system(s
, insn
);
1560 case 0x6b: /* Unconditional branch (register) */
1561 disas_uncond_b_reg(s
, insn
);
1564 unallocated_encoding(s
);
1570 * Load/Store exclusive instructions are implemented by remembering
1571 * the value/address loaded, and seeing if these are the same
1572 * when the store is performed. This is not actually the architecturally
1573 * mandated semantics, but it works for typical guest code sequences
1574 * and avoids having to monitor regular stores.
1576 * In system emulation mode only one CPU will be running at once, so
1577 * this sequence is effectively atomic. In user emulation mode we
1578 * throw an exception and handle the atomic operation elsewhere.
1580 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1581 TCGv_i64 addr
, int size
, bool is_pair
)
1583 TCGv_i64 tmp
= tcg_temp_new_i64();
1584 TCGMemOp memop
= MO_TE
+ size
;
1586 g_assert(size
<= 3);
1587 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1590 TCGv_i64 addr2
= tcg_temp_new_i64();
1591 TCGv_i64 hitmp
= tcg_temp_new_i64();
1593 g_assert(size
>= 2);
1594 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1595 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1596 tcg_temp_free_i64(addr2
);
1597 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1598 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1599 tcg_temp_free_i64(hitmp
);
1602 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1603 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1605 tcg_temp_free_i64(tmp
);
1606 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1609 #ifdef CONFIG_USER_ONLY
1610 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1611 TCGv_i64 addr
, int size
, int is_pair
)
1613 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1614 tcg_gen_movi_i32(cpu_exclusive_info
,
1615 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1616 gen_exception_internal_insn(s
, 4, EXCP_STREX
);
1619 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1620 TCGv_i64 inaddr
, int size
, int is_pair
)
1622 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1623 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1626 * [addr + datasize] = {Rt2};
1632 * env->exclusive_addr = -1;
1634 int fail_label
= gen_new_label();
1635 int done_label
= gen_new_label();
1636 TCGv_i64 addr
= tcg_temp_local_new_i64();
1639 /* Copy input into a local temp so it is not trashed when the
1640 * basic block ends at the branch insn.
1642 tcg_gen_mov_i64(addr
, inaddr
);
1643 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1645 tmp
= tcg_temp_new_i64();
1646 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1647 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1648 tcg_temp_free_i64(tmp
);
1651 TCGv_i64 addrhi
= tcg_temp_new_i64();
1652 TCGv_i64 tmphi
= tcg_temp_new_i64();
1654 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1655 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1656 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1658 tcg_temp_free_i64(tmphi
);
1659 tcg_temp_free_i64(addrhi
);
1662 /* We seem to still have the exclusive monitor, so do the store */
1663 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1665 TCGv_i64 addrhi
= tcg_temp_new_i64();
1667 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1668 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1669 get_mem_index(s
), MO_TE
+ size
);
1670 tcg_temp_free_i64(addrhi
);
1673 tcg_temp_free_i64(addr
);
1675 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1676 tcg_gen_br(done_label
);
1677 gen_set_label(fail_label
);
1678 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1679 gen_set_label(done_label
);
1680 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1685 /* C3.3.6 Load/store exclusive
1687 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1688 * +-----+-------------+----+---+----+------+----+-------+------+------+
1689 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1690 * +-----+-------------+----+---+----+------+----+-------+------+------+
1692 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1693 * L: 0 -> store, 1 -> load
1694 * o2: 0 -> exclusive, 1 -> not
1695 * o1: 0 -> single register, 1 -> register pair
1696 * o0: 1 -> load-acquire/store-release, 0 -> not
1698 * o0 == 0 AND o2 == 1 is un-allocated
1699 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1701 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1703 int rt
= extract32(insn
, 0, 5);
1704 int rn
= extract32(insn
, 5, 5);
1705 int rt2
= extract32(insn
, 10, 5);
1706 int is_lasr
= extract32(insn
, 15, 1);
1707 int rs
= extract32(insn
, 16, 5);
1708 int is_pair
= extract32(insn
, 21, 1);
1709 int is_store
= !extract32(insn
, 22, 1);
1710 int is_excl
= !extract32(insn
, 23, 1);
1711 int size
= extract32(insn
, 30, 2);
1714 if ((!is_excl
&& !is_lasr
) ||
1715 (is_pair
&& size
< 2)) {
1716 unallocated_encoding(s
);
1721 gen_check_sp_alignment(s
);
1723 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1725 /* Note that since TCG is single threaded load-acquire/store-release
1726 * semantics require no extra if (is_lasr) { ... } handling.
1731 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1733 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1736 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1738 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1740 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1743 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt
);
1744 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1746 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1748 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, false, false);
1755 * C3.3.5 Load register (literal)
1757 * 31 30 29 27 26 25 24 23 5 4 0
1758 * +-----+-------+---+-----+-------------------+-------+
1759 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1760 * +-----+-------+---+-----+-------------------+-------+
1762 * V: 1 -> vector (simd/fp)
1763 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1764 * 10-> 32 bit signed, 11 -> prefetch
1765 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1767 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1769 int rt
= extract32(insn
, 0, 5);
1770 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1771 bool is_vector
= extract32(insn
, 26, 1);
1772 int opc
= extract32(insn
, 30, 2);
1773 bool is_signed
= false;
1775 TCGv_i64 tcg_rt
, tcg_addr
;
1779 unallocated_encoding(s
);
1783 if (!fp_access_check(s
)) {
1788 /* PRFM (literal) : prefetch */
1791 size
= 2 + extract32(opc
, 0, 1);
1792 is_signed
= extract32(opc
, 1, 1);
1795 tcg_rt
= cpu_reg(s
, rt
);
1797 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1799 do_fp_ld(s
, rt
, tcg_addr
, size
);
1801 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1803 tcg_temp_free_i64(tcg_addr
);
1807 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1808 * C5.6.81 LDP (Load Pair - non vector)
1809 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1810 * C5.6.176 STNP (Store Pair - non-temporal hint)
1811 * C5.6.177 STP (Store Pair - non vector)
1812 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1813 * C6.3.165 LDP (Load Pair of SIMD&FP)
1814 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1815 * C6.3.284 STP (Store Pair of SIMD&FP)
1817 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1818 * +-----+-------+---+---+-------+---+-----------------------------+
1819 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1820 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1822 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1824 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1825 * V: 0 -> GPR, 1 -> Vector
1826 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1827 * 10 -> signed offset, 11 -> pre-index
1828 * L: 0 -> Store 1 -> Load
1830 * Rt, Rt2 = GPR or SIMD registers to be stored
1831 * Rn = general purpose register containing address
1832 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1834 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1836 int rt
= extract32(insn
, 0, 5);
1837 int rn
= extract32(insn
, 5, 5);
1838 int rt2
= extract32(insn
, 10, 5);
1839 int64_t offset
= sextract32(insn
, 15, 7);
1840 int index
= extract32(insn
, 23, 2);
1841 bool is_vector
= extract32(insn
, 26, 1);
1842 bool is_load
= extract32(insn
, 22, 1);
1843 int opc
= extract32(insn
, 30, 2);
1845 bool is_signed
= false;
1846 bool postindex
= false;
1849 TCGv_i64 tcg_addr
; /* calculated address */
1853 unallocated_encoding(s
);
1860 size
= 2 + extract32(opc
, 1, 1);
1861 is_signed
= extract32(opc
, 0, 1);
1862 if (!is_load
&& is_signed
) {
1863 unallocated_encoding(s
);
1869 case 1: /* post-index */
1874 /* signed offset with "non-temporal" hint. Since we don't emulate
1875 * caches we don't care about hints to the cache system about
1876 * data access patterns, and handle this identically to plain
1880 /* There is no non-temporal-hint version of LDPSW */
1881 unallocated_encoding(s
);
1886 case 2: /* signed offset, rn not updated */
1889 case 3: /* pre-index */
1895 if (is_vector
&& !fp_access_check(s
)) {
1902 gen_check_sp_alignment(s
);
1905 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1908 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1913 do_fp_ld(s
, rt
, tcg_addr
, size
);
1915 do_fp_st(s
, rt
, tcg_addr
, size
);
1918 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1920 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1922 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1925 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1928 do_fp_ld(s
, rt2
, tcg_addr
, size
);
1930 do_fp_st(s
, rt2
, tcg_addr
, size
);
1933 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
1935 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
1937 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1943 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
1945 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1947 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
1952 * C3.3.8 Load/store (immediate post-indexed)
1953 * C3.3.9 Load/store (immediate pre-indexed)
1954 * C3.3.12 Load/store (unscaled immediate)
1956 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1957 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1958 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1959 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1961 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1963 * V = 0 -> non-vector
1964 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1965 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1967 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
1969 int rt
= extract32(insn
, 0, 5);
1970 int rn
= extract32(insn
, 5, 5);
1971 int imm9
= sextract32(insn
, 12, 9);
1972 int opc
= extract32(insn
, 22, 2);
1973 int size
= extract32(insn
, 30, 2);
1974 int idx
= extract32(insn
, 10, 2);
1975 bool is_signed
= false;
1976 bool is_store
= false;
1977 bool is_extended
= false;
1978 bool is_unpriv
= (idx
== 2);
1979 bool is_vector
= extract32(insn
, 26, 1);
1986 size
|= (opc
& 2) << 1;
1987 if (size
> 4 || is_unpriv
) {
1988 unallocated_encoding(s
);
1991 is_store
= ((opc
& 1) == 0);
1992 if (!fp_access_check(s
)) {
1996 if (size
== 3 && opc
== 2) {
1997 /* PRFM - prefetch */
1999 unallocated_encoding(s
);
2004 if (opc
== 3 && size
> 1) {
2005 unallocated_encoding(s
);
2008 is_store
= (opc
== 0);
2009 is_signed
= opc
& (1<<1);
2010 is_extended
= (size
< 3) && (opc
& 1);
2030 gen_check_sp_alignment(s
);
2032 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2035 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2040 do_fp_st(s
, rt
, tcg_addr
, size
);
2042 do_fp_ld(s
, rt
, tcg_addr
, size
);
2045 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2046 int memidx
= is_unpriv
? 1 : get_mem_index(s
);
2049 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
2051 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2052 is_signed
, is_extended
, memidx
);
2057 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2059 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2061 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2066 * C3.3.10 Load/store (register offset)
2068 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2069 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2070 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2071 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2074 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2075 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2077 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2078 * opc<0>: 0 -> store, 1 -> load
2079 * V: 1 -> vector/simd
2080 * opt: extend encoding (see DecodeRegExtend)
2081 * S: if S=1 then scale (essentially index by sizeof(size))
2082 * Rt: register to transfer into/out of
2083 * Rn: address register or SP for base
2084 * Rm: offset register or ZR for offset
2086 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
2088 int rt
= extract32(insn
, 0, 5);
2089 int rn
= extract32(insn
, 5, 5);
2090 int shift
= extract32(insn
, 12, 1);
2091 int rm
= extract32(insn
, 16, 5);
2092 int opc
= extract32(insn
, 22, 2);
2093 int opt
= extract32(insn
, 13, 3);
2094 int size
= extract32(insn
, 30, 2);
2095 bool is_signed
= false;
2096 bool is_store
= false;
2097 bool is_extended
= false;
2098 bool is_vector
= extract32(insn
, 26, 1);
2103 if (extract32(opt
, 1, 1) == 0) {
2104 unallocated_encoding(s
);
2109 size
|= (opc
& 2) << 1;
2111 unallocated_encoding(s
);
2114 is_store
= !extract32(opc
, 0, 1);
2115 if (!fp_access_check(s
)) {
2119 if (size
== 3 && opc
== 2) {
2120 /* PRFM - prefetch */
2123 if (opc
== 3 && size
> 1) {
2124 unallocated_encoding(s
);
2127 is_store
= (opc
== 0);
2128 is_signed
= extract32(opc
, 1, 1);
2129 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2133 gen_check_sp_alignment(s
);
2135 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2137 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2138 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2140 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2144 do_fp_st(s
, rt
, tcg_addr
, size
);
2146 do_fp_ld(s
, rt
, tcg_addr
, size
);
2149 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2151 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2153 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2159 * C3.3.13 Load/store (unsigned immediate)
2161 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2162 * +----+-------+---+-----+-----+------------+-------+------+
2163 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2164 * +----+-------+---+-----+-----+------------+-------+------+
2167 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2168 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2170 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2171 * opc<0>: 0 -> store, 1 -> load
2172 * Rn: base address register (inc SP)
2173 * Rt: target register
2175 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2177 int rt
= extract32(insn
, 0, 5);
2178 int rn
= extract32(insn
, 5, 5);
2179 unsigned int imm12
= extract32(insn
, 10, 12);
2180 bool is_vector
= extract32(insn
, 26, 1);
2181 int size
= extract32(insn
, 30, 2);
2182 int opc
= extract32(insn
, 22, 2);
2183 unsigned int offset
;
2188 bool is_signed
= false;
2189 bool is_extended
= false;
2192 size
|= (opc
& 2) << 1;
2194 unallocated_encoding(s
);
2197 is_store
= !extract32(opc
, 0, 1);
2198 if (!fp_access_check(s
)) {
2202 if (size
== 3 && opc
== 2) {
2203 /* PRFM - prefetch */
2206 if (opc
== 3 && size
> 1) {
2207 unallocated_encoding(s
);
2210 is_store
= (opc
== 0);
2211 is_signed
= extract32(opc
, 1, 1);
2212 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2216 gen_check_sp_alignment(s
);
2218 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2219 offset
= imm12
<< size
;
2220 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2224 do_fp_st(s
, rt
, tcg_addr
, size
);
2226 do_fp_ld(s
, rt
, tcg_addr
, size
);
2229 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2231 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2233 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2238 /* Load/store register (all forms) */
2239 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2241 switch (extract32(insn
, 24, 2)) {
2243 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2244 disas_ldst_reg_roffset(s
, insn
);
2246 /* Load/store register (unscaled immediate)
2247 * Load/store immediate pre/post-indexed
2248 * Load/store register unprivileged
2250 disas_ldst_reg_imm9(s
, insn
);
2254 disas_ldst_reg_unsigned_imm(s
, insn
);
2257 unallocated_encoding(s
);
2262 /* C3.3.1 AdvSIMD load/store multiple structures
2264 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2265 * +---+---+---------------+---+-------------+--------+------+------+------+
2266 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2267 * +---+---+---------------+---+-------------+--------+------+------+------+
2269 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2271 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2272 * +---+---+---------------+---+---+---------+--------+------+------+------+
2273 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2274 * +---+---+---------------+---+---+---------+--------+------+------+------+
2276 * Rt: first (or only) SIMD&FP register to be transferred
2277 * Rn: base address or SP
2278 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2280 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2282 int rt
= extract32(insn
, 0, 5);
2283 int rn
= extract32(insn
, 5, 5);
2284 int size
= extract32(insn
, 10, 2);
2285 int opcode
= extract32(insn
, 12, 4);
2286 bool is_store
= !extract32(insn
, 22, 1);
2287 bool is_postidx
= extract32(insn
, 23, 1);
2288 bool is_q
= extract32(insn
, 30, 1);
2289 TCGv_i64 tcg_addr
, tcg_rn
;
2291 int ebytes
= 1 << size
;
2292 int elements
= (is_q
? 128 : 64) / (8 << size
);
2293 int rpt
; /* num iterations */
2294 int selem
; /* structure elements */
2297 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2298 unallocated_encoding(s
);
2302 /* From the shared decode logic */
2333 unallocated_encoding(s
);
2337 if (size
== 3 && !is_q
&& selem
!= 1) {
2339 unallocated_encoding(s
);
2343 if (!fp_access_check(s
)) {
2348 gen_check_sp_alignment(s
);
2351 tcg_rn
= cpu_reg_sp(s
, rn
);
2352 tcg_addr
= tcg_temp_new_i64();
2353 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2355 for (r
= 0; r
< rpt
; r
++) {
2357 for (e
= 0; e
< elements
; e
++) {
2358 int tt
= (rt
+ r
) % 32;
2360 for (xs
= 0; xs
< selem
; xs
++) {
2362 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2364 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2366 /* For non-quad operations, setting a slice of the low
2367 * 64 bits of the register clears the high 64 bits (in
2368 * the ARM ARM pseudocode this is implicit in the fact
2369 * that 'rval' is a 64 bit wide variable). We optimize
2370 * by noticing that we only need to do this the first
2371 * time we touch a register.
2373 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2374 clear_vec_high(s
, tt
);
2377 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2384 int rm
= extract32(insn
, 16, 5);
2386 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2388 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2391 tcg_temp_free_i64(tcg_addr
);
2394 /* C3.3.3 AdvSIMD load/store single structure
2396 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2397 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2398 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2399 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2401 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2403 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2404 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2405 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2406 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2408 * Rt: first (or only) SIMD&FP register to be transferred
2409 * Rn: base address or SP
2410 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2411 * index = encoded in Q:S:size dependent on size
2413 * lane_size = encoded in R, opc
2414 * transfer width = encoded in opc, S, size
2416 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2418 int rt
= extract32(insn
, 0, 5);
2419 int rn
= extract32(insn
, 5, 5);
2420 int size
= extract32(insn
, 10, 2);
2421 int S
= extract32(insn
, 12, 1);
2422 int opc
= extract32(insn
, 13, 3);
2423 int R
= extract32(insn
, 21, 1);
2424 int is_load
= extract32(insn
, 22, 1);
2425 int is_postidx
= extract32(insn
, 23, 1);
2426 int is_q
= extract32(insn
, 30, 1);
2428 int scale
= extract32(opc
, 1, 2);
2429 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2430 bool replicate
= false;
2431 int index
= is_q
<< 3 | S
<< 2 | size
;
2433 TCGv_i64 tcg_addr
, tcg_rn
;
2437 if (!is_load
|| S
) {
2438 unallocated_encoding(s
);
2447 if (extract32(size
, 0, 1)) {
2448 unallocated_encoding(s
);
2454 if (extract32(size
, 1, 1)) {
2455 unallocated_encoding(s
);
2458 if (!extract32(size
, 0, 1)) {
2462 unallocated_encoding(s
);
2470 g_assert_not_reached();
2473 if (!fp_access_check(s
)) {
2477 ebytes
= 1 << scale
;
2480 gen_check_sp_alignment(s
);
2483 tcg_rn
= cpu_reg_sp(s
, rn
);
2484 tcg_addr
= tcg_temp_new_i64();
2485 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2487 for (xs
= 0; xs
< selem
; xs
++) {
2489 /* Load and replicate to all elements */
2491 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2493 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2494 get_mem_index(s
), MO_TE
+ scale
);
2497 mulconst
= 0x0101010101010101ULL
;
2500 mulconst
= 0x0001000100010001ULL
;
2503 mulconst
= 0x0000000100000001ULL
;
2509 g_assert_not_reached();
2512 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2514 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2516 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2518 clear_vec_high(s
, rt
);
2520 tcg_temp_free_i64(tcg_tmp
);
2522 /* Load/store one element per register */
2524 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2526 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2529 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2534 int rm
= extract32(insn
, 16, 5);
2536 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2538 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2541 tcg_temp_free_i64(tcg_addr
);
2544 /* C3.3 Loads and stores */
2545 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2547 switch (extract32(insn
, 24, 6)) {
2548 case 0x08: /* Load/store exclusive */
2549 disas_ldst_excl(s
, insn
);
2551 case 0x18: case 0x1c: /* Load register (literal) */
2552 disas_ld_lit(s
, insn
);
2554 case 0x28: case 0x29:
2555 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2556 disas_ldst_pair(s
, insn
);
2558 case 0x38: case 0x39:
2559 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2560 disas_ldst_reg(s
, insn
);
2562 case 0x0c: /* AdvSIMD load/store multiple structures */
2563 disas_ldst_multiple_struct(s
, insn
);
2565 case 0x0d: /* AdvSIMD load/store single structure */
2566 disas_ldst_single_struct(s
, insn
);
2569 unallocated_encoding(s
);
2574 /* C3.4.6 PC-rel. addressing
2575 * 31 30 29 28 24 23 5 4 0
2576 * +----+-------+-----------+-------------------+------+
2577 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2578 * +----+-------+-----------+-------------------+------+
2580 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2582 unsigned int page
, rd
;
2586 page
= extract32(insn
, 31, 1);
2587 /* SignExtend(immhi:immlo) -> offset */
2588 offset
= ((int64_t)sextract32(insn
, 5, 19) << 2) | extract32(insn
, 29, 2);
2589 rd
= extract32(insn
, 0, 5);
2593 /* ADRP (page based) */
2598 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2602 * C3.4.1 Add/subtract (immediate)
2604 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2605 * +--+--+--+-----------+-----+-------------+-----+-----+
2606 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2607 * +--+--+--+-----------+-----+-------------+-----+-----+
2609 * sf: 0 -> 32bit, 1 -> 64bit
2610 * op: 0 -> add , 1 -> sub
2612 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2614 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2616 int rd
= extract32(insn
, 0, 5);
2617 int rn
= extract32(insn
, 5, 5);
2618 uint64_t imm
= extract32(insn
, 10, 12);
2619 int shift
= extract32(insn
, 22, 2);
2620 bool setflags
= extract32(insn
, 29, 1);
2621 bool sub_op
= extract32(insn
, 30, 1);
2622 bool is_64bit
= extract32(insn
, 31, 1);
2624 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2625 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2626 TCGv_i64 tcg_result
;
2635 unallocated_encoding(s
);
2639 tcg_result
= tcg_temp_new_i64();
2642 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2644 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2647 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2649 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2651 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2653 tcg_temp_free_i64(tcg_imm
);
2657 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2659 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2662 tcg_temp_free_i64(tcg_result
);
2665 /* The input should be a value in the bottom e bits (with higher
2666 * bits zero); returns that value replicated into every element
2667 * of size e in a 64 bit integer.
2669 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2679 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2680 static inline uint64_t bitmask64(unsigned int length
)
2682 assert(length
> 0 && length
<= 64);
2683 return ~0ULL >> (64 - length
);
2686 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2687 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2688 * value (ie should cause a guest UNDEF exception), and true if they are
2689 * valid, in which case the decoded bit pattern is written to result.
2691 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2692 unsigned int imms
, unsigned int immr
)
2695 unsigned e
, levels
, s
, r
;
2698 assert(immn
< 2 && imms
< 64 && immr
< 64);
2700 /* The bit patterns we create here are 64 bit patterns which
2701 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2702 * 64 bits each. Each element contains the same value: a run
2703 * of between 1 and e-1 non-zero bits, rotated within the
2704 * element by between 0 and e-1 bits.
2706 * The element size and run length are encoded into immn (1 bit)
2707 * and imms (6 bits) as follows:
2708 * 64 bit elements: immn = 1, imms = <length of run - 1>
2709 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2710 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2711 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2712 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2713 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2714 * Notice that immn = 0, imms = 11111x is the only combination
2715 * not covered by one of the above options; this is reserved.
2716 * Further, <length of run - 1> all-ones is a reserved pattern.
2718 * In all cases the rotation is by immr % e (and immr is 6 bits).
2721 /* First determine the element size */
2722 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2724 /* This is the immn == 0, imms == 0x11111x case */
2734 /* <length of run - 1> mustn't be all-ones. */
2738 /* Create the value of one element: s+1 set bits rotated
2739 * by r within the element (which is e bits wide)...
2741 mask
= bitmask64(s
+ 1);
2742 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2743 /* ...then replicate the element over the whole 64 bit value */
2744 mask
= bitfield_replicate(mask
, e
);
2749 /* C3.4.4 Logical (immediate)
2750 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2751 * +----+-----+-------------+---+------+------+------+------+
2752 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2753 * +----+-----+-------------+---+------+------+------+------+
2755 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2757 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2758 TCGv_i64 tcg_rd
, tcg_rn
;
2760 bool is_and
= false;
2762 sf
= extract32(insn
, 31, 1);
2763 opc
= extract32(insn
, 29, 2);
2764 is_n
= extract32(insn
, 22, 1);
2765 immr
= extract32(insn
, 16, 6);
2766 imms
= extract32(insn
, 10, 6);
2767 rn
= extract32(insn
, 5, 5);
2768 rd
= extract32(insn
, 0, 5);
2771 unallocated_encoding(s
);
2775 if (opc
== 0x3) { /* ANDS */
2776 tcg_rd
= cpu_reg(s
, rd
);
2778 tcg_rd
= cpu_reg_sp(s
, rd
);
2780 tcg_rn
= cpu_reg(s
, rn
);
2782 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2783 /* some immediate field values are reserved */
2784 unallocated_encoding(s
);
2789 wmask
&= 0xffffffff;
2793 case 0x3: /* ANDS */
2795 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2799 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2802 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2805 assert(FALSE
); /* must handle all above */
2809 if (!sf
&& !is_and
) {
2810 /* zero extend final result; we know we can skip this for AND
2811 * since the immediate had the high 32 bits clear.
2813 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2816 if (opc
== 3) { /* ANDS */
2817 gen_logic_CC(sf
, tcg_rd
);
2822 * C3.4.5 Move wide (immediate)
2824 * 31 30 29 28 23 22 21 20 5 4 0
2825 * +--+-----+-------------+-----+----------------+------+
2826 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2827 * +--+-----+-------------+-----+----------------+------+
2829 * sf: 0 -> 32 bit, 1 -> 64 bit
2830 * opc: 00 -> N, 10 -> Z, 11 -> K
2831 * hw: shift/16 (0,16, and sf only 32, 48)
2833 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2835 int rd
= extract32(insn
, 0, 5);
2836 uint64_t imm
= extract32(insn
, 5, 16);
2837 int sf
= extract32(insn
, 31, 1);
2838 int opc
= extract32(insn
, 29, 2);
2839 int pos
= extract32(insn
, 21, 2) << 4;
2840 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2843 if (!sf
&& (pos
>= 32)) {
2844 unallocated_encoding(s
);
2858 tcg_gen_movi_i64(tcg_rd
, imm
);
2861 tcg_imm
= tcg_const_i64(imm
);
2862 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2863 tcg_temp_free_i64(tcg_imm
);
2865 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2869 unallocated_encoding(s
);
2875 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2876 * +----+-----+-------------+---+------+------+------+------+
2877 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2878 * +----+-----+-------------+---+------+------+------+------+
2880 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2882 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2883 TCGv_i64 tcg_rd
, tcg_tmp
;
2885 sf
= extract32(insn
, 31, 1);
2886 opc
= extract32(insn
, 29, 2);
2887 n
= extract32(insn
, 22, 1);
2888 ri
= extract32(insn
, 16, 6);
2889 si
= extract32(insn
, 10, 6);
2890 rn
= extract32(insn
, 5, 5);
2891 rd
= extract32(insn
, 0, 5);
2892 bitsize
= sf
? 64 : 32;
2894 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
2895 unallocated_encoding(s
);
2899 tcg_rd
= cpu_reg(s
, rd
);
2900 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
2902 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2904 if (opc
!= 1) { /* SBFM or UBFM */
2905 tcg_gen_movi_i64(tcg_rd
, 0);
2908 /* do the bit move operation */
2910 /* Wd<s-r:0> = Wn<s:r> */
2911 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
2913 len
= (si
- ri
) + 1;
2915 /* Wd<32+s-r,32-r> = Wn<s:0> */
2920 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
2922 if (opc
== 0) { /* SBFM - sign extend the destination field */
2923 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2924 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2927 if (!sf
) { /* zero extend final result */
2928 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2933 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2934 * +----+------+-------------+---+----+------+--------+------+------+
2935 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2936 * +----+------+-------------+---+----+------+--------+------+------+
2938 static void disas_extract(DisasContext
*s
, uint32_t insn
)
2940 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
2942 sf
= extract32(insn
, 31, 1);
2943 n
= extract32(insn
, 22, 1);
2944 rm
= extract32(insn
, 16, 5);
2945 imm
= extract32(insn
, 10, 6);
2946 rn
= extract32(insn
, 5, 5);
2947 rd
= extract32(insn
, 0, 5);
2948 op21
= extract32(insn
, 29, 2);
2949 op0
= extract32(insn
, 21, 1);
2950 bitsize
= sf
? 64 : 32;
2952 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
2953 unallocated_encoding(s
);
2955 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
2957 tcg_rd
= cpu_reg(s
, rd
);
2960 /* OPTME: we can special case rm==rn as a rotate */
2961 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2962 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2963 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
2964 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
2965 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
2967 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2970 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2971 * so an extract from bit 0 is a special case.
2974 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
2976 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
2983 /* C3.4 Data processing - immediate */
2984 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
2986 switch (extract32(insn
, 23, 6)) {
2987 case 0x20: case 0x21: /* PC-rel. addressing */
2988 disas_pc_rel_adr(s
, insn
);
2990 case 0x22: case 0x23: /* Add/subtract (immediate) */
2991 disas_add_sub_imm(s
, insn
);
2993 case 0x24: /* Logical (immediate) */
2994 disas_logic_imm(s
, insn
);
2996 case 0x25: /* Move wide (immediate) */
2997 disas_movw_imm(s
, insn
);
2999 case 0x26: /* Bitfield */
3000 disas_bitfield(s
, insn
);
3002 case 0x27: /* Extract */
3003 disas_extract(s
, insn
);
3006 unallocated_encoding(s
);
3011 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3012 * Note that it is the caller's responsibility to ensure that the
3013 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3014 * mandated semantics for out of range shifts.
3016 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3017 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3019 switch (shift_type
) {
3020 case A64_SHIFT_TYPE_LSL
:
3021 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3023 case A64_SHIFT_TYPE_LSR
:
3024 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3026 case A64_SHIFT_TYPE_ASR
:
3028 tcg_gen_ext32s_i64(dst
, src
);
3030 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3032 case A64_SHIFT_TYPE_ROR
:
3034 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3037 t0
= tcg_temp_new_i32();
3038 t1
= tcg_temp_new_i32();
3039 tcg_gen_trunc_i64_i32(t0
, src
);
3040 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
3041 tcg_gen_rotr_i32(t0
, t0
, t1
);
3042 tcg_gen_extu_i32_i64(dst
, t0
);
3043 tcg_temp_free_i32(t0
);
3044 tcg_temp_free_i32(t1
);
3048 assert(FALSE
); /* all shift types should be handled */
3052 if (!sf
) { /* zero extend final result */
3053 tcg_gen_ext32u_i64(dst
, dst
);
3057 /* Shift a TCGv src by immediate, put result in dst.
3058 * The shift amount must be in range (this should always be true as the
3059 * relevant instructions will UNDEF on bad shift immediates).
3061 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3062 enum a64_shift_type shift_type
, unsigned int shift_i
)
3064 assert(shift_i
< (sf
? 64 : 32));
3067 tcg_gen_mov_i64(dst
, src
);
3069 TCGv_i64 shift_const
;
3071 shift_const
= tcg_const_i64(shift_i
);
3072 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3073 tcg_temp_free_i64(shift_const
);
3077 /* C3.5.10 Logical (shifted register)
3078 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3079 * +----+-----+-----------+-------+---+------+--------+------+------+
3080 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3081 * +----+-----+-----------+-------+---+------+--------+------+------+
3083 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3085 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3086 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3088 sf
= extract32(insn
, 31, 1);
3089 opc
= extract32(insn
, 29, 2);
3090 shift_type
= extract32(insn
, 22, 2);
3091 invert
= extract32(insn
, 21, 1);
3092 rm
= extract32(insn
, 16, 5);
3093 shift_amount
= extract32(insn
, 10, 6);
3094 rn
= extract32(insn
, 5, 5);
3095 rd
= extract32(insn
, 0, 5);
3097 if (!sf
&& (shift_amount
& (1 << 5))) {
3098 unallocated_encoding(s
);
3102 tcg_rd
= cpu_reg(s
, rd
);
3104 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3105 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3106 * register-register MOV and MVN, so it is worth special casing.
3108 tcg_rm
= cpu_reg(s
, rm
);
3110 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3112 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3116 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3118 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3124 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3127 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3130 tcg_rn
= cpu_reg(s
, rn
);
3132 switch (opc
| (invert
<< 2)) {
3135 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3138 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3141 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3145 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3148 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3151 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3159 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3163 gen_logic_CC(sf
, tcg_rd
);
3168 * C3.5.1 Add/subtract (extended register)
3170 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3171 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3172 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3173 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3175 * sf: 0 -> 32bit, 1 -> 64bit
3176 * op: 0 -> add , 1 -> sub
3179 * option: extension type (see DecodeRegExtend)
3180 * imm3: optional shift to Rm
3182 * Rd = Rn + LSL(extend(Rm), amount)
3184 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3186 int rd
= extract32(insn
, 0, 5);
3187 int rn
= extract32(insn
, 5, 5);
3188 int imm3
= extract32(insn
, 10, 3);
3189 int option
= extract32(insn
, 13, 3);
3190 int rm
= extract32(insn
, 16, 5);
3191 bool setflags
= extract32(insn
, 29, 1);
3192 bool sub_op
= extract32(insn
, 30, 1);
3193 bool sf
= extract32(insn
, 31, 1);
3195 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3197 TCGv_i64 tcg_result
;
3200 unallocated_encoding(s
);
3204 /* non-flag setting ops may use SP */
3206 tcg_rd
= cpu_reg_sp(s
, rd
);
3208 tcg_rd
= cpu_reg(s
, rd
);
3210 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3212 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3213 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3215 tcg_result
= tcg_temp_new_i64();
3219 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3221 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3225 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3227 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3232 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3234 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3237 tcg_temp_free_i64(tcg_result
);
3241 * C3.5.2 Add/subtract (shifted register)
3243 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3244 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3245 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3246 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3248 * sf: 0 -> 32bit, 1 -> 64bit
3249 * op: 0 -> add , 1 -> sub
3251 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3252 * imm6: Shift amount to apply to Rm before the add/sub
3254 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3256 int rd
= extract32(insn
, 0, 5);
3257 int rn
= extract32(insn
, 5, 5);
3258 int imm6
= extract32(insn
, 10, 6);
3259 int rm
= extract32(insn
, 16, 5);
3260 int shift_type
= extract32(insn
, 22, 2);
3261 bool setflags
= extract32(insn
, 29, 1);
3262 bool sub_op
= extract32(insn
, 30, 1);
3263 bool sf
= extract32(insn
, 31, 1);
3265 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3266 TCGv_i64 tcg_rn
, tcg_rm
;
3267 TCGv_i64 tcg_result
;
3269 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3270 unallocated_encoding(s
);
3274 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3275 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3277 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3279 tcg_result
= tcg_temp_new_i64();
3283 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3285 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3289 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3291 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3296 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3298 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3301 tcg_temp_free_i64(tcg_result
);
3304 /* C3.5.9 Data-processing (3 source)
3306 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3307 +--+------+-----------+------+------+----+------+------+------+
3308 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3309 +--+------+-----------+------+------+----+------+------+------+
3312 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3314 int rd
= extract32(insn
, 0, 5);
3315 int rn
= extract32(insn
, 5, 5);
3316 int ra
= extract32(insn
, 10, 5);
3317 int rm
= extract32(insn
, 16, 5);
3318 int op_id
= (extract32(insn
, 29, 3) << 4) |
3319 (extract32(insn
, 21, 3) << 1) |
3320 extract32(insn
, 15, 1);
3321 bool sf
= extract32(insn
, 31, 1);
3322 bool is_sub
= extract32(op_id
, 0, 1);
3323 bool is_high
= extract32(op_id
, 2, 1);
3324 bool is_signed
= false;
3329 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3331 case 0x42: /* SMADDL */
3332 case 0x43: /* SMSUBL */
3333 case 0x44: /* SMULH */
3336 case 0x0: /* MADD (32bit) */
3337 case 0x1: /* MSUB (32bit) */
3338 case 0x40: /* MADD (64bit) */
3339 case 0x41: /* MSUB (64bit) */
3340 case 0x4a: /* UMADDL */
3341 case 0x4b: /* UMSUBL */
3342 case 0x4c: /* UMULH */
3345 unallocated_encoding(s
);
3350 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3351 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3352 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3353 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3356 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3358 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3361 tcg_temp_free_i64(low_bits
);
3365 tcg_op1
= tcg_temp_new_i64();
3366 tcg_op2
= tcg_temp_new_i64();
3367 tcg_tmp
= tcg_temp_new_i64();
3370 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3371 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3374 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3375 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3377 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3378 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3382 if (ra
== 31 && !is_sub
) {
3383 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3384 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3386 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3388 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3390 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3395 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3398 tcg_temp_free_i64(tcg_op1
);
3399 tcg_temp_free_i64(tcg_op2
);
3400 tcg_temp_free_i64(tcg_tmp
);
3403 /* C3.5.3 - Add/subtract (with carry)
3404 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3405 * +--+--+--+------------------------+------+---------+------+-----+
3406 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3407 * +--+--+--+------------------------+------+---------+------+-----+
3411 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3413 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3414 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3416 if (extract32(insn
, 10, 6) != 0) {
3417 unallocated_encoding(s
);
3421 sf
= extract32(insn
, 31, 1);
3422 op
= extract32(insn
, 30, 1);
3423 setflags
= extract32(insn
, 29, 1);
3424 rm
= extract32(insn
, 16, 5);
3425 rn
= extract32(insn
, 5, 5);
3426 rd
= extract32(insn
, 0, 5);
3428 tcg_rd
= cpu_reg(s
, rd
);
3429 tcg_rn
= cpu_reg(s
, rn
);
3432 tcg_y
= new_tmp_a64(s
);
3433 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3435 tcg_y
= cpu_reg(s
, rm
);
3439 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3441 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3445 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3446 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3447 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3448 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3449 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3452 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3454 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3455 int label_continue
= -1;
3456 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3458 if (!extract32(insn
, 29, 1)) {
3459 unallocated_encoding(s
);
3462 if (insn
& (1 << 10 | 1 << 4)) {
3463 unallocated_encoding(s
);
3466 sf
= extract32(insn
, 31, 1);
3467 op
= extract32(insn
, 30, 1);
3468 is_imm
= extract32(insn
, 11, 1);
3469 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3470 cond
= extract32(insn
, 12, 4);
3471 rn
= extract32(insn
, 5, 5);
3472 nzcv
= extract32(insn
, 0, 4);
3474 if (cond
< 0x0e) { /* not always */
3475 int label_match
= gen_new_label();
3476 label_continue
= gen_new_label();
3477 arm_gen_test_cc(cond
, label_match
);
3479 tcg_tmp
= tcg_temp_new_i64();
3480 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
3481 gen_set_nzcv(tcg_tmp
);
3482 tcg_temp_free_i64(tcg_tmp
);
3483 tcg_gen_br(label_continue
);
3484 gen_set_label(label_match
);
3486 /* match, or condition is always */
3488 tcg_y
= new_tmp_a64(s
);
3489 tcg_gen_movi_i64(tcg_y
, y
);
3491 tcg_y
= cpu_reg(s
, y
);
3493 tcg_rn
= cpu_reg(s
, rn
);
3495 tcg_tmp
= tcg_temp_new_i64();
3497 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3499 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3501 tcg_temp_free_i64(tcg_tmp
);
3503 if (cond
< 0x0e) { /* continue */
3504 gen_set_label(label_continue
);
3508 /* C3.5.6 Conditional select
3509 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3510 * +----+----+---+-----------------+------+------+-----+------+------+
3511 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3512 * +----+----+---+-----------------+------+------+-----+------+------+
3514 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3516 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3517 TCGv_i64 tcg_rd
, tcg_src
;
3519 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3520 /* S == 1 or op2<1> == 1 */
3521 unallocated_encoding(s
);
3524 sf
= extract32(insn
, 31, 1);
3525 else_inv
= extract32(insn
, 30, 1);
3526 rm
= extract32(insn
, 16, 5);
3527 cond
= extract32(insn
, 12, 4);
3528 else_inc
= extract32(insn
, 10, 1);
3529 rn
= extract32(insn
, 5, 5);
3530 rd
= extract32(insn
, 0, 5);
3533 /* silly no-op write; until we use movcond we must special-case
3534 * this to avoid a dead temporary across basic blocks.
3539 tcg_rd
= cpu_reg(s
, rd
);
3541 if (cond
>= 0x0e) { /* condition "always" */
3542 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3543 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3545 /* OPTME: we could use movcond here, at the cost of duplicating
3546 * a lot of the arm_gen_test_cc() logic.
3548 int label_match
= gen_new_label();
3549 int label_continue
= gen_new_label();
3551 arm_gen_test_cc(cond
, label_match
);
3553 tcg_src
= cpu_reg(s
, rm
);
3555 if (else_inv
&& else_inc
) {
3556 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
3557 } else if (else_inv
) {
3558 tcg_gen_not_i64(tcg_rd
, tcg_src
);
3559 } else if (else_inc
) {
3560 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
3562 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3565 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3567 tcg_gen_br(label_continue
);
3569 gen_set_label(label_match
);
3570 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3571 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3573 gen_set_label(label_continue
);
3577 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3578 unsigned int rn
, unsigned int rd
)
3580 TCGv_i64 tcg_rd
, tcg_rn
;
3581 tcg_rd
= cpu_reg(s
, rd
);
3582 tcg_rn
= cpu_reg(s
, rn
);
3585 gen_helper_clz64(tcg_rd
, tcg_rn
);
3587 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3588 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3589 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3590 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3591 tcg_temp_free_i32(tcg_tmp32
);
3595 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3596 unsigned int rn
, unsigned int rd
)
3598 TCGv_i64 tcg_rd
, tcg_rn
;
3599 tcg_rd
= cpu_reg(s
, rd
);
3600 tcg_rn
= cpu_reg(s
, rn
);
3603 gen_helper_cls64(tcg_rd
, tcg_rn
);
3605 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3606 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3607 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3608 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3609 tcg_temp_free_i32(tcg_tmp32
);
3613 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3614 unsigned int rn
, unsigned int rd
)
3616 TCGv_i64 tcg_rd
, tcg_rn
;
3617 tcg_rd
= cpu_reg(s
, rd
);
3618 tcg_rn
= cpu_reg(s
, rn
);
3621 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3623 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3624 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3625 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3626 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3627 tcg_temp_free_i32(tcg_tmp32
);
3631 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3632 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3633 unsigned int rn
, unsigned int rd
)
3636 unallocated_encoding(s
);
3639 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3642 /* C5.6.149 REV with sf==0, opcode==2
3643 * C5.6.151 REV32 (sf==1, opcode==2)
3645 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3646 unsigned int rn
, unsigned int rd
)
3648 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3651 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3652 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3654 /* bswap32_i64 requires zero high word */
3655 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3656 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3657 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3658 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3659 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3661 tcg_temp_free_i64(tcg_tmp
);
3663 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3664 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3668 /* C5.6.150 REV16 (opcode==1) */
3669 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3670 unsigned int rn
, unsigned int rd
)
3672 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3673 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3674 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3676 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3677 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3679 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3680 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3681 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3682 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3685 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3686 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3687 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3688 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3690 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3691 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3692 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3695 tcg_temp_free_i64(tcg_tmp
);
3698 /* C3.5.7 Data-processing (1 source)
3699 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3700 * +----+---+---+-----------------+---------+--------+------+------+
3701 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3702 * +----+---+---+-----------------+---------+--------+------+------+
3704 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3706 unsigned int sf
, opcode
, rn
, rd
;
3708 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3709 unallocated_encoding(s
);
3713 sf
= extract32(insn
, 31, 1);
3714 opcode
= extract32(insn
, 10, 6);
3715 rn
= extract32(insn
, 5, 5);
3716 rd
= extract32(insn
, 0, 5);
3720 handle_rbit(s
, sf
, rn
, rd
);
3723 handle_rev16(s
, sf
, rn
, rd
);
3726 handle_rev32(s
, sf
, rn
, rd
);
3729 handle_rev64(s
, sf
, rn
, rd
);
3732 handle_clz(s
, sf
, rn
, rd
);
3735 handle_cls(s
, sf
, rn
, rd
);
3740 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3741 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3743 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3744 tcg_rd
= cpu_reg(s
, rd
);
3746 if (!sf
&& is_signed
) {
3747 tcg_n
= new_tmp_a64(s
);
3748 tcg_m
= new_tmp_a64(s
);
3749 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3750 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3752 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3753 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3757 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3759 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3762 if (!sf
) { /* zero extend final result */
3763 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3767 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3768 static void handle_shift_reg(DisasContext
*s
,
3769 enum a64_shift_type shift_type
, unsigned int sf
,
3770 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3772 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3773 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3774 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3776 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3777 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3778 tcg_temp_free_i64(tcg_shift
);
3781 /* CRC32[BHWX], CRC32C[BHWX] */
3782 static void handle_crc32(DisasContext
*s
,
3783 unsigned int sf
, unsigned int sz
, bool crc32c
,
3784 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3786 TCGv_i64 tcg_acc
, tcg_val
;
3789 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
3790 || (sf
== 1 && sz
!= 3)
3791 || (sf
== 0 && sz
== 3)) {
3792 unallocated_encoding(s
);
3797 tcg_val
= cpu_reg(s
, rm
);
3811 g_assert_not_reached();
3813 tcg_val
= new_tmp_a64(s
);
3814 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
3817 tcg_acc
= cpu_reg(s
, rn
);
3818 tcg_bytes
= tcg_const_i32(1 << sz
);
3821 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
3823 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
3826 tcg_temp_free_i32(tcg_bytes
);
3829 /* C3.5.8 Data-processing (2 source)
3830 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3831 * +----+---+---+-----------------+------+--------+------+------+
3832 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3833 * +----+---+---+-----------------+------+--------+------+------+
3835 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
3837 unsigned int sf
, rm
, opcode
, rn
, rd
;
3838 sf
= extract32(insn
, 31, 1);
3839 rm
= extract32(insn
, 16, 5);
3840 opcode
= extract32(insn
, 10, 6);
3841 rn
= extract32(insn
, 5, 5);
3842 rd
= extract32(insn
, 0, 5);
3844 if (extract32(insn
, 29, 1)) {
3845 unallocated_encoding(s
);
3851 handle_div(s
, false, sf
, rm
, rn
, rd
);
3854 handle_div(s
, true, sf
, rm
, rn
, rd
);
3857 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
3860 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
3863 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
3866 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
3875 case 23: /* CRC32 */
3877 int sz
= extract32(opcode
, 0, 2);
3878 bool crc32c
= extract32(opcode
, 2, 1);
3879 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
3883 unallocated_encoding(s
);
3888 /* C3.5 Data processing - register */
3889 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
3891 switch (extract32(insn
, 24, 5)) {
3892 case 0x0a: /* Logical (shifted register) */
3893 disas_logic_reg(s
, insn
);
3895 case 0x0b: /* Add/subtract */
3896 if (insn
& (1 << 21)) { /* (extended register) */
3897 disas_add_sub_ext_reg(s
, insn
);
3899 disas_add_sub_reg(s
, insn
);
3902 case 0x1b: /* Data-processing (3 source) */
3903 disas_data_proc_3src(s
, insn
);
3906 switch (extract32(insn
, 21, 3)) {
3907 case 0x0: /* Add/subtract (with carry) */
3908 disas_adc_sbc(s
, insn
);
3910 case 0x2: /* Conditional compare */
3911 disas_cc(s
, insn
); /* both imm and reg forms */
3913 case 0x4: /* Conditional select */
3914 disas_cond_select(s
, insn
);
3916 case 0x6: /* Data-processing */
3917 if (insn
& (1 << 30)) { /* (1 source) */
3918 disas_data_proc_1src(s
, insn
);
3919 } else { /* (2 source) */
3920 disas_data_proc_2src(s
, insn
);
3924 unallocated_encoding(s
);
3929 unallocated_encoding(s
);
3934 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
3935 unsigned int rn
, unsigned int rm
,
3936 bool cmp_with_zero
, bool signal_all_nans
)
3938 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
3939 TCGv_ptr fpst
= get_fpstatus_ptr();
3942 TCGv_i64 tcg_vn
, tcg_vm
;
3944 tcg_vn
= read_fp_dreg(s
, rn
);
3945 if (cmp_with_zero
) {
3946 tcg_vm
= tcg_const_i64(0);
3948 tcg_vm
= read_fp_dreg(s
, rm
);
3950 if (signal_all_nans
) {
3951 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3953 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3955 tcg_temp_free_i64(tcg_vn
);
3956 tcg_temp_free_i64(tcg_vm
);
3958 TCGv_i32 tcg_vn
, tcg_vm
;
3960 tcg_vn
= read_fp_sreg(s
, rn
);
3961 if (cmp_with_zero
) {
3962 tcg_vm
= tcg_const_i32(0);
3964 tcg_vm
= read_fp_sreg(s
, rm
);
3966 if (signal_all_nans
) {
3967 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3969 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3971 tcg_temp_free_i32(tcg_vn
);
3972 tcg_temp_free_i32(tcg_vm
);
3975 tcg_temp_free_ptr(fpst
);
3977 gen_set_nzcv(tcg_flags
);
3979 tcg_temp_free_i64(tcg_flags
);
3982 /* C3.6.22 Floating point compare
3983 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
3984 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3985 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
3986 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3988 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
3990 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
3992 mos
= extract32(insn
, 29, 3);
3993 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3994 rm
= extract32(insn
, 16, 5);
3995 op
= extract32(insn
, 14, 2);
3996 rn
= extract32(insn
, 5, 5);
3997 opc
= extract32(insn
, 3, 2);
3998 op2r
= extract32(insn
, 0, 3);
4000 if (mos
|| op
|| op2r
|| type
> 1) {
4001 unallocated_encoding(s
);
4005 if (!fp_access_check(s
)) {
4009 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4012 /* C3.6.23 Floating point conditional compare
4013 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4014 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4015 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4016 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4018 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4020 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4022 int label_continue
= -1;
4024 mos
= extract32(insn
, 29, 3);
4025 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4026 rm
= extract32(insn
, 16, 5);
4027 cond
= extract32(insn
, 12, 4);
4028 rn
= extract32(insn
, 5, 5);
4029 op
= extract32(insn
, 4, 1);
4030 nzcv
= extract32(insn
, 0, 4);
4032 if (mos
|| type
> 1) {
4033 unallocated_encoding(s
);
4037 if (!fp_access_check(s
)) {
4041 if (cond
< 0x0e) { /* not always */
4042 int label_match
= gen_new_label();
4043 label_continue
= gen_new_label();
4044 arm_gen_test_cc(cond
, label_match
);
4046 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4047 gen_set_nzcv(tcg_flags
);
4048 tcg_temp_free_i64(tcg_flags
);
4049 tcg_gen_br(label_continue
);
4050 gen_set_label(label_match
);
4053 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4056 gen_set_label(label_continue
);
4060 /* copy src FP register to dst FP register; type specifies single or double */
4061 static void gen_mov_fp2fp(DisasContext
*s
, int type
, int dst
, int src
)
4064 TCGv_i64 v
= read_fp_dreg(s
, src
);
4065 write_fp_dreg(s
, dst
, v
);
4066 tcg_temp_free_i64(v
);
4068 TCGv_i32 v
= read_fp_sreg(s
, src
);
4069 write_fp_sreg(s
, dst
, v
);
4070 tcg_temp_free_i32(v
);
4074 /* C3.6.24 Floating point conditional select
4075 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4076 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4077 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4078 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4080 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4082 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4083 int label_continue
= -1;
4085 mos
= extract32(insn
, 29, 3);
4086 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4087 rm
= extract32(insn
, 16, 5);
4088 cond
= extract32(insn
, 12, 4);
4089 rn
= extract32(insn
, 5, 5);
4090 rd
= extract32(insn
, 0, 5);
4092 if (mos
|| type
> 1) {
4093 unallocated_encoding(s
);
4097 if (!fp_access_check(s
)) {
4101 if (cond
< 0x0e) { /* not always */
4102 int label_match
= gen_new_label();
4103 label_continue
= gen_new_label();
4104 arm_gen_test_cc(cond
, label_match
);
4106 gen_mov_fp2fp(s
, type
, rd
, rm
);
4107 tcg_gen_br(label_continue
);
4108 gen_set_label(label_match
);
4111 gen_mov_fp2fp(s
, type
, rd
, rn
);
4113 if (cond
< 0x0e) { /* continue */
4114 gen_set_label(label_continue
);
4118 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4119 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4125 fpst
= get_fpstatus_ptr();
4126 tcg_op
= read_fp_sreg(s
, rn
);
4127 tcg_res
= tcg_temp_new_i32();
4130 case 0x0: /* FMOV */
4131 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4133 case 0x1: /* FABS */
4134 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4136 case 0x2: /* FNEG */
4137 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4139 case 0x3: /* FSQRT */
4140 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4142 case 0x8: /* FRINTN */
4143 case 0x9: /* FRINTP */
4144 case 0xa: /* FRINTM */
4145 case 0xb: /* FRINTZ */
4146 case 0xc: /* FRINTA */
4148 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4150 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4151 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4153 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4154 tcg_temp_free_i32(tcg_rmode
);
4157 case 0xe: /* FRINTX */
4158 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4160 case 0xf: /* FRINTI */
4161 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4167 write_fp_sreg(s
, rd
, tcg_res
);
4169 tcg_temp_free_ptr(fpst
);
4170 tcg_temp_free_i32(tcg_op
);
4171 tcg_temp_free_i32(tcg_res
);
4174 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4175 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4181 fpst
= get_fpstatus_ptr();
4182 tcg_op
= read_fp_dreg(s
, rn
);
4183 tcg_res
= tcg_temp_new_i64();
4186 case 0x0: /* FMOV */
4187 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4189 case 0x1: /* FABS */
4190 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4192 case 0x2: /* FNEG */
4193 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4195 case 0x3: /* FSQRT */
4196 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4198 case 0x8: /* FRINTN */
4199 case 0x9: /* FRINTP */
4200 case 0xa: /* FRINTM */
4201 case 0xb: /* FRINTZ */
4202 case 0xc: /* FRINTA */
4204 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4206 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4207 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4209 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4210 tcg_temp_free_i32(tcg_rmode
);
4213 case 0xe: /* FRINTX */
4214 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4216 case 0xf: /* FRINTI */
4217 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4223 write_fp_dreg(s
, rd
, tcg_res
);
4225 tcg_temp_free_ptr(fpst
);
4226 tcg_temp_free_i64(tcg_op
);
4227 tcg_temp_free_i64(tcg_res
);
4230 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4231 int rd
, int rn
, int dtype
, int ntype
)
4236 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4238 /* Single to double */
4239 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4240 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4241 write_fp_dreg(s
, rd
, tcg_rd
);
4242 tcg_temp_free_i64(tcg_rd
);
4244 /* Single to half */
4245 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4246 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4247 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4248 write_fp_sreg(s
, rd
, tcg_rd
);
4249 tcg_temp_free_i32(tcg_rd
);
4251 tcg_temp_free_i32(tcg_rn
);
4256 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4257 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4259 /* Double to single */
4260 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4262 /* Double to half */
4263 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4264 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4266 write_fp_sreg(s
, rd
, tcg_rd
);
4267 tcg_temp_free_i32(tcg_rd
);
4268 tcg_temp_free_i64(tcg_rn
);
4273 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4274 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4276 /* Half to single */
4277 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4278 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4279 write_fp_sreg(s
, rd
, tcg_rd
);
4280 tcg_temp_free_i32(tcg_rd
);
4282 /* Half to double */
4283 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4284 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4285 write_fp_dreg(s
, rd
, tcg_rd
);
4286 tcg_temp_free_i64(tcg_rd
);
4288 tcg_temp_free_i32(tcg_rn
);
4296 /* C3.6.25 Floating point data-processing (1 source)
4297 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4298 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4299 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4300 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4302 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4304 int type
= extract32(insn
, 22, 2);
4305 int opcode
= extract32(insn
, 15, 6);
4306 int rn
= extract32(insn
, 5, 5);
4307 int rd
= extract32(insn
, 0, 5);
4310 case 0x4: case 0x5: case 0x7:
4312 /* FCVT between half, single and double precision */
4313 int dtype
= extract32(opcode
, 0, 2);
4314 if (type
== 2 || dtype
== type
) {
4315 unallocated_encoding(s
);
4318 if (!fp_access_check(s
)) {
4322 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4328 /* 32-to-32 and 64-to-64 ops */
4331 if (!fp_access_check(s
)) {
4335 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4338 if (!fp_access_check(s
)) {
4342 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4345 unallocated_encoding(s
);
4349 unallocated_encoding(s
);
4354 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4355 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4356 int rd
, int rn
, int rm
)
4363 tcg_res
= tcg_temp_new_i32();
4364 fpst
= get_fpstatus_ptr();
4365 tcg_op1
= read_fp_sreg(s
, rn
);
4366 tcg_op2
= read_fp_sreg(s
, rm
);
4369 case 0x0: /* FMUL */
4370 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4372 case 0x1: /* FDIV */
4373 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4375 case 0x2: /* FADD */
4376 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4378 case 0x3: /* FSUB */
4379 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4381 case 0x4: /* FMAX */
4382 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4384 case 0x5: /* FMIN */
4385 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4387 case 0x6: /* FMAXNM */
4388 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4390 case 0x7: /* FMINNM */
4391 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4393 case 0x8: /* FNMUL */
4394 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4395 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4399 write_fp_sreg(s
, rd
, tcg_res
);
4401 tcg_temp_free_ptr(fpst
);
4402 tcg_temp_free_i32(tcg_op1
);
4403 tcg_temp_free_i32(tcg_op2
);
4404 tcg_temp_free_i32(tcg_res
);
4407 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4408 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4409 int rd
, int rn
, int rm
)
4416 tcg_res
= tcg_temp_new_i64();
4417 fpst
= get_fpstatus_ptr();
4418 tcg_op1
= read_fp_dreg(s
, rn
);
4419 tcg_op2
= read_fp_dreg(s
, rm
);
4422 case 0x0: /* FMUL */
4423 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4425 case 0x1: /* FDIV */
4426 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4428 case 0x2: /* FADD */
4429 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4431 case 0x3: /* FSUB */
4432 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4434 case 0x4: /* FMAX */
4435 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4437 case 0x5: /* FMIN */
4438 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4440 case 0x6: /* FMAXNM */
4441 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4443 case 0x7: /* FMINNM */
4444 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4446 case 0x8: /* FNMUL */
4447 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4448 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4452 write_fp_dreg(s
, rd
, tcg_res
);
4454 tcg_temp_free_ptr(fpst
);
4455 tcg_temp_free_i64(tcg_op1
);
4456 tcg_temp_free_i64(tcg_op2
);
4457 tcg_temp_free_i64(tcg_res
);
4460 /* C3.6.26 Floating point data-processing (2 source)
4461 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4462 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4463 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4464 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4466 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4468 int type
= extract32(insn
, 22, 2);
4469 int rd
= extract32(insn
, 0, 5);
4470 int rn
= extract32(insn
, 5, 5);
4471 int rm
= extract32(insn
, 16, 5);
4472 int opcode
= extract32(insn
, 12, 4);
4475 unallocated_encoding(s
);
4481 if (!fp_access_check(s
)) {
4484 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4487 if (!fp_access_check(s
)) {
4490 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4493 unallocated_encoding(s
);
4497 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4498 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4499 int rd
, int rn
, int rm
, int ra
)
4501 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4502 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4503 TCGv_ptr fpst
= get_fpstatus_ptr();
4505 tcg_op1
= read_fp_sreg(s
, rn
);
4506 tcg_op2
= read_fp_sreg(s
, rm
);
4507 tcg_op3
= read_fp_sreg(s
, ra
);
4509 /* These are fused multiply-add, and must be done as one
4510 * floating point operation with no rounding between the
4511 * multiplication and addition steps.
4512 * NB that doing the negations here as separate steps is
4513 * correct : an input NaN should come out with its sign bit
4514 * flipped if it is a negated-input.
4517 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4521 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4524 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4526 write_fp_sreg(s
, rd
, tcg_res
);
4528 tcg_temp_free_ptr(fpst
);
4529 tcg_temp_free_i32(tcg_op1
);
4530 tcg_temp_free_i32(tcg_op2
);
4531 tcg_temp_free_i32(tcg_op3
);
4532 tcg_temp_free_i32(tcg_res
);
4535 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4536 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4537 int rd
, int rn
, int rm
, int ra
)
4539 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4540 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4541 TCGv_ptr fpst
= get_fpstatus_ptr();
4543 tcg_op1
= read_fp_dreg(s
, rn
);
4544 tcg_op2
= read_fp_dreg(s
, rm
);
4545 tcg_op3
= read_fp_dreg(s
, ra
);
4547 /* These are fused multiply-add, and must be done as one
4548 * floating point operation with no rounding between the
4549 * multiplication and addition steps.
4550 * NB that doing the negations here as separate steps is
4551 * correct : an input NaN should come out with its sign bit
4552 * flipped if it is a negated-input.
4555 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4559 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4562 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4564 write_fp_dreg(s
, rd
, tcg_res
);
4566 tcg_temp_free_ptr(fpst
);
4567 tcg_temp_free_i64(tcg_op1
);
4568 tcg_temp_free_i64(tcg_op2
);
4569 tcg_temp_free_i64(tcg_op3
);
4570 tcg_temp_free_i64(tcg_res
);
4573 /* C3.6.27 Floating point data-processing (3 source)
4574 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4575 * +---+---+---+-----------+------+----+------+----+------+------+------+
4576 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4577 * +---+---+---+-----------+------+----+------+----+------+------+------+
4579 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4581 int type
= extract32(insn
, 22, 2);
4582 int rd
= extract32(insn
, 0, 5);
4583 int rn
= extract32(insn
, 5, 5);
4584 int ra
= extract32(insn
, 10, 5);
4585 int rm
= extract32(insn
, 16, 5);
4586 bool o0
= extract32(insn
, 15, 1);
4587 bool o1
= extract32(insn
, 21, 1);
4591 if (!fp_access_check(s
)) {
4594 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4597 if (!fp_access_check(s
)) {
4600 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4603 unallocated_encoding(s
);
4607 /* C3.6.28 Floating point immediate
4608 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4609 * +---+---+---+-----------+------+---+------------+-------+------+------+
4610 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4611 * +---+---+---+-----------+------+---+------------+-------+------+------+
4613 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4615 int rd
= extract32(insn
, 0, 5);
4616 int imm8
= extract32(insn
, 13, 8);
4617 int is_double
= extract32(insn
, 22, 2);
4621 if (is_double
> 1) {
4622 unallocated_encoding(s
);
4626 if (!fp_access_check(s
)) {
4630 /* The imm8 encodes the sign bit, enough bits to represent
4631 * an exponent in the range 01....1xx to 10....0xx,
4632 * and the most significant 4 bits of the mantissa; see
4633 * VFPExpandImm() in the v8 ARM ARM.
4636 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4637 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4638 extract32(imm8
, 0, 6);
4641 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4642 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4643 (extract32(imm8
, 0, 6) << 3);
4647 tcg_res
= tcg_const_i64(imm
);
4648 write_fp_dreg(s
, rd
, tcg_res
);
4649 tcg_temp_free_i64(tcg_res
);
4652 /* Handle floating point <=> fixed point conversions. Note that we can
4653 * also deal with fp <=> integer conversions as a special case (scale == 64)
4654 * OPTME: consider handling that special case specially or at least skipping
4655 * the call to scalbn in the helpers for zero shifts.
4657 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4658 bool itof
, int rmode
, int scale
, int sf
, int type
)
4660 bool is_signed
= !(opcode
& 1);
4661 bool is_double
= type
;
4662 TCGv_ptr tcg_fpstatus
;
4665 tcg_fpstatus
= get_fpstatus_ptr();
4667 tcg_shift
= tcg_const_i32(64 - scale
);
4670 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4672 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4675 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4677 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4680 tcg_int
= tcg_extend
;
4684 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4686 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4687 tcg_shift
, tcg_fpstatus
);
4689 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4690 tcg_shift
, tcg_fpstatus
);
4692 write_fp_dreg(s
, rd
, tcg_double
);
4693 tcg_temp_free_i64(tcg_double
);
4695 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4697 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4698 tcg_shift
, tcg_fpstatus
);
4700 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4701 tcg_shift
, tcg_fpstatus
);
4703 write_fp_sreg(s
, rd
, tcg_single
);
4704 tcg_temp_free_i32(tcg_single
);
4707 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4710 if (extract32(opcode
, 2, 1)) {
4711 /* There are too many rounding modes to all fit into rmode,
4712 * so FCVTA[US] is a special case.
4714 rmode
= FPROUNDING_TIEAWAY
;
4717 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4719 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4722 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4725 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4726 tcg_shift
, tcg_fpstatus
);
4728 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4729 tcg_shift
, tcg_fpstatus
);
4733 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4734 tcg_shift
, tcg_fpstatus
);
4736 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4737 tcg_shift
, tcg_fpstatus
);
4740 tcg_temp_free_i64(tcg_double
);
4742 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4745 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4746 tcg_shift
, tcg_fpstatus
);
4748 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4749 tcg_shift
, tcg_fpstatus
);
4752 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4754 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4755 tcg_shift
, tcg_fpstatus
);
4757 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4758 tcg_shift
, tcg_fpstatus
);
4760 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4761 tcg_temp_free_i32(tcg_dest
);
4763 tcg_temp_free_i32(tcg_single
);
4766 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4767 tcg_temp_free_i32(tcg_rmode
);
4770 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4774 tcg_temp_free_ptr(tcg_fpstatus
);
4775 tcg_temp_free_i32(tcg_shift
);
4778 /* C3.6.29 Floating point <-> fixed point conversions
4779 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4780 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4781 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4782 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4784 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4786 int rd
= extract32(insn
, 0, 5);
4787 int rn
= extract32(insn
, 5, 5);
4788 int scale
= extract32(insn
, 10, 6);
4789 int opcode
= extract32(insn
, 16, 3);
4790 int rmode
= extract32(insn
, 19, 2);
4791 int type
= extract32(insn
, 22, 2);
4792 bool sbit
= extract32(insn
, 29, 1);
4793 bool sf
= extract32(insn
, 31, 1);
4796 if (sbit
|| (type
> 1)
4797 || (!sf
&& scale
< 32)) {
4798 unallocated_encoding(s
);
4802 switch ((rmode
<< 3) | opcode
) {
4803 case 0x2: /* SCVTF */
4804 case 0x3: /* UCVTF */
4807 case 0x18: /* FCVTZS */
4808 case 0x19: /* FCVTZU */
4812 unallocated_encoding(s
);
4816 if (!fp_access_check(s
)) {
4820 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
4823 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
4825 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
4826 * without conversion.
4830 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4836 TCGv_i64 tmp
= tcg_temp_new_i64();
4837 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
4838 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4839 tcg_gen_movi_i64(tmp
, 0);
4840 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4841 tcg_temp_free_i64(tmp
);
4847 TCGv_i64 tmp
= tcg_const_i64(0);
4848 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4849 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4850 tcg_temp_free_i64(tmp
);
4854 /* 64 bit to top half. */
4855 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4859 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4864 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
4868 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
4871 /* 64 bits from top half */
4872 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
4878 /* C3.6.30 Floating point <-> integer conversions
4879 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4880 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4881 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
4882 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4884 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
4886 int rd
= extract32(insn
, 0, 5);
4887 int rn
= extract32(insn
, 5, 5);
4888 int opcode
= extract32(insn
, 16, 3);
4889 int rmode
= extract32(insn
, 19, 2);
4890 int type
= extract32(insn
, 22, 2);
4891 bool sbit
= extract32(insn
, 29, 1);
4892 bool sf
= extract32(insn
, 31, 1);
4895 unallocated_encoding(s
);
4901 bool itof
= opcode
& 1;
4904 unallocated_encoding(s
);
4908 switch (sf
<< 3 | type
<< 1 | rmode
) {
4909 case 0x0: /* 32 bit */
4910 case 0xa: /* 64 bit */
4911 case 0xd: /* 64 bit to top half of quad */
4914 /* all other sf/type/rmode combinations are invalid */
4915 unallocated_encoding(s
);
4919 if (!fp_access_check(s
)) {
4922 handle_fmov(s
, rd
, rn
, type
, itof
);
4924 /* actual FP conversions */
4925 bool itof
= extract32(opcode
, 1, 1);
4927 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
4928 unallocated_encoding(s
);
4932 if (!fp_access_check(s
)) {
4935 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
4939 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
4940 * 31 30 29 28 25 24 0
4941 * +---+---+---+---------+-----------------------------+
4942 * | | 0 | | 1 1 1 1 | |
4943 * +---+---+---+---------+-----------------------------+
4945 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
4947 if (extract32(insn
, 24, 1)) {
4948 /* Floating point data-processing (3 source) */
4949 disas_fp_3src(s
, insn
);
4950 } else if (extract32(insn
, 21, 1) == 0) {
4951 /* Floating point to fixed point conversions */
4952 disas_fp_fixed_conv(s
, insn
);
4954 switch (extract32(insn
, 10, 2)) {
4956 /* Floating point conditional compare */
4957 disas_fp_ccomp(s
, insn
);
4960 /* Floating point data-processing (2 source) */
4961 disas_fp_2src(s
, insn
);
4964 /* Floating point conditional select */
4965 disas_fp_csel(s
, insn
);
4968 switch (ctz32(extract32(insn
, 12, 4))) {
4969 case 0: /* [15:12] == xxx1 */
4970 /* Floating point immediate */
4971 disas_fp_imm(s
, insn
);
4973 case 1: /* [15:12] == xx10 */
4974 /* Floating point compare */
4975 disas_fp_compare(s
, insn
);
4977 case 2: /* [15:12] == x100 */
4978 /* Floating point data-processing (1 source) */
4979 disas_fp_1src(s
, insn
);
4981 case 3: /* [15:12] == 1000 */
4982 unallocated_encoding(s
);
4984 default: /* [15:12] == 0000 */
4985 /* Floating point <-> integer conversions */
4986 disas_fp_int_conv(s
, insn
);
4994 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
4997 /* Extract 64 bits from the middle of two concatenated 64 bit
4998 * vector register slices left:right. The extracted bits start
4999 * at 'pos' bits into the right (least significant) side.
5000 * We return the result in tcg_right, and guarantee not to
5003 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5004 assert(pos
> 0 && pos
< 64);
5006 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5007 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5008 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5010 tcg_temp_free_i64(tcg_tmp
);
5014 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5015 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5016 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5017 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5019 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5021 int is_q
= extract32(insn
, 30, 1);
5022 int op2
= extract32(insn
, 22, 2);
5023 int imm4
= extract32(insn
, 11, 4);
5024 int rm
= extract32(insn
, 16, 5);
5025 int rn
= extract32(insn
, 5, 5);
5026 int rd
= extract32(insn
, 0, 5);
5027 int pos
= imm4
<< 3;
5028 TCGv_i64 tcg_resl
, tcg_resh
;
5030 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5031 unallocated_encoding(s
);
5035 if (!fp_access_check(s
)) {
5039 tcg_resh
= tcg_temp_new_i64();
5040 tcg_resl
= tcg_temp_new_i64();
5042 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5043 * either extracting 128 bits from a 128:128 concatenation, or
5044 * extracting 64 bits from a 64:64 concatenation.
5047 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5049 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5050 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5052 tcg_gen_movi_i64(tcg_resh
, 0);
5059 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5060 EltPosns
*elt
= eltposns
;
5067 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5069 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5072 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5073 tcg_hh
= tcg_temp_new_i64();
5074 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5075 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5076 tcg_temp_free_i64(tcg_hh
);
5080 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5081 tcg_temp_free_i64(tcg_resl
);
5082 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5083 tcg_temp_free_i64(tcg_resh
);
5087 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5088 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5089 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5090 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5092 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5094 int op2
= extract32(insn
, 22, 2);
5095 int is_q
= extract32(insn
, 30, 1);
5096 int rm
= extract32(insn
, 16, 5);
5097 int rn
= extract32(insn
, 5, 5);
5098 int rd
= extract32(insn
, 0, 5);
5099 int is_tblx
= extract32(insn
, 12, 1);
5100 int len
= extract32(insn
, 13, 2);
5101 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5102 TCGv_i32 tcg_regno
, tcg_numregs
;
5105 unallocated_encoding(s
);
5109 if (!fp_access_check(s
)) {
5113 /* This does a table lookup: for every byte element in the input
5114 * we index into a table formed from up to four vector registers,
5115 * and then the output is the result of the lookups. Our helper
5116 * function does the lookup operation for a single 64 bit part of
5119 tcg_resl
= tcg_temp_new_i64();
5120 tcg_resh
= tcg_temp_new_i64();
5123 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5125 tcg_gen_movi_i64(tcg_resl
, 0);
5127 if (is_tblx
&& is_q
) {
5128 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5130 tcg_gen_movi_i64(tcg_resh
, 0);
5133 tcg_idx
= tcg_temp_new_i64();
5134 tcg_regno
= tcg_const_i32(rn
);
5135 tcg_numregs
= tcg_const_i32(len
+ 1);
5136 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5137 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5138 tcg_regno
, tcg_numregs
);
5140 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5141 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5142 tcg_regno
, tcg_numregs
);
5144 tcg_temp_free_i64(tcg_idx
);
5145 tcg_temp_free_i32(tcg_regno
);
5146 tcg_temp_free_i32(tcg_numregs
);
5148 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5149 tcg_temp_free_i64(tcg_resl
);
5150 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5151 tcg_temp_free_i64(tcg_resh
);
5154 /* C3.6.3 ZIP/UZP/TRN
5155 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5156 * +---+---+-------------+------+---+------+---+------------------+------+
5157 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5158 * +---+---+-------------+------+---+------+---+------------------+------+
5160 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5162 int rd
= extract32(insn
, 0, 5);
5163 int rn
= extract32(insn
, 5, 5);
5164 int rm
= extract32(insn
, 16, 5);
5165 int size
= extract32(insn
, 22, 2);
5166 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5167 * bit 2 indicates 1 vs 2 variant of the insn.
5169 int opcode
= extract32(insn
, 12, 2);
5170 bool part
= extract32(insn
, 14, 1);
5171 bool is_q
= extract32(insn
, 30, 1);
5172 int esize
= 8 << size
;
5174 int datasize
= is_q
? 128 : 64;
5175 int elements
= datasize
/ esize
;
5176 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5178 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5179 unallocated_encoding(s
);
5183 if (!fp_access_check(s
)) {
5187 tcg_resl
= tcg_const_i64(0);
5188 tcg_resh
= tcg_const_i64(0);
5189 tcg_res
= tcg_temp_new_i64();
5191 for (i
= 0; i
< elements
; i
++) {
5193 case 1: /* UZP1/2 */
5195 int midpoint
= elements
/ 2;
5197 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5199 read_vec_element(s
, tcg_res
, rm
,
5200 2 * (i
- midpoint
) + part
, size
);
5204 case 2: /* TRN1/2 */
5206 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5208 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5211 case 3: /* ZIP1/2 */
5213 int base
= part
* elements
/ 2;
5215 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5217 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5222 g_assert_not_reached();
5227 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5228 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5230 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5231 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5235 tcg_temp_free_i64(tcg_res
);
5237 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5238 tcg_temp_free_i64(tcg_resl
);
5239 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5240 tcg_temp_free_i64(tcg_resh
);
5243 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5244 int opc
, bool is_min
, TCGv_ptr fpst
)
5246 /* Helper function for disas_simd_across_lanes: do a single precision
5247 * min/max operation on the specified two inputs,
5248 * and return the result in tcg_elt1.
5252 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5254 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5259 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5261 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5266 /* C3.6.4 AdvSIMD across lanes
5267 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5268 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5269 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5270 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5272 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5274 int rd
= extract32(insn
, 0, 5);
5275 int rn
= extract32(insn
, 5, 5);
5276 int size
= extract32(insn
, 22, 2);
5277 int opcode
= extract32(insn
, 12, 5);
5278 bool is_q
= extract32(insn
, 30, 1);
5279 bool is_u
= extract32(insn
, 29, 1);
5281 bool is_min
= false;
5285 TCGv_i64 tcg_res
, tcg_elt
;
5288 case 0x1b: /* ADDV */
5290 unallocated_encoding(s
);
5294 case 0x3: /* SADDLV, UADDLV */
5295 case 0xa: /* SMAXV, UMAXV */
5296 case 0x1a: /* SMINV, UMINV */
5297 if (size
== 3 || (size
== 2 && !is_q
)) {
5298 unallocated_encoding(s
);
5302 case 0xc: /* FMAXNMV, FMINNMV */
5303 case 0xf: /* FMAXV, FMINV */
5304 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5305 unallocated_encoding(s
);
5308 /* Bit 1 of size field encodes min vs max, and actual size is always
5309 * 32 bits: adjust the size variable so following code can rely on it
5311 is_min
= extract32(size
, 1, 1);
5316 unallocated_encoding(s
);
5320 if (!fp_access_check(s
)) {
5325 elements
= (is_q
? 128 : 64) / esize
;
5327 tcg_res
= tcg_temp_new_i64();
5328 tcg_elt
= tcg_temp_new_i64();
5330 /* These instructions operate across all lanes of a vector
5331 * to produce a single result. We can guarantee that a 64
5332 * bit intermediate is sufficient:
5333 * + for [US]ADDLV the maximum element size is 32 bits, and
5334 * the result type is 64 bits
5335 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5336 * same as the element size, which is 32 bits at most
5337 * For the integer operations we can choose to work at 64
5338 * or 32 bits and truncate at the end; for simplicity
5339 * we use 64 bits always. The floating point
5340 * ops do require 32 bit intermediates, though.
5343 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5345 for (i
= 1; i
< elements
; i
++) {
5346 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5349 case 0x03: /* SADDLV / UADDLV */
5350 case 0x1b: /* ADDV */
5351 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5353 case 0x0a: /* SMAXV / UMAXV */
5354 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5356 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5358 case 0x1a: /* SMINV / UMINV */
5359 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5361 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5365 g_assert_not_reached();
5370 /* Floating point ops which work on 32 bit (single) intermediates.
5371 * Note that correct NaN propagation requires that we do these
5372 * operations in exactly the order specified by the pseudocode.
5374 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5375 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5376 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5377 TCGv_ptr fpst
= get_fpstatus_ptr();
5379 assert(esize
== 32);
5380 assert(elements
== 4);
5382 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5383 tcg_gen_trunc_i64_i32(tcg_elt1
, tcg_elt
);
5384 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5385 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5387 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5389 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5390 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5391 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5392 tcg_gen_trunc_i64_i32(tcg_elt3
, tcg_elt
);
5394 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5396 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5398 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5399 tcg_temp_free_i32(tcg_elt1
);
5400 tcg_temp_free_i32(tcg_elt2
);
5401 tcg_temp_free_i32(tcg_elt3
);
5402 tcg_temp_free_ptr(fpst
);
5405 tcg_temp_free_i64(tcg_elt
);
5407 /* Now truncate the result to the width required for the final output */
5408 if (opcode
== 0x03) {
5409 /* SADDLV, UADDLV: result is 2*esize */
5415 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5418 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5421 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5426 g_assert_not_reached();
5429 write_fp_dreg(s
, rd
, tcg_res
);
5430 tcg_temp_free_i64(tcg_res
);
5433 /* C6.3.31 DUP (Element, Vector)
5435 * 31 30 29 21 20 16 15 10 9 5 4 0
5436 * +---+---+-------------------+--------+-------------+------+------+
5437 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5438 * +---+---+-------------------+--------+-------------+------+------+
5440 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5442 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5445 int size
= ctz32(imm5
);
5446 int esize
= 8 << size
;
5447 int elements
= (is_q
? 128 : 64) / esize
;
5451 if (size
> 3 || (size
== 3 && !is_q
)) {
5452 unallocated_encoding(s
);
5456 if (!fp_access_check(s
)) {
5460 index
= imm5
>> (size
+ 1);
5462 tmp
= tcg_temp_new_i64();
5463 read_vec_element(s
, tmp
, rn
, index
, size
);
5465 for (i
= 0; i
< elements
; i
++) {
5466 write_vec_element(s
, tmp
, rd
, i
, size
);
5470 clear_vec_high(s
, rd
);
5473 tcg_temp_free_i64(tmp
);
5476 /* C6.3.31 DUP (element, scalar)
5477 * 31 21 20 16 15 10 9 5 4 0
5478 * +-----------------------+--------+-------------+------+------+
5479 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5480 * +-----------------------+--------+-------------+------+------+
5482 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5485 int size
= ctz32(imm5
);
5490 unallocated_encoding(s
);
5494 if (!fp_access_check(s
)) {
5498 index
= imm5
>> (size
+ 1);
5500 /* This instruction just extracts the specified element and
5501 * zero-extends it into the bottom of the destination register.
5503 tmp
= tcg_temp_new_i64();
5504 read_vec_element(s
, tmp
, rn
, index
, size
);
5505 write_fp_dreg(s
, rd
, tmp
);
5506 tcg_temp_free_i64(tmp
);
5509 /* C6.3.32 DUP (General)
5511 * 31 30 29 21 20 16 15 10 9 5 4 0
5512 * +---+---+-------------------+--------+-------------+------+------+
5513 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5514 * +---+---+-------------------+--------+-------------+------+------+
5516 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5518 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5521 int size
= ctz32(imm5
);
5522 int esize
= 8 << size
;
5523 int elements
= (is_q
? 128 : 64)/esize
;
5526 if (size
> 3 || ((size
== 3) && !is_q
)) {
5527 unallocated_encoding(s
);
5531 if (!fp_access_check(s
)) {
5535 for (i
= 0; i
< elements
; i
++) {
5536 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5539 clear_vec_high(s
, rd
);
5543 /* C6.3.150 INS (Element)
5545 * 31 21 20 16 15 14 11 10 9 5 4 0
5546 * +-----------------------+--------+------------+---+------+------+
5547 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5548 * +-----------------------+--------+------------+---+------+------+
5550 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5551 * index: encoded in imm5<4:size+1>
5553 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5556 int size
= ctz32(imm5
);
5557 int src_index
, dst_index
;
5561 unallocated_encoding(s
);
5565 if (!fp_access_check(s
)) {
5569 dst_index
= extract32(imm5
, 1+size
, 5);
5570 src_index
= extract32(imm4
, size
, 4);
5572 tmp
= tcg_temp_new_i64();
5574 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5575 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5577 tcg_temp_free_i64(tmp
);
5581 /* C6.3.151 INS (General)
5583 * 31 21 20 16 15 10 9 5 4 0
5584 * +-----------------------+--------+-------------+------+------+
5585 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5586 * +-----------------------+--------+-------------+------+------+
5588 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5589 * index: encoded in imm5<4:size+1>
5591 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5593 int size
= ctz32(imm5
);
5597 unallocated_encoding(s
);
5601 if (!fp_access_check(s
)) {
5605 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5606 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5610 * C6.3.321 UMOV (General)
5611 * C6.3.237 SMOV (General)
5613 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5614 * +---+---+-------------------+--------+-------------+------+------+
5615 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5616 * +---+---+-------------------+--------+-------------+------+------+
5618 * U: unsigned when set
5619 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5621 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5622 int rn
, int rd
, int imm5
)
5624 int size
= ctz32(imm5
);
5628 /* Check for UnallocatedEncodings */
5630 if (size
> 2 || (size
== 2 && !is_q
)) {
5631 unallocated_encoding(s
);
5636 || (size
< 3 && is_q
)
5637 || (size
== 3 && !is_q
)) {
5638 unallocated_encoding(s
);
5643 if (!fp_access_check(s
)) {
5647 element
= extract32(imm5
, 1+size
, 4);
5649 tcg_rd
= cpu_reg(s
, rd
);
5650 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5651 if (is_signed
&& !is_q
) {
5652 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5656 /* C3.6.5 AdvSIMD copy
5657 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5658 * +---+---+----+-----------------+------+---+------+---+------+------+
5659 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5660 * +---+---+----+-----------------+------+---+------+---+------+------+
5662 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5664 int rd
= extract32(insn
, 0, 5);
5665 int rn
= extract32(insn
, 5, 5);
5666 int imm4
= extract32(insn
, 11, 4);
5667 int op
= extract32(insn
, 29, 1);
5668 int is_q
= extract32(insn
, 30, 1);
5669 int imm5
= extract32(insn
, 16, 5);
5674 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5676 unallocated_encoding(s
);
5681 /* DUP (element - vector) */
5682 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5686 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5691 handle_simd_insg(s
, rd
, rn
, imm5
);
5693 unallocated_encoding(s
);
5698 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5699 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5702 unallocated_encoding(s
);
5708 /* C3.6.6 AdvSIMD modified immediate
5709 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5710 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5711 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5712 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5714 * There are a number of operations that can be carried out here:
5715 * MOVI - move (shifted) imm into register
5716 * MVNI - move inverted (shifted) imm into register
5717 * ORR - bitwise OR of (shifted) imm with register
5718 * BIC - bitwise clear of (shifted) imm with register
5720 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5722 int rd
= extract32(insn
, 0, 5);
5723 int cmode
= extract32(insn
, 12, 4);
5724 int cmode_3_1
= extract32(cmode
, 1, 3);
5725 int cmode_0
= extract32(cmode
, 0, 1);
5726 int o2
= extract32(insn
, 11, 1);
5727 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5728 bool is_neg
= extract32(insn
, 29, 1);
5729 bool is_q
= extract32(insn
, 30, 1);
5731 TCGv_i64 tcg_rd
, tcg_imm
;
5734 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5735 unallocated_encoding(s
);
5739 if (!fp_access_check(s
)) {
5743 /* See AdvSIMDExpandImm() in ARM ARM */
5744 switch (cmode_3_1
) {
5745 case 0: /* Replicate(Zeros(24):imm8, 2) */
5746 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5747 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5748 case 3: /* Replicate(imm8:Zeros(24), 2) */
5750 int shift
= cmode_3_1
* 8;
5751 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5754 case 4: /* Replicate(Zeros(8):imm8, 4) */
5755 case 5: /* Replicate(imm8:Zeros(8), 4) */
5757 int shift
= (cmode_3_1
& 0x1) * 8;
5758 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5763 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5764 imm
= (abcdefgh
<< 16) | 0xffff;
5766 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5767 imm
= (abcdefgh
<< 8) | 0xff;
5769 imm
= bitfield_replicate(imm
, 32);
5772 if (!cmode_0
&& !is_neg
) {
5773 imm
= bitfield_replicate(abcdefgh
, 8);
5774 } else if (!cmode_0
&& is_neg
) {
5777 for (i
= 0; i
< 8; i
++) {
5778 if ((abcdefgh
) & (1 << i
)) {
5779 imm
|= 0xffULL
<< (i
* 8);
5782 } else if (cmode_0
) {
5784 imm
= (abcdefgh
& 0x3f) << 48;
5785 if (abcdefgh
& 0x80) {
5786 imm
|= 0x8000000000000000ULL
;
5788 if (abcdefgh
& 0x40) {
5789 imm
|= 0x3fc0000000000000ULL
;
5791 imm
|= 0x4000000000000000ULL
;
5794 imm
= (abcdefgh
& 0x3f) << 19;
5795 if (abcdefgh
& 0x80) {
5798 if (abcdefgh
& 0x40) {
5809 if (cmode_3_1
!= 7 && is_neg
) {
5813 tcg_imm
= tcg_const_i64(imm
);
5814 tcg_rd
= new_tmp_a64(s
);
5816 for (i
= 0; i
< 2; i
++) {
5817 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
5819 if (i
== 1 && !is_q
) {
5820 /* non-quad ops clear high half of vector */
5821 tcg_gen_movi_i64(tcg_rd
, 0);
5822 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
5823 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
5826 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5829 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5833 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
5835 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
5838 tcg_temp_free_i64(tcg_imm
);
5841 /* C3.6.7 AdvSIMD scalar copy
5842 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5843 * +-----+----+-----------------+------+---+------+---+------+------+
5844 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5845 * +-----+----+-----------------+------+---+------+---+------+------+
5847 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
5849 int rd
= extract32(insn
, 0, 5);
5850 int rn
= extract32(insn
, 5, 5);
5851 int imm4
= extract32(insn
, 11, 4);
5852 int imm5
= extract32(insn
, 16, 5);
5853 int op
= extract32(insn
, 29, 1);
5855 if (op
!= 0 || imm4
!= 0) {
5856 unallocated_encoding(s
);
5860 /* DUP (element, scalar) */
5861 handle_simd_dupes(s
, rd
, rn
, imm5
);
5864 /* C3.6.8 AdvSIMD scalar pairwise
5865 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5866 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5867 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5868 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5870 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
5872 int u
= extract32(insn
, 29, 1);
5873 int size
= extract32(insn
, 22, 2);
5874 int opcode
= extract32(insn
, 12, 5);
5875 int rn
= extract32(insn
, 5, 5);
5876 int rd
= extract32(insn
, 0, 5);
5879 /* For some ops (the FP ones), size[1] is part of the encoding.
5880 * For ADDP strictly it is not but size[1] is always 1 for valid
5883 opcode
|= (extract32(size
, 1, 1) << 5);
5886 case 0x3b: /* ADDP */
5887 if (u
|| size
!= 3) {
5888 unallocated_encoding(s
);
5891 if (!fp_access_check(s
)) {
5895 TCGV_UNUSED_PTR(fpst
);
5897 case 0xc: /* FMAXNMP */
5898 case 0xd: /* FADDP */
5899 case 0xf: /* FMAXP */
5900 case 0x2c: /* FMINNMP */
5901 case 0x2f: /* FMINP */
5902 /* FP op, size[0] is 32 or 64 bit */
5904 unallocated_encoding(s
);
5907 if (!fp_access_check(s
)) {
5911 size
= extract32(size
, 0, 1) ? 3 : 2;
5912 fpst
= get_fpstatus_ptr();
5915 unallocated_encoding(s
);
5920 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
5921 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
5922 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5924 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
5925 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
5928 case 0x3b: /* ADDP */
5929 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
5931 case 0xc: /* FMAXNMP */
5932 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5934 case 0xd: /* FADDP */
5935 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5937 case 0xf: /* FMAXP */
5938 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5940 case 0x2c: /* FMINNMP */
5941 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5943 case 0x2f: /* FMINP */
5944 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5947 g_assert_not_reached();
5950 write_fp_dreg(s
, rd
, tcg_res
);
5952 tcg_temp_free_i64(tcg_op1
);
5953 tcg_temp_free_i64(tcg_op2
);
5954 tcg_temp_free_i64(tcg_res
);
5956 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
5957 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
5958 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5960 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
5961 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
5964 case 0xc: /* FMAXNMP */
5965 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5967 case 0xd: /* FADDP */
5968 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5970 case 0xf: /* FMAXP */
5971 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5973 case 0x2c: /* FMINNMP */
5974 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5976 case 0x2f: /* FMINP */
5977 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5980 g_assert_not_reached();
5983 write_fp_sreg(s
, rd
, tcg_res
);
5985 tcg_temp_free_i32(tcg_op1
);
5986 tcg_temp_free_i32(tcg_op2
);
5987 tcg_temp_free_i32(tcg_res
);
5990 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
5991 tcg_temp_free_ptr(fpst
);
5996 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
5998 * This code is handles the common shifting code and is used by both
5999 * the vector and scalar code.
6001 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6002 TCGv_i64 tcg_rnd
, bool accumulate
,
6003 bool is_u
, int size
, int shift
)
6005 bool extended_result
= false;
6006 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6008 TCGv_i64 tcg_src_hi
;
6010 if (round
&& size
== 3) {
6011 extended_result
= true;
6012 ext_lshift
= 64 - shift
;
6013 tcg_src_hi
= tcg_temp_new_i64();
6014 } else if (shift
== 64) {
6015 if (!accumulate
&& is_u
) {
6016 /* result is zero */
6017 tcg_gen_movi_i64(tcg_res
, 0);
6022 /* Deal with the rounding step */
6024 if (extended_result
) {
6025 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6027 /* take care of sign extending tcg_res */
6028 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6029 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6030 tcg_src
, tcg_src_hi
,
6033 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6037 tcg_temp_free_i64(tcg_zero
);
6039 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6043 /* Now do the shift right */
6044 if (round
&& extended_result
) {
6045 /* extended case, >64 bit precision required */
6046 if (ext_lshift
== 0) {
6047 /* special case, only high bits matter */
6048 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6050 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6051 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6052 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6057 /* essentially shifting in 64 zeros */
6058 tcg_gen_movi_i64(tcg_src
, 0);
6060 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6064 /* effectively extending the sign-bit */
6065 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6067 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6073 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6075 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6078 if (extended_result
) {
6079 tcg_temp_free_i64(tcg_src_hi
);
6083 /* Common SHL/SLI - Shift left with an optional insert */
6084 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6085 bool insert
, int shift
)
6087 if (insert
) { /* SLI */
6088 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6090 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6094 /* SRI: shift right with insert */
6095 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6096 int size
, int shift
)
6098 int esize
= 8 << size
;
6100 /* shift count same as element size is valid but does nothing;
6101 * special case to avoid potential shift by 64.
6103 if (shift
!= esize
) {
6104 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6105 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6109 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6110 static void handle_scalar_simd_shri(DisasContext
*s
,
6111 bool is_u
, int immh
, int immb
,
6112 int opcode
, int rn
, int rd
)
6115 int immhb
= immh
<< 3 | immb
;
6116 int shift
= 2 * (8 << size
) - immhb
;
6117 bool accumulate
= false;
6119 bool insert
= false;
6124 if (!extract32(immh
, 3, 1)) {
6125 unallocated_encoding(s
);
6129 if (!fp_access_check(s
)) {
6134 case 0x02: /* SSRA / USRA (accumulate) */
6137 case 0x04: /* SRSHR / URSHR (rounding) */
6140 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6141 accumulate
= round
= true;
6143 case 0x08: /* SRI */
6149 uint64_t round_const
= 1ULL << (shift
- 1);
6150 tcg_round
= tcg_const_i64(round_const
);
6152 TCGV_UNUSED_I64(tcg_round
);
6155 tcg_rn
= read_fp_dreg(s
, rn
);
6156 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6159 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6161 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6162 accumulate
, is_u
, size
, shift
);
6165 write_fp_dreg(s
, rd
, tcg_rd
);
6167 tcg_temp_free_i64(tcg_rn
);
6168 tcg_temp_free_i64(tcg_rd
);
6170 tcg_temp_free_i64(tcg_round
);
6174 /* SHL/SLI - Scalar shift left */
6175 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6176 int immh
, int immb
, int opcode
,
6179 int size
= 32 - clz32(immh
) - 1;
6180 int immhb
= immh
<< 3 | immb
;
6181 int shift
= immhb
- (8 << size
);
6182 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6183 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6185 if (!extract32(immh
, 3, 1)) {
6186 unallocated_encoding(s
);
6190 if (!fp_access_check(s
)) {
6194 tcg_rn
= read_fp_dreg(s
, rn
);
6195 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6197 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6199 write_fp_dreg(s
, rd
, tcg_rd
);
6201 tcg_temp_free_i64(tcg_rn
);
6202 tcg_temp_free_i64(tcg_rd
);
6205 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6206 * (signed/unsigned) narrowing */
6207 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6208 bool is_u_shift
, bool is_u_narrow
,
6209 int immh
, int immb
, int opcode
,
6212 int immhb
= immh
<< 3 | immb
;
6213 int size
= 32 - clz32(immh
) - 1;
6214 int esize
= 8 << size
;
6215 int shift
= (2 * esize
) - immhb
;
6216 int elements
= is_scalar
? 1 : (64 / esize
);
6217 bool round
= extract32(opcode
, 0, 1);
6218 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6219 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6220 TCGv_i32 tcg_rd_narrowed
;
6223 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6224 { gen_helper_neon_narrow_sat_s8
,
6225 gen_helper_neon_unarrow_sat8
},
6226 { gen_helper_neon_narrow_sat_s16
,
6227 gen_helper_neon_unarrow_sat16
},
6228 { gen_helper_neon_narrow_sat_s32
,
6229 gen_helper_neon_unarrow_sat32
},
6232 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6233 gen_helper_neon_narrow_sat_u8
,
6234 gen_helper_neon_narrow_sat_u16
,
6235 gen_helper_neon_narrow_sat_u32
,
6238 NeonGenNarrowEnvFn
*narrowfn
;
6244 if (extract32(immh
, 3, 1)) {
6245 unallocated_encoding(s
);
6249 if (!fp_access_check(s
)) {
6254 narrowfn
= unsigned_narrow_fns
[size
];
6256 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6259 tcg_rn
= tcg_temp_new_i64();
6260 tcg_rd
= tcg_temp_new_i64();
6261 tcg_rd_narrowed
= tcg_temp_new_i32();
6262 tcg_final
= tcg_const_i64(0);
6265 uint64_t round_const
= 1ULL << (shift
- 1);
6266 tcg_round
= tcg_const_i64(round_const
);
6268 TCGV_UNUSED_I64(tcg_round
);
6271 for (i
= 0; i
< elements
; i
++) {
6272 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6273 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6274 false, is_u_shift
, size
+1, shift
);
6275 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6276 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6277 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6281 clear_vec_high(s
, rd
);
6282 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6284 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6288 tcg_temp_free_i64(tcg_round
);
6290 tcg_temp_free_i64(tcg_rn
);
6291 tcg_temp_free_i64(tcg_rd
);
6292 tcg_temp_free_i32(tcg_rd_narrowed
);
6293 tcg_temp_free_i64(tcg_final
);
6297 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6298 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6299 bool src_unsigned
, bool dst_unsigned
,
6300 int immh
, int immb
, int rn
, int rd
)
6302 int immhb
= immh
<< 3 | immb
;
6303 int size
= 32 - clz32(immh
) - 1;
6304 int shift
= immhb
- (8 << size
);
6308 assert(!(scalar
&& is_q
));
6311 if (!is_q
&& extract32(immh
, 3, 1)) {
6312 unallocated_encoding(s
);
6316 /* Since we use the variable-shift helpers we must
6317 * replicate the shift count into each element of
6318 * the tcg_shift value.
6322 shift
|= shift
<< 8;
6325 shift
|= shift
<< 16;
6331 g_assert_not_reached();
6335 if (!fp_access_check(s
)) {
6340 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6341 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6342 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6343 { NULL
, gen_helper_neon_qshl_u64
},
6345 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6346 int maxpass
= is_q
? 2 : 1;
6348 for (pass
= 0; pass
< maxpass
; pass
++) {
6349 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6351 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6352 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6353 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6355 tcg_temp_free_i64(tcg_op
);
6357 tcg_temp_free_i64(tcg_shift
);
6360 clear_vec_high(s
, rd
);
6363 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6364 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6366 { gen_helper_neon_qshl_s8
,
6367 gen_helper_neon_qshl_s16
,
6368 gen_helper_neon_qshl_s32
},
6369 { gen_helper_neon_qshlu_s8
,
6370 gen_helper_neon_qshlu_s16
,
6371 gen_helper_neon_qshlu_s32
}
6373 { NULL
, NULL
, NULL
},
6374 { gen_helper_neon_qshl_u8
,
6375 gen_helper_neon_qshl_u16
,
6376 gen_helper_neon_qshl_u32
}
6379 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6380 TCGMemOp memop
= scalar
? size
: MO_32
;
6381 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6383 for (pass
= 0; pass
< maxpass
; pass
++) {
6384 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6386 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6387 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6391 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6394 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6399 g_assert_not_reached();
6401 write_fp_sreg(s
, rd
, tcg_op
);
6403 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6406 tcg_temp_free_i32(tcg_op
);
6408 tcg_temp_free_i32(tcg_shift
);
6410 if (!is_q
&& !scalar
) {
6411 clear_vec_high(s
, rd
);
6416 /* Common vector code for handling integer to FP conversion */
6417 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6418 int elements
, int is_signed
,
6419 int fracbits
, int size
)
6421 bool is_double
= size
== 3 ? true : false;
6422 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6423 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6424 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6425 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6428 for (pass
= 0; pass
< elements
; pass
++) {
6429 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6432 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6434 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6435 tcg_shift
, tcg_fpst
);
6437 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6438 tcg_shift
, tcg_fpst
);
6440 if (elements
== 1) {
6441 write_fp_dreg(s
, rd
, tcg_double
);
6443 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6445 tcg_temp_free_i64(tcg_double
);
6447 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6449 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6450 tcg_shift
, tcg_fpst
);
6452 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6453 tcg_shift
, tcg_fpst
);
6455 if (elements
== 1) {
6456 write_fp_sreg(s
, rd
, tcg_single
);
6458 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6460 tcg_temp_free_i32(tcg_single
);
6464 if (!is_double
&& elements
== 2) {
6465 clear_vec_high(s
, rd
);
6468 tcg_temp_free_i64(tcg_int
);
6469 tcg_temp_free_ptr(tcg_fpst
);
6470 tcg_temp_free_i32(tcg_shift
);
6473 /* UCVTF/SCVTF - Integer to FP conversion */
6474 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6475 bool is_q
, bool is_u
,
6476 int immh
, int immb
, int opcode
,
6479 bool is_double
= extract32(immh
, 3, 1);
6480 int size
= is_double
? MO_64
: MO_32
;
6482 int immhb
= immh
<< 3 | immb
;
6483 int fracbits
= (is_double
? 128 : 64) - immhb
;
6485 if (!extract32(immh
, 2, 2)) {
6486 unallocated_encoding(s
);
6493 elements
= is_double
? 2 : is_q
? 4 : 2;
6494 if (is_double
&& !is_q
) {
6495 unallocated_encoding(s
);
6500 if (!fp_access_check(s
)) {
6504 /* immh == 0 would be a failure of the decode logic */
6507 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6510 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6511 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6512 bool is_q
, bool is_u
,
6513 int immh
, int immb
, int rn
, int rd
)
6515 bool is_double
= extract32(immh
, 3, 1);
6516 int immhb
= immh
<< 3 | immb
;
6517 int fracbits
= (is_double
? 128 : 64) - immhb
;
6519 TCGv_ptr tcg_fpstatus
;
6520 TCGv_i32 tcg_rmode
, tcg_shift
;
6522 if (!extract32(immh
, 2, 2)) {
6523 unallocated_encoding(s
);
6527 if (!is_scalar
&& !is_q
&& is_double
) {
6528 unallocated_encoding(s
);
6532 if (!fp_access_check(s
)) {
6536 assert(!(is_scalar
&& is_q
));
6538 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6539 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6540 tcg_fpstatus
= get_fpstatus_ptr();
6541 tcg_shift
= tcg_const_i32(fracbits
);
6544 int maxpass
= is_scalar
? 1 : 2;
6546 for (pass
= 0; pass
< maxpass
; pass
++) {
6547 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6549 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6551 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6553 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6555 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6556 tcg_temp_free_i64(tcg_op
);
6559 clear_vec_high(s
, rd
);
6562 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6563 for (pass
= 0; pass
< maxpass
; pass
++) {
6564 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6566 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6568 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6570 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6573 write_fp_sreg(s
, rd
, tcg_op
);
6575 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6577 tcg_temp_free_i32(tcg_op
);
6579 if (!is_q
&& !is_scalar
) {
6580 clear_vec_high(s
, rd
);
6584 tcg_temp_free_ptr(tcg_fpstatus
);
6585 tcg_temp_free_i32(tcg_shift
);
6586 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6587 tcg_temp_free_i32(tcg_rmode
);
6590 /* C3.6.9 AdvSIMD scalar shift by immediate
6591 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6592 * +-----+---+-------------+------+------+--------+---+------+------+
6593 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6594 * +-----+---+-------------+------+------+--------+---+------+------+
6596 * This is the scalar version so it works on a fixed sized registers
6598 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6600 int rd
= extract32(insn
, 0, 5);
6601 int rn
= extract32(insn
, 5, 5);
6602 int opcode
= extract32(insn
, 11, 5);
6603 int immb
= extract32(insn
, 16, 3);
6604 int immh
= extract32(insn
, 19, 4);
6605 bool is_u
= extract32(insn
, 29, 1);
6608 unallocated_encoding(s
);
6613 case 0x08: /* SRI */
6615 unallocated_encoding(s
);
6619 case 0x00: /* SSHR / USHR */
6620 case 0x02: /* SSRA / USRA */
6621 case 0x04: /* SRSHR / URSHR */
6622 case 0x06: /* SRSRA / URSRA */
6623 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6625 case 0x0a: /* SHL / SLI */
6626 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6628 case 0x1c: /* SCVTF, UCVTF */
6629 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6632 case 0x10: /* SQSHRUN, SQSHRUN2 */
6633 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6635 unallocated_encoding(s
);
6638 handle_vec_simd_sqshrn(s
, true, false, false, true,
6639 immh
, immb
, opcode
, rn
, rd
);
6641 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6642 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6643 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6644 immh
, immb
, opcode
, rn
, rd
);
6646 case 0xc: /* SQSHLU */
6648 unallocated_encoding(s
);
6651 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
6653 case 0xe: /* SQSHL, UQSHL */
6654 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
6656 case 0x1f: /* FCVTZS, FCVTZU */
6657 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
6660 unallocated_encoding(s
);
6665 /* C3.6.10 AdvSIMD scalar three different
6666 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6667 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6668 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6669 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6671 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6673 bool is_u
= extract32(insn
, 29, 1);
6674 int size
= extract32(insn
, 22, 2);
6675 int opcode
= extract32(insn
, 12, 4);
6676 int rm
= extract32(insn
, 16, 5);
6677 int rn
= extract32(insn
, 5, 5);
6678 int rd
= extract32(insn
, 0, 5);
6681 unallocated_encoding(s
);
6686 case 0x9: /* SQDMLAL, SQDMLAL2 */
6687 case 0xb: /* SQDMLSL, SQDMLSL2 */
6688 case 0xd: /* SQDMULL, SQDMULL2 */
6689 if (size
== 0 || size
== 3) {
6690 unallocated_encoding(s
);
6695 unallocated_encoding(s
);
6699 if (!fp_access_check(s
)) {
6704 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6705 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6706 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6708 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6709 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6711 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6712 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6715 case 0xd: /* SQDMULL, SQDMULL2 */
6717 case 0xb: /* SQDMLSL, SQDMLSL2 */
6718 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6720 case 0x9: /* SQDMLAL, SQDMLAL2 */
6721 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6722 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6726 g_assert_not_reached();
6729 write_fp_dreg(s
, rd
, tcg_res
);
6731 tcg_temp_free_i64(tcg_op1
);
6732 tcg_temp_free_i64(tcg_op2
);
6733 tcg_temp_free_i64(tcg_res
);
6735 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6736 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6737 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6739 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6740 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6742 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6743 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6746 case 0xd: /* SQDMULL, SQDMULL2 */
6748 case 0xb: /* SQDMLSL, SQDMLSL2 */
6749 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6751 case 0x9: /* SQDMLAL, SQDMLAL2 */
6753 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6754 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6755 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6757 tcg_temp_free_i64(tcg_op3
);
6761 g_assert_not_reached();
6764 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6765 write_fp_dreg(s
, rd
, tcg_res
);
6767 tcg_temp_free_i32(tcg_op1
);
6768 tcg_temp_free_i32(tcg_op2
);
6769 tcg_temp_free_i64(tcg_res
);
6773 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6774 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6776 /* Handle 64x64->64 opcodes which are shared between the scalar
6777 * and vector 3-same groups. We cover every opcode where size == 3
6778 * is valid in either the three-reg-same (integer, not pairwise)
6779 * or scalar-three-reg-same groups. (Some opcodes are not yet
6785 case 0x1: /* SQADD */
6787 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6789 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6792 case 0x5: /* SQSUB */
6794 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6796 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6799 case 0x6: /* CMGT, CMHI */
6800 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6801 * We implement this using setcond (test) and then negating.
6803 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6805 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6806 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6808 case 0x7: /* CMGE, CMHS */
6809 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6811 case 0x11: /* CMTST, CMEQ */
6816 /* CMTST : test is "if (X & Y != 0)". */
6817 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6818 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
6819 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6821 case 0x8: /* SSHL, USHL */
6823 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6825 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6828 case 0x9: /* SQSHL, UQSHL */
6830 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6832 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6835 case 0xa: /* SRSHL, URSHL */
6837 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6839 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6842 case 0xb: /* SQRSHL, UQRSHL */
6844 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6846 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6849 case 0x10: /* ADD, SUB */
6851 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6853 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6857 g_assert_not_reached();
6861 /* Handle the 3-same-operands float operations; shared by the scalar
6862 * and vector encodings. The caller must filter out any encodings
6863 * not allocated for the encoding it is dealing with.
6865 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
6866 int fpopcode
, int rd
, int rn
, int rm
)
6869 TCGv_ptr fpst
= get_fpstatus_ptr();
6871 for (pass
= 0; pass
< elements
; pass
++) {
6874 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6875 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6876 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6878 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
6879 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
6882 case 0x39: /* FMLS */
6883 /* As usual for ARM, separate negation for fused multiply-add */
6884 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6886 case 0x19: /* FMLA */
6887 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6888 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
6891 case 0x18: /* FMAXNM */
6892 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6894 case 0x1a: /* FADD */
6895 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6897 case 0x1b: /* FMULX */
6898 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6900 case 0x1c: /* FCMEQ */
6901 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6903 case 0x1e: /* FMAX */
6904 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6906 case 0x1f: /* FRECPS */
6907 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6909 case 0x38: /* FMINNM */
6910 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6912 case 0x3a: /* FSUB */
6913 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6915 case 0x3e: /* FMIN */
6916 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6918 case 0x3f: /* FRSQRTS */
6919 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6921 case 0x5b: /* FMUL */
6922 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6924 case 0x5c: /* FCMGE */
6925 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6927 case 0x5d: /* FACGE */
6928 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6930 case 0x5f: /* FDIV */
6931 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6933 case 0x7a: /* FABD */
6934 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6935 gen_helper_vfp_absd(tcg_res
, tcg_res
);
6937 case 0x7c: /* FCMGT */
6938 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6940 case 0x7d: /* FACGT */
6941 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6944 g_assert_not_reached();
6947 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6949 tcg_temp_free_i64(tcg_res
);
6950 tcg_temp_free_i64(tcg_op1
);
6951 tcg_temp_free_i64(tcg_op2
);
6954 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6955 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6956 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6958 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
6959 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
6962 case 0x39: /* FMLS */
6963 /* As usual for ARM, separate negation for fused multiply-add */
6964 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6966 case 0x19: /* FMLA */
6967 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6968 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
6971 case 0x1a: /* FADD */
6972 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6974 case 0x1b: /* FMULX */
6975 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6977 case 0x1c: /* FCMEQ */
6978 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6980 case 0x1e: /* FMAX */
6981 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6983 case 0x1f: /* FRECPS */
6984 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6986 case 0x18: /* FMAXNM */
6987 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6989 case 0x38: /* FMINNM */
6990 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6992 case 0x3a: /* FSUB */
6993 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6995 case 0x3e: /* FMIN */
6996 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6998 case 0x3f: /* FRSQRTS */
6999 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7001 case 0x5b: /* FMUL */
7002 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7004 case 0x5c: /* FCMGE */
7005 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7007 case 0x5d: /* FACGE */
7008 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7010 case 0x5f: /* FDIV */
7011 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7013 case 0x7a: /* FABD */
7014 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7015 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7017 case 0x7c: /* FCMGT */
7018 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7020 case 0x7d: /* FACGT */
7021 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7024 g_assert_not_reached();
7027 if (elements
== 1) {
7028 /* scalar single so clear high part */
7029 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7031 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7032 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7033 tcg_temp_free_i64(tcg_tmp
);
7035 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7038 tcg_temp_free_i32(tcg_res
);
7039 tcg_temp_free_i32(tcg_op1
);
7040 tcg_temp_free_i32(tcg_op2
);
7044 tcg_temp_free_ptr(fpst
);
7046 if ((elements
<< size
) < 4) {
7047 /* scalar, or non-quad vector op */
7048 clear_vec_high(s
, rd
);
7052 /* C3.6.11 AdvSIMD scalar three same
7053 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7054 * +-----+---+-----------+------+---+------+--------+---+------+------+
7055 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7056 * +-----+---+-----------+------+---+------+--------+---+------+------+
7058 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7060 int rd
= extract32(insn
, 0, 5);
7061 int rn
= extract32(insn
, 5, 5);
7062 int opcode
= extract32(insn
, 11, 5);
7063 int rm
= extract32(insn
, 16, 5);
7064 int size
= extract32(insn
, 22, 2);
7065 bool u
= extract32(insn
, 29, 1);
7068 if (opcode
>= 0x18) {
7069 /* Floating point: U, size[1] and opcode indicate operation */
7070 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7072 case 0x1b: /* FMULX */
7073 case 0x1f: /* FRECPS */
7074 case 0x3f: /* FRSQRTS */
7075 case 0x5d: /* FACGE */
7076 case 0x7d: /* FACGT */
7077 case 0x1c: /* FCMEQ */
7078 case 0x5c: /* FCMGE */
7079 case 0x7c: /* FCMGT */
7080 case 0x7a: /* FABD */
7083 unallocated_encoding(s
);
7087 if (!fp_access_check(s
)) {
7091 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7096 case 0x1: /* SQADD, UQADD */
7097 case 0x5: /* SQSUB, UQSUB */
7098 case 0x9: /* SQSHL, UQSHL */
7099 case 0xb: /* SQRSHL, UQRSHL */
7101 case 0x8: /* SSHL, USHL */
7102 case 0xa: /* SRSHL, URSHL */
7103 case 0x6: /* CMGT, CMHI */
7104 case 0x7: /* CMGE, CMHS */
7105 case 0x11: /* CMTST, CMEQ */
7106 case 0x10: /* ADD, SUB (vector) */
7108 unallocated_encoding(s
);
7112 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7113 if (size
!= 1 && size
!= 2) {
7114 unallocated_encoding(s
);
7119 unallocated_encoding(s
);
7123 if (!fp_access_check(s
)) {
7127 tcg_rd
= tcg_temp_new_i64();
7130 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7131 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7133 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7134 tcg_temp_free_i64(tcg_rn
);
7135 tcg_temp_free_i64(tcg_rm
);
7137 /* Do a single operation on the lowest element in the vector.
7138 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7139 * no side effects for all these operations.
7140 * OPTME: special-purpose helpers would avoid doing some
7141 * unnecessary work in the helper for the 8 and 16 bit cases.
7143 NeonGenTwoOpEnvFn
*genenvfn
;
7144 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7145 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7146 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7148 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7149 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7152 case 0x1: /* SQADD, UQADD */
7154 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7155 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7156 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7157 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7159 genenvfn
= fns
[size
][u
];
7162 case 0x5: /* SQSUB, UQSUB */
7164 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7165 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7166 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7167 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7169 genenvfn
= fns
[size
][u
];
7172 case 0x9: /* SQSHL, UQSHL */
7174 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7175 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7176 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7177 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7179 genenvfn
= fns
[size
][u
];
7182 case 0xb: /* SQRSHL, UQRSHL */
7184 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7185 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7186 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7187 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7189 genenvfn
= fns
[size
][u
];
7192 case 0x16: /* SQDMULH, SQRDMULH */
7194 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7195 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7196 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7198 assert(size
== 1 || size
== 2);
7199 genenvfn
= fns
[size
- 1][u
];
7203 g_assert_not_reached();
7206 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7207 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7208 tcg_temp_free_i32(tcg_rd32
);
7209 tcg_temp_free_i32(tcg_rn
);
7210 tcg_temp_free_i32(tcg_rm
);
7213 write_fp_dreg(s
, rd
, tcg_rd
);
7215 tcg_temp_free_i64(tcg_rd
);
7218 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7219 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7220 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7222 /* Handle 64->64 opcodes which are shared between the scalar and
7223 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7224 * is valid in either group and also the double-precision fp ops.
7225 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7231 case 0x4: /* CLS, CLZ */
7233 gen_helper_clz64(tcg_rd
, tcg_rn
);
7235 gen_helper_cls64(tcg_rd
, tcg_rn
);
7239 /* This opcode is shared with CNT and RBIT but we have earlier
7240 * enforced that size == 3 if and only if this is the NOT insn.
7242 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7244 case 0x7: /* SQABS, SQNEG */
7246 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7248 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7251 case 0xa: /* CMLT */
7252 /* 64 bit integer comparison against zero, result is
7253 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7258 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7259 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7261 case 0x8: /* CMGT, CMGE */
7262 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7264 case 0x9: /* CMEQ, CMLE */
7265 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7267 case 0xb: /* ABS, NEG */
7269 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7271 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7272 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7273 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7275 tcg_temp_free_i64(tcg_zero
);
7278 case 0x2f: /* FABS */
7279 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7281 case 0x6f: /* FNEG */
7282 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7284 case 0x7f: /* FSQRT */
7285 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7287 case 0x1a: /* FCVTNS */
7288 case 0x1b: /* FCVTMS */
7289 case 0x1c: /* FCVTAS */
7290 case 0x3a: /* FCVTPS */
7291 case 0x3b: /* FCVTZS */
7293 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7294 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7295 tcg_temp_free_i32(tcg_shift
);
7298 case 0x5a: /* FCVTNU */
7299 case 0x5b: /* FCVTMU */
7300 case 0x5c: /* FCVTAU */
7301 case 0x7a: /* FCVTPU */
7302 case 0x7b: /* FCVTZU */
7304 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7305 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7306 tcg_temp_free_i32(tcg_shift
);
7309 case 0x18: /* FRINTN */
7310 case 0x19: /* FRINTM */
7311 case 0x38: /* FRINTP */
7312 case 0x39: /* FRINTZ */
7313 case 0x58: /* FRINTA */
7314 case 0x79: /* FRINTI */
7315 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7317 case 0x59: /* FRINTX */
7318 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7321 g_assert_not_reached();
7325 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7326 bool is_scalar
, bool is_u
, bool is_q
,
7327 int size
, int rn
, int rd
)
7329 bool is_double
= (size
== 3);
7332 if (!fp_access_check(s
)) {
7336 fpst
= get_fpstatus_ptr();
7339 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7340 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7341 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7342 NeonGenTwoDoubleOPFn
*genfn
;
7347 case 0x2e: /* FCMLT (zero) */
7350 case 0x2c: /* FCMGT (zero) */
7351 genfn
= gen_helper_neon_cgt_f64
;
7353 case 0x2d: /* FCMEQ (zero) */
7354 genfn
= gen_helper_neon_ceq_f64
;
7356 case 0x6d: /* FCMLE (zero) */
7359 case 0x6c: /* FCMGE (zero) */
7360 genfn
= gen_helper_neon_cge_f64
;
7363 g_assert_not_reached();
7366 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7367 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7369 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7371 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7373 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7376 clear_vec_high(s
, rd
);
7379 tcg_temp_free_i64(tcg_res
);
7380 tcg_temp_free_i64(tcg_zero
);
7381 tcg_temp_free_i64(tcg_op
);
7383 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7384 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7385 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7386 NeonGenTwoSingleOPFn
*genfn
;
7388 int pass
, maxpasses
;
7391 case 0x2e: /* FCMLT (zero) */
7394 case 0x2c: /* FCMGT (zero) */
7395 genfn
= gen_helper_neon_cgt_f32
;
7397 case 0x2d: /* FCMEQ (zero) */
7398 genfn
= gen_helper_neon_ceq_f32
;
7400 case 0x6d: /* FCMLE (zero) */
7403 case 0x6c: /* FCMGE (zero) */
7404 genfn
= gen_helper_neon_cge_f32
;
7407 g_assert_not_reached();
7413 maxpasses
= is_q
? 4 : 2;
7416 for (pass
= 0; pass
< maxpasses
; pass
++) {
7417 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7419 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7421 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7424 write_fp_sreg(s
, rd
, tcg_res
);
7426 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7429 tcg_temp_free_i32(tcg_res
);
7430 tcg_temp_free_i32(tcg_zero
);
7431 tcg_temp_free_i32(tcg_op
);
7432 if (!is_q
&& !is_scalar
) {
7433 clear_vec_high(s
, rd
);
7437 tcg_temp_free_ptr(fpst
);
7440 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7441 bool is_scalar
, bool is_u
, bool is_q
,
7442 int size
, int rn
, int rd
)
7444 bool is_double
= (size
== 3);
7445 TCGv_ptr fpst
= get_fpstatus_ptr();
7448 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7449 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7452 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7453 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7455 case 0x3d: /* FRECPE */
7456 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7458 case 0x3f: /* FRECPX */
7459 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7461 case 0x7d: /* FRSQRTE */
7462 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7465 g_assert_not_reached();
7467 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7470 clear_vec_high(s
, rd
);
7473 tcg_temp_free_i64(tcg_res
);
7474 tcg_temp_free_i64(tcg_op
);
7476 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7477 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7478 int pass
, maxpasses
;
7483 maxpasses
= is_q
? 4 : 2;
7486 for (pass
= 0; pass
< maxpasses
; pass
++) {
7487 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7490 case 0x3c: /* URECPE */
7491 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7493 case 0x3d: /* FRECPE */
7494 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7496 case 0x3f: /* FRECPX */
7497 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7499 case 0x7d: /* FRSQRTE */
7500 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7503 g_assert_not_reached();
7507 write_fp_sreg(s
, rd
, tcg_res
);
7509 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7512 tcg_temp_free_i32(tcg_res
);
7513 tcg_temp_free_i32(tcg_op
);
7514 if (!is_q
&& !is_scalar
) {
7515 clear_vec_high(s
, rd
);
7518 tcg_temp_free_ptr(fpst
);
7521 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7522 int opcode
, bool u
, bool is_q
,
7523 int size
, int rn
, int rd
)
7525 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7526 * in the source becomes a size element in the destination).
7529 TCGv_i32 tcg_res
[2];
7530 int destelt
= is_q
? 2 : 0;
7531 int passes
= scalar
? 1 : 2;
7534 tcg_res
[1] = tcg_const_i32(0);
7537 for (pass
= 0; pass
< passes
; pass
++) {
7538 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7539 NeonGenNarrowFn
*genfn
= NULL
;
7540 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7543 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7545 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7547 tcg_res
[pass
] = tcg_temp_new_i32();
7550 case 0x12: /* XTN, SQXTUN */
7552 static NeonGenNarrowFn
* const xtnfns
[3] = {
7553 gen_helper_neon_narrow_u8
,
7554 gen_helper_neon_narrow_u16
,
7555 tcg_gen_trunc_i64_i32
,
7557 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7558 gen_helper_neon_unarrow_sat8
,
7559 gen_helper_neon_unarrow_sat16
,
7560 gen_helper_neon_unarrow_sat32
,
7563 genenvfn
= sqxtunfns
[size
];
7565 genfn
= xtnfns
[size
];
7569 case 0x14: /* SQXTN, UQXTN */
7571 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7572 { gen_helper_neon_narrow_sat_s8
,
7573 gen_helper_neon_narrow_sat_u8
},
7574 { gen_helper_neon_narrow_sat_s16
,
7575 gen_helper_neon_narrow_sat_u16
},
7576 { gen_helper_neon_narrow_sat_s32
,
7577 gen_helper_neon_narrow_sat_u32
},
7579 genenvfn
= fns
[size
][u
];
7582 case 0x16: /* FCVTN, FCVTN2 */
7583 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7585 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7587 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7588 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7589 tcg_gen_trunc_i64_i32(tcg_lo
, tcg_op
);
7590 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7591 tcg_gen_shri_i64(tcg_op
, tcg_op
, 32);
7592 tcg_gen_trunc_i64_i32(tcg_hi
, tcg_op
);
7593 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7594 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7595 tcg_temp_free_i32(tcg_lo
);
7596 tcg_temp_free_i32(tcg_hi
);
7599 case 0x56: /* FCVTXN, FCVTXN2 */
7600 /* 64 bit to 32 bit float conversion
7601 * with von Neumann rounding (round to odd)
7604 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7607 g_assert_not_reached();
7611 genfn(tcg_res
[pass
], tcg_op
);
7612 } else if (genenvfn
) {
7613 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7616 tcg_temp_free_i64(tcg_op
);
7619 for (pass
= 0; pass
< 2; pass
++) {
7620 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7621 tcg_temp_free_i32(tcg_res
[pass
]);
7624 clear_vec_high(s
, rd
);
7628 /* Remaining saturating accumulating ops */
7629 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7630 bool is_q
, int size
, int rn
, int rd
)
7632 bool is_double
= (size
== 3);
7635 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7636 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7639 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7640 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7641 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7643 if (is_u
) { /* USQADD */
7644 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7645 } else { /* SUQADD */
7646 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7648 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7651 clear_vec_high(s
, rd
);
7654 tcg_temp_free_i64(tcg_rd
);
7655 tcg_temp_free_i64(tcg_rn
);
7657 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7658 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7659 int pass
, maxpasses
;
7664 maxpasses
= is_q
? 4 : 2;
7667 for (pass
= 0; pass
< maxpasses
; pass
++) {
7669 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
7670 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
7672 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
7673 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7676 if (is_u
) { /* USQADD */
7679 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7682 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7685 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7688 g_assert_not_reached();
7690 } else { /* SUQADD */
7693 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7696 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7699 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7702 g_assert_not_reached();
7707 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7708 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
7709 tcg_temp_free_i64(tcg_zero
);
7711 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7715 clear_vec_high(s
, rd
);
7718 tcg_temp_free_i32(tcg_rd
);
7719 tcg_temp_free_i32(tcg_rn
);
7723 /* C3.6.12 AdvSIMD scalar two reg misc
7724 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7725 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7726 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7727 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7729 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7731 int rd
= extract32(insn
, 0, 5);
7732 int rn
= extract32(insn
, 5, 5);
7733 int opcode
= extract32(insn
, 12, 5);
7734 int size
= extract32(insn
, 22, 2);
7735 bool u
= extract32(insn
, 29, 1);
7736 bool is_fcvt
= false;
7739 TCGv_ptr tcg_fpstatus
;
7742 case 0x3: /* USQADD / SUQADD*/
7743 if (!fp_access_check(s
)) {
7746 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
7748 case 0x7: /* SQABS / SQNEG */
7750 case 0xa: /* CMLT */
7752 unallocated_encoding(s
);
7756 case 0x8: /* CMGT, CMGE */
7757 case 0x9: /* CMEQ, CMLE */
7758 case 0xb: /* ABS, NEG */
7760 unallocated_encoding(s
);
7764 case 0x12: /* SQXTUN */
7766 unallocated_encoding(s
);
7770 case 0x14: /* SQXTN, UQXTN */
7772 unallocated_encoding(s
);
7775 if (!fp_access_check(s
)) {
7778 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
7783 /* Floating point: U, size[1] and opcode indicate operation;
7784 * size[0] indicates single or double precision.
7786 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7787 size
= extract32(size
, 0, 1) ? 3 : 2;
7789 case 0x2c: /* FCMGT (zero) */
7790 case 0x2d: /* FCMEQ (zero) */
7791 case 0x2e: /* FCMLT (zero) */
7792 case 0x6c: /* FCMGE (zero) */
7793 case 0x6d: /* FCMLE (zero) */
7794 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7796 case 0x1d: /* SCVTF */
7797 case 0x5d: /* UCVTF */
7799 bool is_signed
= (opcode
== 0x1d);
7800 if (!fp_access_check(s
)) {
7803 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
7806 case 0x3d: /* FRECPE */
7807 case 0x3f: /* FRECPX */
7808 case 0x7d: /* FRSQRTE */
7809 if (!fp_access_check(s
)) {
7812 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
7814 case 0x1a: /* FCVTNS */
7815 case 0x1b: /* FCVTMS */
7816 case 0x3a: /* FCVTPS */
7817 case 0x3b: /* FCVTZS */
7818 case 0x5a: /* FCVTNU */
7819 case 0x5b: /* FCVTMU */
7820 case 0x7a: /* FCVTPU */
7821 case 0x7b: /* FCVTZU */
7823 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
7825 case 0x1c: /* FCVTAS */
7826 case 0x5c: /* FCVTAU */
7827 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
7829 rmode
= FPROUNDING_TIEAWAY
;
7831 case 0x56: /* FCVTXN, FCVTXN2 */
7833 unallocated_encoding(s
);
7836 if (!fp_access_check(s
)) {
7839 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
7842 unallocated_encoding(s
);
7847 unallocated_encoding(s
);
7851 if (!fp_access_check(s
)) {
7856 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7857 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7858 tcg_fpstatus
= get_fpstatus_ptr();
7860 TCGV_UNUSED_I32(tcg_rmode
);
7861 TCGV_UNUSED_PTR(tcg_fpstatus
);
7865 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7866 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7868 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
7869 write_fp_dreg(s
, rd
, tcg_rd
);
7870 tcg_temp_free_i64(tcg_rd
);
7871 tcg_temp_free_i64(tcg_rn
);
7873 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7874 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7876 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7879 case 0x7: /* SQABS, SQNEG */
7881 NeonGenOneOpEnvFn
*genfn
;
7882 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
7883 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
7884 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
7885 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
7887 genfn
= fns
[size
][u
];
7888 genfn(tcg_rd
, cpu_env
, tcg_rn
);
7891 case 0x1a: /* FCVTNS */
7892 case 0x1b: /* FCVTMS */
7893 case 0x1c: /* FCVTAS */
7894 case 0x3a: /* FCVTPS */
7895 case 0x3b: /* FCVTZS */
7897 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7898 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7899 tcg_temp_free_i32(tcg_shift
);
7902 case 0x5a: /* FCVTNU */
7903 case 0x5b: /* FCVTMU */
7904 case 0x5c: /* FCVTAU */
7905 case 0x7a: /* FCVTPU */
7906 case 0x7b: /* FCVTZU */
7908 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7909 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7910 tcg_temp_free_i32(tcg_shift
);
7914 g_assert_not_reached();
7917 write_fp_sreg(s
, rd
, tcg_rd
);
7918 tcg_temp_free_i32(tcg_rd
);
7919 tcg_temp_free_i32(tcg_rn
);
7923 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7924 tcg_temp_free_i32(tcg_rmode
);
7925 tcg_temp_free_ptr(tcg_fpstatus
);
7929 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
7930 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
7931 int immh
, int immb
, int opcode
, int rn
, int rd
)
7933 int size
= 32 - clz32(immh
) - 1;
7934 int immhb
= immh
<< 3 | immb
;
7935 int shift
= 2 * (8 << size
) - immhb
;
7936 bool accumulate
= false;
7938 bool insert
= false;
7939 int dsize
= is_q
? 128 : 64;
7940 int esize
= 8 << size
;
7941 int elements
= dsize
/esize
;
7942 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
7943 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7944 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7948 if (extract32(immh
, 3, 1) && !is_q
) {
7949 unallocated_encoding(s
);
7953 if (size
> 3 && !is_q
) {
7954 unallocated_encoding(s
);
7958 if (!fp_access_check(s
)) {
7963 case 0x02: /* SSRA / USRA (accumulate) */
7966 case 0x04: /* SRSHR / URSHR (rounding) */
7969 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7970 accumulate
= round
= true;
7972 case 0x08: /* SRI */
7978 uint64_t round_const
= 1ULL << (shift
- 1);
7979 tcg_round
= tcg_const_i64(round_const
);
7981 TCGV_UNUSED_I64(tcg_round
);
7984 for (i
= 0; i
< elements
; i
++) {
7985 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
7986 if (accumulate
|| insert
) {
7987 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
7991 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
7993 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7994 accumulate
, is_u
, size
, shift
);
7997 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8001 clear_vec_high(s
, rd
);
8005 tcg_temp_free_i64(tcg_round
);
8009 /* SHL/SLI - Vector shift left */
8010 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8011 int immh
, int immb
, int opcode
, int rn
, int rd
)
8013 int size
= 32 - clz32(immh
) - 1;
8014 int immhb
= immh
<< 3 | immb
;
8015 int shift
= immhb
- (8 << size
);
8016 int dsize
= is_q
? 128 : 64;
8017 int esize
= 8 << size
;
8018 int elements
= dsize
/esize
;
8019 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8020 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8023 if (extract32(immh
, 3, 1) && !is_q
) {
8024 unallocated_encoding(s
);
8028 if (size
> 3 && !is_q
) {
8029 unallocated_encoding(s
);
8033 if (!fp_access_check(s
)) {
8037 for (i
= 0; i
< elements
; i
++) {
8038 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8040 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8043 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8045 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8049 clear_vec_high(s
, rd
);
8053 /* USHLL/SHLL - Vector shift left with widening */
8054 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8055 int immh
, int immb
, int opcode
, int rn
, int rd
)
8057 int size
= 32 - clz32(immh
) - 1;
8058 int immhb
= immh
<< 3 | immb
;
8059 int shift
= immhb
- (8 << size
);
8061 int esize
= 8 << size
;
8062 int elements
= dsize
/esize
;
8063 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8064 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8068 unallocated_encoding(s
);
8072 if (!fp_access_check(s
)) {
8076 /* For the LL variants the store is larger than the load,
8077 * so if rd == rn we would overwrite parts of our input.
8078 * So load everything right now and use shifts in the main loop.
8080 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8082 for (i
= 0; i
< elements
; i
++) {
8083 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8084 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8085 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8086 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8090 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8091 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8092 int immh
, int immb
, int opcode
, int rn
, int rd
)
8094 int immhb
= immh
<< 3 | immb
;
8095 int size
= 32 - clz32(immh
) - 1;
8097 int esize
= 8 << size
;
8098 int elements
= dsize
/esize
;
8099 int shift
= (2 * esize
) - immhb
;
8100 bool round
= extract32(opcode
, 0, 1);
8101 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8105 if (extract32(immh
, 3, 1)) {
8106 unallocated_encoding(s
);
8110 if (!fp_access_check(s
)) {
8114 tcg_rn
= tcg_temp_new_i64();
8115 tcg_rd
= tcg_temp_new_i64();
8116 tcg_final
= tcg_temp_new_i64();
8117 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8120 uint64_t round_const
= 1ULL << (shift
- 1);
8121 tcg_round
= tcg_const_i64(round_const
);
8123 TCGV_UNUSED_I64(tcg_round
);
8126 for (i
= 0; i
< elements
; i
++) {
8127 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8128 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8129 false, true, size
+1, shift
);
8131 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8135 clear_vec_high(s
, rd
);
8136 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8138 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8142 tcg_temp_free_i64(tcg_round
);
8144 tcg_temp_free_i64(tcg_rn
);
8145 tcg_temp_free_i64(tcg_rd
);
8146 tcg_temp_free_i64(tcg_final
);
8151 /* C3.6.14 AdvSIMD shift by immediate
8152 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8153 * +---+---+---+-------------+------+------+--------+---+------+------+
8154 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8155 * +---+---+---+-------------+------+------+--------+---+------+------+
8157 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8159 int rd
= extract32(insn
, 0, 5);
8160 int rn
= extract32(insn
, 5, 5);
8161 int opcode
= extract32(insn
, 11, 5);
8162 int immb
= extract32(insn
, 16, 3);
8163 int immh
= extract32(insn
, 19, 4);
8164 bool is_u
= extract32(insn
, 29, 1);
8165 bool is_q
= extract32(insn
, 30, 1);
8168 case 0x08: /* SRI */
8170 unallocated_encoding(s
);
8174 case 0x00: /* SSHR / USHR */
8175 case 0x02: /* SSRA / USRA (accumulate) */
8176 case 0x04: /* SRSHR / URSHR (rounding) */
8177 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8178 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8180 case 0x0a: /* SHL / SLI */
8181 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8183 case 0x10: /* SHRN */
8184 case 0x11: /* RSHRN / SQRSHRUN */
8186 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8189 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8192 case 0x12: /* SQSHRN / UQSHRN */
8193 case 0x13: /* SQRSHRN / UQRSHRN */
8194 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8197 case 0x14: /* SSHLL / USHLL */
8198 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8200 case 0x1c: /* SCVTF / UCVTF */
8201 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8204 case 0xc: /* SQSHLU */
8206 unallocated_encoding(s
);
8209 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8211 case 0xe: /* SQSHL, UQSHL */
8212 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8214 case 0x1f: /* FCVTZS/ FCVTZU */
8215 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8218 unallocated_encoding(s
);
8223 /* Generate code to do a "long" addition or subtraction, ie one done in
8224 * TCGv_i64 on vector lanes twice the width specified by size.
8226 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8227 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8229 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8230 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8231 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8232 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8234 NeonGenTwo64OpFn
*genfn
;
8237 genfn
= fns
[size
][is_sub
];
8238 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8241 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8242 int opcode
, int rd
, int rn
, int rm
)
8244 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8245 TCGv_i64 tcg_res
[2];
8248 tcg_res
[0] = tcg_temp_new_i64();
8249 tcg_res
[1] = tcg_temp_new_i64();
8251 /* Does this op do an adding accumulate, a subtracting accumulate,
8252 * or no accumulate at all?
8270 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8271 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8274 /* size == 2 means two 32x32->64 operations; this is worth special
8275 * casing because we can generally handle it inline.
8278 for (pass
= 0; pass
< 2; pass
++) {
8279 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8280 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8281 TCGv_i64 tcg_passres
;
8282 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8284 int elt
= pass
+ is_q
* 2;
8286 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8287 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8290 tcg_passres
= tcg_res
[pass
];
8292 tcg_passres
= tcg_temp_new_i64();
8296 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8297 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8299 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8300 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8302 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8303 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8305 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8306 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8308 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8309 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8310 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8312 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8313 tcg_temp_free_i64(tcg_tmp1
);
8314 tcg_temp_free_i64(tcg_tmp2
);
8317 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8318 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8319 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8320 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8322 case 9: /* SQDMLAL, SQDMLAL2 */
8323 case 11: /* SQDMLSL, SQDMLSL2 */
8324 case 13: /* SQDMULL, SQDMULL2 */
8325 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8326 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8327 tcg_passres
, tcg_passres
);
8330 g_assert_not_reached();
8333 if (opcode
== 9 || opcode
== 11) {
8334 /* saturating accumulate ops */
8336 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8338 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8339 tcg_res
[pass
], tcg_passres
);
8340 } else if (accop
> 0) {
8341 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8342 } else if (accop
< 0) {
8343 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8347 tcg_temp_free_i64(tcg_passres
);
8350 tcg_temp_free_i64(tcg_op1
);
8351 tcg_temp_free_i64(tcg_op2
);
8354 /* size 0 or 1, generally helper functions */
8355 for (pass
= 0; pass
< 2; pass
++) {
8356 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8357 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8358 TCGv_i64 tcg_passres
;
8359 int elt
= pass
+ is_q
* 2;
8361 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8362 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8365 tcg_passres
= tcg_res
[pass
];
8367 tcg_passres
= tcg_temp_new_i64();
8371 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8372 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8374 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8375 static NeonGenWidenFn
* const widenfns
[2][2] = {
8376 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8377 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8379 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8381 widenfn(tcg_op2_64
, tcg_op2
);
8382 widenfn(tcg_passres
, tcg_op1
);
8383 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8384 tcg_passres
, tcg_op2_64
);
8385 tcg_temp_free_i64(tcg_op2_64
);
8388 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8389 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8392 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8394 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8398 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8400 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8404 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8405 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8406 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8409 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8411 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8415 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8417 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8421 case 9: /* SQDMLAL, SQDMLAL2 */
8422 case 11: /* SQDMLSL, SQDMLSL2 */
8423 case 13: /* SQDMULL, SQDMULL2 */
8425 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8426 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8427 tcg_passres
, tcg_passres
);
8429 case 14: /* PMULL */
8431 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8434 g_assert_not_reached();
8436 tcg_temp_free_i32(tcg_op1
);
8437 tcg_temp_free_i32(tcg_op2
);
8440 if (opcode
== 9 || opcode
== 11) {
8441 /* saturating accumulate ops */
8443 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8445 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8449 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8450 tcg_res
[pass
], tcg_passres
);
8452 tcg_temp_free_i64(tcg_passres
);
8457 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8458 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8459 tcg_temp_free_i64(tcg_res
[0]);
8460 tcg_temp_free_i64(tcg_res
[1]);
8463 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8464 int opcode
, int rd
, int rn
, int rm
)
8466 TCGv_i64 tcg_res
[2];
8467 int part
= is_q
? 2 : 0;
8470 for (pass
= 0; pass
< 2; pass
++) {
8471 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8472 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8473 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8474 static NeonGenWidenFn
* const widenfns
[3][2] = {
8475 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8476 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8477 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8479 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8481 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8482 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8483 widenfn(tcg_op2_wide
, tcg_op2
);
8484 tcg_temp_free_i32(tcg_op2
);
8485 tcg_res
[pass
] = tcg_temp_new_i64();
8486 gen_neon_addl(size
, (opcode
== 3),
8487 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8488 tcg_temp_free_i64(tcg_op1
);
8489 tcg_temp_free_i64(tcg_op2_wide
);
8492 for (pass
= 0; pass
< 2; pass
++) {
8493 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8494 tcg_temp_free_i64(tcg_res
[pass
]);
8498 static void do_narrow_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8500 tcg_gen_shri_i64(in
, in
, 32);
8501 tcg_gen_trunc_i64_i32(res
, in
);
8504 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8506 tcg_gen_addi_i64(in
, in
, 1U << 31);
8507 do_narrow_high_u32(res
, in
);
8510 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8511 int opcode
, int rd
, int rn
, int rm
)
8513 TCGv_i32 tcg_res
[2];
8514 int part
= is_q
? 2 : 0;
8517 for (pass
= 0; pass
< 2; pass
++) {
8518 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8519 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8520 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8521 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8522 { gen_helper_neon_narrow_high_u8
,
8523 gen_helper_neon_narrow_round_high_u8
},
8524 { gen_helper_neon_narrow_high_u16
,
8525 gen_helper_neon_narrow_round_high_u16
},
8526 { do_narrow_high_u32
, do_narrow_round_high_u32
},
8528 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8530 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8531 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8533 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8535 tcg_temp_free_i64(tcg_op1
);
8536 tcg_temp_free_i64(tcg_op2
);
8538 tcg_res
[pass
] = tcg_temp_new_i32();
8539 gennarrow(tcg_res
[pass
], tcg_wideres
);
8540 tcg_temp_free_i64(tcg_wideres
);
8543 for (pass
= 0; pass
< 2; pass
++) {
8544 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8545 tcg_temp_free_i32(tcg_res
[pass
]);
8548 clear_vec_high(s
, rd
);
8552 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8554 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8555 * is the only three-reg-diff instruction which produces a
8556 * 128-bit wide result from a single operation. However since
8557 * it's possible to calculate the two halves more or less
8558 * separately we just use two helper calls.
8560 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8561 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8562 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8564 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8565 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8566 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8567 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8568 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8569 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8571 tcg_temp_free_i64(tcg_op1
);
8572 tcg_temp_free_i64(tcg_op2
);
8573 tcg_temp_free_i64(tcg_res
);
8576 /* C3.6.15 AdvSIMD three different
8577 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8578 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8579 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8580 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8582 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8584 /* Instructions in this group fall into three basic classes
8585 * (in each case with the operation working on each element in
8586 * the input vectors):
8587 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8589 * (2) wide 64 x 128 -> 128
8590 * (3) narrowing 128 x 128 -> 64
8591 * Here we do initial decode, catch unallocated cases and
8592 * dispatch to separate functions for each class.
8594 int is_q
= extract32(insn
, 30, 1);
8595 int is_u
= extract32(insn
, 29, 1);
8596 int size
= extract32(insn
, 22, 2);
8597 int opcode
= extract32(insn
, 12, 4);
8598 int rm
= extract32(insn
, 16, 5);
8599 int rn
= extract32(insn
, 5, 5);
8600 int rd
= extract32(insn
, 0, 5);
8603 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8604 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8605 /* 64 x 128 -> 128 */
8607 unallocated_encoding(s
);
8610 if (!fp_access_check(s
)) {
8613 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8615 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8616 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8617 /* 128 x 128 -> 64 */
8619 unallocated_encoding(s
);
8622 if (!fp_access_check(s
)) {
8625 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8627 case 14: /* PMULL, PMULL2 */
8628 if (is_u
|| size
== 1 || size
== 2) {
8629 unallocated_encoding(s
);
8633 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8634 unallocated_encoding(s
);
8637 if (!fp_access_check(s
)) {
8640 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8644 case 9: /* SQDMLAL, SQDMLAL2 */
8645 case 11: /* SQDMLSL, SQDMLSL2 */
8646 case 13: /* SQDMULL, SQDMULL2 */
8647 if (is_u
|| size
== 0) {
8648 unallocated_encoding(s
);
8652 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8653 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8654 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8655 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8656 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8657 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8658 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8659 /* 64 x 64 -> 128 */
8661 unallocated_encoding(s
);
8665 if (!fp_access_check(s
)) {
8669 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8672 /* opcode 15 not allocated */
8673 unallocated_encoding(s
);
8678 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8679 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
8681 int rd
= extract32(insn
, 0, 5);
8682 int rn
= extract32(insn
, 5, 5);
8683 int rm
= extract32(insn
, 16, 5);
8684 int size
= extract32(insn
, 22, 2);
8685 bool is_u
= extract32(insn
, 29, 1);
8686 bool is_q
= extract32(insn
, 30, 1);
8687 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
8690 if (!fp_access_check(s
)) {
8694 tcg_op1
= tcg_temp_new_i64();
8695 tcg_op2
= tcg_temp_new_i64();
8696 tcg_res
[0] = tcg_temp_new_i64();
8697 tcg_res
[1] = tcg_temp_new_i64();
8699 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8700 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8701 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8706 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8709 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8712 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8715 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8720 /* B* ops need res loaded to operate on */
8721 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8726 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8728 case 1: /* BSL bitwise select */
8729 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8730 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8731 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
8733 case 2: /* BIT, bitwise insert if true */
8734 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8735 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8736 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8738 case 3: /* BIF, bitwise insert if false */
8739 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8740 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8741 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8747 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8749 tcg_gen_movi_i64(tcg_res
[1], 0);
8751 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8753 tcg_temp_free_i64(tcg_op1
);
8754 tcg_temp_free_i64(tcg_op2
);
8755 tcg_temp_free_i64(tcg_res
[0]);
8756 tcg_temp_free_i64(tcg_res
[1]);
8759 /* Helper functions for 32 bit comparisons */
8760 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8762 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
8765 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8767 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
8770 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8772 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
8775 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8777 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
8780 /* Pairwise op subgroup of C3.6.16.
8782 * This is called directly or via the handle_3same_float for float pairwise
8783 * operations where the opcode and size are calculated differently.
8785 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
8786 int size
, int rn
, int rm
, int rd
)
8791 /* Floating point operations need fpst */
8792 if (opcode
>= 0x58) {
8793 fpst
= get_fpstatus_ptr();
8795 TCGV_UNUSED_PTR(fpst
);
8798 if (!fp_access_check(s
)) {
8802 /* These operations work on the concatenated rm:rn, with each pair of
8803 * adjacent elements being operated on to produce an element in the result.
8806 TCGv_i64 tcg_res
[2];
8808 for (pass
= 0; pass
< 2; pass
++) {
8809 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8810 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8811 int passreg
= (pass
== 0) ? rn
: rm
;
8813 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
8814 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
8815 tcg_res
[pass
] = tcg_temp_new_i64();
8818 case 0x17: /* ADDP */
8819 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8821 case 0x58: /* FMAXNMP */
8822 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8824 case 0x5a: /* FADDP */
8825 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8827 case 0x5e: /* FMAXP */
8828 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8830 case 0x78: /* FMINNMP */
8831 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8833 case 0x7e: /* FMINP */
8834 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8837 g_assert_not_reached();
8840 tcg_temp_free_i64(tcg_op1
);
8841 tcg_temp_free_i64(tcg_op2
);
8844 for (pass
= 0; pass
< 2; pass
++) {
8845 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8846 tcg_temp_free_i64(tcg_res
[pass
]);
8849 int maxpass
= is_q
? 4 : 2;
8850 TCGv_i32 tcg_res
[4];
8852 for (pass
= 0; pass
< maxpass
; pass
++) {
8853 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8854 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8855 NeonGenTwoOpFn
*genfn
= NULL
;
8856 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
8857 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
8859 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
8860 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
8861 tcg_res
[pass
] = tcg_temp_new_i32();
8864 case 0x17: /* ADDP */
8866 static NeonGenTwoOpFn
* const fns
[3] = {
8867 gen_helper_neon_padd_u8
,
8868 gen_helper_neon_padd_u16
,
8874 case 0x14: /* SMAXP, UMAXP */
8876 static NeonGenTwoOpFn
* const fns
[3][2] = {
8877 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
8878 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
8879 { gen_max_s32
, gen_max_u32
},
8881 genfn
= fns
[size
][u
];
8884 case 0x15: /* SMINP, UMINP */
8886 static NeonGenTwoOpFn
* const fns
[3][2] = {
8887 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
8888 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
8889 { gen_min_s32
, gen_min_u32
},
8891 genfn
= fns
[size
][u
];
8894 /* The FP operations are all on single floats (32 bit) */
8895 case 0x58: /* FMAXNMP */
8896 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8898 case 0x5a: /* FADDP */
8899 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8901 case 0x5e: /* FMAXP */
8902 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8904 case 0x78: /* FMINNMP */
8905 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8907 case 0x7e: /* FMINP */
8908 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8911 g_assert_not_reached();
8914 /* FP ops called directly, otherwise call now */
8916 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8919 tcg_temp_free_i32(tcg_op1
);
8920 tcg_temp_free_i32(tcg_op2
);
8923 for (pass
= 0; pass
< maxpass
; pass
++) {
8924 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
8925 tcg_temp_free_i32(tcg_res
[pass
]);
8928 clear_vec_high(s
, rd
);
8932 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
8933 tcg_temp_free_ptr(fpst
);
8937 /* Floating point op subgroup of C3.6.16. */
8938 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
8940 /* For floating point ops, the U, size[1] and opcode bits
8941 * together indicate the operation. size[0] indicates single
8944 int fpopcode
= extract32(insn
, 11, 5)
8945 | (extract32(insn
, 23, 1) << 5)
8946 | (extract32(insn
, 29, 1) << 6);
8947 int is_q
= extract32(insn
, 30, 1);
8948 int size
= extract32(insn
, 22, 1);
8949 int rm
= extract32(insn
, 16, 5);
8950 int rn
= extract32(insn
, 5, 5);
8951 int rd
= extract32(insn
, 0, 5);
8953 int datasize
= is_q
? 128 : 64;
8954 int esize
= 32 << size
;
8955 int elements
= datasize
/ esize
;
8957 if (size
== 1 && !is_q
) {
8958 unallocated_encoding(s
);
8963 case 0x58: /* FMAXNMP */
8964 case 0x5a: /* FADDP */
8965 case 0x5e: /* FMAXP */
8966 case 0x78: /* FMINNMP */
8967 case 0x7e: /* FMINP */
8968 if (size
&& !is_q
) {
8969 unallocated_encoding(s
);
8972 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
8975 case 0x1b: /* FMULX */
8976 case 0x1f: /* FRECPS */
8977 case 0x3f: /* FRSQRTS */
8978 case 0x5d: /* FACGE */
8979 case 0x7d: /* FACGT */
8980 case 0x19: /* FMLA */
8981 case 0x39: /* FMLS */
8982 case 0x18: /* FMAXNM */
8983 case 0x1a: /* FADD */
8984 case 0x1c: /* FCMEQ */
8985 case 0x1e: /* FMAX */
8986 case 0x38: /* FMINNM */
8987 case 0x3a: /* FSUB */
8988 case 0x3e: /* FMIN */
8989 case 0x5b: /* FMUL */
8990 case 0x5c: /* FCMGE */
8991 case 0x5f: /* FDIV */
8992 case 0x7a: /* FABD */
8993 case 0x7c: /* FCMGT */
8994 if (!fp_access_check(s
)) {
8998 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9001 unallocated_encoding(s
);
9006 /* Integer op subgroup of C3.6.16. */
9007 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9009 int is_q
= extract32(insn
, 30, 1);
9010 int u
= extract32(insn
, 29, 1);
9011 int size
= extract32(insn
, 22, 2);
9012 int opcode
= extract32(insn
, 11, 5);
9013 int rm
= extract32(insn
, 16, 5);
9014 int rn
= extract32(insn
, 5, 5);
9015 int rd
= extract32(insn
, 0, 5);
9019 case 0x13: /* MUL, PMUL */
9020 if (u
&& size
!= 0) {
9021 unallocated_encoding(s
);
9025 case 0x0: /* SHADD, UHADD */
9026 case 0x2: /* SRHADD, URHADD */
9027 case 0x4: /* SHSUB, UHSUB */
9028 case 0xc: /* SMAX, UMAX */
9029 case 0xd: /* SMIN, UMIN */
9030 case 0xe: /* SABD, UABD */
9031 case 0xf: /* SABA, UABA */
9032 case 0x12: /* MLA, MLS */
9034 unallocated_encoding(s
);
9038 case 0x16: /* SQDMULH, SQRDMULH */
9039 if (size
== 0 || size
== 3) {
9040 unallocated_encoding(s
);
9045 if (size
== 3 && !is_q
) {
9046 unallocated_encoding(s
);
9052 if (!fp_access_check(s
)) {
9058 for (pass
= 0; pass
< 2; pass
++) {
9059 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9060 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9061 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9063 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9064 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9066 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9068 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9070 tcg_temp_free_i64(tcg_res
);
9071 tcg_temp_free_i64(tcg_op1
);
9072 tcg_temp_free_i64(tcg_op2
);
9075 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9076 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9077 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9078 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9079 NeonGenTwoOpFn
*genfn
= NULL
;
9080 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9082 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9083 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9086 case 0x0: /* SHADD, UHADD */
9088 static NeonGenTwoOpFn
* const fns
[3][2] = {
9089 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9090 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9091 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9093 genfn
= fns
[size
][u
];
9096 case 0x1: /* SQADD, UQADD */
9098 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9099 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9100 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9101 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9103 genenvfn
= fns
[size
][u
];
9106 case 0x2: /* SRHADD, URHADD */
9108 static NeonGenTwoOpFn
* const fns
[3][2] = {
9109 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9110 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9111 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9113 genfn
= fns
[size
][u
];
9116 case 0x4: /* SHSUB, UHSUB */
9118 static NeonGenTwoOpFn
* const fns
[3][2] = {
9119 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9120 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9121 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9123 genfn
= fns
[size
][u
];
9126 case 0x5: /* SQSUB, UQSUB */
9128 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9129 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9130 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9131 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9133 genenvfn
= fns
[size
][u
];
9136 case 0x6: /* CMGT, CMHI */
9138 static NeonGenTwoOpFn
* const fns
[3][2] = {
9139 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9140 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9141 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9143 genfn
= fns
[size
][u
];
9146 case 0x7: /* CMGE, CMHS */
9148 static NeonGenTwoOpFn
* const fns
[3][2] = {
9149 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9150 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9151 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9153 genfn
= fns
[size
][u
];
9156 case 0x8: /* SSHL, USHL */
9158 static NeonGenTwoOpFn
* const fns
[3][2] = {
9159 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9160 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9161 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9163 genfn
= fns
[size
][u
];
9166 case 0x9: /* SQSHL, UQSHL */
9168 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9169 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9170 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9171 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9173 genenvfn
= fns
[size
][u
];
9176 case 0xa: /* SRSHL, URSHL */
9178 static NeonGenTwoOpFn
* const fns
[3][2] = {
9179 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9180 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9181 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9183 genfn
= fns
[size
][u
];
9186 case 0xb: /* SQRSHL, UQRSHL */
9188 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9189 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9190 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9191 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9193 genenvfn
= fns
[size
][u
];
9196 case 0xc: /* SMAX, UMAX */
9198 static NeonGenTwoOpFn
* const fns
[3][2] = {
9199 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9200 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9201 { gen_max_s32
, gen_max_u32
},
9203 genfn
= fns
[size
][u
];
9207 case 0xd: /* SMIN, UMIN */
9209 static NeonGenTwoOpFn
* const fns
[3][2] = {
9210 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9211 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9212 { gen_min_s32
, gen_min_u32
},
9214 genfn
= fns
[size
][u
];
9217 case 0xe: /* SABD, UABD */
9218 case 0xf: /* SABA, UABA */
9220 static NeonGenTwoOpFn
* const fns
[3][2] = {
9221 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9222 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9223 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9225 genfn
= fns
[size
][u
];
9228 case 0x10: /* ADD, SUB */
9230 static NeonGenTwoOpFn
* const fns
[3][2] = {
9231 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9232 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9233 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9235 genfn
= fns
[size
][u
];
9238 case 0x11: /* CMTST, CMEQ */
9240 static NeonGenTwoOpFn
* const fns
[3][2] = {
9241 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9242 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9243 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9245 genfn
= fns
[size
][u
];
9248 case 0x13: /* MUL, PMUL */
9252 genfn
= gen_helper_neon_mul_p8
;
9255 /* fall through : MUL */
9256 case 0x12: /* MLA, MLS */
9258 static NeonGenTwoOpFn
* const fns
[3] = {
9259 gen_helper_neon_mul_u8
,
9260 gen_helper_neon_mul_u16
,
9266 case 0x16: /* SQDMULH, SQRDMULH */
9268 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9269 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9270 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9272 assert(size
== 1 || size
== 2);
9273 genenvfn
= fns
[size
- 1][u
];
9277 g_assert_not_reached();
9281 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9283 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9286 if (opcode
== 0xf || opcode
== 0x12) {
9287 /* SABA, UABA, MLA, MLS: accumulating ops */
9288 static NeonGenTwoOpFn
* const fns
[3][2] = {
9289 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9290 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9291 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9293 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9295 genfn
= fns
[size
][is_sub
];
9296 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9297 genfn(tcg_res
, tcg_op1
, tcg_res
);
9300 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9302 tcg_temp_free_i32(tcg_res
);
9303 tcg_temp_free_i32(tcg_op1
);
9304 tcg_temp_free_i32(tcg_op2
);
9309 clear_vec_high(s
, rd
);
9313 /* C3.6.16 AdvSIMD three same
9314 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9315 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9316 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9317 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9319 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9321 int opcode
= extract32(insn
, 11, 5);
9324 case 0x3: /* logic ops */
9325 disas_simd_3same_logic(s
, insn
);
9327 case 0x17: /* ADDP */
9328 case 0x14: /* SMAXP, UMAXP */
9329 case 0x15: /* SMINP, UMINP */
9331 /* Pairwise operations */
9332 int is_q
= extract32(insn
, 30, 1);
9333 int u
= extract32(insn
, 29, 1);
9334 int size
= extract32(insn
, 22, 2);
9335 int rm
= extract32(insn
, 16, 5);
9336 int rn
= extract32(insn
, 5, 5);
9337 int rd
= extract32(insn
, 0, 5);
9338 if (opcode
== 0x17) {
9339 if (u
|| (size
== 3 && !is_q
)) {
9340 unallocated_encoding(s
);
9345 unallocated_encoding(s
);
9349 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9353 /* floating point ops, sz[1] and U are part of opcode */
9354 disas_simd_3same_float(s
, insn
);
9357 disas_simd_3same_int(s
, insn
);
9362 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9363 int size
, int rn
, int rd
)
9365 /* Handle 2-reg-misc ops which are widening (so each size element
9366 * in the source becomes a 2*size element in the destination.
9367 * The only instruction like this is FCVTL.
9372 /* 32 -> 64 bit fp conversion */
9373 TCGv_i64 tcg_res
[2];
9374 int srcelt
= is_q
? 2 : 0;
9376 for (pass
= 0; pass
< 2; pass
++) {
9377 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9378 tcg_res
[pass
] = tcg_temp_new_i64();
9380 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9381 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9382 tcg_temp_free_i32(tcg_op
);
9384 for (pass
= 0; pass
< 2; pass
++) {
9385 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9386 tcg_temp_free_i64(tcg_res
[pass
]);
9389 /* 16 -> 32 bit fp conversion */
9390 int srcelt
= is_q
? 4 : 0;
9391 TCGv_i32 tcg_res
[4];
9393 for (pass
= 0; pass
< 4; pass
++) {
9394 tcg_res
[pass
] = tcg_temp_new_i32();
9396 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9397 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9400 for (pass
= 0; pass
< 4; pass
++) {
9401 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9402 tcg_temp_free_i32(tcg_res
[pass
]);
9407 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9408 bool is_q
, int size
, int rn
, int rd
)
9410 int op
= (opcode
<< 1) | u
;
9411 int opsz
= op
+ size
;
9412 int grp_size
= 3 - opsz
;
9413 int dsize
= is_q
? 128 : 64;
9417 unallocated_encoding(s
);
9421 if (!fp_access_check(s
)) {
9426 /* Special case bytes, use bswap op on each group of elements */
9427 int groups
= dsize
/ (8 << grp_size
);
9429 for (i
= 0; i
< groups
; i
++) {
9430 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9432 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9435 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9438 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9441 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9444 g_assert_not_reached();
9446 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9447 tcg_temp_free_i64(tcg_tmp
);
9450 clear_vec_high(s
, rd
);
9453 int revmask
= (1 << grp_size
) - 1;
9454 int esize
= 8 << size
;
9455 int elements
= dsize
/ esize
;
9456 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9457 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9458 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9460 for (i
= 0; i
< elements
; i
++) {
9461 int e_rev
= (i
& 0xf) ^ revmask
;
9462 int off
= e_rev
* esize
;
9463 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9465 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9466 tcg_rn
, off
- 64, esize
);
9468 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9471 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9472 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9474 tcg_temp_free_i64(tcg_rd_hi
);
9475 tcg_temp_free_i64(tcg_rd
);
9476 tcg_temp_free_i64(tcg_rn
);
9480 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9481 bool is_q
, int size
, int rn
, int rd
)
9483 /* Implement the pairwise operations from 2-misc:
9484 * SADDLP, UADDLP, SADALP, UADALP.
9485 * These all add pairs of elements in the input to produce a
9486 * double-width result element in the output (possibly accumulating).
9488 bool accum
= (opcode
== 0x6);
9489 int maxpass
= is_q
? 2 : 1;
9491 TCGv_i64 tcg_res
[2];
9494 /* 32 + 32 -> 64 op */
9495 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9497 for (pass
= 0; pass
< maxpass
; pass
++) {
9498 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9499 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9501 tcg_res
[pass
] = tcg_temp_new_i64();
9503 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9504 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9505 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9507 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9508 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9511 tcg_temp_free_i64(tcg_op1
);
9512 tcg_temp_free_i64(tcg_op2
);
9515 for (pass
= 0; pass
< maxpass
; pass
++) {
9516 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9517 NeonGenOneOpFn
*genfn
;
9518 static NeonGenOneOpFn
* const fns
[2][2] = {
9519 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9520 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9523 genfn
= fns
[size
][u
];
9525 tcg_res
[pass
] = tcg_temp_new_i64();
9527 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9528 genfn(tcg_res
[pass
], tcg_op
);
9531 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9533 gen_helper_neon_addl_u16(tcg_res
[pass
],
9534 tcg_res
[pass
], tcg_op
);
9536 gen_helper_neon_addl_u32(tcg_res
[pass
],
9537 tcg_res
[pass
], tcg_op
);
9540 tcg_temp_free_i64(tcg_op
);
9544 tcg_res
[1] = tcg_const_i64(0);
9546 for (pass
= 0; pass
< 2; pass
++) {
9547 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9548 tcg_temp_free_i64(tcg_res
[pass
]);
9552 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9554 /* Implement SHLL and SHLL2 */
9556 int part
= is_q
? 2 : 0;
9557 TCGv_i64 tcg_res
[2];
9559 for (pass
= 0; pass
< 2; pass
++) {
9560 static NeonGenWidenFn
* const widenfns
[3] = {
9561 gen_helper_neon_widen_u8
,
9562 gen_helper_neon_widen_u16
,
9563 tcg_gen_extu_i32_i64
,
9565 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9566 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9568 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9569 tcg_res
[pass
] = tcg_temp_new_i64();
9570 widenfn(tcg_res
[pass
], tcg_op
);
9571 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9573 tcg_temp_free_i32(tcg_op
);
9576 for (pass
= 0; pass
< 2; pass
++) {
9577 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9578 tcg_temp_free_i64(tcg_res
[pass
]);
9582 /* C3.6.17 AdvSIMD two reg misc
9583 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9584 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9585 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9586 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9588 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9590 int size
= extract32(insn
, 22, 2);
9591 int opcode
= extract32(insn
, 12, 5);
9592 bool u
= extract32(insn
, 29, 1);
9593 bool is_q
= extract32(insn
, 30, 1);
9594 int rn
= extract32(insn
, 5, 5);
9595 int rd
= extract32(insn
, 0, 5);
9596 bool need_fpstatus
= false;
9597 bool need_rmode
= false;
9600 TCGv_ptr tcg_fpstatus
;
9603 case 0x0: /* REV64, REV32 */
9604 case 0x1: /* REV16 */
9605 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9607 case 0x5: /* CNT, NOT, RBIT */
9608 if (u
&& size
== 0) {
9609 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9612 } else if (u
&& size
== 1) {
9615 } else if (!u
&& size
== 0) {
9619 unallocated_encoding(s
);
9621 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9622 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9624 unallocated_encoding(s
);
9627 if (!fp_access_check(s
)) {
9631 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9633 case 0x4: /* CLS, CLZ */
9635 unallocated_encoding(s
);
9639 case 0x2: /* SADDLP, UADDLP */
9640 case 0x6: /* SADALP, UADALP */
9642 unallocated_encoding(s
);
9645 if (!fp_access_check(s
)) {
9648 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9650 case 0x13: /* SHLL, SHLL2 */
9651 if (u
== 0 || size
== 3) {
9652 unallocated_encoding(s
);
9655 if (!fp_access_check(s
)) {
9658 handle_shll(s
, is_q
, size
, rn
, rd
);
9660 case 0xa: /* CMLT */
9662 unallocated_encoding(s
);
9666 case 0x8: /* CMGT, CMGE */
9667 case 0x9: /* CMEQ, CMLE */
9668 case 0xb: /* ABS, NEG */
9669 if (size
== 3 && !is_q
) {
9670 unallocated_encoding(s
);
9674 case 0x3: /* SUQADD, USQADD */
9675 if (size
== 3 && !is_q
) {
9676 unallocated_encoding(s
);
9679 if (!fp_access_check(s
)) {
9682 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
9684 case 0x7: /* SQABS, SQNEG */
9685 if (size
== 3 && !is_q
) {
9686 unallocated_encoding(s
);
9694 /* Floating point: U, size[1] and opcode indicate operation;
9695 * size[0] indicates single or double precision.
9697 int is_double
= extract32(size
, 0, 1);
9698 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9699 size
= is_double
? 3 : 2;
9701 case 0x2f: /* FABS */
9702 case 0x6f: /* FNEG */
9703 if (size
== 3 && !is_q
) {
9704 unallocated_encoding(s
);
9708 case 0x1d: /* SCVTF */
9709 case 0x5d: /* UCVTF */
9711 bool is_signed
= (opcode
== 0x1d) ? true : false;
9712 int elements
= is_double
? 2 : is_q
? 4 : 2;
9713 if (is_double
&& !is_q
) {
9714 unallocated_encoding(s
);
9717 if (!fp_access_check(s
)) {
9720 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
9723 case 0x2c: /* FCMGT (zero) */
9724 case 0x2d: /* FCMEQ (zero) */
9725 case 0x2e: /* FCMLT (zero) */
9726 case 0x6c: /* FCMGE (zero) */
9727 case 0x6d: /* FCMLE (zero) */
9728 if (size
== 3 && !is_q
) {
9729 unallocated_encoding(s
);
9732 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9734 case 0x7f: /* FSQRT */
9735 if (size
== 3 && !is_q
) {
9736 unallocated_encoding(s
);
9740 case 0x1a: /* FCVTNS */
9741 case 0x1b: /* FCVTMS */
9742 case 0x3a: /* FCVTPS */
9743 case 0x3b: /* FCVTZS */
9744 case 0x5a: /* FCVTNU */
9745 case 0x5b: /* FCVTMU */
9746 case 0x7a: /* FCVTPU */
9747 case 0x7b: /* FCVTZU */
9748 need_fpstatus
= true;
9750 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9751 if (size
== 3 && !is_q
) {
9752 unallocated_encoding(s
);
9756 case 0x5c: /* FCVTAU */
9757 case 0x1c: /* FCVTAS */
9758 need_fpstatus
= true;
9760 rmode
= FPROUNDING_TIEAWAY
;
9761 if (size
== 3 && !is_q
) {
9762 unallocated_encoding(s
);
9766 case 0x3c: /* URECPE */
9768 unallocated_encoding(s
);
9772 case 0x3d: /* FRECPE */
9773 case 0x7d: /* FRSQRTE */
9774 if (size
== 3 && !is_q
) {
9775 unallocated_encoding(s
);
9778 if (!fp_access_check(s
)) {
9781 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9783 case 0x56: /* FCVTXN, FCVTXN2 */
9785 unallocated_encoding(s
);
9789 case 0x16: /* FCVTN, FCVTN2 */
9790 /* handle_2misc_narrow does a 2*size -> size operation, but these
9791 * instructions encode the source size rather than dest size.
9793 if (!fp_access_check(s
)) {
9796 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9798 case 0x17: /* FCVTL, FCVTL2 */
9799 if (!fp_access_check(s
)) {
9802 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9804 case 0x18: /* FRINTN */
9805 case 0x19: /* FRINTM */
9806 case 0x38: /* FRINTP */
9807 case 0x39: /* FRINTZ */
9809 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9811 case 0x59: /* FRINTX */
9812 case 0x79: /* FRINTI */
9813 need_fpstatus
= true;
9814 if (size
== 3 && !is_q
) {
9815 unallocated_encoding(s
);
9819 case 0x58: /* FRINTA */
9821 rmode
= FPROUNDING_TIEAWAY
;
9822 need_fpstatus
= true;
9823 if (size
== 3 && !is_q
) {
9824 unallocated_encoding(s
);
9828 case 0x7c: /* URSQRTE */
9830 unallocated_encoding(s
);
9833 need_fpstatus
= true;
9836 unallocated_encoding(s
);
9842 unallocated_encoding(s
);
9846 if (!fp_access_check(s
)) {
9850 if (need_fpstatus
) {
9851 tcg_fpstatus
= get_fpstatus_ptr();
9853 TCGV_UNUSED_PTR(tcg_fpstatus
);
9856 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9857 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
9859 TCGV_UNUSED_I32(tcg_rmode
);
9863 /* All 64-bit element operations can be shared with scalar 2misc */
9866 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9867 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9868 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9870 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9872 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
9873 tcg_rmode
, tcg_fpstatus
);
9875 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9877 tcg_temp_free_i64(tcg_res
);
9878 tcg_temp_free_i64(tcg_op
);
9883 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9884 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9885 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9888 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9891 /* Special cases for 32 bit elements */
9893 case 0xa: /* CMLT */
9894 /* 32 bit integer comparison against zero, result is
9895 * test ? (2^32 - 1) : 0. We implement via setcond(test)
9900 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
9901 tcg_gen_neg_i32(tcg_res
, tcg_res
);
9903 case 0x8: /* CMGT, CMGE */
9904 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9906 case 0x9: /* CMEQ, CMLE */
9907 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9911 gen_helper_clz32(tcg_res
, tcg_op
);
9913 gen_helper_cls32(tcg_res
, tcg_op
);
9916 case 0x7: /* SQABS, SQNEG */
9918 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
9920 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
9923 case 0xb: /* ABS, NEG */
9925 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9927 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9928 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9929 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
9930 tcg_zero
, tcg_op
, tcg_res
);
9931 tcg_temp_free_i32(tcg_zero
);
9934 case 0x2f: /* FABS */
9935 gen_helper_vfp_abss(tcg_res
, tcg_op
);
9937 case 0x6f: /* FNEG */
9938 gen_helper_vfp_negs(tcg_res
, tcg_op
);
9940 case 0x7f: /* FSQRT */
9941 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
9943 case 0x1a: /* FCVTNS */
9944 case 0x1b: /* FCVTMS */
9945 case 0x1c: /* FCVTAS */
9946 case 0x3a: /* FCVTPS */
9947 case 0x3b: /* FCVTZS */
9949 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9950 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
9951 tcg_shift
, tcg_fpstatus
);
9952 tcg_temp_free_i32(tcg_shift
);
9955 case 0x5a: /* FCVTNU */
9956 case 0x5b: /* FCVTMU */
9957 case 0x5c: /* FCVTAU */
9958 case 0x7a: /* FCVTPU */
9959 case 0x7b: /* FCVTZU */
9961 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9962 gen_helper_vfp_touls(tcg_res
, tcg_op
,
9963 tcg_shift
, tcg_fpstatus
);
9964 tcg_temp_free_i32(tcg_shift
);
9967 case 0x18: /* FRINTN */
9968 case 0x19: /* FRINTM */
9969 case 0x38: /* FRINTP */
9970 case 0x39: /* FRINTZ */
9971 case 0x58: /* FRINTA */
9972 case 0x79: /* FRINTI */
9973 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
9975 case 0x59: /* FRINTX */
9976 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
9978 case 0x7c: /* URSQRTE */
9979 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
9982 g_assert_not_reached();
9985 /* Use helpers for 8 and 16 bit elements */
9987 case 0x5: /* CNT, RBIT */
9988 /* For these two insns size is part of the opcode specifier
9989 * (handled earlier); they always operate on byte elements.
9992 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
9994 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
9997 case 0x7: /* SQABS, SQNEG */
9999 NeonGenOneOpEnvFn
*genfn
;
10000 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10001 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10002 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10004 genfn
= fns
[size
][u
];
10005 genfn(tcg_res
, cpu_env
, tcg_op
);
10008 case 0x8: /* CMGT, CMGE */
10009 case 0x9: /* CMEQ, CMLE */
10010 case 0xa: /* CMLT */
10012 static NeonGenTwoOpFn
* const fns
[3][2] = {
10013 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10014 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10015 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10017 NeonGenTwoOpFn
*genfn
;
10020 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10022 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10023 comp
= (opcode
- 0x8) * 2 + u
;
10024 /* ...but LE, LT are implemented as reverse GE, GT */
10025 reverse
= (comp
> 2);
10029 genfn
= fns
[comp
][size
];
10031 genfn(tcg_res
, tcg_zero
, tcg_op
);
10033 genfn(tcg_res
, tcg_op
, tcg_zero
);
10035 tcg_temp_free_i32(tcg_zero
);
10038 case 0xb: /* ABS, NEG */
10040 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10042 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10044 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10046 tcg_temp_free_i32(tcg_zero
);
10049 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10051 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10055 case 0x4: /* CLS, CLZ */
10058 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10060 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10064 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10066 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10071 g_assert_not_reached();
10075 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10077 tcg_temp_free_i32(tcg_res
);
10078 tcg_temp_free_i32(tcg_op
);
10082 clear_vec_high(s
, rd
);
10086 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10087 tcg_temp_free_i32(tcg_rmode
);
10089 if (need_fpstatus
) {
10090 tcg_temp_free_ptr(tcg_fpstatus
);
10094 /* C3.6.13 AdvSIMD scalar x indexed element
10095 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10096 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10097 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10098 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10099 * C3.6.18 AdvSIMD vector x indexed element
10100 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10101 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10102 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10103 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10105 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10107 /* This encoding has two kinds of instruction:
10108 * normal, where we perform elt x idxelt => elt for each
10109 * element in the vector
10110 * long, where we perform elt x idxelt and generate a result of
10111 * double the width of the input element
10112 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10114 bool is_scalar
= extract32(insn
, 28, 1);
10115 bool is_q
= extract32(insn
, 30, 1);
10116 bool u
= extract32(insn
, 29, 1);
10117 int size
= extract32(insn
, 22, 2);
10118 int l
= extract32(insn
, 21, 1);
10119 int m
= extract32(insn
, 20, 1);
10120 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10121 int rm
= extract32(insn
, 16, 4);
10122 int opcode
= extract32(insn
, 12, 4);
10123 int h
= extract32(insn
, 11, 1);
10124 int rn
= extract32(insn
, 5, 5);
10125 int rd
= extract32(insn
, 0, 5);
10126 bool is_long
= false;
10127 bool is_fp
= false;
10132 case 0x0: /* MLA */
10133 case 0x4: /* MLS */
10134 if (!u
|| is_scalar
) {
10135 unallocated_encoding(s
);
10139 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10140 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10141 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10143 unallocated_encoding(s
);
10148 case 0x3: /* SQDMLAL, SQDMLAL2 */
10149 case 0x7: /* SQDMLSL, SQDMLSL2 */
10150 case 0xb: /* SQDMULL, SQDMULL2 */
10153 case 0xc: /* SQDMULH */
10154 case 0xd: /* SQRDMULH */
10156 unallocated_encoding(s
);
10160 case 0x8: /* MUL */
10161 if (u
|| is_scalar
) {
10162 unallocated_encoding(s
);
10166 case 0x1: /* FMLA */
10167 case 0x5: /* FMLS */
10169 unallocated_encoding(s
);
10173 case 0x9: /* FMUL, FMULX */
10174 if (!extract32(size
, 1, 1)) {
10175 unallocated_encoding(s
);
10181 unallocated_encoding(s
);
10186 /* low bit of size indicates single/double */
10187 size
= extract32(size
, 0, 1) ? 3 : 2;
10189 index
= h
<< 1 | l
;
10192 unallocated_encoding(s
);
10201 index
= h
<< 2 | l
<< 1 | m
;
10204 index
= h
<< 1 | l
;
10208 unallocated_encoding(s
);
10213 if (!fp_access_check(s
)) {
10218 fpst
= get_fpstatus_ptr();
10220 TCGV_UNUSED_PTR(fpst
);
10224 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10227 assert(is_fp
&& is_q
&& !is_long
);
10229 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10231 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10232 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10233 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10235 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10238 case 0x5: /* FMLS */
10239 /* As usual for ARM, separate negation for fused multiply-add */
10240 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10242 case 0x1: /* FMLA */
10243 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10244 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10246 case 0x9: /* FMUL, FMULX */
10248 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10250 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10254 g_assert_not_reached();
10257 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10258 tcg_temp_free_i64(tcg_op
);
10259 tcg_temp_free_i64(tcg_res
);
10263 clear_vec_high(s
, rd
);
10266 tcg_temp_free_i64(tcg_idx
);
10267 } else if (!is_long
) {
10268 /* 32 bit floating point, or 16 or 32 bit integer.
10269 * For the 16 bit scalar case we use the usual Neon helpers and
10270 * rely on the fact that 0 op 0 == 0 with no side effects.
10272 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10273 int pass
, maxpasses
;
10278 maxpasses
= is_q
? 4 : 2;
10281 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10283 if (size
== 1 && !is_scalar
) {
10284 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10285 * the index into both halves of the 32 bit tcg_idx and then use
10286 * the usual Neon helpers.
10288 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10291 for (pass
= 0; pass
< maxpasses
; pass
++) {
10292 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10293 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10295 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10298 case 0x0: /* MLA */
10299 case 0x4: /* MLS */
10300 case 0x8: /* MUL */
10302 static NeonGenTwoOpFn
* const fns
[2][2] = {
10303 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10304 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10306 NeonGenTwoOpFn
*genfn
;
10307 bool is_sub
= opcode
== 0x4;
10310 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10312 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10314 if (opcode
== 0x8) {
10317 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10318 genfn
= fns
[size
- 1][is_sub
];
10319 genfn(tcg_res
, tcg_op
, tcg_res
);
10322 case 0x5: /* FMLS */
10323 /* As usual for ARM, separate negation for fused multiply-add */
10324 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10326 case 0x1: /* FMLA */
10327 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10328 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10330 case 0x9: /* FMUL, FMULX */
10332 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10334 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10337 case 0xc: /* SQDMULH */
10339 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10342 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10346 case 0xd: /* SQRDMULH */
10348 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10351 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10356 g_assert_not_reached();
10360 write_fp_sreg(s
, rd
, tcg_res
);
10362 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10365 tcg_temp_free_i32(tcg_op
);
10366 tcg_temp_free_i32(tcg_res
);
10369 tcg_temp_free_i32(tcg_idx
);
10372 clear_vec_high(s
, rd
);
10375 /* long ops: 16x16->32 or 32x32->64 */
10376 TCGv_i64 tcg_res
[2];
10378 bool satop
= extract32(opcode
, 0, 1);
10379 TCGMemOp memop
= MO_32
;
10386 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10388 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10390 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10391 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10392 TCGv_i64 tcg_passres
;
10398 passelt
= pass
+ (is_q
* 2);
10401 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10403 tcg_res
[pass
] = tcg_temp_new_i64();
10405 if (opcode
== 0xa || opcode
== 0xb) {
10406 /* Non-accumulating ops */
10407 tcg_passres
= tcg_res
[pass
];
10409 tcg_passres
= tcg_temp_new_i64();
10412 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10413 tcg_temp_free_i64(tcg_op
);
10416 /* saturating, doubling */
10417 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10418 tcg_passres
, tcg_passres
);
10421 if (opcode
== 0xa || opcode
== 0xb) {
10425 /* Accumulating op: handle accumulate step */
10426 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10429 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10430 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10432 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10433 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10435 case 0x7: /* SQDMLSL, SQDMLSL2 */
10436 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10438 case 0x3: /* SQDMLAL, SQDMLAL2 */
10439 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10444 g_assert_not_reached();
10446 tcg_temp_free_i64(tcg_passres
);
10448 tcg_temp_free_i64(tcg_idx
);
10451 clear_vec_high(s
, rd
);
10454 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10457 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10460 /* The simplest way to handle the 16x16 indexed ops is to
10461 * duplicate the index into both halves of the 32 bit tcg_idx
10462 * and then use the usual Neon helpers.
10464 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10467 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10468 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10469 TCGv_i64 tcg_passres
;
10472 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10474 read_vec_element_i32(s
, tcg_op
, rn
,
10475 pass
+ (is_q
* 2), MO_32
);
10478 tcg_res
[pass
] = tcg_temp_new_i64();
10480 if (opcode
== 0xa || opcode
== 0xb) {
10481 /* Non-accumulating ops */
10482 tcg_passres
= tcg_res
[pass
];
10484 tcg_passres
= tcg_temp_new_i64();
10487 if (memop
& MO_SIGN
) {
10488 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10490 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10493 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10494 tcg_passres
, tcg_passres
);
10496 tcg_temp_free_i32(tcg_op
);
10498 if (opcode
== 0xa || opcode
== 0xb) {
10502 /* Accumulating op: handle accumulate step */
10503 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10506 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10507 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10510 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10511 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10514 case 0x7: /* SQDMLSL, SQDMLSL2 */
10515 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10517 case 0x3: /* SQDMLAL, SQDMLAL2 */
10518 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10523 g_assert_not_reached();
10525 tcg_temp_free_i64(tcg_passres
);
10527 tcg_temp_free_i32(tcg_idx
);
10530 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10535 tcg_res
[1] = tcg_const_i64(0);
10538 for (pass
= 0; pass
< 2; pass
++) {
10539 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10540 tcg_temp_free_i64(tcg_res
[pass
]);
10544 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10545 tcg_temp_free_ptr(fpst
);
10549 /* C3.6.19 Crypto AES
10550 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10551 * +-----------------+------+-----------+--------+-----+------+------+
10552 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10553 * +-----------------+------+-----------+--------+-----+------+------+
10555 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10557 int size
= extract32(insn
, 22, 2);
10558 int opcode
= extract32(insn
, 12, 5);
10559 int rn
= extract32(insn
, 5, 5);
10560 int rd
= extract32(insn
, 0, 5);
10562 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10563 CryptoThreeOpEnvFn
*genfn
;
10565 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10567 unallocated_encoding(s
);
10572 case 0x4: /* AESE */
10574 genfn
= gen_helper_crypto_aese
;
10576 case 0x6: /* AESMC */
10578 genfn
= gen_helper_crypto_aesmc
;
10580 case 0x5: /* AESD */
10582 genfn
= gen_helper_crypto_aese
;
10584 case 0x7: /* AESIMC */
10586 genfn
= gen_helper_crypto_aesmc
;
10589 unallocated_encoding(s
);
10593 /* Note that we convert the Vx register indexes into the
10594 * index within the vfp.regs[] array, so we can share the
10595 * helper with the AArch32 instructions.
10597 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10598 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10599 tcg_decrypt
= tcg_const_i32(decrypt
);
10601 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10603 tcg_temp_free_i32(tcg_rd_regno
);
10604 tcg_temp_free_i32(tcg_rn_regno
);
10605 tcg_temp_free_i32(tcg_decrypt
);
10608 /* C3.6.20 Crypto three-reg SHA
10609 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10610 * +-----------------+------+---+------+---+--------+-----+------+------+
10611 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10612 * +-----------------+------+---+------+---+--------+-----+------+------+
10614 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10616 int size
= extract32(insn
, 22, 2);
10617 int opcode
= extract32(insn
, 12, 3);
10618 int rm
= extract32(insn
, 16, 5);
10619 int rn
= extract32(insn
, 5, 5);
10620 int rd
= extract32(insn
, 0, 5);
10621 CryptoThreeOpEnvFn
*genfn
;
10622 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10623 int feature
= ARM_FEATURE_V8_SHA256
;
10626 unallocated_encoding(s
);
10631 case 0: /* SHA1C */
10632 case 1: /* SHA1P */
10633 case 2: /* SHA1M */
10634 case 3: /* SHA1SU0 */
10636 feature
= ARM_FEATURE_V8_SHA1
;
10638 case 4: /* SHA256H */
10639 genfn
= gen_helper_crypto_sha256h
;
10641 case 5: /* SHA256H2 */
10642 genfn
= gen_helper_crypto_sha256h2
;
10644 case 6: /* SHA256SU1 */
10645 genfn
= gen_helper_crypto_sha256su1
;
10648 unallocated_encoding(s
);
10652 if (!arm_dc_feature(s
, feature
)) {
10653 unallocated_encoding(s
);
10657 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10658 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10659 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
10662 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
10664 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
10666 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
10667 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
10668 tcg_temp_free_i32(tcg_opcode
);
10671 tcg_temp_free_i32(tcg_rd_regno
);
10672 tcg_temp_free_i32(tcg_rn_regno
);
10673 tcg_temp_free_i32(tcg_rm_regno
);
10676 /* C3.6.21 Crypto two-reg SHA
10677 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10678 * +-----------------+------+-----------+--------+-----+------+------+
10679 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10680 * +-----------------+------+-----------+--------+-----+------+------+
10682 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
10684 int size
= extract32(insn
, 22, 2);
10685 int opcode
= extract32(insn
, 12, 5);
10686 int rn
= extract32(insn
, 5, 5);
10687 int rd
= extract32(insn
, 0, 5);
10688 CryptoTwoOpEnvFn
*genfn
;
10690 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
10693 unallocated_encoding(s
);
10698 case 0: /* SHA1H */
10699 feature
= ARM_FEATURE_V8_SHA1
;
10700 genfn
= gen_helper_crypto_sha1h
;
10702 case 1: /* SHA1SU1 */
10703 feature
= ARM_FEATURE_V8_SHA1
;
10704 genfn
= gen_helper_crypto_sha1su1
;
10706 case 2: /* SHA256SU0 */
10707 feature
= ARM_FEATURE_V8_SHA256
;
10708 genfn
= gen_helper_crypto_sha256su0
;
10711 unallocated_encoding(s
);
10715 if (!arm_dc_feature(s
, feature
)) {
10716 unallocated_encoding(s
);
10720 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10721 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10723 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
10725 tcg_temp_free_i32(tcg_rd_regno
);
10726 tcg_temp_free_i32(tcg_rn_regno
);
10729 /* C3.6 Data processing - SIMD, inc Crypto
10731 * As the decode gets a little complex we are using a table based
10732 * approach for this part of the decode.
10734 static const AArch64DecodeTable data_proc_simd
[] = {
10735 /* pattern , mask , fn */
10736 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
10737 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
10738 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
10739 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
10740 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
10741 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
10742 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10743 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
10744 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
10745 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
10746 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
10747 { 0x2e000000, 0xbf208400, disas_simd_ext
},
10748 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
10749 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
10750 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
10751 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
10752 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
10753 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
10754 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
10755 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
10756 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
10757 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
10758 { 0x00000000, 0x00000000, NULL
}
10761 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
10763 /* Note that this is called with all non-FP cases from
10764 * table C3-6 so it must UNDEF for entries not specifically
10765 * allocated to instructions in that table.
10767 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
10771 unallocated_encoding(s
);
10775 /* C3.6 Data processing - SIMD and floating point */
10776 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
10778 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
10779 disas_data_proc_fp(s
, insn
);
10781 /* SIMD, including crypto */
10782 disas_data_proc_simd(s
, insn
);
10786 /* C3.1 A64 instruction index by encoding */
10787 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
10791 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
10795 s
->fp_access_checked
= false;
10797 switch (extract32(insn
, 25, 4)) {
10798 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10799 unallocated_encoding(s
);
10801 case 0x8: case 0x9: /* Data processing - immediate */
10802 disas_data_proc_imm(s
, insn
);
10804 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10805 disas_b_exc_sys(s
, insn
);
10810 case 0xe: /* Loads and stores */
10811 disas_ldst(s
, insn
);
10814 case 0xd: /* Data processing - register */
10815 disas_data_proc_reg(s
, insn
);
10818 case 0xf: /* Data processing - SIMD and floating point */
10819 disas_data_proc_simd_fp(s
, insn
);
10822 assert(FALSE
); /* all 15 cases should be handled above */
10826 /* if we allocated any temporaries, free them here */
10830 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
10831 TranslationBlock
*tb
,
10834 CPUState
*cs
= CPU(cpu
);
10835 CPUARMState
*env
= &cpu
->env
;
10836 DisasContext dc1
, *dc
= &dc1
;
10838 uint16_t *gen_opc_end
;
10840 target_ulong pc_start
;
10841 target_ulong next_page_start
;
10849 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
10851 dc
->is_jmp
= DISAS_NEXT
;
10853 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
10858 dc
->bswap_code
= 0;
10859 dc
->condexec_mask
= 0;
10860 dc
->condexec_cond
= 0;
10861 #if !defined(CONFIG_USER_ONLY)
10862 dc
->user
= (ARM_TBFLAG_AA64_EL(tb
->flags
) == 0);
10864 dc
->cpacr_fpen
= ARM_TBFLAG_AA64_FPEN(tb
->flags
);
10866 dc
->vec_stride
= 0;
10867 dc
->cp_regs
= cpu
->cp_regs
;
10868 dc
->current_pl
= arm_current_pl(env
);
10869 dc
->features
= env
->features
;
10871 init_tmp_a64_array(dc
);
10873 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
10876 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
10877 if (max_insns
== 0) {
10878 max_insns
= CF_COUNT_MASK
;
10883 tcg_clear_temp_count();
10886 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
10887 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
10888 if (bp
->pc
== dc
->pc
) {
10889 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
10890 /* Advance PC so that clearing the breakpoint will
10891 invalidate this TB. */
10893 goto done_generating
;
10899 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10903 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10906 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
10907 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
10908 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
10911 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
10915 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
10916 tcg_gen_debug_insn_start(dc
->pc
);
10919 disas_a64_insn(env
, dc
);
10921 if (tcg_check_temp_count()) {
10922 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
10926 /* Translation stops when a conditional branch is encountered.
10927 * Otherwise the subsequent code could get translated several times.
10928 * Also stop translation when a page boundary is reached. This
10929 * ensures prefetch aborts occur at the right place.
10932 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
10933 !cs
->singlestep_enabled
&&
10935 dc
->pc
< next_page_start
&&
10936 num_insns
< max_insns
);
10938 if (tb
->cflags
& CF_LAST_IO
) {
10942 if (unlikely(cs
->singlestep_enabled
) && dc
->is_jmp
!= DISAS_EXC
) {
10943 /* Note that this means single stepping WFI doesn't halt the CPU.
10944 * For conditional branch insns this is harmless unreachable code as
10945 * gen_goto_tb() has already handled emitting the debug exception
10946 * (and thus a tb-jump is not possible when singlestepping).
10948 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
10949 if (dc
->is_jmp
!= DISAS_JUMP
) {
10950 gen_a64_set_pc_im(dc
->pc
);
10952 gen_exception_internal(EXCP_DEBUG
);
10954 switch (dc
->is_jmp
) {
10956 gen_goto_tb(dc
, 1, dc
->pc
);
10960 gen_a64_set_pc_im(dc
->pc
);
10963 /* indicate that the hash table must be used to find the next TB */
10964 tcg_gen_exit_tb(0);
10966 case DISAS_TB_JUMP
:
10971 gen_a64_set_pc_im(dc
->pc
);
10972 gen_helper_wfe(cpu_env
);
10975 /* This is a special case because we don't want to just halt the CPU
10976 * if trying to debug across a WFI.
10978 gen_a64_set_pc_im(dc
->pc
);
10979 gen_helper_wfi(cpu_env
);
10985 gen_tb_end(tb
, num_insns
);
10986 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
10989 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
10990 qemu_log("----------------\n");
10991 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
10992 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
10993 4 | (dc
->bswap_code
<< 1));
10998 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
11001 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
11004 tb
->size
= dc
->pc
- pc_start
;
11005 tb
->icount
= num_insns
;