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MAINTAINERS: add entry for virtio-rng
[qemu/ar7.git] / target-ppc / translate.c
blobd381632c86ada72e64eb1084a986e3f1f9bd691f
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #include "trace-tcg.h"
31
32
33 #define CPU_SINGLE_STEP 0x1
34 #define CPU_BRANCH_STEP 0x2
35 #define GDBSTUB_SINGLE_STEP 0x4
36
37 /* Include definitions for instructions classes and implementations flags */
38 //#define PPC_DEBUG_DISAS
39 //#define DO_PPC_STATISTICS
40
41 #ifdef PPC_DEBUG_DISAS
42 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DISAS(...) do { } while (0)
45 #endif
46 /*****************************************************************************/
47 /* Code translation helpers */
48
49 /* global register indexes */
50 static TCGv_ptr cpu_env;
51 static char cpu_reg_names[10*3 + 22*4 /* GPR */
52 + 10*4 + 22*5 /* SPE GPRh */
53 + 10*4 + 22*5 /* FPR */
54 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 + 10*5 + 22*6 /* VSR */
56 + 8*5 /* CRF */];
57 static TCGv cpu_gpr[32];
58 static TCGv cpu_gprh[32];
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i64 cpu_vsr[32];
62 static TCGv_i32 cpu_crf[8];
63 static TCGv cpu_nip;
64 static TCGv cpu_msr;
65 static TCGv cpu_ctr;
66 static TCGv cpu_lr;
67 #if defined(TARGET_PPC64)
68 static TCGv cpu_cfar;
69 #endif
70 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
71 static TCGv cpu_reserve;
72 static TCGv cpu_fpscr;
73 static TCGv_i32 cpu_access_type;
74
75 #include "exec/gen-icount.h"
76
77 void ppc_translate_init(void)
78 {
79 int i;
80 char* p;
81 size_t cpu_reg_names_size;
82 static int done_init = 0;
83
84 if (done_init)
85 return;
86
87 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
88
89 p = cpu_reg_names;
90 cpu_reg_names_size = sizeof(cpu_reg_names);
91
92 for (i = 0; i < 8; i++) {
93 snprintf(p, cpu_reg_names_size, "crf%d", i);
94 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
95 offsetof(CPUPPCState, crf[i]), p);
96 p += 5;
97 cpu_reg_names_size -= 5;
98 }
99
100 for (i = 0; i < 32; i++) {
101 snprintf(p, cpu_reg_names_size, "r%d", i);
102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUPPCState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105 cpu_reg_names_size -= (i < 10) ? 3 : 4;
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111
112 snprintf(p, cpu_reg_names_size, "fp%d", i);
113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUPPCState, fpr[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "avr%dH", i);
119 #ifdef HOST_WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUPPCState, avr[i].u64[0]), p);
122 #else
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[1]), p);
125 #endif
126 p += (i < 10) ? 6 : 7;
127 cpu_reg_names_size -= (i < 10) ? 6 : 7;
128
129 snprintf(p, cpu_reg_names_size, "avr%dL", i);
130 #ifdef HOST_WORDS_BIGENDIAN
131 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
132 offsetof(CPUPPCState, avr[i].u64[1]), p);
133 #else
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[0]), p);
136 #endif
137 p += (i < 10) ? 6 : 7;
138 cpu_reg_names_size -= (i < 10) ? 6 : 7;
139 snprintf(p, cpu_reg_names_size, "vsr%d", i);
140 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
141 offsetof(CPUPPCState, vsr[i]), p);
142 p += (i < 10) ? 5 : 6;
143 cpu_reg_names_size -= (i < 10) ? 5 : 6;
144 }
145
146 cpu_nip = tcg_global_mem_new(TCG_AREG0,
147 offsetof(CPUPPCState, nip), "nip");
148
149 cpu_msr = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, msr), "msr");
151
152 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, ctr), "ctr");
154
155 cpu_lr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, lr), "lr");
157
158 #if defined(TARGET_PPC64)
159 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, cfar), "cfar");
161 #endif
162
163 cpu_xer = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, xer), "xer");
165 cpu_so = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, so), "SO");
167 cpu_ov = tcg_global_mem_new(TCG_AREG0,
168 offsetof(CPUPPCState, ov), "OV");
169 cpu_ca = tcg_global_mem_new(TCG_AREG0,
170 offsetof(CPUPPCState, ca), "CA");
171
172 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, reserve_addr),
174 "reserve_addr");
175
176 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
177 offsetof(CPUPPCState, fpscr), "fpscr");
178
179 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
180 offsetof(CPUPPCState, access_type), "access_type");
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 bool pr, hv;
193 int mem_idx;
194 int access_type;
195 /* Translation flags */
196 int le_mode;
197 TCGMemOp default_tcg_memop_mask;
198 #if defined(TARGET_PPC64)
199 int sf_mode;
200 int has_cfar;
201 #endif
202 int fpu_enabled;
203 int altivec_enabled;
204 int vsx_enabled;
205 int spe_enabled;
206 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
207 int singlestep_enabled;
208 uint64_t insns_flags;
209 uint64_t insns_flags2;
210 } DisasContext;
211
212 /* Return true iff byteswap is needed in a scalar memop */
213 static inline bool need_byteswap(const DisasContext *ctx)
214 {
215 #if defined(TARGET_WORDS_BIGENDIAN)
216 return ctx->le_mode;
217 #else
218 return !ctx->le_mode;
219 #endif
220 }
221
222 /* True when active word size < size of target_long. */
223 #ifdef TARGET_PPC64
224 # define NARROW_MODE(C) (!(C)->sf_mode)
225 #else
226 # define NARROW_MODE(C) 0
227 #endif
228
229 struct opc_handler_t {
230 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
231 uint32_t inval1;
232 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
233 uint32_t inval2;
234 /* instruction type */
235 uint64_t type;
236 /* extended instruction type */
237 uint64_t type2;
238 /* handler */
239 void (*handler)(DisasContext *ctx);
240 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
241 const char *oname;
242 #endif
243 #if defined(DO_PPC_STATISTICS)
244 uint64_t count;
245 #endif
246 };
247
248 static inline void gen_reset_fpstatus(void)
249 {
250 gen_helper_reset_fpstatus(cpu_env);
251 }
252
253 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
254 {
255 TCGv_i32 t0 = tcg_temp_new_i32();
256
257 if (set_fprf != 0) {
258 /* This case might be optimized later */
259 tcg_gen_movi_i32(t0, 1);
260 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
261 if (unlikely(set_rc)) {
262 tcg_gen_mov_i32(cpu_crf[1], t0);
263 }
264 gen_helper_float_check_status(cpu_env);
265 } else if (unlikely(set_rc)) {
266 /* We always need to compute fpcc */
267 tcg_gen_movi_i32(t0, 0);
268 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
269 tcg_gen_mov_i32(cpu_crf[1], t0);
270 }
271
272 tcg_temp_free_i32(t0);
273 }
274
275 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
276 {
277 if (ctx->access_type != access_type) {
278 tcg_gen_movi_i32(cpu_access_type, access_type);
279 ctx->access_type = access_type;
280 }
281 }
282
283 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
284 {
285 if (NARROW_MODE(ctx)) {
286 nip = (uint32_t)nip;
287 }
288 tcg_gen_movi_tl(cpu_nip, nip);
289 }
290
291 void gen_update_current_nip(void *opaque)
292 {
293 DisasContext *ctx = opaque;
294
295 tcg_gen_movi_tl(cpu_nip, ctx->nip);
296 }
297
298 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
299 {
300 TCGv_i32 t0, t1;
301 if (ctx->exception == POWERPC_EXCP_NONE) {
302 gen_update_nip(ctx, ctx->nip);
303 }
304 t0 = tcg_const_i32(excp);
305 t1 = tcg_const_i32(error);
306 gen_helper_raise_exception_err(cpu_env, t0, t1);
307 tcg_temp_free_i32(t0);
308 tcg_temp_free_i32(t1);
309 ctx->exception = (excp);
310 }
311
312 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
313 {
314 TCGv_i32 t0;
315 if (ctx->exception == POWERPC_EXCP_NONE) {
316 gen_update_nip(ctx, ctx->nip);
317 }
318 t0 = tcg_const_i32(excp);
319 gen_helper_raise_exception(cpu_env, t0);
320 tcg_temp_free_i32(t0);
321 ctx->exception = (excp);
322 }
323
324 static inline void gen_debug_exception(DisasContext *ctx)
325 {
326 TCGv_i32 t0;
327
328 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
329 (ctx->exception != POWERPC_EXCP_SYNC)) {
330 gen_update_nip(ctx, ctx->nip);
331 }
332 t0 = tcg_const_i32(EXCP_DEBUG);
333 gen_helper_raise_exception(cpu_env, t0);
334 tcg_temp_free_i32(t0);
335 }
336
337 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
338 {
339 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
340 }
341
342 /* Stop translation */
343 static inline void gen_stop_exception(DisasContext *ctx)
344 {
345 gen_update_nip(ctx, ctx->nip);
346 ctx->exception = POWERPC_EXCP_STOP;
347 }
348
349 /* No need to update nip here, as execution flow will change */
350 static inline void gen_sync_exception(DisasContext *ctx)
351 {
352 ctx->exception = POWERPC_EXCP_SYNC;
353 }
354
355 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
356 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
357
358 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
359 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
360
361 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
362 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
363
364 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
365 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
366
367 typedef struct opcode_t {
368 unsigned char opc1, opc2, opc3;
369 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
370 unsigned char pad[5];
371 #else
372 unsigned char pad[1];
373 #endif
374 opc_handler_t handler;
375 const char *oname;
376 } opcode_t;
377
378 /*****************************************************************************/
379 /*** Instruction decoding ***/
380 #define EXTRACT_HELPER(name, shift, nb) \
381 static inline uint32_t name(uint32_t opcode) \
382 { \
383 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
384 }
385
386 #define EXTRACT_SHELPER(name, shift, nb) \
387 static inline int32_t name(uint32_t opcode) \
388 { \
389 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
390 }
391
392 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
393 static inline uint32_t name(uint32_t opcode) \
394 { \
395 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
396 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
397 }
398 /* Opcode part 1 */
399 EXTRACT_HELPER(opc1, 26, 6);
400 /* Opcode part 2 */
401 EXTRACT_HELPER(opc2, 1, 5);
402 /* Opcode part 3 */
403 EXTRACT_HELPER(opc3, 6, 5);
404 /* Update Cr0 flags */
405 EXTRACT_HELPER(Rc, 0, 1);
406 /* Update Cr6 flags (Altivec) */
407 EXTRACT_HELPER(Rc21, 10, 1);
408 /* Destination */
409 EXTRACT_HELPER(rD, 21, 5);
410 /* Source */
411 EXTRACT_HELPER(rS, 21, 5);
412 /* First operand */
413 EXTRACT_HELPER(rA, 16, 5);
414 /* Second operand */
415 EXTRACT_HELPER(rB, 11, 5);
416 /* Third operand */
417 EXTRACT_HELPER(rC, 6, 5);
418 /*** Get CRn ***/
419 EXTRACT_HELPER(crfD, 23, 3);
420 EXTRACT_HELPER(crfS, 18, 3);
421 EXTRACT_HELPER(crbD, 21, 5);
422 EXTRACT_HELPER(crbA, 16, 5);
423 EXTRACT_HELPER(crbB, 11, 5);
424 /* SPR / TBL */
425 EXTRACT_HELPER(_SPR, 11, 10);
426 static inline uint32_t SPR(uint32_t opcode)
427 {
428 uint32_t sprn = _SPR(opcode);
429
430 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
431 }
432 /*** Get constants ***/
433 /* 16 bits signed immediate value */
434 EXTRACT_SHELPER(SIMM, 0, 16);
435 /* 16 bits unsigned immediate value */
436 EXTRACT_HELPER(UIMM, 0, 16);
437 /* 5 bits signed immediate value */
438 EXTRACT_HELPER(SIMM5, 16, 5);
439 /* 5 bits signed immediate value */
440 EXTRACT_HELPER(UIMM5, 16, 5);
441 /* Bit count */
442 EXTRACT_HELPER(NB, 11, 5);
443 /* Shift count */
444 EXTRACT_HELPER(SH, 11, 5);
445 /* Vector shift count */
446 EXTRACT_HELPER(VSH, 6, 4);
447 /* Mask start */
448 EXTRACT_HELPER(MB, 6, 5);
449 /* Mask end */
450 EXTRACT_HELPER(ME, 1, 5);
451 /* Trap operand */
452 EXTRACT_HELPER(TO, 21, 5);
453
454 EXTRACT_HELPER(CRM, 12, 8);
455 EXTRACT_HELPER(SR, 16, 4);
456
457 /* mtfsf/mtfsfi */
458 EXTRACT_HELPER(FPBF, 23, 3);
459 EXTRACT_HELPER(FPIMM, 12, 4);
460 EXTRACT_HELPER(FPL, 25, 1);
461 EXTRACT_HELPER(FPFLM, 17, 8);
462 EXTRACT_HELPER(FPW, 16, 1);
463
464 /*** Jump target decoding ***/
465 /* Immediate address */
466 static inline target_ulong LI(uint32_t opcode)
467 {
468 return (opcode >> 0) & 0x03FFFFFC;
469 }
470
471 static inline uint32_t BD(uint32_t opcode)
472 {
473 return (opcode >> 0) & 0xFFFC;
474 }
475
476 EXTRACT_HELPER(BO, 21, 5);
477 EXTRACT_HELPER(BI, 16, 5);
478 /* Absolute/relative address */
479 EXTRACT_HELPER(AA, 1, 1);
480 /* Link */
481 EXTRACT_HELPER(LK, 0, 1);
482
483 /* DFP Z22-form */
484 EXTRACT_HELPER(DCM, 10, 6)
485
486 /* DFP Z23-form */
487 EXTRACT_HELPER(RMC, 9, 2)
488
489 /* Create a mask between <start> and <end> bits */
490 static inline target_ulong MASK(uint32_t start, uint32_t end)
491 {
492 target_ulong ret;
493
494 #if defined(TARGET_PPC64)
495 if (likely(start == 0)) {
496 ret = UINT64_MAX << (63 - end);
497 } else if (likely(end == 63)) {
498 ret = UINT64_MAX >> start;
499 }
500 #else
501 if (likely(start == 0)) {
502 ret = UINT32_MAX << (31 - end);
503 } else if (likely(end == 31)) {
504 ret = UINT32_MAX >> start;
505 }
506 #endif
507 else {
508 ret = (((target_ulong)(-1ULL)) >> (start)) ^
509 (((target_ulong)(-1ULL) >> (end)) >> 1);
510 if (unlikely(start > end))
511 return ~ret;
512 }
513
514 return ret;
515 }
516
517 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
518 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
519 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
520 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
521 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
522 EXTRACT_HELPER(DM, 8, 2);
523 EXTRACT_HELPER(UIM, 16, 2);
524 EXTRACT_HELPER(SHW, 8, 2);
525 EXTRACT_HELPER(SP, 19, 2);
526 /*****************************************************************************/
527 /* PowerPC instructions table */
528
529 #if defined(DO_PPC_STATISTICS)
530 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
531 { \
532 .opc1 = op1, \
533 .opc2 = op2, \
534 .opc3 = op3, \
535 .pad = { 0, }, \
536 .handler = { \
537 .inval1 = invl, \
538 .type = _typ, \
539 .type2 = _typ2, \
540 .handler = &gen_##name, \
541 .oname = stringify(name), \
542 }, \
543 .oname = stringify(name), \
544 }
545 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
546 { \
547 .opc1 = op1, \
548 .opc2 = op2, \
549 .opc3 = op3, \
550 .pad = { 0, }, \
551 .handler = { \
552 .inval1 = invl1, \
553 .inval2 = invl2, \
554 .type = _typ, \
555 .type2 = _typ2, \
556 .handler = &gen_##name, \
557 .oname = stringify(name), \
558 }, \
559 .oname = stringify(name), \
560 }
561 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
562 { \
563 .opc1 = op1, \
564 .opc2 = op2, \
565 .opc3 = op3, \
566 .pad = { 0, }, \
567 .handler = { \
568 .inval1 = invl, \
569 .type = _typ, \
570 .type2 = _typ2, \
571 .handler = &gen_##name, \
572 .oname = onam, \
573 }, \
574 .oname = onam, \
575 }
576 #else
577 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
578 { \
579 .opc1 = op1, \
580 .opc2 = op2, \
581 .opc3 = op3, \
582 .pad = { 0, }, \
583 .handler = { \
584 .inval1 = invl, \
585 .type = _typ, \
586 .type2 = _typ2, \
587 .handler = &gen_##name, \
588 }, \
589 .oname = stringify(name), \
590 }
591 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
592 { \
593 .opc1 = op1, \
594 .opc2 = op2, \
595 .opc3 = op3, \
596 .pad = { 0, }, \
597 .handler = { \
598 .inval1 = invl1, \
599 .inval2 = invl2, \
600 .type = _typ, \
601 .type2 = _typ2, \
602 .handler = &gen_##name, \
603 }, \
604 .oname = stringify(name), \
605 }
606 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
607 { \
608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
611 .pad = { 0, }, \
612 .handler = { \
613 .inval1 = invl, \
614 .type = _typ, \
615 .type2 = _typ2, \
616 .handler = &gen_##name, \
617 }, \
618 .oname = onam, \
619 }
620 #endif
621
622 /* SPR load/store helpers */
623 static inline void gen_load_spr(TCGv t, int reg)
624 {
625 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
626 }
627
628 static inline void gen_store_spr(int reg, TCGv t)
629 {
630 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
631 }
632
633 /* Invalid instruction */
634 static void gen_invalid(DisasContext *ctx)
635 {
636 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
637 }
638
639 static opc_handler_t invalid_handler = {
640 .inval1 = 0xFFFFFFFF,
641 .inval2 = 0xFFFFFFFF,
642 .type = PPC_NONE,
643 .type2 = PPC_NONE,
644 .handler = gen_invalid,
645 };
646
647 /*** Integer comparison ***/
648
649 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
650 {
651 TCGv t0 = tcg_temp_new();
652 TCGv_i32 t1 = tcg_temp_new_i32();
653
654 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
655
656 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
657 tcg_gen_trunc_tl_i32(t1, t0);
658 tcg_gen_shli_i32(t1, t1, CRF_LT);
659 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
660
661 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
662 tcg_gen_trunc_tl_i32(t1, t0);
663 tcg_gen_shli_i32(t1, t1, CRF_GT);
664 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
665
666 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
667 tcg_gen_trunc_tl_i32(t1, t0);
668 tcg_gen_shli_i32(t1, t1, CRF_EQ);
669 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
670
671 tcg_temp_free(t0);
672 tcg_temp_free_i32(t1);
673 }
674
675 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
676 {
677 TCGv t0 = tcg_const_tl(arg1);
678 gen_op_cmp(arg0, t0, s, crf);
679 tcg_temp_free(t0);
680 }
681
682 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
683 {
684 TCGv t0, t1;
685 t0 = tcg_temp_new();
686 t1 = tcg_temp_new();
687 if (s) {
688 tcg_gen_ext32s_tl(t0, arg0);
689 tcg_gen_ext32s_tl(t1, arg1);
690 } else {
691 tcg_gen_ext32u_tl(t0, arg0);
692 tcg_gen_ext32u_tl(t1, arg1);
693 }
694 gen_op_cmp(t0, t1, s, crf);
695 tcg_temp_free(t1);
696 tcg_temp_free(t0);
697 }
698
699 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
700 {
701 TCGv t0 = tcg_const_tl(arg1);
702 gen_op_cmp32(arg0, t0, s, crf);
703 tcg_temp_free(t0);
704 }
705
706 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
707 {
708 if (NARROW_MODE(ctx)) {
709 gen_op_cmpi32(reg, 0, 1, 0);
710 } else {
711 gen_op_cmpi(reg, 0, 1, 0);
712 }
713 }
714
715 /* cmp */
716 static void gen_cmp(DisasContext *ctx)
717 {
718 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
719 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
720 1, crfD(ctx->opcode));
721 } else {
722 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
723 1, crfD(ctx->opcode));
724 }
725 }
726
727 /* cmpi */
728 static void gen_cmpi(DisasContext *ctx)
729 {
730 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
731 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
732 1, crfD(ctx->opcode));
733 } else {
734 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
735 1, crfD(ctx->opcode));
736 }
737 }
738
739 /* cmpl */
740 static void gen_cmpl(DisasContext *ctx)
741 {
742 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
743 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
744 0, crfD(ctx->opcode));
745 } else {
746 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
747 0, crfD(ctx->opcode));
748 }
749 }
750
751 /* cmpli */
752 static void gen_cmpli(DisasContext *ctx)
753 {
754 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
755 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
756 0, crfD(ctx->opcode));
757 } else {
758 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
759 0, crfD(ctx->opcode));
760 }
761 }
762
763 /* isel (PowerPC 2.03 specification) */
764 static void gen_isel(DisasContext *ctx)
765 {
766 int l1, l2;
767 uint32_t bi = rC(ctx->opcode);
768 uint32_t mask;
769 TCGv_i32 t0;
770
771 l1 = gen_new_label();
772 l2 = gen_new_label();
773
774 mask = 0x08 >> (bi & 0x03);
775 t0 = tcg_temp_new_i32();
776 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
777 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
778 if (rA(ctx->opcode) == 0)
779 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
780 else
781 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
782 tcg_gen_br(l2);
783 gen_set_label(l1);
784 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
785 gen_set_label(l2);
786 tcg_temp_free_i32(t0);
787 }
788
789 /* cmpb: PowerPC 2.05 specification */
790 static void gen_cmpb(DisasContext *ctx)
791 {
792 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
793 cpu_gpr[rB(ctx->opcode)]);
794 }
795
796 /*** Integer arithmetic ***/
797
798 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
799 TCGv arg1, TCGv arg2, int sub)
800 {
801 TCGv t0 = tcg_temp_new();
802
803 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
804 tcg_gen_xor_tl(t0, arg1, arg2);
805 if (sub) {
806 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
807 } else {
808 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
809 }
810 tcg_temp_free(t0);
811 if (NARROW_MODE(ctx)) {
812 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
813 }
814 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
815 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
816 }
817
818 /* Common add function */
819 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
820 TCGv arg2, bool add_ca, bool compute_ca,
821 bool compute_ov, bool compute_rc0)
822 {
823 TCGv t0 = ret;
824
825 if (compute_ca || compute_ov) {
826 t0 = tcg_temp_new();
827 }
828
829 if (compute_ca) {
830 if (NARROW_MODE(ctx)) {
831 /* Caution: a non-obvious corner case of the spec is that we
832 must produce the *entire* 64-bit addition, but produce the
833 carry into bit 32. */
834 TCGv t1 = tcg_temp_new();
835 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
836 tcg_gen_add_tl(t0, arg1, arg2);
837 if (add_ca) {
838 tcg_gen_add_tl(t0, t0, cpu_ca);
839 }
840 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
841 tcg_temp_free(t1);
842 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
843 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
844 } else {
845 TCGv zero = tcg_const_tl(0);
846 if (add_ca) {
847 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
848 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
849 } else {
850 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
851 }
852 tcg_temp_free(zero);
853 }
854 } else {
855 tcg_gen_add_tl(t0, arg1, arg2);
856 if (add_ca) {
857 tcg_gen_add_tl(t0, t0, cpu_ca);
858 }
859 }
860
861 if (compute_ov) {
862 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
863 }
864 if (unlikely(compute_rc0)) {
865 gen_set_Rc0(ctx, t0);
866 }
867
868 if (!TCGV_EQUAL(t0, ret)) {
869 tcg_gen_mov_tl(ret, t0);
870 tcg_temp_free(t0);
871 }
872 }
873 /* Add functions with two operands */
874 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
875 static void glue(gen_, name)(DisasContext *ctx) \
876 { \
877 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
878 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
879 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
880 }
881 /* Add functions with one operand and one immediate */
882 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
883 add_ca, compute_ca, compute_ov) \
884 static void glue(gen_, name)(DisasContext *ctx) \
885 { \
886 TCGv t0 = tcg_const_tl(const_val); \
887 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
888 cpu_gpr[rA(ctx->opcode)], t0, \
889 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
890 tcg_temp_free(t0); \
891 }
892
893 /* add add. addo addo. */
894 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
895 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
896 /* addc addc. addco addco. */
897 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
898 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
899 /* adde adde. addeo addeo. */
900 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
901 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
902 /* addme addme. addmeo addmeo. */
903 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
904 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
905 /* addze addze. addzeo addzeo.*/
906 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
907 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
908 /* addi */
909 static void gen_addi(DisasContext *ctx)
910 {
911 target_long simm = SIMM(ctx->opcode);
912
913 if (rA(ctx->opcode) == 0) {
914 /* li case */
915 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
916 } else {
917 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
918 cpu_gpr[rA(ctx->opcode)], simm);
919 }
920 }
921 /* addic addic.*/
922 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
923 {
924 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
925 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
926 c, 0, 1, 0, compute_rc0);
927 tcg_temp_free(c);
928 }
929
930 static void gen_addic(DisasContext *ctx)
931 {
932 gen_op_addic(ctx, 0);
933 }
934
935 static void gen_addic_(DisasContext *ctx)
936 {
937 gen_op_addic(ctx, 1);
938 }
939
940 /* addis */
941 static void gen_addis(DisasContext *ctx)
942 {
943 target_long simm = SIMM(ctx->opcode);
944
945 if (rA(ctx->opcode) == 0) {
946 /* lis case */
947 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
948 } else {
949 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
950 cpu_gpr[rA(ctx->opcode)], simm << 16);
951 }
952 }
953
954 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
955 TCGv arg2, int sign, int compute_ov)
956 {
957 int l1 = gen_new_label();
958 int l2 = gen_new_label();
959 TCGv_i32 t0 = tcg_temp_local_new_i32();
960 TCGv_i32 t1 = tcg_temp_local_new_i32();
961
962 tcg_gen_trunc_tl_i32(t0, arg1);
963 tcg_gen_trunc_tl_i32(t1, arg2);
964 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
965 if (sign) {
966 int l3 = gen_new_label();
967 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
968 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
969 gen_set_label(l3);
970 tcg_gen_div_i32(t0, t0, t1);
971 } else {
972 tcg_gen_divu_i32(t0, t0, t1);
973 }
974 if (compute_ov) {
975 tcg_gen_movi_tl(cpu_ov, 0);
976 }
977 tcg_gen_br(l2);
978 gen_set_label(l1);
979 if (sign) {
980 tcg_gen_sari_i32(t0, t0, 31);
981 } else {
982 tcg_gen_movi_i32(t0, 0);
983 }
984 if (compute_ov) {
985 tcg_gen_movi_tl(cpu_ov, 1);
986 tcg_gen_movi_tl(cpu_so, 1);
987 }
988 gen_set_label(l2);
989 tcg_gen_extu_i32_tl(ret, t0);
990 tcg_temp_free_i32(t0);
991 tcg_temp_free_i32(t1);
992 if (unlikely(Rc(ctx->opcode) != 0))
993 gen_set_Rc0(ctx, ret);
994 }
995 /* Div functions */
996 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
997 static void glue(gen_, name)(DisasContext *ctx) \
998 { \
999 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1000 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1001 sign, compute_ov); \
1002 }
1003 /* divwu divwu. divwuo divwuo. */
1004 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1005 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1006 /* divw divw. divwo divwo. */
1007 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1008 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1009
1010 /* div[wd]eu[o][.] */
1011 #define GEN_DIVE(name, hlpr, compute_ov) \
1012 static void gen_##name(DisasContext *ctx) \
1013 { \
1014 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1015 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1016 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1017 tcg_temp_free_i32(t0); \
1018 if (unlikely(Rc(ctx->opcode) != 0)) { \
1019 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1020 } \
1021 }
1022
1023 GEN_DIVE(divweu, divweu, 0);
1024 GEN_DIVE(divweuo, divweu, 1);
1025 GEN_DIVE(divwe, divwe, 0);
1026 GEN_DIVE(divweo, divwe, 1);
1027
1028 #if defined(TARGET_PPC64)
1029 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1030 TCGv arg2, int sign, int compute_ov)
1031 {
1032 int l1 = gen_new_label();
1033 int l2 = gen_new_label();
1034
1035 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1036 if (sign) {
1037 int l3 = gen_new_label();
1038 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1039 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1040 gen_set_label(l3);
1041 tcg_gen_div_i64(ret, arg1, arg2);
1042 } else {
1043 tcg_gen_divu_i64(ret, arg1, arg2);
1044 }
1045 if (compute_ov) {
1046 tcg_gen_movi_tl(cpu_ov, 0);
1047 }
1048 tcg_gen_br(l2);
1049 gen_set_label(l1);
1050 if (sign) {
1051 tcg_gen_sari_i64(ret, arg1, 63);
1052 } else {
1053 tcg_gen_movi_i64(ret, 0);
1054 }
1055 if (compute_ov) {
1056 tcg_gen_movi_tl(cpu_ov, 1);
1057 tcg_gen_movi_tl(cpu_so, 1);
1058 }
1059 gen_set_label(l2);
1060 if (unlikely(Rc(ctx->opcode) != 0))
1061 gen_set_Rc0(ctx, ret);
1062 }
1063 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1064 static void glue(gen_, name)(DisasContext *ctx) \
1065 { \
1066 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1067 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1068 sign, compute_ov); \
1069 }
1070 /* divwu divwu. divwuo divwuo. */
1071 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1072 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1073 /* divw divw. divwo divwo. */
1074 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1075 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1076
1077 GEN_DIVE(divdeu, divdeu, 0);
1078 GEN_DIVE(divdeuo, divdeu, 1);
1079 GEN_DIVE(divde, divde, 0);
1080 GEN_DIVE(divdeo, divde, 1);
1081 #endif
1082
1083 /* mulhw mulhw. */
1084 static void gen_mulhw(DisasContext *ctx)
1085 {
1086 TCGv_i32 t0 = tcg_temp_new_i32();
1087 TCGv_i32 t1 = tcg_temp_new_i32();
1088
1089 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1090 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1091 tcg_gen_muls2_i32(t0, t1, t0, t1);
1092 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1093 tcg_temp_free_i32(t0);
1094 tcg_temp_free_i32(t1);
1095 if (unlikely(Rc(ctx->opcode) != 0))
1096 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1097 }
1098
1099 /* mulhwu mulhwu. */
1100 static void gen_mulhwu(DisasContext *ctx)
1101 {
1102 TCGv_i32 t0 = tcg_temp_new_i32();
1103 TCGv_i32 t1 = tcg_temp_new_i32();
1104
1105 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1106 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1107 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1108 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1109 tcg_temp_free_i32(t0);
1110 tcg_temp_free_i32(t1);
1111 if (unlikely(Rc(ctx->opcode) != 0))
1112 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1113 }
1114
1115 /* mullw mullw. */
1116 static void gen_mullw(DisasContext *ctx)
1117 {
1118 #if defined(TARGET_PPC64)
1119 TCGv_i64 t0, t1;
1120 t0 = tcg_temp_new_i64();
1121 t1 = tcg_temp_new_i64();
1122 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1123 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1124 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1125 tcg_temp_free(t0);
1126 tcg_temp_free(t1);
1127 #else
1128 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1129 cpu_gpr[rB(ctx->opcode)]);
1130 #endif
1131 if (unlikely(Rc(ctx->opcode) != 0))
1132 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1133 }
1134
1135 /* mullwo mullwo. */
1136 static void gen_mullwo(DisasContext *ctx)
1137 {
1138 TCGv_i32 t0 = tcg_temp_new_i32();
1139 TCGv_i32 t1 = tcg_temp_new_i32();
1140
1141 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1142 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1143 tcg_gen_muls2_i32(t0, t1, t0, t1);
1144 #if defined(TARGET_PPC64)
1145 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1146 #else
1147 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1148 #endif
1149
1150 tcg_gen_sari_i32(t0, t0, 31);
1151 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1152 tcg_gen_extu_i32_tl(cpu_ov, t0);
1153 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1154
1155 tcg_temp_free_i32(t0);
1156 tcg_temp_free_i32(t1);
1157 if (unlikely(Rc(ctx->opcode) != 0))
1158 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1159 }
1160
1161 /* mulli */
1162 static void gen_mulli(DisasContext *ctx)
1163 {
1164 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1165 SIMM(ctx->opcode));
1166 }
1167
1168 #if defined(TARGET_PPC64)
1169 /* mulhd mulhd. */
1170 static void gen_mulhd(DisasContext *ctx)
1171 {
1172 TCGv lo = tcg_temp_new();
1173 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1174 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1175 tcg_temp_free(lo);
1176 if (unlikely(Rc(ctx->opcode) != 0)) {
1177 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1178 }
1179 }
1180
1181 /* mulhdu mulhdu. */
1182 static void gen_mulhdu(DisasContext *ctx)
1183 {
1184 TCGv lo = tcg_temp_new();
1185 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1186 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1187 tcg_temp_free(lo);
1188 if (unlikely(Rc(ctx->opcode) != 0)) {
1189 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1190 }
1191 }
1192
1193 /* mulld mulld. */
1194 static void gen_mulld(DisasContext *ctx)
1195 {
1196 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1197 cpu_gpr[rB(ctx->opcode)]);
1198 if (unlikely(Rc(ctx->opcode) != 0))
1199 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1200 }
1201
1202 /* mulldo mulldo. */
1203 static void gen_mulldo(DisasContext *ctx)
1204 {
1205 TCGv_i64 t0 = tcg_temp_new_i64();
1206 TCGv_i64 t1 = tcg_temp_new_i64();
1207
1208 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1209 cpu_gpr[rB(ctx->opcode)]);
1210 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1211
1212 tcg_gen_sari_i64(t0, t0, 63);
1213 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1214 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1215
1216 tcg_temp_free_i64(t0);
1217 tcg_temp_free_i64(t1);
1218
1219 if (unlikely(Rc(ctx->opcode) != 0)) {
1220 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1221 }
1222 }
1223 #endif
1224
1225 /* Common subf function */
1226 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1227 TCGv arg2, bool add_ca, bool compute_ca,
1228 bool compute_ov, bool compute_rc0)
1229 {
1230 TCGv t0 = ret;
1231
1232 if (compute_ca || compute_ov) {
1233 t0 = tcg_temp_new();
1234 }
1235
1236 if (compute_ca) {
1237 /* dest = ~arg1 + arg2 [+ ca]. */
1238 if (NARROW_MODE(ctx)) {
1239 /* Caution: a non-obvious corner case of the spec is that we
1240 must produce the *entire* 64-bit addition, but produce the
1241 carry into bit 32. */
1242 TCGv inv1 = tcg_temp_new();
1243 TCGv t1 = tcg_temp_new();
1244 tcg_gen_not_tl(inv1, arg1);
1245 if (add_ca) {
1246 tcg_gen_add_tl(t0, arg2, cpu_ca);
1247 } else {
1248 tcg_gen_addi_tl(t0, arg2, 1);
1249 }
1250 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1251 tcg_gen_add_tl(t0, t0, inv1);
1252 tcg_temp_free(inv1);
1253 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1254 tcg_temp_free(t1);
1255 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1256 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1257 } else if (add_ca) {
1258 TCGv zero, inv1 = tcg_temp_new();
1259 tcg_gen_not_tl(inv1, arg1);
1260 zero = tcg_const_tl(0);
1261 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1262 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1263 tcg_temp_free(zero);
1264 tcg_temp_free(inv1);
1265 } else {
1266 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1267 tcg_gen_sub_tl(t0, arg2, arg1);
1268 }
1269 } else if (add_ca) {
1270 /* Since we're ignoring carry-out, we can simplify the
1271 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1272 tcg_gen_sub_tl(t0, arg2, arg1);
1273 tcg_gen_add_tl(t0, t0, cpu_ca);
1274 tcg_gen_subi_tl(t0, t0, 1);
1275 } else {
1276 tcg_gen_sub_tl(t0, arg2, arg1);
1277 }
1278
1279 if (compute_ov) {
1280 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1281 }
1282 if (unlikely(compute_rc0)) {
1283 gen_set_Rc0(ctx, t0);
1284 }
1285
1286 if (!TCGV_EQUAL(t0, ret)) {
1287 tcg_gen_mov_tl(ret, t0);
1288 tcg_temp_free(t0);
1289 }
1290 }
1291 /* Sub functions with Two operands functions */
1292 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1293 static void glue(gen_, name)(DisasContext *ctx) \
1294 { \
1295 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1296 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1297 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1298 }
1299 /* Sub functions with one operand and one immediate */
1300 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1301 add_ca, compute_ca, compute_ov) \
1302 static void glue(gen_, name)(DisasContext *ctx) \
1303 { \
1304 TCGv t0 = tcg_const_tl(const_val); \
1305 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1306 cpu_gpr[rA(ctx->opcode)], t0, \
1307 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1308 tcg_temp_free(t0); \
1309 }
1310 /* subf subf. subfo subfo. */
1311 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1312 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1313 /* subfc subfc. subfco subfco. */
1314 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1315 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1316 /* subfe subfe. subfeo subfo. */
1317 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1318 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1319 /* subfme subfme. subfmeo subfmeo. */
1320 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1321 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1322 /* subfze subfze. subfzeo subfzeo.*/
1323 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1324 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1325
1326 /* subfic */
1327 static void gen_subfic(DisasContext *ctx)
1328 {
1329 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1330 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1331 c, 0, 1, 0, 0);
1332 tcg_temp_free(c);
1333 }
1334
1335 /* neg neg. nego nego. */
1336 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1337 {
1338 TCGv zero = tcg_const_tl(0);
1339 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1340 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1341 tcg_temp_free(zero);
1342 }
1343
1344 static void gen_neg(DisasContext *ctx)
1345 {
1346 gen_op_arith_neg(ctx, 0);
1347 }
1348
1349 static void gen_nego(DisasContext *ctx)
1350 {
1351 gen_op_arith_neg(ctx, 1);
1352 }
1353
1354 /*** Integer logical ***/
1355 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1356 static void glue(gen_, name)(DisasContext *ctx) \
1357 { \
1358 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1359 cpu_gpr[rB(ctx->opcode)]); \
1360 if (unlikely(Rc(ctx->opcode) != 0)) \
1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1362 }
1363
1364 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1365 static void glue(gen_, name)(DisasContext *ctx) \
1366 { \
1367 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1368 if (unlikely(Rc(ctx->opcode) != 0)) \
1369 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1370 }
1371
1372 /* and & and. */
1373 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1374 /* andc & andc. */
1375 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1376
1377 /* andi. */
1378 static void gen_andi_(DisasContext *ctx)
1379 {
1380 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1381 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1382 }
1383
1384 /* andis. */
1385 static void gen_andis_(DisasContext *ctx)
1386 {
1387 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1388 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1389 }
1390
1391 /* cntlzw */
1392 static void gen_cntlzw(DisasContext *ctx)
1393 {
1394 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1395 if (unlikely(Rc(ctx->opcode) != 0))
1396 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1397 }
1398 /* eqv & eqv. */
1399 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1400 /* extsb & extsb. */
1401 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1402 /* extsh & extsh. */
1403 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1404 /* nand & nand. */
1405 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1406 /* nor & nor. */
1407 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1408
1409 /* or & or. */
1410 static void gen_or(DisasContext *ctx)
1411 {
1412 int rs, ra, rb;
1413
1414 rs = rS(ctx->opcode);
1415 ra = rA(ctx->opcode);
1416 rb = rB(ctx->opcode);
1417 /* Optimisation for mr. ri case */
1418 if (rs != ra || rs != rb) {
1419 if (rs != rb)
1420 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1421 else
1422 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1423 if (unlikely(Rc(ctx->opcode) != 0))
1424 gen_set_Rc0(ctx, cpu_gpr[ra]);
1425 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1426 gen_set_Rc0(ctx, cpu_gpr[rs]);
1427 #if defined(TARGET_PPC64)
1428 } else {
1429 int prio = 0;
1430
1431 switch (rs) {
1432 case 1:
1433 /* Set process priority to low */
1434 prio = 2;
1435 break;
1436 case 6:
1437 /* Set process priority to medium-low */
1438 prio = 3;
1439 break;
1440 case 2:
1441 /* Set process priority to normal */
1442 prio = 4;
1443 break;
1444 #if !defined(CONFIG_USER_ONLY)
1445 case 31:
1446 if (!ctx->pr) {
1447 /* Set process priority to very low */
1448 prio = 1;
1449 }
1450 break;
1451 case 5:
1452 if (!ctx->pr) {
1453 /* Set process priority to medium-hight */
1454 prio = 5;
1455 }
1456 break;
1457 case 3:
1458 if (!ctx->pr) {
1459 /* Set process priority to high */
1460 prio = 6;
1461 }
1462 break;
1463 case 7:
1464 if (ctx->hv) {
1465 /* Set process priority to very high */
1466 prio = 7;
1467 }
1468 break;
1469 #endif
1470 default:
1471 /* nop */
1472 break;
1473 }
1474 if (prio) {
1475 TCGv t0 = tcg_temp_new();
1476 gen_load_spr(t0, SPR_PPR);
1477 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1478 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1479 gen_store_spr(SPR_PPR, t0);
1480 tcg_temp_free(t0);
1481 }
1482 #endif
1483 }
1484 }
1485 /* orc & orc. */
1486 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1487
1488 /* xor & xor. */
1489 static void gen_xor(DisasContext *ctx)
1490 {
1491 /* Optimisation for "set to zero" case */
1492 if (rS(ctx->opcode) != rB(ctx->opcode))
1493 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1494 else
1495 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1496 if (unlikely(Rc(ctx->opcode) != 0))
1497 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1498 }
1499
1500 /* ori */
1501 static void gen_ori(DisasContext *ctx)
1502 {
1503 target_ulong uimm = UIMM(ctx->opcode);
1504
1505 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1506 /* NOP */
1507 /* XXX: should handle special NOPs for POWER series */
1508 return;
1509 }
1510 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1511 }
1512
1513 /* oris */
1514 static void gen_oris(DisasContext *ctx)
1515 {
1516 target_ulong uimm = UIMM(ctx->opcode);
1517
1518 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1519 /* NOP */
1520 return;
1521 }
1522 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1523 }
1524
1525 /* xori */
1526 static void gen_xori(DisasContext *ctx)
1527 {
1528 target_ulong uimm = UIMM(ctx->opcode);
1529
1530 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1531 /* NOP */
1532 return;
1533 }
1534 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1535 }
1536
1537 /* xoris */
1538 static void gen_xoris(DisasContext *ctx)
1539 {
1540 target_ulong uimm = UIMM(ctx->opcode);
1541
1542 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1543 /* NOP */
1544 return;
1545 }
1546 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1547 }
1548
1549 /* popcntb : PowerPC 2.03 specification */
1550 static void gen_popcntb(DisasContext *ctx)
1551 {
1552 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1553 }
1554
1555 static void gen_popcntw(DisasContext *ctx)
1556 {
1557 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1558 }
1559
1560 #if defined(TARGET_PPC64)
1561 /* popcntd: PowerPC 2.06 specification */
1562 static void gen_popcntd(DisasContext *ctx)
1563 {
1564 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1565 }
1566 #endif
1567
1568 /* prtyw: PowerPC 2.05 specification */
1569 static void gen_prtyw(DisasContext *ctx)
1570 {
1571 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1572 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1573 TCGv t0 = tcg_temp_new();
1574 tcg_gen_shri_tl(t0, rs, 16);
1575 tcg_gen_xor_tl(ra, rs, t0);
1576 tcg_gen_shri_tl(t0, ra, 8);
1577 tcg_gen_xor_tl(ra, ra, t0);
1578 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1579 tcg_temp_free(t0);
1580 }
1581
1582 #if defined(TARGET_PPC64)
1583 /* prtyd: PowerPC 2.05 specification */
1584 static void gen_prtyd(DisasContext *ctx)
1585 {
1586 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1587 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1588 TCGv t0 = tcg_temp_new();
1589 tcg_gen_shri_tl(t0, rs, 32);
1590 tcg_gen_xor_tl(ra, rs, t0);
1591 tcg_gen_shri_tl(t0, ra, 16);
1592 tcg_gen_xor_tl(ra, ra, t0);
1593 tcg_gen_shri_tl(t0, ra, 8);
1594 tcg_gen_xor_tl(ra, ra, t0);
1595 tcg_gen_andi_tl(ra, ra, 1);
1596 tcg_temp_free(t0);
1597 }
1598 #endif
1599
1600 #if defined(TARGET_PPC64)
1601 /* bpermd */
1602 static void gen_bpermd(DisasContext *ctx)
1603 {
1604 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1605 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1606 }
1607 #endif
1608
1609 #if defined(TARGET_PPC64)
1610 /* extsw & extsw. */
1611 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1612
1613 /* cntlzd */
1614 static void gen_cntlzd(DisasContext *ctx)
1615 {
1616 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1617 if (unlikely(Rc(ctx->opcode) != 0))
1618 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1619 }
1620 #endif
1621
1622 /*** Integer rotate ***/
1623
1624 /* rlwimi & rlwimi. */
1625 static void gen_rlwimi(DisasContext *ctx)
1626 {
1627 uint32_t mb, me, sh;
1628
1629 mb = MB(ctx->opcode);
1630 me = ME(ctx->opcode);
1631 sh = SH(ctx->opcode);
1632 if (likely(sh == (31-me) && mb <= me)) {
1633 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1634 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
1635 } else {
1636 target_ulong mask;
1637 TCGv t1;
1638 TCGv t0 = tcg_temp_new();
1639 #if defined(TARGET_PPC64)
1640 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1641 cpu_gpr[rS(ctx->opcode)], 32, 32);
1642 tcg_gen_rotli_i64(t0, t0, sh);
1643 #else
1644 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1645 #endif
1646 #if defined(TARGET_PPC64)
1647 mb += 32;
1648 me += 32;
1649 #endif
1650 mask = MASK(mb, me);
1651 t1 = tcg_temp_new();
1652 tcg_gen_andi_tl(t0, t0, mask);
1653 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1654 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1655 tcg_temp_free(t0);
1656 tcg_temp_free(t1);
1657 }
1658 if (unlikely(Rc(ctx->opcode) != 0))
1659 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1660 }
1661
1662 /* rlwinm & rlwinm. */
1663 static void gen_rlwinm(DisasContext *ctx)
1664 {
1665 uint32_t mb, me, sh;
1666
1667 sh = SH(ctx->opcode);
1668 mb = MB(ctx->opcode);
1669 me = ME(ctx->opcode);
1670
1671 if (likely(mb == 0 && me == (31 - sh))) {
1672 if (likely(sh == 0)) {
1673 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1674 } else {
1675 TCGv t0 = tcg_temp_new();
1676 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1677 tcg_gen_shli_tl(t0, t0, sh);
1678 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1679 tcg_temp_free(t0);
1680 }
1681 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1682 TCGv t0 = tcg_temp_new();
1683 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1684 tcg_gen_shri_tl(t0, t0, mb);
1685 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1686 tcg_temp_free(t0);
1687 } else if (likely(mb == 0 && me == 31)) {
1688 TCGv_i32 t0 = tcg_temp_new_i32();
1689 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1690 tcg_gen_rotli_i32(t0, t0, sh);
1691 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1692 tcg_temp_free_i32(t0);
1693 } else {
1694 TCGv t0 = tcg_temp_new();
1695 #if defined(TARGET_PPC64)
1696 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1697 cpu_gpr[rS(ctx->opcode)], 32, 32);
1698 tcg_gen_rotli_i64(t0, t0, sh);
1699 #else
1700 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1701 #endif
1702 #if defined(TARGET_PPC64)
1703 mb += 32;
1704 me += 32;
1705 #endif
1706 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1707 tcg_temp_free(t0);
1708 }
1709 if (unlikely(Rc(ctx->opcode) != 0))
1710 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1711 }
1712
1713 /* rlwnm & rlwnm. */
1714 static void gen_rlwnm(DisasContext *ctx)
1715 {
1716 uint32_t mb, me;
1717 mb = MB(ctx->opcode);
1718 me = ME(ctx->opcode);
1719
1720 if (likely(mb == 0 && me == 31)) {
1721 TCGv_i32 t0, t1;
1722 t0 = tcg_temp_new_i32();
1723 t1 = tcg_temp_new_i32();
1724 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1725 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1726 tcg_gen_andi_i32(t0, t0, 0x1f);
1727 tcg_gen_rotl_i32(t1, t1, t0);
1728 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1729 tcg_temp_free_i32(t0);
1730 tcg_temp_free_i32(t1);
1731 } else {
1732 TCGv t0;
1733 #if defined(TARGET_PPC64)
1734 TCGv t1;
1735 #endif
1736
1737 t0 = tcg_temp_new();
1738 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1739 #if defined(TARGET_PPC64)
1740 t1 = tcg_temp_new_i64();
1741 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1742 cpu_gpr[rS(ctx->opcode)], 32, 32);
1743 tcg_gen_rotl_i64(t0, t1, t0);
1744 tcg_temp_free_i64(t1);
1745 #else
1746 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1747 #endif
1748 if (unlikely(mb != 0 || me != 31)) {
1749 #if defined(TARGET_PPC64)
1750 mb += 32;
1751 me += 32;
1752 #endif
1753 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1754 } else {
1755 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1756 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1757 }
1758 tcg_temp_free(t0);
1759 }
1760 if (unlikely(Rc(ctx->opcode) != 0))
1761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1762 }
1763
1764 #if defined(TARGET_PPC64)
1765 #define GEN_PPC64_R2(name, opc1, opc2) \
1766 static void glue(gen_, name##0)(DisasContext *ctx) \
1767 { \
1768 gen_##name(ctx, 0); \
1769 } \
1770 \
1771 static void glue(gen_, name##1)(DisasContext *ctx) \
1772 { \
1773 gen_##name(ctx, 1); \
1774 }
1775 #define GEN_PPC64_R4(name, opc1, opc2) \
1776 static void glue(gen_, name##0)(DisasContext *ctx) \
1777 { \
1778 gen_##name(ctx, 0, 0); \
1779 } \
1780 \
1781 static void glue(gen_, name##1)(DisasContext *ctx) \
1782 { \
1783 gen_##name(ctx, 0, 1); \
1784 } \
1785 \
1786 static void glue(gen_, name##2)(DisasContext *ctx) \
1787 { \
1788 gen_##name(ctx, 1, 0); \
1789 } \
1790 \
1791 static void glue(gen_, name##3)(DisasContext *ctx) \
1792 { \
1793 gen_##name(ctx, 1, 1); \
1794 }
1795
1796 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1797 uint32_t sh)
1798 {
1799 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1800 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1801 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1802 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1803 } else {
1804 TCGv t0 = tcg_temp_new();
1805 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1806 if (likely(mb == 0 && me == 63)) {
1807 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1808 } else {
1809 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1810 }
1811 tcg_temp_free(t0);
1812 }
1813 if (unlikely(Rc(ctx->opcode) != 0))
1814 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1815 }
1816 /* rldicl - rldicl. */
1817 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1818 {
1819 uint32_t sh, mb;
1820
1821 sh = SH(ctx->opcode) | (shn << 5);
1822 mb = MB(ctx->opcode) | (mbn << 5);
1823 gen_rldinm(ctx, mb, 63, sh);
1824 }
1825 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1826 /* rldicr - rldicr. */
1827 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1828 {
1829 uint32_t sh, me;
1830
1831 sh = SH(ctx->opcode) | (shn << 5);
1832 me = MB(ctx->opcode) | (men << 5);
1833 gen_rldinm(ctx, 0, me, sh);
1834 }
1835 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1836 /* rldic - rldic. */
1837 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1838 {
1839 uint32_t sh, mb;
1840
1841 sh = SH(ctx->opcode) | (shn << 5);
1842 mb = MB(ctx->opcode) | (mbn << 5);
1843 gen_rldinm(ctx, mb, 63 - sh, sh);
1844 }
1845 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1846
1847 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1848 {
1849 TCGv t0;
1850
1851 t0 = tcg_temp_new();
1852 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1853 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1854 if (unlikely(mb != 0 || me != 63)) {
1855 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1856 } else {
1857 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1858 }
1859 tcg_temp_free(t0);
1860 if (unlikely(Rc(ctx->opcode) != 0))
1861 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1862 }
1863
1864 /* rldcl - rldcl. */
1865 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1866 {
1867 uint32_t mb;
1868
1869 mb = MB(ctx->opcode) | (mbn << 5);
1870 gen_rldnm(ctx, mb, 63);
1871 }
1872 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1873 /* rldcr - rldcr. */
1874 static inline void gen_rldcr(DisasContext *ctx, int men)
1875 {
1876 uint32_t me;
1877
1878 me = MB(ctx->opcode) | (men << 5);
1879 gen_rldnm(ctx, 0, me);
1880 }
1881 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1882 /* rldimi - rldimi. */
1883 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1884 {
1885 uint32_t sh, mb, me;
1886
1887 sh = SH(ctx->opcode) | (shn << 5);
1888 mb = MB(ctx->opcode) | (mbn << 5);
1889 me = 63 - sh;
1890 if (unlikely(sh == 0 && mb == 0)) {
1891 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1892 } else {
1893 TCGv t0, t1;
1894 target_ulong mask;
1895
1896 t0 = tcg_temp_new();
1897 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1898 t1 = tcg_temp_new();
1899 mask = MASK(mb, me);
1900 tcg_gen_andi_tl(t0, t0, mask);
1901 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1902 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1903 tcg_temp_free(t0);
1904 tcg_temp_free(t1);
1905 }
1906 if (unlikely(Rc(ctx->opcode) != 0))
1907 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1908 }
1909 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1910 #endif
1911
1912 /*** Integer shift ***/
1913
1914 /* slw & slw. */
1915 static void gen_slw(DisasContext *ctx)
1916 {
1917 TCGv t0, t1;
1918
1919 t0 = tcg_temp_new();
1920 /* AND rS with a mask that is 0 when rB >= 0x20 */
1921 #if defined(TARGET_PPC64)
1922 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1923 tcg_gen_sari_tl(t0, t0, 0x3f);
1924 #else
1925 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1926 tcg_gen_sari_tl(t0, t0, 0x1f);
1927 #endif
1928 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1929 t1 = tcg_temp_new();
1930 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1931 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1932 tcg_temp_free(t1);
1933 tcg_temp_free(t0);
1934 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1935 if (unlikely(Rc(ctx->opcode) != 0))
1936 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1937 }
1938
1939 /* sraw & sraw. */
1940 static void gen_sraw(DisasContext *ctx)
1941 {
1942 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1943 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1944 if (unlikely(Rc(ctx->opcode) != 0))
1945 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1946 }
1947
1948 /* srawi & srawi. */
1949 static void gen_srawi(DisasContext *ctx)
1950 {
1951 int sh = SH(ctx->opcode);
1952 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1953 TCGv src = cpu_gpr[rS(ctx->opcode)];
1954 if (sh == 0) {
1955 tcg_gen_ext32s_tl(dst, src);
1956 tcg_gen_movi_tl(cpu_ca, 0);
1957 } else {
1958 TCGv t0;
1959 tcg_gen_ext32s_tl(dst, src);
1960 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1961 t0 = tcg_temp_new();
1962 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1963 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1964 tcg_temp_free(t0);
1965 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1966 tcg_gen_sari_tl(dst, dst, sh);
1967 }
1968 if (unlikely(Rc(ctx->opcode) != 0)) {
1969 gen_set_Rc0(ctx, dst);
1970 }
1971 }
1972
1973 /* srw & srw. */
1974 static void gen_srw(DisasContext *ctx)
1975 {
1976 TCGv t0, t1;
1977
1978 t0 = tcg_temp_new();
1979 /* AND rS with a mask that is 0 when rB >= 0x20 */
1980 #if defined(TARGET_PPC64)
1981 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1982 tcg_gen_sari_tl(t0, t0, 0x3f);
1983 #else
1984 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1985 tcg_gen_sari_tl(t0, t0, 0x1f);
1986 #endif
1987 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1988 tcg_gen_ext32u_tl(t0, t0);
1989 t1 = tcg_temp_new();
1990 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1991 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1992 tcg_temp_free(t1);
1993 tcg_temp_free(t0);
1994 if (unlikely(Rc(ctx->opcode) != 0))
1995 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1996 }
1997
1998 #if defined(TARGET_PPC64)
1999 /* sld & sld. */
2000 static void gen_sld(DisasContext *ctx)
2001 {
2002 TCGv t0, t1;
2003
2004 t0 = tcg_temp_new();
2005 /* AND rS with a mask that is 0 when rB >= 0x40 */
2006 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2007 tcg_gen_sari_tl(t0, t0, 0x3f);
2008 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2009 t1 = tcg_temp_new();
2010 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2011 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2012 tcg_temp_free(t1);
2013 tcg_temp_free(t0);
2014 if (unlikely(Rc(ctx->opcode) != 0))
2015 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2016 }
2017
2018 /* srad & srad. */
2019 static void gen_srad(DisasContext *ctx)
2020 {
2021 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2022 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2023 if (unlikely(Rc(ctx->opcode) != 0))
2024 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2025 }
2026 /* sradi & sradi. */
2027 static inline void gen_sradi(DisasContext *ctx, int n)
2028 {
2029 int sh = SH(ctx->opcode) + (n << 5);
2030 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2031 TCGv src = cpu_gpr[rS(ctx->opcode)];
2032 if (sh == 0) {
2033 tcg_gen_mov_tl(dst, src);
2034 tcg_gen_movi_tl(cpu_ca, 0);
2035 } else {
2036 TCGv t0;
2037 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2038 t0 = tcg_temp_new();
2039 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2040 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2041 tcg_temp_free(t0);
2042 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2043 tcg_gen_sari_tl(dst, src, sh);
2044 }
2045 if (unlikely(Rc(ctx->opcode) != 0)) {
2046 gen_set_Rc0(ctx, dst);
2047 }
2048 }
2049
2050 static void gen_sradi0(DisasContext *ctx)
2051 {
2052 gen_sradi(ctx, 0);
2053 }
2054
2055 static void gen_sradi1(DisasContext *ctx)
2056 {
2057 gen_sradi(ctx, 1);
2058 }
2059
2060 /* srd & srd. */
2061 static void gen_srd(DisasContext *ctx)
2062 {
2063 TCGv t0, t1;
2064
2065 t0 = tcg_temp_new();
2066 /* AND rS with a mask that is 0 when rB >= 0x40 */
2067 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2068 tcg_gen_sari_tl(t0, t0, 0x3f);
2069 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2070 t1 = tcg_temp_new();
2071 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2072 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2073 tcg_temp_free(t1);
2074 tcg_temp_free(t0);
2075 if (unlikely(Rc(ctx->opcode) != 0))
2076 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2077 }
2078 #endif
2079
2080 /*** Floating-Point arithmetic ***/
2081 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2082 static void gen_f##name(DisasContext *ctx) \
2083 { \
2084 if (unlikely(!ctx->fpu_enabled)) { \
2085 gen_exception(ctx, POWERPC_EXCP_FPU); \
2086 return; \
2087 } \
2088 /* NIP cannot be restored if the memory exception comes from an helper */ \
2089 gen_update_nip(ctx, ctx->nip - 4); \
2090 gen_reset_fpstatus(); \
2091 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2092 cpu_fpr[rA(ctx->opcode)], \
2093 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2094 if (isfloat) { \
2095 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2096 cpu_fpr[rD(ctx->opcode)]); \
2097 } \
2098 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2099 Rc(ctx->opcode) != 0); \
2100 }
2101
2102 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2103 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2104 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2105
2106 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2107 static void gen_f##name(DisasContext *ctx) \
2108 { \
2109 if (unlikely(!ctx->fpu_enabled)) { \
2110 gen_exception(ctx, POWERPC_EXCP_FPU); \
2111 return; \
2112 } \
2113 /* NIP cannot be restored if the memory exception comes from an helper */ \
2114 gen_update_nip(ctx, ctx->nip - 4); \
2115 gen_reset_fpstatus(); \
2116 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2117 cpu_fpr[rA(ctx->opcode)], \
2118 cpu_fpr[rB(ctx->opcode)]); \
2119 if (isfloat) { \
2120 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2121 cpu_fpr[rD(ctx->opcode)]); \
2122 } \
2123 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2124 set_fprf, Rc(ctx->opcode) != 0); \
2125 }
2126 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2127 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2128 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2129
2130 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2131 static void gen_f##name(DisasContext *ctx) \
2132 { \
2133 if (unlikely(!ctx->fpu_enabled)) { \
2134 gen_exception(ctx, POWERPC_EXCP_FPU); \
2135 return; \
2136 } \
2137 /* NIP cannot be restored if the memory exception comes from an helper */ \
2138 gen_update_nip(ctx, ctx->nip - 4); \
2139 gen_reset_fpstatus(); \
2140 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2141 cpu_fpr[rA(ctx->opcode)], \
2142 cpu_fpr[rC(ctx->opcode)]); \
2143 if (isfloat) { \
2144 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2145 cpu_fpr[rD(ctx->opcode)]); \
2146 } \
2147 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2148 set_fprf, Rc(ctx->opcode) != 0); \
2149 }
2150 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2151 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2152 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2153
2154 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2155 static void gen_f##name(DisasContext *ctx) \
2156 { \
2157 if (unlikely(!ctx->fpu_enabled)) { \
2158 gen_exception(ctx, POWERPC_EXCP_FPU); \
2159 return; \
2160 } \
2161 /* NIP cannot be restored if the memory exception comes from an helper */ \
2162 gen_update_nip(ctx, ctx->nip - 4); \
2163 gen_reset_fpstatus(); \
2164 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2165 cpu_fpr[rB(ctx->opcode)]); \
2166 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2167 set_fprf, Rc(ctx->opcode) != 0); \
2168 }
2169
2170 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2171 static void gen_f##name(DisasContext *ctx) \
2172 { \
2173 if (unlikely(!ctx->fpu_enabled)) { \
2174 gen_exception(ctx, POWERPC_EXCP_FPU); \
2175 return; \
2176 } \
2177 /* NIP cannot be restored if the memory exception comes from an helper */ \
2178 gen_update_nip(ctx, ctx->nip - 4); \
2179 gen_reset_fpstatus(); \
2180 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2181 cpu_fpr[rB(ctx->opcode)]); \
2182 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2183 set_fprf, Rc(ctx->opcode) != 0); \
2184 }
2185
2186 /* fadd - fadds */
2187 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2188 /* fdiv - fdivs */
2189 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2190 /* fmul - fmuls */
2191 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2192
2193 /* fre */
2194 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2195
2196 /* fres */
2197 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2198
2199 /* frsqrte */
2200 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2201
2202 /* frsqrtes */
2203 static void gen_frsqrtes(DisasContext *ctx)
2204 {
2205 if (unlikely(!ctx->fpu_enabled)) {
2206 gen_exception(ctx, POWERPC_EXCP_FPU);
2207 return;
2208 }
2209 /* NIP cannot be restored if the memory exception comes from an helper */
2210 gen_update_nip(ctx, ctx->nip - 4);
2211 gen_reset_fpstatus();
2212 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2213 cpu_fpr[rB(ctx->opcode)]);
2214 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2215 cpu_fpr[rD(ctx->opcode)]);
2216 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2217 }
2218
2219 /* fsel */
2220 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2221 /* fsub - fsubs */
2222 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2223 /* Optional: */
2224
2225 /* fsqrt */
2226 static void gen_fsqrt(DisasContext *ctx)
2227 {
2228 if (unlikely(!ctx->fpu_enabled)) {
2229 gen_exception(ctx, POWERPC_EXCP_FPU);
2230 return;
2231 }
2232 /* NIP cannot be restored if the memory exception comes from an helper */
2233 gen_update_nip(ctx, ctx->nip - 4);
2234 gen_reset_fpstatus();
2235 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2236 cpu_fpr[rB(ctx->opcode)]);
2237 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2238 }
2239
2240 static void gen_fsqrts(DisasContext *ctx)
2241 {
2242 if (unlikely(!ctx->fpu_enabled)) {
2243 gen_exception(ctx, POWERPC_EXCP_FPU);
2244 return;
2245 }
2246 /* NIP cannot be restored if the memory exception comes from an helper */
2247 gen_update_nip(ctx, ctx->nip - 4);
2248 gen_reset_fpstatus();
2249 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2250 cpu_fpr[rB(ctx->opcode)]);
2251 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2252 cpu_fpr[rD(ctx->opcode)]);
2253 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2254 }
2255
2256 /*** Floating-Point multiply-and-add ***/
2257 /* fmadd - fmadds */
2258 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2259 /* fmsub - fmsubs */
2260 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2261 /* fnmadd - fnmadds */
2262 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2263 /* fnmsub - fnmsubs */
2264 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2265
2266 /*** Floating-Point round & convert ***/
2267 /* fctiw */
2268 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2269 /* fctiwu */
2270 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2271 /* fctiwz */
2272 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2273 /* fctiwuz */
2274 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2275 /* frsp */
2276 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2277 /* fcfid */
2278 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2279 /* fcfids */
2280 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2281 /* fcfidu */
2282 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2283 /* fcfidus */
2284 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2285 /* fctid */
2286 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2287 /* fctidu */
2288 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2289 /* fctidz */
2290 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2291 /* fctidu */
2292 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2293
2294 /* frin */
2295 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2296 /* friz */
2297 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2298 /* frip */
2299 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2300 /* frim */
2301 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2302
2303 static void gen_ftdiv(DisasContext *ctx)
2304 {
2305 if (unlikely(!ctx->fpu_enabled)) {
2306 gen_exception(ctx, POWERPC_EXCP_FPU);
2307 return;
2308 }
2309 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2310 cpu_fpr[rB(ctx->opcode)]);
2311 }
2312
2313 static void gen_ftsqrt(DisasContext *ctx)
2314 {
2315 if (unlikely(!ctx->fpu_enabled)) {
2316 gen_exception(ctx, POWERPC_EXCP_FPU);
2317 return;
2318 }
2319 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2320 }
2321
2322
2323
2324 /*** Floating-Point compare ***/
2325
2326 /* fcmpo */
2327 static void gen_fcmpo(DisasContext *ctx)
2328 {
2329 TCGv_i32 crf;
2330 if (unlikely(!ctx->fpu_enabled)) {
2331 gen_exception(ctx, POWERPC_EXCP_FPU);
2332 return;
2333 }
2334 /* NIP cannot be restored if the memory exception comes from an helper */
2335 gen_update_nip(ctx, ctx->nip - 4);
2336 gen_reset_fpstatus();
2337 crf = tcg_const_i32(crfD(ctx->opcode));
2338 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2339 cpu_fpr[rB(ctx->opcode)], crf);
2340 tcg_temp_free_i32(crf);
2341 gen_helper_float_check_status(cpu_env);
2342 }
2343
2344 /* fcmpu */
2345 static void gen_fcmpu(DisasContext *ctx)
2346 {
2347 TCGv_i32 crf;
2348 if (unlikely(!ctx->fpu_enabled)) {
2349 gen_exception(ctx, POWERPC_EXCP_FPU);
2350 return;
2351 }
2352 /* NIP cannot be restored if the memory exception comes from an helper */
2353 gen_update_nip(ctx, ctx->nip - 4);
2354 gen_reset_fpstatus();
2355 crf = tcg_const_i32(crfD(ctx->opcode));
2356 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2357 cpu_fpr[rB(ctx->opcode)], crf);
2358 tcg_temp_free_i32(crf);
2359 gen_helper_float_check_status(cpu_env);
2360 }
2361
2362 /*** Floating-point move ***/
2363 /* fabs */
2364 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2365 static void gen_fabs(DisasContext *ctx)
2366 {
2367 if (unlikely(!ctx->fpu_enabled)) {
2368 gen_exception(ctx, POWERPC_EXCP_FPU);
2369 return;
2370 }
2371 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2372 ~(1ULL << 63));
2373 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2374 }
2375
2376 /* fmr - fmr. */
2377 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2378 static void gen_fmr(DisasContext *ctx)
2379 {
2380 if (unlikely(!ctx->fpu_enabled)) {
2381 gen_exception(ctx, POWERPC_EXCP_FPU);
2382 return;
2383 }
2384 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2385 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2386 }
2387
2388 /* fnabs */
2389 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2390 static void gen_fnabs(DisasContext *ctx)
2391 {
2392 if (unlikely(!ctx->fpu_enabled)) {
2393 gen_exception(ctx, POWERPC_EXCP_FPU);
2394 return;
2395 }
2396 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2397 1ULL << 63);
2398 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2399 }
2400
2401 /* fneg */
2402 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2403 static void gen_fneg(DisasContext *ctx)
2404 {
2405 if (unlikely(!ctx->fpu_enabled)) {
2406 gen_exception(ctx, POWERPC_EXCP_FPU);
2407 return;
2408 }
2409 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2410 1ULL << 63);
2411 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2412 }
2413
2414 /* fcpsgn: PowerPC 2.05 specification */
2415 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2416 static void gen_fcpsgn(DisasContext *ctx)
2417 {
2418 if (unlikely(!ctx->fpu_enabled)) {
2419 gen_exception(ctx, POWERPC_EXCP_FPU);
2420 return;
2421 }
2422 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2423 cpu_fpr[rB(ctx->opcode)], 0, 63);
2424 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2425 }
2426
2427 static void gen_fmrgew(DisasContext *ctx)
2428 {
2429 TCGv_i64 b0;
2430 if (unlikely(!ctx->fpu_enabled)) {
2431 gen_exception(ctx, POWERPC_EXCP_FPU);
2432 return;
2433 }
2434 b0 = tcg_temp_new_i64();
2435 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2436 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2437 b0, 0, 32);
2438 tcg_temp_free_i64(b0);
2439 }
2440
2441 static void gen_fmrgow(DisasContext *ctx)
2442 {
2443 if (unlikely(!ctx->fpu_enabled)) {
2444 gen_exception(ctx, POWERPC_EXCP_FPU);
2445 return;
2446 }
2447 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2448 cpu_fpr[rB(ctx->opcode)],
2449 cpu_fpr[rA(ctx->opcode)],
2450 32, 32);
2451 }
2452
2453 /*** Floating-Point status & ctrl register ***/
2454
2455 /* mcrfs */
2456 static void gen_mcrfs(DisasContext *ctx)
2457 {
2458 TCGv tmp = tcg_temp_new();
2459 int bfa;
2460
2461 if (unlikely(!ctx->fpu_enabled)) {
2462 gen_exception(ctx, POWERPC_EXCP_FPU);
2463 return;
2464 }
2465 bfa = 4 * (7 - crfS(ctx->opcode));
2466 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2467 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2468 tcg_temp_free(tmp);
2469 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2470 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2471 }
2472
2473 /* mffs */
2474 static void gen_mffs(DisasContext *ctx)
2475 {
2476 if (unlikely(!ctx->fpu_enabled)) {
2477 gen_exception(ctx, POWERPC_EXCP_FPU);
2478 return;
2479 }
2480 gen_reset_fpstatus();
2481 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2482 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2483 }
2484
2485 /* mtfsb0 */
2486 static void gen_mtfsb0(DisasContext *ctx)
2487 {
2488 uint8_t crb;
2489
2490 if (unlikely(!ctx->fpu_enabled)) {
2491 gen_exception(ctx, POWERPC_EXCP_FPU);
2492 return;
2493 }
2494 crb = 31 - crbD(ctx->opcode);
2495 gen_reset_fpstatus();
2496 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2497 TCGv_i32 t0;
2498 /* NIP cannot be restored if the memory exception comes from an helper */
2499 gen_update_nip(ctx, ctx->nip - 4);
2500 t0 = tcg_const_i32(crb);
2501 gen_helper_fpscr_clrbit(cpu_env, t0);
2502 tcg_temp_free_i32(t0);
2503 }
2504 if (unlikely(Rc(ctx->opcode) != 0)) {
2505 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2506 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2507 }
2508 }
2509
2510 /* mtfsb1 */
2511 static void gen_mtfsb1(DisasContext *ctx)
2512 {
2513 uint8_t crb;
2514
2515 if (unlikely(!ctx->fpu_enabled)) {
2516 gen_exception(ctx, POWERPC_EXCP_FPU);
2517 return;
2518 }
2519 crb = 31 - crbD(ctx->opcode);
2520 gen_reset_fpstatus();
2521 /* XXX: we pretend we can only do IEEE floating-point computations */
2522 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2523 TCGv_i32 t0;
2524 /* NIP cannot be restored if the memory exception comes from an helper */
2525 gen_update_nip(ctx, ctx->nip - 4);
2526 t0 = tcg_const_i32(crb);
2527 gen_helper_fpscr_setbit(cpu_env, t0);
2528 tcg_temp_free_i32(t0);
2529 }
2530 if (unlikely(Rc(ctx->opcode) != 0)) {
2531 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2532 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2533 }
2534 /* We can raise a differed exception */
2535 gen_helper_float_check_status(cpu_env);
2536 }
2537
2538 /* mtfsf */
2539 static void gen_mtfsf(DisasContext *ctx)
2540 {
2541 TCGv_i32 t0;
2542 int flm, l, w;
2543
2544 if (unlikely(!ctx->fpu_enabled)) {
2545 gen_exception(ctx, POWERPC_EXCP_FPU);
2546 return;
2547 }
2548 flm = FPFLM(ctx->opcode);
2549 l = FPL(ctx->opcode);
2550 w = FPW(ctx->opcode);
2551 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2552 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2553 return;
2554 }
2555 /* NIP cannot be restored if the memory exception comes from an helper */
2556 gen_update_nip(ctx, ctx->nip - 4);
2557 gen_reset_fpstatus();
2558 if (l) {
2559 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2560 } else {
2561 t0 = tcg_const_i32(flm << (w * 8));
2562 }
2563 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2564 tcg_temp_free_i32(t0);
2565 if (unlikely(Rc(ctx->opcode) != 0)) {
2566 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2567 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2568 }
2569 /* We can raise a differed exception */
2570 gen_helper_float_check_status(cpu_env);
2571 }
2572
2573 /* mtfsfi */
2574 static void gen_mtfsfi(DisasContext *ctx)
2575 {
2576 int bf, sh, w;
2577 TCGv_i64 t0;
2578 TCGv_i32 t1;
2579
2580 if (unlikely(!ctx->fpu_enabled)) {
2581 gen_exception(ctx, POWERPC_EXCP_FPU);
2582 return;
2583 }
2584 w = FPW(ctx->opcode);
2585 bf = FPBF(ctx->opcode);
2586 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2587 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2588 return;
2589 }
2590 sh = (8 * w) + 7 - bf;
2591 /* NIP cannot be restored if the memory exception comes from an helper */
2592 gen_update_nip(ctx, ctx->nip - 4);
2593 gen_reset_fpstatus();
2594 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2595 t1 = tcg_const_i32(1 << sh);
2596 gen_helper_store_fpscr(cpu_env, t0, t1);
2597 tcg_temp_free_i64(t0);
2598 tcg_temp_free_i32(t1);
2599 if (unlikely(Rc(ctx->opcode) != 0)) {
2600 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2601 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2602 }
2603 /* We can raise a differed exception */
2604 gen_helper_float_check_status(cpu_env);
2605 }
2606
2607 /*** Addressing modes ***/
2608 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2609 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2610 target_long maskl)
2611 {
2612 target_long simm = SIMM(ctx->opcode);
2613
2614 simm &= ~maskl;
2615 if (rA(ctx->opcode) == 0) {
2616 if (NARROW_MODE(ctx)) {
2617 simm = (uint32_t)simm;
2618 }
2619 tcg_gen_movi_tl(EA, simm);
2620 } else if (likely(simm != 0)) {
2621 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2622 if (NARROW_MODE(ctx)) {
2623 tcg_gen_ext32u_tl(EA, EA);
2624 }
2625 } else {
2626 if (NARROW_MODE(ctx)) {
2627 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2628 } else {
2629 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2630 }
2631 }
2632 }
2633
2634 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2635 {
2636 if (rA(ctx->opcode) == 0) {
2637 if (NARROW_MODE(ctx)) {
2638 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2639 } else {
2640 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2641 }
2642 } else {
2643 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2644 if (NARROW_MODE(ctx)) {
2645 tcg_gen_ext32u_tl(EA, EA);
2646 }
2647 }
2648 }
2649
2650 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2651 {
2652 if (rA(ctx->opcode) == 0) {
2653 tcg_gen_movi_tl(EA, 0);
2654 } else if (NARROW_MODE(ctx)) {
2655 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2656 } else {
2657 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2658 }
2659 }
2660
2661 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2662 target_long val)
2663 {
2664 tcg_gen_addi_tl(ret, arg1, val);
2665 if (NARROW_MODE(ctx)) {
2666 tcg_gen_ext32u_tl(ret, ret);
2667 }
2668 }
2669
2670 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2671 {
2672 int l1 = gen_new_label();
2673 TCGv t0 = tcg_temp_new();
2674 TCGv_i32 t1, t2;
2675 /* NIP cannot be restored if the memory exception comes from an helper */
2676 gen_update_nip(ctx, ctx->nip - 4);
2677 tcg_gen_andi_tl(t0, EA, mask);
2678 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2679 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2680 t2 = tcg_const_i32(0);
2681 gen_helper_raise_exception_err(cpu_env, t1, t2);
2682 tcg_temp_free_i32(t1);
2683 tcg_temp_free_i32(t2);
2684 gen_set_label(l1);
2685 tcg_temp_free(t0);
2686 }
2687
2688 /*** Integer load ***/
2689 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2690 {
2691 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2692 }
2693
2694 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2695 {
2696 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2697 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2698 }
2699
2700 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2701 {
2702 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2703 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2704 }
2705
2706 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2707 {
2708 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2709 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2710 }
2711
2712 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2713 {
2714 TCGv tmp = tcg_temp_new();
2715 gen_qemu_ld32u(ctx, tmp, addr);
2716 tcg_gen_extu_tl_i64(val, tmp);
2717 tcg_temp_free(tmp);
2718 }
2719
2720 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2721 {
2722 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2723 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2724 }
2725
2726 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2727 {
2728 TCGv tmp = tcg_temp_new();
2729 gen_qemu_ld32s(ctx, tmp, addr);
2730 tcg_gen_ext_tl_i64(val, tmp);
2731 tcg_temp_free(tmp);
2732 }
2733
2734 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2735 {
2736 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2737 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2738 }
2739
2740 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2741 {
2742 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2743 }
2744
2745 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2746 {
2747 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2748 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2749 }
2750
2751 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2752 {
2753 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2754 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2755 }
2756
2757 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2758 {
2759 TCGv tmp = tcg_temp_new();
2760 tcg_gen_trunc_i64_tl(tmp, val);
2761 gen_qemu_st32(ctx, tmp, addr);
2762 tcg_temp_free(tmp);
2763 }
2764
2765 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2766 {
2767 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2768 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2769 }
2770
2771 #define GEN_LD(name, ldop, opc, type) \
2772 static void glue(gen_, name)(DisasContext *ctx) \
2773 { \
2774 TCGv EA; \
2775 gen_set_access_type(ctx, ACCESS_INT); \
2776 EA = tcg_temp_new(); \
2777 gen_addr_imm_index(ctx, EA, 0); \
2778 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2779 tcg_temp_free(EA); \
2780 }
2781
2782 #define GEN_LDU(name, ldop, opc, type) \
2783 static void glue(gen_, name##u)(DisasContext *ctx) \
2784 { \
2785 TCGv EA; \
2786 if (unlikely(rA(ctx->opcode) == 0 || \
2787 rA(ctx->opcode) == rD(ctx->opcode))) { \
2788 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2789 return; \
2790 } \
2791 gen_set_access_type(ctx, ACCESS_INT); \
2792 EA = tcg_temp_new(); \
2793 if (type == PPC_64B) \
2794 gen_addr_imm_index(ctx, EA, 0x03); \
2795 else \
2796 gen_addr_imm_index(ctx, EA, 0); \
2797 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2798 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2799 tcg_temp_free(EA); \
2800 }
2801
2802 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2803 static void glue(gen_, name##ux)(DisasContext *ctx) \
2804 { \
2805 TCGv EA; \
2806 if (unlikely(rA(ctx->opcode) == 0 || \
2807 rA(ctx->opcode) == rD(ctx->opcode))) { \
2808 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2809 return; \
2810 } \
2811 gen_set_access_type(ctx, ACCESS_INT); \
2812 EA = tcg_temp_new(); \
2813 gen_addr_reg_index(ctx, EA); \
2814 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2815 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2816 tcg_temp_free(EA); \
2817 }
2818
2819 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2820 static void glue(gen_, name##x)(DisasContext *ctx) \
2821 { \
2822 TCGv EA; \
2823 gen_set_access_type(ctx, ACCESS_INT); \
2824 EA = tcg_temp_new(); \
2825 gen_addr_reg_index(ctx, EA); \
2826 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2827 tcg_temp_free(EA); \
2828 }
2829 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2830 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2831
2832 #define GEN_LDS(name, ldop, op, type) \
2833 GEN_LD(name, ldop, op | 0x20, type); \
2834 GEN_LDU(name, ldop, op | 0x21, type); \
2835 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2836 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2837
2838 /* lbz lbzu lbzux lbzx */
2839 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2840 /* lha lhau lhaux lhax */
2841 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2842 /* lhz lhzu lhzux lhzx */
2843 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2844 /* lwz lwzu lwzux lwzx */
2845 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2846 #if defined(TARGET_PPC64)
2847 /* lwaux */
2848 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2849 /* lwax */
2850 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2851 /* ldux */
2852 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2853 /* ldx */
2854 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2855
2856 static void gen_ld(DisasContext *ctx)
2857 {
2858 TCGv EA;
2859 if (Rc(ctx->opcode)) {
2860 if (unlikely(rA(ctx->opcode) == 0 ||
2861 rA(ctx->opcode) == rD(ctx->opcode))) {
2862 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2863 return;
2864 }
2865 }
2866 gen_set_access_type(ctx, ACCESS_INT);
2867 EA = tcg_temp_new();
2868 gen_addr_imm_index(ctx, EA, 0x03);
2869 if (ctx->opcode & 0x02) {
2870 /* lwa (lwau is undefined) */
2871 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2872 } else {
2873 /* ld - ldu */
2874 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2875 }
2876 if (Rc(ctx->opcode))
2877 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2878 tcg_temp_free(EA);
2879 }
2880
2881 /* lq */
2882 static void gen_lq(DisasContext *ctx)
2883 {
2884 int ra, rd;
2885 TCGv EA;
2886
2887 /* lq is a legal user mode instruction starting in ISA 2.07 */
2888 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2889 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2890
2891 if (!legal_in_user_mode && ctx->pr) {
2892 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2893 return;
2894 }
2895
2896 if (!le_is_supported && ctx->le_mode) {
2897 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2898 return;
2899 }
2900
2901 ra = rA(ctx->opcode);
2902 rd = rD(ctx->opcode);
2903 if (unlikely((rd & 1) || rd == ra)) {
2904 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2905 return;
2906 }
2907
2908 gen_set_access_type(ctx, ACCESS_INT);
2909 EA = tcg_temp_new();
2910 gen_addr_imm_index(ctx, EA, 0x0F);
2911
2912 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2913 64-bit byteswap already. */
2914 if (unlikely(ctx->le_mode)) {
2915 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2916 gen_addr_add(ctx, EA, EA, 8);
2917 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2918 } else {
2919 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2920 gen_addr_add(ctx, EA, EA, 8);
2921 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2922 }
2923 tcg_temp_free(EA);
2924 }
2925 #endif
2926
2927 /*** Integer store ***/
2928 #define GEN_ST(name, stop, opc, type) \
2929 static void glue(gen_, name)(DisasContext *ctx) \
2930 { \
2931 TCGv EA; \
2932 gen_set_access_type(ctx, ACCESS_INT); \
2933 EA = tcg_temp_new(); \
2934 gen_addr_imm_index(ctx, EA, 0); \
2935 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2936 tcg_temp_free(EA); \
2937 }
2938
2939 #define GEN_STU(name, stop, opc, type) \
2940 static void glue(gen_, stop##u)(DisasContext *ctx) \
2941 { \
2942 TCGv EA; \
2943 if (unlikely(rA(ctx->opcode) == 0)) { \
2944 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2945 return; \
2946 } \
2947 gen_set_access_type(ctx, ACCESS_INT); \
2948 EA = tcg_temp_new(); \
2949 if (type == PPC_64B) \
2950 gen_addr_imm_index(ctx, EA, 0x03); \
2951 else \
2952 gen_addr_imm_index(ctx, EA, 0); \
2953 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2954 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2955 tcg_temp_free(EA); \
2956 }
2957
2958 #define GEN_STUX(name, stop, opc2, opc3, type) \
2959 static void glue(gen_, name##ux)(DisasContext *ctx) \
2960 { \
2961 TCGv EA; \
2962 if (unlikely(rA(ctx->opcode) == 0)) { \
2963 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2964 return; \
2965 } \
2966 gen_set_access_type(ctx, ACCESS_INT); \
2967 EA = tcg_temp_new(); \
2968 gen_addr_reg_index(ctx, EA); \
2969 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2970 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2971 tcg_temp_free(EA); \
2972 }
2973
2974 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2975 static void glue(gen_, name##x)(DisasContext *ctx) \
2976 { \
2977 TCGv EA; \
2978 gen_set_access_type(ctx, ACCESS_INT); \
2979 EA = tcg_temp_new(); \
2980 gen_addr_reg_index(ctx, EA); \
2981 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2982 tcg_temp_free(EA); \
2983 }
2984 #define GEN_STX(name, stop, opc2, opc3, type) \
2985 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2986
2987 #define GEN_STS(name, stop, op, type) \
2988 GEN_ST(name, stop, op | 0x20, type); \
2989 GEN_STU(name, stop, op | 0x21, type); \
2990 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2991 GEN_STX(name, stop, 0x17, op | 0x00, type)
2992
2993 /* stb stbu stbux stbx */
2994 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2995 /* sth sthu sthux sthx */
2996 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2997 /* stw stwu stwux stwx */
2998 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2999 #if defined(TARGET_PPC64)
3000 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3001 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3002
3003 static void gen_std(DisasContext *ctx)
3004 {
3005 int rs;
3006 TCGv EA;
3007
3008 rs = rS(ctx->opcode);
3009 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3010
3011 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3012 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3013
3014 if (!legal_in_user_mode && ctx->pr) {
3015 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3016 return;
3017 }
3018
3019 if (!le_is_supported && ctx->le_mode) {
3020 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3021 return;
3022 }
3023
3024 if (unlikely(rs & 1)) {
3025 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3026 return;
3027 }
3028 gen_set_access_type(ctx, ACCESS_INT);
3029 EA = tcg_temp_new();
3030 gen_addr_imm_index(ctx, EA, 0x03);
3031
3032 /* We only need to swap high and low halves. gen_qemu_st64 does
3033 necessary 64-bit byteswap already. */
3034 if (unlikely(ctx->le_mode)) {
3035 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3036 gen_addr_add(ctx, EA, EA, 8);
3037 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3038 } else {
3039 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3040 gen_addr_add(ctx, EA, EA, 8);
3041 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3042 }
3043 tcg_temp_free(EA);
3044 } else {
3045 /* std / stdu*/
3046 if (Rc(ctx->opcode)) {
3047 if (unlikely(rA(ctx->opcode) == 0)) {
3048 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3049 return;
3050 }
3051 }
3052 gen_set_access_type(ctx, ACCESS_INT);
3053 EA = tcg_temp_new();
3054 gen_addr_imm_index(ctx, EA, 0x03);
3055 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3056 if (Rc(ctx->opcode))
3057 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3058 tcg_temp_free(EA);
3059 }
3060 }
3061 #endif
3062 /*** Integer load and store with byte reverse ***/
3063
3064 /* lhbrx */
3065 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3066 {
3067 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3068 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3069 }
3070 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3071
3072 /* lwbrx */
3073 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3074 {
3075 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3076 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3077 }
3078 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3079
3080 #if defined(TARGET_PPC64)
3081 /* ldbrx */
3082 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3083 {
3084 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3085 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3086 }
3087 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3088 #endif /* TARGET_PPC64 */
3089
3090 /* sthbrx */
3091 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3092 {
3093 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3094 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3095 }
3096 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3097
3098 /* stwbrx */
3099 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3100 {
3101 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3102 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3103 }
3104 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3105
3106 #if defined(TARGET_PPC64)
3107 /* stdbrx */
3108 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3109 {
3110 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3111 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3112 }
3113 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3114 #endif /* TARGET_PPC64 */
3115
3116 /*** Integer load and store multiple ***/
3117
3118 /* lmw */
3119 static void gen_lmw(DisasContext *ctx)
3120 {
3121 TCGv t0;
3122 TCGv_i32 t1;
3123 gen_set_access_type(ctx, ACCESS_INT);
3124 /* NIP cannot be restored if the memory exception comes from an helper */
3125 gen_update_nip(ctx, ctx->nip - 4);
3126 t0 = tcg_temp_new();
3127 t1 = tcg_const_i32(rD(ctx->opcode));
3128 gen_addr_imm_index(ctx, t0, 0);
3129 gen_helper_lmw(cpu_env, t0, t1);
3130 tcg_temp_free(t0);
3131 tcg_temp_free_i32(t1);
3132 }
3133
3134 /* stmw */
3135 static void gen_stmw(DisasContext *ctx)
3136 {
3137 TCGv t0;
3138 TCGv_i32 t1;
3139 gen_set_access_type(ctx, ACCESS_INT);
3140 /* NIP cannot be restored if the memory exception comes from an helper */
3141 gen_update_nip(ctx, ctx->nip - 4);
3142 t0 = tcg_temp_new();
3143 t1 = tcg_const_i32(rS(ctx->opcode));
3144 gen_addr_imm_index(ctx, t0, 0);
3145 gen_helper_stmw(cpu_env, t0, t1);
3146 tcg_temp_free(t0);
3147 tcg_temp_free_i32(t1);
3148 }
3149
3150 /*** Integer load and store strings ***/
3151
3152 /* lswi */
3153 /* PowerPC32 specification says we must generate an exception if
3154 * rA is in the range of registers to be loaded.
3155 * In an other hand, IBM says this is valid, but rA won't be loaded.
3156 * For now, I'll follow the spec...
3157 */
3158 static void gen_lswi(DisasContext *ctx)
3159 {
3160 TCGv t0;
3161 TCGv_i32 t1, t2;
3162 int nb = NB(ctx->opcode);
3163 int start = rD(ctx->opcode);
3164 int ra = rA(ctx->opcode);
3165 int nr;
3166
3167 if (nb == 0)
3168 nb = 32;
3169 nr = nb / 4;
3170 if (unlikely(((start + nr) > 32 &&
3171 start <= ra && (start + nr - 32) > ra) ||
3172 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3173 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3174 return;
3175 }
3176 gen_set_access_type(ctx, ACCESS_INT);
3177 /* NIP cannot be restored if the memory exception comes from an helper */
3178 gen_update_nip(ctx, ctx->nip - 4);
3179 t0 = tcg_temp_new();
3180 gen_addr_register(ctx, t0);
3181 t1 = tcg_const_i32(nb);
3182 t2 = tcg_const_i32(start);
3183 gen_helper_lsw(cpu_env, t0, t1, t2);
3184 tcg_temp_free(t0);
3185 tcg_temp_free_i32(t1);
3186 tcg_temp_free_i32(t2);
3187 }
3188
3189 /* lswx */
3190 static void gen_lswx(DisasContext *ctx)
3191 {
3192 TCGv t0;
3193 TCGv_i32 t1, t2, t3;
3194 gen_set_access_type(ctx, ACCESS_INT);
3195 /* NIP cannot be restored if the memory exception comes from an helper */
3196 gen_update_nip(ctx, ctx->nip - 4);
3197 t0 = tcg_temp_new();
3198 gen_addr_reg_index(ctx, t0);
3199 t1 = tcg_const_i32(rD(ctx->opcode));
3200 t2 = tcg_const_i32(rA(ctx->opcode));
3201 t3 = tcg_const_i32(rB(ctx->opcode));
3202 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3203 tcg_temp_free(t0);
3204 tcg_temp_free_i32(t1);
3205 tcg_temp_free_i32(t2);
3206 tcg_temp_free_i32(t3);
3207 }
3208
3209 /* stswi */
3210 static void gen_stswi(DisasContext *ctx)
3211 {
3212 TCGv t0;
3213 TCGv_i32 t1, t2;
3214 int nb = NB(ctx->opcode);
3215 gen_set_access_type(ctx, ACCESS_INT);
3216 /* NIP cannot be restored if the memory exception comes from an helper */
3217 gen_update_nip(ctx, ctx->nip - 4);
3218 t0 = tcg_temp_new();
3219 gen_addr_register(ctx, t0);
3220 if (nb == 0)
3221 nb = 32;
3222 t1 = tcg_const_i32(nb);
3223 t2 = tcg_const_i32(rS(ctx->opcode));
3224 gen_helper_stsw(cpu_env, t0, t1, t2);
3225 tcg_temp_free(t0);
3226 tcg_temp_free_i32(t1);
3227 tcg_temp_free_i32(t2);
3228 }
3229
3230 /* stswx */
3231 static void gen_stswx(DisasContext *ctx)
3232 {
3233 TCGv t0;
3234 TCGv_i32 t1, t2;
3235 gen_set_access_type(ctx, ACCESS_INT);
3236 /* NIP cannot be restored if the memory exception comes from an helper */
3237 gen_update_nip(ctx, ctx->nip - 4);
3238 t0 = tcg_temp_new();
3239 gen_addr_reg_index(ctx, t0);
3240 t1 = tcg_temp_new_i32();
3241 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3242 tcg_gen_andi_i32(t1, t1, 0x7F);
3243 t2 = tcg_const_i32(rS(ctx->opcode));
3244 gen_helper_stsw(cpu_env, t0, t1, t2);
3245 tcg_temp_free(t0);
3246 tcg_temp_free_i32(t1);
3247 tcg_temp_free_i32(t2);
3248 }
3249
3250 /*** Memory synchronisation ***/
3251 /* eieio */
3252 static void gen_eieio(DisasContext *ctx)
3253 {
3254 }
3255
3256 /* isync */
3257 static void gen_isync(DisasContext *ctx)
3258 {
3259 gen_stop_exception(ctx);
3260 }
3261
3262 #define LARX(name, len, loadop) \
3263 static void gen_##name(DisasContext *ctx) \
3264 { \
3265 TCGv t0; \
3266 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3267 gen_set_access_type(ctx, ACCESS_RES); \
3268 t0 = tcg_temp_local_new(); \
3269 gen_addr_reg_index(ctx, t0); \
3270 if ((len) > 1) { \
3271 gen_check_align(ctx, t0, (len)-1); \
3272 } \
3273 gen_qemu_##loadop(ctx, gpr, t0); \
3274 tcg_gen_mov_tl(cpu_reserve, t0); \
3275 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3276 tcg_temp_free(t0); \
3277 }
3278
3279 /* lwarx */
3280 LARX(lbarx, 1, ld8u);
3281 LARX(lharx, 2, ld16u);
3282 LARX(lwarx, 4, ld32u);
3283
3284
3285 #if defined(CONFIG_USER_ONLY)
3286 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3287 int reg, int size)
3288 {
3289 TCGv t0 = tcg_temp_new();
3290 uint32_t save_exception = ctx->exception;
3291
3292 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3293 tcg_gen_movi_tl(t0, (size << 5) | reg);
3294 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3295 tcg_temp_free(t0);
3296 gen_update_nip(ctx, ctx->nip-4);
3297 ctx->exception = POWERPC_EXCP_BRANCH;
3298 gen_exception(ctx, POWERPC_EXCP_STCX);
3299 ctx->exception = save_exception;
3300 }
3301 #else
3302 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3303 int reg, int size)
3304 {
3305 int l1;
3306
3307 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3308 l1 = gen_new_label();
3309 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3310 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3311 #if defined(TARGET_PPC64)
3312 if (size == 8) {
3313 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3314 } else
3315 #endif
3316 if (size == 4) {
3317 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3318 } else if (size == 2) {
3319 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3320 #if defined(TARGET_PPC64)
3321 } else if (size == 16) {
3322 TCGv gpr1, gpr2 , EA8;
3323 if (unlikely(ctx->le_mode)) {
3324 gpr1 = cpu_gpr[reg+1];
3325 gpr2 = cpu_gpr[reg];
3326 } else {
3327 gpr1 = cpu_gpr[reg];
3328 gpr2 = cpu_gpr[reg+1];
3329 }
3330 gen_qemu_st64(ctx, gpr1, EA);
3331 EA8 = tcg_temp_local_new();
3332 gen_addr_add(ctx, EA8, EA, 8);
3333 gen_qemu_st64(ctx, gpr2, EA8);
3334 tcg_temp_free(EA8);
3335 #endif
3336 } else {
3337 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3338 }
3339 gen_set_label(l1);
3340 tcg_gen_movi_tl(cpu_reserve, -1);
3341 }
3342 #endif
3343
3344 #define STCX(name, len) \
3345 static void gen_##name(DisasContext *ctx) \
3346 { \
3347 TCGv t0; \
3348 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3349 gen_inval_exception(ctx, \
3350 POWERPC_EXCP_INVAL_INVAL); \
3351 return; \
3352 } \
3353 gen_set_access_type(ctx, ACCESS_RES); \
3354 t0 = tcg_temp_local_new(); \
3355 gen_addr_reg_index(ctx, t0); \
3356 if (len > 1) { \
3357 gen_check_align(ctx, t0, (len)-1); \
3358 } \
3359 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3360 tcg_temp_free(t0); \
3361 }
3362
3363 STCX(stbcx_, 1);
3364 STCX(sthcx_, 2);
3365 STCX(stwcx_, 4);
3366
3367 #if defined(TARGET_PPC64)
3368 /* ldarx */
3369 LARX(ldarx, 8, ld64);
3370
3371 /* lqarx */
3372 static void gen_lqarx(DisasContext *ctx)
3373 {
3374 TCGv EA;
3375 int rd = rD(ctx->opcode);
3376 TCGv gpr1, gpr2;
3377
3378 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3379 (rd == rB(ctx->opcode)))) {
3380 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3381 return;
3382 }
3383
3384 gen_set_access_type(ctx, ACCESS_RES);
3385 EA = tcg_temp_local_new();
3386 gen_addr_reg_index(ctx, EA);
3387 gen_check_align(ctx, EA, 15);
3388 if (unlikely(ctx->le_mode)) {
3389 gpr1 = cpu_gpr[rd+1];
3390 gpr2 = cpu_gpr[rd];
3391 } else {
3392 gpr1 = cpu_gpr[rd];
3393 gpr2 = cpu_gpr[rd+1];
3394 }
3395 gen_qemu_ld64(ctx, gpr1, EA);
3396 tcg_gen_mov_tl(cpu_reserve, EA);
3397
3398 gen_addr_add(ctx, EA, EA, 8);
3399 gen_qemu_ld64(ctx, gpr2, EA);
3400
3401 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3402 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3403
3404 tcg_temp_free(EA);
3405 }
3406
3407 /* stdcx. */
3408 STCX(stdcx_, 8);
3409 STCX(stqcx_, 16);
3410 #endif /* defined(TARGET_PPC64) */
3411
3412 /* sync */
3413 static void gen_sync(DisasContext *ctx)
3414 {
3415 }
3416
3417 /* wait */
3418 static void gen_wait(DisasContext *ctx)
3419 {
3420 TCGv_i32 t0 = tcg_temp_new_i32();
3421 tcg_gen_st_i32(t0, cpu_env,
3422 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3423 tcg_temp_free_i32(t0);
3424 /* Stop translation, as the CPU is supposed to sleep from now */
3425 gen_exception_err(ctx, EXCP_HLT, 1);
3426 }
3427
3428 /*** Floating-point load ***/
3429 #define GEN_LDF(name, ldop, opc, type) \
3430 static void glue(gen_, name)(DisasContext *ctx) \
3431 { \
3432 TCGv EA; \
3433 if (unlikely(!ctx->fpu_enabled)) { \
3434 gen_exception(ctx, POWERPC_EXCP_FPU); \
3435 return; \
3436 } \
3437 gen_set_access_type(ctx, ACCESS_FLOAT); \
3438 EA = tcg_temp_new(); \
3439 gen_addr_imm_index(ctx, EA, 0); \
3440 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3441 tcg_temp_free(EA); \
3442 }
3443
3444 #define GEN_LDUF(name, ldop, opc, type) \
3445 static void glue(gen_, name##u)(DisasContext *ctx) \
3446 { \
3447 TCGv EA; \
3448 if (unlikely(!ctx->fpu_enabled)) { \
3449 gen_exception(ctx, POWERPC_EXCP_FPU); \
3450 return; \
3451 } \
3452 if (unlikely(rA(ctx->opcode) == 0)) { \
3453 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3454 return; \
3455 } \
3456 gen_set_access_type(ctx, ACCESS_FLOAT); \
3457 EA = tcg_temp_new(); \
3458 gen_addr_imm_index(ctx, EA, 0); \
3459 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3460 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3461 tcg_temp_free(EA); \
3462 }
3463
3464 #define GEN_LDUXF(name, ldop, opc, type) \
3465 static void glue(gen_, name##ux)(DisasContext *ctx) \
3466 { \
3467 TCGv EA; \
3468 if (unlikely(!ctx->fpu_enabled)) { \
3469 gen_exception(ctx, POWERPC_EXCP_FPU); \
3470 return; \
3471 } \
3472 if (unlikely(rA(ctx->opcode) == 0)) { \
3473 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3474 return; \
3475 } \
3476 gen_set_access_type(ctx, ACCESS_FLOAT); \
3477 EA = tcg_temp_new(); \
3478 gen_addr_reg_index(ctx, EA); \
3479 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3480 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3481 tcg_temp_free(EA); \
3482 }
3483
3484 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3485 static void glue(gen_, name##x)(DisasContext *ctx) \
3486 { \
3487 TCGv EA; \
3488 if (unlikely(!ctx->fpu_enabled)) { \
3489 gen_exception(ctx, POWERPC_EXCP_FPU); \
3490 return; \
3491 } \
3492 gen_set_access_type(ctx, ACCESS_FLOAT); \
3493 EA = tcg_temp_new(); \
3494 gen_addr_reg_index(ctx, EA); \
3495 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3496 tcg_temp_free(EA); \
3497 }
3498
3499 #define GEN_LDFS(name, ldop, op, type) \
3500 GEN_LDF(name, ldop, op | 0x20, type); \
3501 GEN_LDUF(name, ldop, op | 0x21, type); \
3502 GEN_LDUXF(name, ldop, op | 0x01, type); \
3503 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3504
3505 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3506 {
3507 TCGv t0 = tcg_temp_new();
3508 TCGv_i32 t1 = tcg_temp_new_i32();
3509 gen_qemu_ld32u(ctx, t0, arg2);
3510 tcg_gen_trunc_tl_i32(t1, t0);
3511 tcg_temp_free(t0);
3512 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3513 tcg_temp_free_i32(t1);
3514 }
3515
3516 /* lfd lfdu lfdux lfdx */
3517 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3518 /* lfs lfsu lfsux lfsx */
3519 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3520
3521 /* lfdp */
3522 static void gen_lfdp(DisasContext *ctx)
3523 {
3524 TCGv EA;
3525 if (unlikely(!ctx->fpu_enabled)) {
3526 gen_exception(ctx, POWERPC_EXCP_FPU);
3527 return;
3528 }
3529 gen_set_access_type(ctx, ACCESS_FLOAT);
3530 EA = tcg_temp_new();
3531 gen_addr_imm_index(ctx, EA, 0);
3532 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3533 64-bit byteswap already. */
3534 if (unlikely(ctx->le_mode)) {
3535 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3536 tcg_gen_addi_tl(EA, EA, 8);
3537 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3538 } else {
3539 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3540 tcg_gen_addi_tl(EA, EA, 8);
3541 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3542 }
3543 tcg_temp_free(EA);
3544 }
3545
3546 /* lfdpx */
3547 static void gen_lfdpx(DisasContext *ctx)
3548 {
3549 TCGv EA;
3550 if (unlikely(!ctx->fpu_enabled)) {
3551 gen_exception(ctx, POWERPC_EXCP_FPU);
3552 return;
3553 }
3554 gen_set_access_type(ctx, ACCESS_FLOAT);
3555 EA = tcg_temp_new();
3556 gen_addr_reg_index(ctx, EA);
3557 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3558 64-bit byteswap already. */
3559 if (unlikely(ctx->le_mode)) {
3560 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3561 tcg_gen_addi_tl(EA, EA, 8);
3562 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3563 } else {
3564 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3565 tcg_gen_addi_tl(EA, EA, 8);
3566 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3567 }
3568 tcg_temp_free(EA);
3569 }
3570
3571 /* lfiwax */
3572 static void gen_lfiwax(DisasContext *ctx)
3573 {
3574 TCGv EA;
3575 TCGv t0;
3576 if (unlikely(!ctx->fpu_enabled)) {
3577 gen_exception(ctx, POWERPC_EXCP_FPU);
3578 return;
3579 }
3580 gen_set_access_type(ctx, ACCESS_FLOAT);
3581 EA = tcg_temp_new();
3582 t0 = tcg_temp_new();
3583 gen_addr_reg_index(ctx, EA);
3584 gen_qemu_ld32s(ctx, t0, EA);
3585 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3586 tcg_temp_free(EA);
3587 tcg_temp_free(t0);
3588 }
3589
3590 /* lfiwzx */
3591 static void gen_lfiwzx(DisasContext *ctx)
3592 {
3593 TCGv EA;
3594 if (unlikely(!ctx->fpu_enabled)) {
3595 gen_exception(ctx, POWERPC_EXCP_FPU);
3596 return;
3597 }
3598 gen_set_access_type(ctx, ACCESS_FLOAT);
3599 EA = tcg_temp_new();
3600 gen_addr_reg_index(ctx, EA);
3601 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3602 tcg_temp_free(EA);
3603 }
3604 /*** Floating-point store ***/
3605 #define GEN_STF(name, stop, opc, type) \
3606 static void glue(gen_, name)(DisasContext *ctx) \
3607 { \
3608 TCGv EA; \
3609 if (unlikely(!ctx->fpu_enabled)) { \
3610 gen_exception(ctx, POWERPC_EXCP_FPU); \
3611 return; \
3612 } \
3613 gen_set_access_type(ctx, ACCESS_FLOAT); \
3614 EA = tcg_temp_new(); \
3615 gen_addr_imm_index(ctx, EA, 0); \
3616 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3617 tcg_temp_free(EA); \
3618 }
3619
3620 #define GEN_STUF(name, stop, opc, type) \
3621 static void glue(gen_, name##u)(DisasContext *ctx) \
3622 { \
3623 TCGv EA; \
3624 if (unlikely(!ctx->fpu_enabled)) { \
3625 gen_exception(ctx, POWERPC_EXCP_FPU); \
3626 return; \
3627 } \
3628 if (unlikely(rA(ctx->opcode) == 0)) { \
3629 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3630 return; \
3631 } \
3632 gen_set_access_type(ctx, ACCESS_FLOAT); \
3633 EA = tcg_temp_new(); \
3634 gen_addr_imm_index(ctx, EA, 0); \
3635 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3636 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3637 tcg_temp_free(EA); \
3638 }
3639
3640 #define GEN_STUXF(name, stop, opc, type) \
3641 static void glue(gen_, name##ux)(DisasContext *ctx) \
3642 { \
3643 TCGv EA; \
3644 if (unlikely(!ctx->fpu_enabled)) { \
3645 gen_exception(ctx, POWERPC_EXCP_FPU); \
3646 return; \
3647 } \
3648 if (unlikely(rA(ctx->opcode) == 0)) { \
3649 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3650 return; \
3651 } \
3652 gen_set_access_type(ctx, ACCESS_FLOAT); \
3653 EA = tcg_temp_new(); \
3654 gen_addr_reg_index(ctx, EA); \
3655 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3656 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3657 tcg_temp_free(EA); \
3658 }
3659
3660 #define GEN_STXF(name, stop, opc2, opc3, type) \
3661 static void glue(gen_, name##x)(DisasContext *ctx) \
3662 { \
3663 TCGv EA; \
3664 if (unlikely(!ctx->fpu_enabled)) { \
3665 gen_exception(ctx, POWERPC_EXCP_FPU); \
3666 return; \
3667 } \
3668 gen_set_access_type(ctx, ACCESS_FLOAT); \
3669 EA = tcg_temp_new(); \
3670 gen_addr_reg_index(ctx, EA); \
3671 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3672 tcg_temp_free(EA); \
3673 }
3674
3675 #define GEN_STFS(name, stop, op, type) \
3676 GEN_STF(name, stop, op | 0x20, type); \
3677 GEN_STUF(name, stop, op | 0x21, type); \
3678 GEN_STUXF(name, stop, op | 0x01, type); \
3679 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3680
3681 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3682 {
3683 TCGv_i32 t0 = tcg_temp_new_i32();
3684 TCGv t1 = tcg_temp_new();
3685 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3686 tcg_gen_extu_i32_tl(t1, t0);
3687 tcg_temp_free_i32(t0);
3688 gen_qemu_st32(ctx, t1, arg2);
3689 tcg_temp_free(t1);
3690 }
3691
3692 /* stfd stfdu stfdux stfdx */
3693 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3694 /* stfs stfsu stfsux stfsx */
3695 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3696
3697 /* stfdp */
3698 static void gen_stfdp(DisasContext *ctx)
3699 {
3700 TCGv EA;
3701 if (unlikely(!ctx->fpu_enabled)) {
3702 gen_exception(ctx, POWERPC_EXCP_FPU);
3703 return;
3704 }
3705 gen_set_access_type(ctx, ACCESS_FLOAT);
3706 EA = tcg_temp_new();
3707 gen_addr_imm_index(ctx, EA, 0);
3708 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3709 64-bit byteswap already. */
3710 if (unlikely(ctx->le_mode)) {
3711 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3712 tcg_gen_addi_tl(EA, EA, 8);
3713 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3714 } else {
3715 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3716 tcg_gen_addi_tl(EA, EA, 8);
3717 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3718 }
3719 tcg_temp_free(EA);
3720 }
3721
3722 /* stfdpx */
3723 static void gen_stfdpx(DisasContext *ctx)
3724 {
3725 TCGv EA;
3726 if (unlikely(!ctx->fpu_enabled)) {
3727 gen_exception(ctx, POWERPC_EXCP_FPU);
3728 return;
3729 }
3730 gen_set_access_type(ctx, ACCESS_FLOAT);
3731 EA = tcg_temp_new();
3732 gen_addr_reg_index(ctx, EA);
3733 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3734 64-bit byteswap already. */
3735 if (unlikely(ctx->le_mode)) {
3736 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3737 tcg_gen_addi_tl(EA, EA, 8);
3738 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3739 } else {
3740 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3741 tcg_gen_addi_tl(EA, EA, 8);
3742 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3743 }
3744 tcg_temp_free(EA);
3745 }
3746
3747 /* Optional: */
3748 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3749 {
3750 TCGv t0 = tcg_temp_new();
3751 tcg_gen_trunc_i64_tl(t0, arg1),
3752 gen_qemu_st32(ctx, t0, arg2);
3753 tcg_temp_free(t0);
3754 }
3755 /* stfiwx */
3756 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3757
3758 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3759 {
3760 #if defined(TARGET_PPC64)
3761 if (ctx->has_cfar)
3762 tcg_gen_movi_tl(cpu_cfar, nip);
3763 #endif
3764 }
3765
3766 /*** Branch ***/
3767 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3768 {
3769 TranslationBlock *tb;
3770 tb = ctx->tb;
3771 if (NARROW_MODE(ctx)) {
3772 dest = (uint32_t) dest;
3773 }
3774 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3775 likely(!ctx->singlestep_enabled)) {
3776 tcg_gen_goto_tb(n);
3777 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3778 tcg_gen_exit_tb((uintptr_t)tb + n);
3779 } else {
3780 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3781 if (unlikely(ctx->singlestep_enabled)) {
3782 if ((ctx->singlestep_enabled &
3783 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3784 (ctx->exception == POWERPC_EXCP_BRANCH ||
3785 ctx->exception == POWERPC_EXCP_TRACE)) {
3786 target_ulong tmp = ctx->nip;
3787 ctx->nip = dest;
3788 gen_exception(ctx, POWERPC_EXCP_TRACE);
3789 ctx->nip = tmp;
3790 }
3791 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3792 gen_debug_exception(ctx);
3793 }
3794 }
3795 tcg_gen_exit_tb(0);
3796 }
3797 }
3798
3799 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3800 {
3801 if (NARROW_MODE(ctx)) {
3802 nip = (uint32_t)nip;
3803 }
3804 tcg_gen_movi_tl(cpu_lr, nip);
3805 }
3806
3807 /* b ba bl bla */
3808 static void gen_b(DisasContext *ctx)
3809 {
3810 target_ulong li, target;
3811
3812 ctx->exception = POWERPC_EXCP_BRANCH;
3813 /* sign extend LI */
3814 li = LI(ctx->opcode);
3815 li = (li ^ 0x02000000) - 0x02000000;
3816 if (likely(AA(ctx->opcode) == 0)) {
3817 target = ctx->nip + li - 4;
3818 } else {
3819 target = li;
3820 }
3821 if (LK(ctx->opcode)) {
3822 gen_setlr(ctx, ctx->nip);
3823 }
3824 gen_update_cfar(ctx, ctx->nip);
3825 gen_goto_tb(ctx, 0, target);
3826 }
3827
3828 #define BCOND_IM 0
3829 #define BCOND_LR 1
3830 #define BCOND_CTR 2
3831 #define BCOND_TAR 3
3832
3833 static inline void gen_bcond(DisasContext *ctx, int type)
3834 {
3835 uint32_t bo = BO(ctx->opcode);
3836 int l1;
3837 TCGv target;
3838
3839 ctx->exception = POWERPC_EXCP_BRANCH;
3840 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3841 target = tcg_temp_local_new();
3842 if (type == BCOND_CTR)
3843 tcg_gen_mov_tl(target, cpu_ctr);
3844 else if (type == BCOND_TAR)
3845 gen_load_spr(target, SPR_TAR);
3846 else
3847 tcg_gen_mov_tl(target, cpu_lr);
3848 } else {
3849 TCGV_UNUSED(target);
3850 }
3851 if (LK(ctx->opcode))
3852 gen_setlr(ctx, ctx->nip);
3853 l1 = gen_new_label();
3854 if ((bo & 0x4) == 0) {
3855 /* Decrement and test CTR */
3856 TCGv temp = tcg_temp_new();
3857 if (unlikely(type == BCOND_CTR)) {
3858 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3859 return;
3860 }
3861 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3862 if (NARROW_MODE(ctx)) {
3863 tcg_gen_ext32u_tl(temp, cpu_ctr);
3864 } else {
3865 tcg_gen_mov_tl(temp, cpu_ctr);
3866 }
3867 if (bo & 0x2) {
3868 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3869 } else {
3870 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3871 }
3872 tcg_temp_free(temp);
3873 }
3874 if ((bo & 0x10) == 0) {
3875 /* Test CR */
3876 uint32_t bi = BI(ctx->opcode);
3877 uint32_t mask = 0x08 >> (bi & 0x03);
3878 TCGv_i32 temp = tcg_temp_new_i32();
3879
3880 if (bo & 0x8) {
3881 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3882 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3883 } else {
3884 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3885 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3886 }
3887 tcg_temp_free_i32(temp);
3888 }
3889 gen_update_cfar(ctx, ctx->nip);
3890 if (type == BCOND_IM) {
3891 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3892 if (likely(AA(ctx->opcode) == 0)) {
3893 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3894 } else {
3895 gen_goto_tb(ctx, 0, li);
3896 }
3897 gen_set_label(l1);
3898 gen_goto_tb(ctx, 1, ctx->nip);
3899 } else {
3900 if (NARROW_MODE(ctx)) {
3901 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3902 } else {
3903 tcg_gen_andi_tl(cpu_nip, target, ~3);
3904 }
3905 tcg_gen_exit_tb(0);
3906 gen_set_label(l1);
3907 gen_update_nip(ctx, ctx->nip);
3908 tcg_gen_exit_tb(0);
3909 }
3910 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3911 tcg_temp_free(target);
3912 }
3913 }
3914
3915 static void gen_bc(DisasContext *ctx)
3916 {
3917 gen_bcond(ctx, BCOND_IM);
3918 }
3919
3920 static void gen_bcctr(DisasContext *ctx)
3921 {
3922 gen_bcond(ctx, BCOND_CTR);
3923 }
3924
3925 static void gen_bclr(DisasContext *ctx)
3926 {
3927 gen_bcond(ctx, BCOND_LR);
3928 }
3929
3930 static void gen_bctar(DisasContext *ctx)
3931 {
3932 gen_bcond(ctx, BCOND_TAR);
3933 }
3934
3935 /*** Condition register logical ***/
3936 #define GEN_CRLOGIC(name, tcg_op, opc) \
3937 static void glue(gen_, name)(DisasContext *ctx) \
3938 { \
3939 uint8_t bitmask; \
3940 int sh; \
3941 TCGv_i32 t0, t1; \
3942 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3943 t0 = tcg_temp_new_i32(); \
3944 if (sh > 0) \
3945 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3946 else if (sh < 0) \
3947 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3948 else \
3949 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3950 t1 = tcg_temp_new_i32(); \
3951 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3952 if (sh > 0) \
3953 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3954 else if (sh < 0) \
3955 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3956 else \
3957 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3958 tcg_op(t0, t0, t1); \
3959 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3960 tcg_gen_andi_i32(t0, t0, bitmask); \
3961 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3962 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3963 tcg_temp_free_i32(t0); \
3964 tcg_temp_free_i32(t1); \
3965 }
3966
3967 /* crand */
3968 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3969 /* crandc */
3970 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3971 /* creqv */
3972 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3973 /* crnand */
3974 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3975 /* crnor */
3976 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3977 /* cror */
3978 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3979 /* crorc */
3980 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3981 /* crxor */
3982 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3983
3984 /* mcrf */
3985 static void gen_mcrf(DisasContext *ctx)
3986 {
3987 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3988 }
3989
3990 /*** System linkage ***/
3991
3992 /* rfi (supervisor only) */
3993 static void gen_rfi(DisasContext *ctx)
3994 {
3995 #if defined(CONFIG_USER_ONLY)
3996 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3997 #else
3998 /* Restore CPU state */
3999 if (unlikely(ctx->pr)) {
4000 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4001 return;
4002 }
4003 gen_update_cfar(ctx, ctx->nip);
4004 gen_helper_rfi(cpu_env);
4005 gen_sync_exception(ctx);
4006 #endif
4007 }
4008
4009 #if defined(TARGET_PPC64)
4010 static void gen_rfid(DisasContext *ctx)
4011 {
4012 #if defined(CONFIG_USER_ONLY)
4013 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4014 #else
4015 /* Restore CPU state */
4016 if (unlikely(ctx->pr)) {
4017 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4018 return;
4019 }
4020 gen_update_cfar(ctx, ctx->nip);
4021 gen_helper_rfid(cpu_env);
4022 gen_sync_exception(ctx);
4023 #endif
4024 }
4025
4026 static void gen_hrfid(DisasContext *ctx)
4027 {
4028 #if defined(CONFIG_USER_ONLY)
4029 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4030 #else
4031 /* Restore CPU state */
4032 if (unlikely(!ctx->hv)) {
4033 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4034 return;
4035 }
4036 gen_helper_hrfid(cpu_env);
4037 gen_sync_exception(ctx);
4038 #endif
4039 }
4040 #endif
4041
4042 /* sc */
4043 #if defined(CONFIG_USER_ONLY)
4044 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4045 #else
4046 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4047 #endif
4048 static void gen_sc(DisasContext *ctx)
4049 {
4050 uint32_t lev;
4051
4052 lev = (ctx->opcode >> 5) & 0x7F;
4053 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4054 }
4055
4056 /*** Trap ***/
4057
4058 /* tw */
4059 static void gen_tw(DisasContext *ctx)
4060 {
4061 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4062 /* Update the nip since this might generate a trap exception */
4063 gen_update_nip(ctx, ctx->nip);
4064 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4065 t0);
4066 tcg_temp_free_i32(t0);
4067 }
4068
4069 /* twi */
4070 static void gen_twi(DisasContext *ctx)
4071 {
4072 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4073 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4074 /* Update the nip since this might generate a trap exception */
4075 gen_update_nip(ctx, ctx->nip);
4076 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4077 tcg_temp_free(t0);
4078 tcg_temp_free_i32(t1);
4079 }
4080
4081 #if defined(TARGET_PPC64)
4082 /* td */
4083 static void gen_td(DisasContext *ctx)
4084 {
4085 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4086 /* Update the nip since this might generate a trap exception */
4087 gen_update_nip(ctx, ctx->nip);
4088 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4089 t0);
4090 tcg_temp_free_i32(t0);
4091 }
4092
4093 /* tdi */
4094 static void gen_tdi(DisasContext *ctx)
4095 {
4096 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4097 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4098 /* Update the nip since this might generate a trap exception */
4099 gen_update_nip(ctx, ctx->nip);
4100 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4101 tcg_temp_free(t0);
4102 tcg_temp_free_i32(t1);
4103 }
4104 #endif
4105
4106 /*** Processor control ***/
4107
4108 static void gen_read_xer(TCGv dst)
4109 {
4110 TCGv t0 = tcg_temp_new();
4111 TCGv t1 = tcg_temp_new();
4112 TCGv t2 = tcg_temp_new();
4113 tcg_gen_mov_tl(dst, cpu_xer);
4114 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4115 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4116 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4117 tcg_gen_or_tl(t0, t0, t1);
4118 tcg_gen_or_tl(dst, dst, t2);
4119 tcg_gen_or_tl(dst, dst, t0);
4120 tcg_temp_free(t0);
4121 tcg_temp_free(t1);
4122 tcg_temp_free(t2);
4123 }
4124
4125 static void gen_write_xer(TCGv src)
4126 {
4127 tcg_gen_andi_tl(cpu_xer, src,
4128 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4129 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4130 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4131 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4132 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4133 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4134 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4135 }
4136
4137 /* mcrxr */
4138 static void gen_mcrxr(DisasContext *ctx)
4139 {
4140 TCGv_i32 t0 = tcg_temp_new_i32();
4141 TCGv_i32 t1 = tcg_temp_new_i32();
4142 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4143
4144 tcg_gen_trunc_tl_i32(t0, cpu_so);
4145 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4146 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4147 tcg_gen_shli_i32(t0, t0, 3);
4148 tcg_gen_shli_i32(t1, t1, 2);
4149 tcg_gen_shli_i32(dst, dst, 1);
4150 tcg_gen_or_i32(dst, dst, t0);
4151 tcg_gen_or_i32(dst, dst, t1);
4152 tcg_temp_free_i32(t0);
4153 tcg_temp_free_i32(t1);
4154
4155 tcg_gen_movi_tl(cpu_so, 0);
4156 tcg_gen_movi_tl(cpu_ov, 0);
4157 tcg_gen_movi_tl(cpu_ca, 0);
4158 }
4159
4160 /* mfcr mfocrf */
4161 static void gen_mfcr(DisasContext *ctx)
4162 {
4163 uint32_t crm, crn;
4164
4165 if (likely(ctx->opcode & 0x00100000)) {
4166 crm = CRM(ctx->opcode);
4167 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4168 crn = ctz32 (crm);
4169 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4170 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4171 cpu_gpr[rD(ctx->opcode)], crn * 4);
4172 }
4173 } else {
4174 TCGv_i32 t0 = tcg_temp_new_i32();
4175 tcg_gen_mov_i32(t0, cpu_crf[0]);
4176 tcg_gen_shli_i32(t0, t0, 4);
4177 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4178 tcg_gen_shli_i32(t0, t0, 4);
4179 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4180 tcg_gen_shli_i32(t0, t0, 4);
4181 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4182 tcg_gen_shli_i32(t0, t0, 4);
4183 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4184 tcg_gen_shli_i32(t0, t0, 4);
4185 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4186 tcg_gen_shli_i32(t0, t0, 4);
4187 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4188 tcg_gen_shli_i32(t0, t0, 4);
4189 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4190 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4191 tcg_temp_free_i32(t0);
4192 }
4193 }
4194
4195 /* mfmsr */
4196 static void gen_mfmsr(DisasContext *ctx)
4197 {
4198 #if defined(CONFIG_USER_ONLY)
4199 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4200 #else
4201 if (unlikely(ctx->pr)) {
4202 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4203 return;
4204 }
4205 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4206 #endif
4207 }
4208
4209 static void spr_noaccess(void *opaque, int gprn, int sprn)
4210 {
4211 #if 0
4212 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4213 printf("ERROR: try to access SPR %d !\n", sprn);
4214 #endif
4215 }
4216 #define SPR_NOACCESS (&spr_noaccess)
4217
4218 /* mfspr */
4219 static inline void gen_op_mfspr(DisasContext *ctx)
4220 {
4221 void (*read_cb)(void *opaque, int gprn, int sprn);
4222 uint32_t sprn = SPR(ctx->opcode);
4223
4224 #if !defined(CONFIG_USER_ONLY)
4225 if (ctx->hv)
4226 read_cb = ctx->spr_cb[sprn].hea_read;
4227 else if (!ctx->pr)
4228 read_cb = ctx->spr_cb[sprn].oea_read;
4229 else
4230 #endif
4231 read_cb = ctx->spr_cb[sprn].uea_read;
4232 if (likely(read_cb != NULL)) {
4233 if (likely(read_cb != SPR_NOACCESS)) {
4234 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4235 } else {
4236 /* Privilege exception */
4237 /* This is a hack to avoid warnings when running Linux:
4238 * this OS breaks the PowerPC virtualisation model,
4239 * allowing userland application to read the PVR
4240 */
4241 if (sprn != SPR_PVR) {
4242 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4243 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4244 printf("Trying to read privileged spr %d (0x%03x) at "
4245 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4246 }
4247 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4248 }
4249 } else {
4250 /* Not defined */
4251 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4252 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4253 printf("Trying to read invalid spr %d (0x%03x) at "
4254 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4255 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4256 }
4257 }
4258
4259 static void gen_mfspr(DisasContext *ctx)
4260 {
4261 gen_op_mfspr(ctx);
4262 }
4263
4264 /* mftb */
4265 static void gen_mftb(DisasContext *ctx)
4266 {
4267 gen_op_mfspr(ctx);
4268 }
4269
4270 /* mtcrf mtocrf*/
4271 static void gen_mtcrf(DisasContext *ctx)
4272 {
4273 uint32_t crm, crn;
4274
4275 crm = CRM(ctx->opcode);
4276 if (likely((ctx->opcode & 0x00100000))) {
4277 if (crm && ((crm & (crm - 1)) == 0)) {
4278 TCGv_i32 temp = tcg_temp_new_i32();
4279 crn = ctz32 (crm);
4280 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4281 tcg_gen_shri_i32(temp, temp, crn * 4);
4282 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4283 tcg_temp_free_i32(temp);
4284 }
4285 } else {
4286 TCGv_i32 temp = tcg_temp_new_i32();
4287 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4288 for (crn = 0 ; crn < 8 ; crn++) {
4289 if (crm & (1 << crn)) {
4290 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4291 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4292 }
4293 }
4294 tcg_temp_free_i32(temp);
4295 }
4296 }
4297
4298 /* mtmsr */
4299 #if defined(TARGET_PPC64)
4300 static void gen_mtmsrd(DisasContext *ctx)
4301 {
4302 #if defined(CONFIG_USER_ONLY)
4303 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4304 #else
4305 if (unlikely(ctx->pr)) {
4306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4307 return;
4308 }
4309 if (ctx->opcode & 0x00010000) {
4310 /* Special form that does not need any synchronisation */
4311 TCGv t0 = tcg_temp_new();
4312 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4313 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4314 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4315 tcg_temp_free(t0);
4316 } else {
4317 /* XXX: we need to update nip before the store
4318 * if we enter power saving mode, we will exit the loop
4319 * directly from ppc_store_msr
4320 */
4321 gen_update_nip(ctx, ctx->nip);
4322 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4323 /* Must stop the translation as machine state (may have) changed */
4324 /* Note that mtmsr is not always defined as context-synchronizing */
4325 gen_stop_exception(ctx);
4326 }
4327 #endif
4328 }
4329 #endif
4330
4331 static void gen_mtmsr(DisasContext *ctx)
4332 {
4333 #if defined(CONFIG_USER_ONLY)
4334 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4335 #else
4336 if (unlikely(ctx->pr)) {
4337 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4338 return;
4339 }
4340 if (ctx->opcode & 0x00010000) {
4341 /* Special form that does not need any synchronisation */
4342 TCGv t0 = tcg_temp_new();
4343 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4344 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4345 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4346 tcg_temp_free(t0);
4347 } else {
4348 TCGv msr = tcg_temp_new();
4349
4350 /* XXX: we need to update nip before the store
4351 * if we enter power saving mode, we will exit the loop
4352 * directly from ppc_store_msr
4353 */
4354 gen_update_nip(ctx, ctx->nip);
4355 #if defined(TARGET_PPC64)
4356 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4357 #else
4358 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4359 #endif
4360 gen_helper_store_msr(cpu_env, msr);
4361 tcg_temp_free(msr);
4362 /* Must stop the translation as machine state (may have) changed */
4363 /* Note that mtmsr is not always defined as context-synchronizing */
4364 gen_stop_exception(ctx);
4365 }
4366 #endif
4367 }
4368
4369 /* mtspr */
4370 static void gen_mtspr(DisasContext *ctx)
4371 {
4372 void (*write_cb)(void *opaque, int sprn, int gprn);
4373 uint32_t sprn = SPR(ctx->opcode);
4374
4375 #if !defined(CONFIG_USER_ONLY)
4376 if (ctx->hv)
4377 write_cb = ctx->spr_cb[sprn].hea_write;
4378 else if (!ctx->pr)
4379 write_cb = ctx->spr_cb[sprn].oea_write;
4380 else
4381 #endif
4382 write_cb = ctx->spr_cb[sprn].uea_write;
4383 if (likely(write_cb != NULL)) {
4384 if (likely(write_cb != SPR_NOACCESS)) {
4385 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4386 } else {
4387 /* Privilege exception */
4388 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4389 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4390 printf("Trying to write privileged spr %d (0x%03x) at "
4391 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4393 }
4394 } else {
4395 /* Not defined */
4396 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4397 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4398 printf("Trying to write invalid spr %d (0x%03x) at "
4399 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4400 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4401 }
4402 }
4403
4404 /*** Cache management ***/
4405
4406 /* dcbf */
4407 static void gen_dcbf(DisasContext *ctx)
4408 {
4409 /* XXX: specification says this is treated as a load by the MMU */
4410 TCGv t0;
4411 gen_set_access_type(ctx, ACCESS_CACHE);
4412 t0 = tcg_temp_new();
4413 gen_addr_reg_index(ctx, t0);
4414 gen_qemu_ld8u(ctx, t0, t0);
4415 tcg_temp_free(t0);
4416 }
4417
4418 /* dcbi (Supervisor only) */
4419 static void gen_dcbi(DisasContext *ctx)
4420 {
4421 #if defined(CONFIG_USER_ONLY)
4422 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4423 #else
4424 TCGv EA, val;
4425 if (unlikely(ctx->pr)) {
4426 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4427 return;
4428 }
4429 EA = tcg_temp_new();
4430 gen_set_access_type(ctx, ACCESS_CACHE);
4431 gen_addr_reg_index(ctx, EA);
4432 val = tcg_temp_new();
4433 /* XXX: specification says this should be treated as a store by the MMU */
4434 gen_qemu_ld8u(ctx, val, EA);
4435 gen_qemu_st8(ctx, val, EA);
4436 tcg_temp_free(val);
4437 tcg_temp_free(EA);
4438 #endif
4439 }
4440
4441 /* dcdst */
4442 static void gen_dcbst(DisasContext *ctx)
4443 {
4444 /* XXX: specification say this is treated as a load by the MMU */
4445 TCGv t0;
4446 gen_set_access_type(ctx, ACCESS_CACHE);
4447 t0 = tcg_temp_new();
4448 gen_addr_reg_index(ctx, t0);
4449 gen_qemu_ld8u(ctx, t0, t0);
4450 tcg_temp_free(t0);
4451 }
4452
4453 /* dcbt */
4454 static void gen_dcbt(DisasContext *ctx)
4455 {
4456 /* interpreted as no-op */
4457 /* XXX: specification say this is treated as a load by the MMU
4458 * but does not generate any exception
4459 */
4460 }
4461
4462 /* dcbtst */
4463 static void gen_dcbtst(DisasContext *ctx)
4464 {
4465 /* interpreted as no-op */
4466 /* XXX: specification say this is treated as a load by the MMU
4467 * but does not generate any exception
4468 */
4469 }
4470
4471 /* dcbtls */
4472 static void gen_dcbtls(DisasContext *ctx)
4473 {
4474 /* Always fails locking the cache */
4475 TCGv t0 = tcg_temp_new();
4476 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4477 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4478 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4479 tcg_temp_free(t0);
4480 }
4481
4482 /* dcbz */
4483 static void gen_dcbz(DisasContext *ctx)
4484 {
4485 TCGv tcgv_addr;
4486 TCGv_i32 tcgv_is_dcbzl;
4487 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4488
4489 gen_set_access_type(ctx, ACCESS_CACHE);
4490 /* NIP cannot be restored if the memory exception comes from an helper */
4491 gen_update_nip(ctx, ctx->nip - 4);
4492 tcgv_addr = tcg_temp_new();
4493 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4494
4495 gen_addr_reg_index(ctx, tcgv_addr);
4496 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4497
4498 tcg_temp_free(tcgv_addr);
4499 tcg_temp_free_i32(tcgv_is_dcbzl);
4500 }
4501
4502 /* dst / dstt */
4503 static void gen_dst(DisasContext *ctx)
4504 {
4505 if (rA(ctx->opcode) == 0) {
4506 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4507 } else {
4508 /* interpreted as no-op */
4509 }
4510 }
4511
4512 /* dstst /dststt */
4513 static void gen_dstst(DisasContext *ctx)
4514 {
4515 if (rA(ctx->opcode) == 0) {
4516 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4517 } else {
4518 /* interpreted as no-op */
4519 }
4520
4521 }
4522
4523 /* dss / dssall */
4524 static void gen_dss(DisasContext *ctx)
4525 {
4526 /* interpreted as no-op */
4527 }
4528
4529 /* icbi */
4530 static void gen_icbi(DisasContext *ctx)
4531 {
4532 TCGv t0;
4533 gen_set_access_type(ctx, ACCESS_CACHE);
4534 /* NIP cannot be restored if the memory exception comes from an helper */
4535 gen_update_nip(ctx, ctx->nip - 4);
4536 t0 = tcg_temp_new();
4537 gen_addr_reg_index(ctx, t0);
4538 gen_helper_icbi(cpu_env, t0);
4539 tcg_temp_free(t0);
4540 }
4541
4542 /* Optional: */
4543 /* dcba */
4544 static void gen_dcba(DisasContext *ctx)
4545 {
4546 /* interpreted as no-op */
4547 /* XXX: specification say this is treated as a store by the MMU
4548 * but does not generate any exception
4549 */
4550 }
4551
4552 /*** Segment register manipulation ***/
4553 /* Supervisor only: */
4554
4555 /* mfsr */
4556 static void gen_mfsr(DisasContext *ctx)
4557 {
4558 #if defined(CONFIG_USER_ONLY)
4559 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4560 #else
4561 TCGv t0;
4562 if (unlikely(ctx->pr)) {
4563 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4564 return;
4565 }
4566 t0 = tcg_const_tl(SR(ctx->opcode));
4567 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4568 tcg_temp_free(t0);
4569 #endif
4570 }
4571
4572 /* mfsrin */
4573 static void gen_mfsrin(DisasContext *ctx)
4574 {
4575 #if defined(CONFIG_USER_ONLY)
4576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4577 #else
4578 TCGv t0;
4579 if (unlikely(ctx->pr)) {
4580 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4581 return;
4582 }
4583 t0 = tcg_temp_new();
4584 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4585 tcg_gen_andi_tl(t0, t0, 0xF);
4586 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4587 tcg_temp_free(t0);
4588 #endif
4589 }
4590
4591 /* mtsr */
4592 static void gen_mtsr(DisasContext *ctx)
4593 {
4594 #if defined(CONFIG_USER_ONLY)
4595 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4596 #else
4597 TCGv t0;
4598 if (unlikely(ctx->pr)) {
4599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4600 return;
4601 }
4602 t0 = tcg_const_tl(SR(ctx->opcode));
4603 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4604 tcg_temp_free(t0);
4605 #endif
4606 }
4607
4608 /* mtsrin */
4609 static void gen_mtsrin(DisasContext *ctx)
4610 {
4611 #if defined(CONFIG_USER_ONLY)
4612 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4613 #else
4614 TCGv t0;
4615 if (unlikely(ctx->pr)) {
4616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4617 return;
4618 }
4619 t0 = tcg_temp_new();
4620 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4621 tcg_gen_andi_tl(t0, t0, 0xF);
4622 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4623 tcg_temp_free(t0);
4624 #endif
4625 }
4626
4627 #if defined(TARGET_PPC64)
4628 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4629
4630 /* mfsr */
4631 static void gen_mfsr_64b(DisasContext *ctx)
4632 {
4633 #if defined(CONFIG_USER_ONLY)
4634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4635 #else
4636 TCGv t0;
4637 if (unlikely(ctx->pr)) {
4638 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4639 return;
4640 }
4641 t0 = tcg_const_tl(SR(ctx->opcode));
4642 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4643 tcg_temp_free(t0);
4644 #endif
4645 }
4646
4647 /* mfsrin */
4648 static void gen_mfsrin_64b(DisasContext *ctx)
4649 {
4650 #if defined(CONFIG_USER_ONLY)
4651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4652 #else
4653 TCGv t0;
4654 if (unlikely(ctx->pr)) {
4655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4656 return;
4657 }
4658 t0 = tcg_temp_new();
4659 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4660 tcg_gen_andi_tl(t0, t0, 0xF);
4661 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4662 tcg_temp_free(t0);
4663 #endif
4664 }
4665
4666 /* mtsr */
4667 static void gen_mtsr_64b(DisasContext *ctx)
4668 {
4669 #if defined(CONFIG_USER_ONLY)
4670 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4671 #else
4672 TCGv t0;
4673 if (unlikely(ctx->pr)) {
4674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4675 return;
4676 }
4677 t0 = tcg_const_tl(SR(ctx->opcode));
4678 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4679 tcg_temp_free(t0);
4680 #endif
4681 }
4682
4683 /* mtsrin */
4684 static void gen_mtsrin_64b(DisasContext *ctx)
4685 {
4686 #if defined(CONFIG_USER_ONLY)
4687 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4688 #else
4689 TCGv t0;
4690 if (unlikely(ctx->pr)) {
4691 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4692 return;
4693 }
4694 t0 = tcg_temp_new();
4695 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4696 tcg_gen_andi_tl(t0, t0, 0xF);
4697 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4698 tcg_temp_free(t0);
4699 #endif
4700 }
4701
4702 /* slbmte */
4703 static void gen_slbmte(DisasContext *ctx)
4704 {
4705 #if defined(CONFIG_USER_ONLY)
4706 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4707 #else
4708 if (unlikely(ctx->pr)) {
4709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4710 return;
4711 }
4712 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4713 cpu_gpr[rS(ctx->opcode)]);
4714 #endif
4715 }
4716
4717 static void gen_slbmfee(DisasContext *ctx)
4718 {
4719 #if defined(CONFIG_USER_ONLY)
4720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4721 #else
4722 if (unlikely(ctx->pr)) {
4723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4724 return;
4725 }
4726 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4727 cpu_gpr[rB(ctx->opcode)]);
4728 #endif
4729 }
4730
4731 static void gen_slbmfev(DisasContext *ctx)
4732 {
4733 #if defined(CONFIG_USER_ONLY)
4734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4735 #else
4736 if (unlikely(ctx->pr)) {
4737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4738 return;
4739 }
4740 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4741 cpu_gpr[rB(ctx->opcode)]);
4742 #endif
4743 }
4744 #endif /* defined(TARGET_PPC64) */
4745
4746 /*** Lookaside buffer management ***/
4747 /* Optional & supervisor only: */
4748
4749 /* tlbia */
4750 static void gen_tlbia(DisasContext *ctx)
4751 {
4752 #if defined(CONFIG_USER_ONLY)
4753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4754 #else
4755 if (unlikely(ctx->pr)) {
4756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4757 return;
4758 }
4759 gen_helper_tlbia(cpu_env);
4760 #endif
4761 }
4762
4763 /* tlbiel */
4764 static void gen_tlbiel(DisasContext *ctx)
4765 {
4766 #if defined(CONFIG_USER_ONLY)
4767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4768 #else
4769 if (unlikely(ctx->pr)) {
4770 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4771 return;
4772 }
4773 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4774 #endif
4775 }
4776
4777 /* tlbie */
4778 static void gen_tlbie(DisasContext *ctx)
4779 {
4780 #if defined(CONFIG_USER_ONLY)
4781 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4782 #else
4783 if (unlikely(ctx->pr)) {
4784 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4785 return;
4786 }
4787 if (NARROW_MODE(ctx)) {
4788 TCGv t0 = tcg_temp_new();
4789 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4790 gen_helper_tlbie(cpu_env, t0);
4791 tcg_temp_free(t0);
4792 } else {
4793 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4794 }
4795 #endif
4796 }
4797
4798 /* tlbsync */
4799 static void gen_tlbsync(DisasContext *ctx)
4800 {
4801 #if defined(CONFIG_USER_ONLY)
4802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4803 #else
4804 if (unlikely(ctx->pr)) {
4805 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4806 return;
4807 }
4808 /* This has no effect: it should ensure that all previous
4809 * tlbie have completed
4810 */
4811 gen_stop_exception(ctx);
4812 #endif
4813 }
4814
4815 #if defined(TARGET_PPC64)
4816 /* slbia */
4817 static void gen_slbia(DisasContext *ctx)
4818 {
4819 #if defined(CONFIG_USER_ONLY)
4820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4821 #else
4822 if (unlikely(ctx->pr)) {
4823 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4824 return;
4825 }
4826 gen_helper_slbia(cpu_env);
4827 #endif
4828 }
4829
4830 /* slbie */
4831 static void gen_slbie(DisasContext *ctx)
4832 {
4833 #if defined(CONFIG_USER_ONLY)
4834 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4835 #else
4836 if (unlikely(ctx->pr)) {
4837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4838 return;
4839 }
4840 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4841 #endif
4842 }
4843 #endif
4844
4845 /*** External control ***/
4846 /* Optional: */
4847
4848 /* eciwx */
4849 static void gen_eciwx(DisasContext *ctx)
4850 {
4851 TCGv t0;
4852 /* Should check EAR[E] ! */
4853 gen_set_access_type(ctx, ACCESS_EXT);
4854 t0 = tcg_temp_new();
4855 gen_addr_reg_index(ctx, t0);
4856 gen_check_align(ctx, t0, 0x03);
4857 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4858 tcg_temp_free(t0);
4859 }
4860
4861 /* ecowx */
4862 static void gen_ecowx(DisasContext *ctx)
4863 {
4864 TCGv t0;
4865 /* Should check EAR[E] ! */
4866 gen_set_access_type(ctx, ACCESS_EXT);
4867 t0 = tcg_temp_new();
4868 gen_addr_reg_index(ctx, t0);
4869 gen_check_align(ctx, t0, 0x03);
4870 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4871 tcg_temp_free(t0);
4872 }
4873
4874 /* PowerPC 601 specific instructions */
4875
4876 /* abs - abs. */
4877 static void gen_abs(DisasContext *ctx)
4878 {
4879 int l1 = gen_new_label();
4880 int l2 = gen_new_label();
4881 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4882 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4883 tcg_gen_br(l2);
4884 gen_set_label(l1);
4885 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4886 gen_set_label(l2);
4887 if (unlikely(Rc(ctx->opcode) != 0))
4888 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4889 }
4890
4891 /* abso - abso. */
4892 static void gen_abso(DisasContext *ctx)
4893 {
4894 int l1 = gen_new_label();
4895 int l2 = gen_new_label();
4896 int l3 = gen_new_label();
4897 /* Start with XER OV disabled, the most likely case */
4898 tcg_gen_movi_tl(cpu_ov, 0);
4899 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4900 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4901 tcg_gen_movi_tl(cpu_ov, 1);
4902 tcg_gen_movi_tl(cpu_so, 1);
4903 tcg_gen_br(l2);
4904 gen_set_label(l1);
4905 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4906 tcg_gen_br(l3);
4907 gen_set_label(l2);
4908 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4909 gen_set_label(l3);
4910 if (unlikely(Rc(ctx->opcode) != 0))
4911 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4912 }
4913
4914 /* clcs */
4915 static void gen_clcs(DisasContext *ctx)
4916 {
4917 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4918 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4919 tcg_temp_free_i32(t0);
4920 /* Rc=1 sets CR0 to an undefined state */
4921 }
4922
4923 /* div - div. */
4924 static void gen_div(DisasContext *ctx)
4925 {
4926 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4927 cpu_gpr[rB(ctx->opcode)]);
4928 if (unlikely(Rc(ctx->opcode) != 0))
4929 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4930 }
4931
4932 /* divo - divo. */
4933 static void gen_divo(DisasContext *ctx)
4934 {
4935 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4936 cpu_gpr[rB(ctx->opcode)]);
4937 if (unlikely(Rc(ctx->opcode) != 0))
4938 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4939 }
4940
4941 /* divs - divs. */
4942 static void gen_divs(DisasContext *ctx)
4943 {
4944 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4945 cpu_gpr[rB(ctx->opcode)]);
4946 if (unlikely(Rc(ctx->opcode) != 0))
4947 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4948 }
4949
4950 /* divso - divso. */
4951 static void gen_divso(DisasContext *ctx)
4952 {
4953 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4954 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4955 if (unlikely(Rc(ctx->opcode) != 0))
4956 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4957 }
4958
4959 /* doz - doz. */
4960 static void gen_doz(DisasContext *ctx)
4961 {
4962 int l1 = gen_new_label();
4963 int l2 = gen_new_label();
4964 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4965 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4966 tcg_gen_br(l2);
4967 gen_set_label(l1);
4968 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4969 gen_set_label(l2);
4970 if (unlikely(Rc(ctx->opcode) != 0))
4971 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4972 }
4973
4974 /* dozo - dozo. */
4975 static void gen_dozo(DisasContext *ctx)
4976 {
4977 int l1 = gen_new_label();
4978 int l2 = gen_new_label();
4979 TCGv t0 = tcg_temp_new();
4980 TCGv t1 = tcg_temp_new();
4981 TCGv t2 = tcg_temp_new();
4982 /* Start with XER OV disabled, the most likely case */
4983 tcg_gen_movi_tl(cpu_ov, 0);
4984 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4985 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4986 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4987 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4988 tcg_gen_andc_tl(t1, t1, t2);
4989 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4990 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4991 tcg_gen_movi_tl(cpu_ov, 1);
4992 tcg_gen_movi_tl(cpu_so, 1);
4993 tcg_gen_br(l2);
4994 gen_set_label(l1);
4995 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4996 gen_set_label(l2);
4997 tcg_temp_free(t0);
4998 tcg_temp_free(t1);
4999 tcg_temp_free(t2);
5000 if (unlikely(Rc(ctx->opcode) != 0))
5001 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5002 }
5003
5004 /* dozi */
5005 static void gen_dozi(DisasContext *ctx)
5006 {
5007 target_long simm = SIMM(ctx->opcode);
5008 int l1 = gen_new_label();
5009 int l2 = gen_new_label();
5010 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5011 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5012 tcg_gen_br(l2);
5013 gen_set_label(l1);
5014 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5015 gen_set_label(l2);
5016 if (unlikely(Rc(ctx->opcode) != 0))
5017 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5018 }
5019
5020 /* lscbx - lscbx. */
5021 static void gen_lscbx(DisasContext *ctx)
5022 {
5023 TCGv t0 = tcg_temp_new();
5024 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5025 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5026 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5027
5028 gen_addr_reg_index(ctx, t0);
5029 /* NIP cannot be restored if the memory exception comes from an helper */
5030 gen_update_nip(ctx, ctx->nip - 4);
5031 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5032 tcg_temp_free_i32(t1);
5033 tcg_temp_free_i32(t2);
5034 tcg_temp_free_i32(t3);
5035 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5036 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5037 if (unlikely(Rc(ctx->opcode) != 0))
5038 gen_set_Rc0(ctx, t0);
5039 tcg_temp_free(t0);
5040 }
5041
5042 /* maskg - maskg. */
5043 static void gen_maskg(DisasContext *ctx)
5044 {
5045 int l1 = gen_new_label();
5046 TCGv t0 = tcg_temp_new();
5047 TCGv t1 = tcg_temp_new();
5048 TCGv t2 = tcg_temp_new();
5049 TCGv t3 = tcg_temp_new();
5050 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5051 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5052 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5053 tcg_gen_addi_tl(t2, t0, 1);
5054 tcg_gen_shr_tl(t2, t3, t2);
5055 tcg_gen_shr_tl(t3, t3, t1);
5056 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5057 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5058 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5059 gen_set_label(l1);
5060 tcg_temp_free(t0);
5061 tcg_temp_free(t1);
5062 tcg_temp_free(t2);
5063 tcg_temp_free(t3);
5064 if (unlikely(Rc(ctx->opcode) != 0))
5065 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5066 }
5067
5068 /* maskir - maskir. */
5069 static void gen_maskir(DisasContext *ctx)
5070 {
5071 TCGv t0 = tcg_temp_new();
5072 TCGv t1 = tcg_temp_new();
5073 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5074 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5075 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5076 tcg_temp_free(t0);
5077 tcg_temp_free(t1);
5078 if (unlikely(Rc(ctx->opcode) != 0))
5079 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5080 }
5081
5082 /* mul - mul. */
5083 static void gen_mul(DisasContext *ctx)
5084 {
5085 TCGv_i64 t0 = tcg_temp_new_i64();
5086 TCGv_i64 t1 = tcg_temp_new_i64();
5087 TCGv t2 = tcg_temp_new();
5088 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5089 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5090 tcg_gen_mul_i64(t0, t0, t1);
5091 tcg_gen_trunc_i64_tl(t2, t0);
5092 gen_store_spr(SPR_MQ, t2);
5093 tcg_gen_shri_i64(t1, t0, 32);
5094 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5095 tcg_temp_free_i64(t0);
5096 tcg_temp_free_i64(t1);
5097 tcg_temp_free(t2);
5098 if (unlikely(Rc(ctx->opcode) != 0))
5099 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5100 }
5101
5102 /* mulo - mulo. */
5103 static void gen_mulo(DisasContext *ctx)
5104 {
5105 int l1 = gen_new_label();
5106 TCGv_i64 t0 = tcg_temp_new_i64();
5107 TCGv_i64 t1 = tcg_temp_new_i64();
5108 TCGv t2 = tcg_temp_new();
5109 /* Start with XER OV disabled, the most likely case */
5110 tcg_gen_movi_tl(cpu_ov, 0);
5111 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5112 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5113 tcg_gen_mul_i64(t0, t0, t1);
5114 tcg_gen_trunc_i64_tl(t2, t0);
5115 gen_store_spr(SPR_MQ, t2);
5116 tcg_gen_shri_i64(t1, t0, 32);
5117 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5118 tcg_gen_ext32s_i64(t1, t0);
5119 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5120 tcg_gen_movi_tl(cpu_ov, 1);
5121 tcg_gen_movi_tl(cpu_so, 1);
5122 gen_set_label(l1);
5123 tcg_temp_free_i64(t0);
5124 tcg_temp_free_i64(t1);
5125 tcg_temp_free(t2);
5126 if (unlikely(Rc(ctx->opcode) != 0))
5127 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5128 }
5129
5130 /* nabs - nabs. */
5131 static void gen_nabs(DisasContext *ctx)
5132 {
5133 int l1 = gen_new_label();
5134 int l2 = gen_new_label();
5135 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5136 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5137 tcg_gen_br(l2);
5138 gen_set_label(l1);
5139 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5140 gen_set_label(l2);
5141 if (unlikely(Rc(ctx->opcode) != 0))
5142 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5143 }
5144
5145 /* nabso - nabso. */
5146 static void gen_nabso(DisasContext *ctx)
5147 {
5148 int l1 = gen_new_label();
5149 int l2 = gen_new_label();
5150 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5151 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5152 tcg_gen_br(l2);
5153 gen_set_label(l1);
5154 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5155 gen_set_label(l2);
5156 /* nabs never overflows */
5157 tcg_gen_movi_tl(cpu_ov, 0);
5158 if (unlikely(Rc(ctx->opcode) != 0))
5159 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5160 }
5161
5162 /* rlmi - rlmi. */
5163 static void gen_rlmi(DisasContext *ctx)
5164 {
5165 uint32_t mb = MB(ctx->opcode);
5166 uint32_t me = ME(ctx->opcode);
5167 TCGv t0 = tcg_temp_new();
5168 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5169 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5170 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5171 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5172 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5173 tcg_temp_free(t0);
5174 if (unlikely(Rc(ctx->opcode) != 0))
5175 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5176 }
5177
5178 /* rrib - rrib. */
5179 static void gen_rrib(DisasContext *ctx)
5180 {
5181 TCGv t0 = tcg_temp_new();
5182 TCGv t1 = tcg_temp_new();
5183 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5184 tcg_gen_movi_tl(t1, 0x80000000);
5185 tcg_gen_shr_tl(t1, t1, t0);
5186 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5187 tcg_gen_and_tl(t0, t0, t1);
5188 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5189 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5190 tcg_temp_free(t0);
5191 tcg_temp_free(t1);
5192 if (unlikely(Rc(ctx->opcode) != 0))
5193 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5194 }
5195
5196 /* sle - sle. */
5197 static void gen_sle(DisasContext *ctx)
5198 {
5199 TCGv t0 = tcg_temp_new();
5200 TCGv t1 = tcg_temp_new();
5201 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5202 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5203 tcg_gen_subfi_tl(t1, 32, t1);
5204 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5205 tcg_gen_or_tl(t1, t0, t1);
5206 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5207 gen_store_spr(SPR_MQ, t1);
5208 tcg_temp_free(t0);
5209 tcg_temp_free(t1);
5210 if (unlikely(Rc(ctx->opcode) != 0))
5211 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5212 }
5213
5214 /* sleq - sleq. */
5215 static void gen_sleq(DisasContext *ctx)
5216 {
5217 TCGv t0 = tcg_temp_new();
5218 TCGv t1 = tcg_temp_new();
5219 TCGv t2 = tcg_temp_new();
5220 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5221 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5222 tcg_gen_shl_tl(t2, t2, t0);
5223 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5224 gen_load_spr(t1, SPR_MQ);
5225 gen_store_spr(SPR_MQ, t0);
5226 tcg_gen_and_tl(t0, t0, t2);
5227 tcg_gen_andc_tl(t1, t1, t2);
5228 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5229 tcg_temp_free(t0);
5230 tcg_temp_free(t1);
5231 tcg_temp_free(t2);
5232 if (unlikely(Rc(ctx->opcode) != 0))
5233 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5234 }
5235
5236 /* sliq - sliq. */
5237 static void gen_sliq(DisasContext *ctx)
5238 {
5239 int sh = SH(ctx->opcode);
5240 TCGv t0 = tcg_temp_new();
5241 TCGv t1 = tcg_temp_new();
5242 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5243 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5244 tcg_gen_or_tl(t1, t0, t1);
5245 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5246 gen_store_spr(SPR_MQ, t1);
5247 tcg_temp_free(t0);
5248 tcg_temp_free(t1);
5249 if (unlikely(Rc(ctx->opcode) != 0))
5250 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5251 }
5252
5253 /* slliq - slliq. */
5254 static void gen_slliq(DisasContext *ctx)
5255 {
5256 int sh = SH(ctx->opcode);
5257 TCGv t0 = tcg_temp_new();
5258 TCGv t1 = tcg_temp_new();
5259 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5260 gen_load_spr(t1, SPR_MQ);
5261 gen_store_spr(SPR_MQ, t0);
5262 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5263 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5264 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5265 tcg_temp_free(t0);
5266 tcg_temp_free(t1);
5267 if (unlikely(Rc(ctx->opcode) != 0))
5268 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5269 }
5270
5271 /* sllq - sllq. */
5272 static void gen_sllq(DisasContext *ctx)
5273 {
5274 int l1 = gen_new_label();
5275 int l2 = gen_new_label();
5276 TCGv t0 = tcg_temp_local_new();
5277 TCGv t1 = tcg_temp_local_new();
5278 TCGv t2 = tcg_temp_local_new();
5279 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5280 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5281 tcg_gen_shl_tl(t1, t1, t2);
5282 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5283 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5284 gen_load_spr(t0, SPR_MQ);
5285 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5286 tcg_gen_br(l2);
5287 gen_set_label(l1);
5288 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5289 gen_load_spr(t2, SPR_MQ);
5290 tcg_gen_andc_tl(t1, t2, t1);
5291 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5292 gen_set_label(l2);
5293 tcg_temp_free(t0);
5294 tcg_temp_free(t1);
5295 tcg_temp_free(t2);
5296 if (unlikely(Rc(ctx->opcode) != 0))
5297 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5298 }
5299
5300 /* slq - slq. */
5301 static void gen_slq(DisasContext *ctx)
5302 {
5303 int l1 = gen_new_label();
5304 TCGv t0 = tcg_temp_new();
5305 TCGv t1 = tcg_temp_new();
5306 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5307 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5308 tcg_gen_subfi_tl(t1, 32, t1);
5309 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5310 tcg_gen_or_tl(t1, t0, t1);
5311 gen_store_spr(SPR_MQ, t1);
5312 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5313 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5314 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5315 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5316 gen_set_label(l1);
5317 tcg_temp_free(t0);
5318 tcg_temp_free(t1);
5319 if (unlikely(Rc(ctx->opcode) != 0))
5320 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5321 }
5322
5323 /* sraiq - sraiq. */
5324 static void gen_sraiq(DisasContext *ctx)
5325 {
5326 int sh = SH(ctx->opcode);
5327 int l1 = gen_new_label();
5328 TCGv t0 = tcg_temp_new();
5329 TCGv t1 = tcg_temp_new();
5330 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5331 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5332 tcg_gen_or_tl(t0, t0, t1);
5333 gen_store_spr(SPR_MQ, t0);
5334 tcg_gen_movi_tl(cpu_ca, 0);
5335 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5336 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5337 tcg_gen_movi_tl(cpu_ca, 1);
5338 gen_set_label(l1);
5339 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5340 tcg_temp_free(t0);
5341 tcg_temp_free(t1);
5342 if (unlikely(Rc(ctx->opcode) != 0))
5343 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5344 }
5345
5346 /* sraq - sraq. */
5347 static void gen_sraq(DisasContext *ctx)
5348 {
5349 int l1 = gen_new_label();
5350 int l2 = gen_new_label();
5351 TCGv t0 = tcg_temp_new();
5352 TCGv t1 = tcg_temp_local_new();
5353 TCGv t2 = tcg_temp_local_new();
5354 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5355 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5356 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5357 tcg_gen_subfi_tl(t2, 32, t2);
5358 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5359 tcg_gen_or_tl(t0, t0, t2);
5360 gen_store_spr(SPR_MQ, t0);
5361 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5362 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5363 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5364 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5365 gen_set_label(l1);
5366 tcg_temp_free(t0);
5367 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5368 tcg_gen_movi_tl(cpu_ca, 0);
5369 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5370 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5371 tcg_gen_movi_tl(cpu_ca, 1);
5372 gen_set_label(l2);
5373 tcg_temp_free(t1);
5374 tcg_temp_free(t2);
5375 if (unlikely(Rc(ctx->opcode) != 0))
5376 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5377 }
5378
5379 /* sre - sre. */
5380 static void gen_sre(DisasContext *ctx)
5381 {
5382 TCGv t0 = tcg_temp_new();
5383 TCGv t1 = tcg_temp_new();
5384 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5385 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5386 tcg_gen_subfi_tl(t1, 32, t1);
5387 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5388 tcg_gen_or_tl(t1, t0, t1);
5389 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5390 gen_store_spr(SPR_MQ, t1);
5391 tcg_temp_free(t0);
5392 tcg_temp_free(t1);
5393 if (unlikely(Rc(ctx->opcode) != 0))
5394 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5395 }
5396
5397 /* srea - srea. */
5398 static void gen_srea(DisasContext *ctx)
5399 {
5400 TCGv t0 = tcg_temp_new();
5401 TCGv t1 = tcg_temp_new();
5402 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5403 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5404 gen_store_spr(SPR_MQ, t0);
5405 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5406 tcg_temp_free(t0);
5407 tcg_temp_free(t1);
5408 if (unlikely(Rc(ctx->opcode) != 0))
5409 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5410 }
5411
5412 /* sreq */
5413 static void gen_sreq(DisasContext *ctx)
5414 {
5415 TCGv t0 = tcg_temp_new();
5416 TCGv t1 = tcg_temp_new();
5417 TCGv t2 = tcg_temp_new();
5418 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5419 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5420 tcg_gen_shr_tl(t1, t1, t0);
5421 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5422 gen_load_spr(t2, SPR_MQ);
5423 gen_store_spr(SPR_MQ, t0);
5424 tcg_gen_and_tl(t0, t0, t1);
5425 tcg_gen_andc_tl(t2, t2, t1);
5426 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5427 tcg_temp_free(t0);
5428 tcg_temp_free(t1);
5429 tcg_temp_free(t2);
5430 if (unlikely(Rc(ctx->opcode) != 0))
5431 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5432 }
5433
5434 /* sriq */
5435 static void gen_sriq(DisasContext *ctx)
5436 {
5437 int sh = SH(ctx->opcode);
5438 TCGv t0 = tcg_temp_new();
5439 TCGv t1 = tcg_temp_new();
5440 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5441 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5442 tcg_gen_or_tl(t1, t0, t1);
5443 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5444 gen_store_spr(SPR_MQ, t1);
5445 tcg_temp_free(t0);
5446 tcg_temp_free(t1);
5447 if (unlikely(Rc(ctx->opcode) != 0))
5448 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5449 }
5450
5451 /* srliq */
5452 static void gen_srliq(DisasContext *ctx)
5453 {
5454 int sh = SH(ctx->opcode);
5455 TCGv t0 = tcg_temp_new();
5456 TCGv t1 = tcg_temp_new();
5457 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5458 gen_load_spr(t1, SPR_MQ);
5459 gen_store_spr(SPR_MQ, t0);
5460 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5461 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5462 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5463 tcg_temp_free(t0);
5464 tcg_temp_free(t1);
5465 if (unlikely(Rc(ctx->opcode) != 0))
5466 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5467 }
5468
5469 /* srlq */
5470 static void gen_srlq(DisasContext *ctx)
5471 {
5472 int l1 = gen_new_label();
5473 int l2 = gen_new_label();
5474 TCGv t0 = tcg_temp_local_new();
5475 TCGv t1 = tcg_temp_local_new();
5476 TCGv t2 = tcg_temp_local_new();
5477 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5478 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5479 tcg_gen_shr_tl(t2, t1, t2);
5480 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5481 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5482 gen_load_spr(t0, SPR_MQ);
5483 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5484 tcg_gen_br(l2);
5485 gen_set_label(l1);
5486 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5487 tcg_gen_and_tl(t0, t0, t2);
5488 gen_load_spr(t1, SPR_MQ);
5489 tcg_gen_andc_tl(t1, t1, t2);
5490 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5491 gen_set_label(l2);
5492 tcg_temp_free(t0);
5493 tcg_temp_free(t1);
5494 tcg_temp_free(t2);
5495 if (unlikely(Rc(ctx->opcode) != 0))
5496 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5497 }
5498
5499 /* srq */
5500 static void gen_srq(DisasContext *ctx)
5501 {
5502 int l1 = gen_new_label();
5503 TCGv t0 = tcg_temp_new();
5504 TCGv t1 = tcg_temp_new();
5505 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5506 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5507 tcg_gen_subfi_tl(t1, 32, t1);
5508 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5509 tcg_gen_or_tl(t1, t0, t1);
5510 gen_store_spr(SPR_MQ, t1);
5511 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5512 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5513 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5514 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5515 gen_set_label(l1);
5516 tcg_temp_free(t0);
5517 tcg_temp_free(t1);
5518 if (unlikely(Rc(ctx->opcode) != 0))
5519 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5520 }
5521
5522 /* PowerPC 602 specific instructions */
5523
5524 /* dsa */
5525 static void gen_dsa(DisasContext *ctx)
5526 {
5527 /* XXX: TODO */
5528 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5529 }
5530
5531 /* esa */
5532 static void gen_esa(DisasContext *ctx)
5533 {
5534 /* XXX: TODO */
5535 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5536 }
5537
5538 /* mfrom */
5539 static void gen_mfrom(DisasContext *ctx)
5540 {
5541 #if defined(CONFIG_USER_ONLY)
5542 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5543 #else
5544 if (unlikely(ctx->pr)) {
5545 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5546 return;
5547 }
5548 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5549 #endif
5550 }
5551
5552 /* 602 - 603 - G2 TLB management */
5553
5554 /* tlbld */
5555 static void gen_tlbld_6xx(DisasContext *ctx)
5556 {
5557 #if defined(CONFIG_USER_ONLY)
5558 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5559 #else
5560 if (unlikely(ctx->pr)) {
5561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5562 return;
5563 }
5564 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5565 #endif
5566 }
5567
5568 /* tlbli */
5569 static void gen_tlbli_6xx(DisasContext *ctx)
5570 {
5571 #if defined(CONFIG_USER_ONLY)
5572 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5573 #else
5574 if (unlikely(ctx->pr)) {
5575 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5576 return;
5577 }
5578 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5579 #endif
5580 }
5581
5582 /* 74xx TLB management */
5583
5584 /* tlbld */
5585 static void gen_tlbld_74xx(DisasContext *ctx)
5586 {
5587 #if defined(CONFIG_USER_ONLY)
5588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5589 #else
5590 if (unlikely(ctx->pr)) {
5591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5592 return;
5593 }
5594 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5595 #endif
5596 }
5597
5598 /* tlbli */
5599 static void gen_tlbli_74xx(DisasContext *ctx)
5600 {
5601 #if defined(CONFIG_USER_ONLY)
5602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5603 #else
5604 if (unlikely(ctx->pr)) {
5605 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5606 return;
5607 }
5608 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5609 #endif
5610 }
5611
5612 /* POWER instructions not in PowerPC 601 */
5613
5614 /* clf */
5615 static void gen_clf(DisasContext *ctx)
5616 {
5617 /* Cache line flush: implemented as no-op */
5618 }
5619
5620 /* cli */
5621 static void gen_cli(DisasContext *ctx)
5622 {
5623 /* Cache line invalidate: privileged and treated as no-op */
5624 #if defined(CONFIG_USER_ONLY)
5625 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5626 #else
5627 if (unlikely(ctx->pr)) {
5628 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5629 return;
5630 }
5631 #endif
5632 }
5633
5634 /* dclst */
5635 static void gen_dclst(DisasContext *ctx)
5636 {
5637 /* Data cache line store: treated as no-op */
5638 }
5639
5640 static void gen_mfsri(DisasContext *ctx)
5641 {
5642 #if defined(CONFIG_USER_ONLY)
5643 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5644 #else
5645 int ra = rA(ctx->opcode);
5646 int rd = rD(ctx->opcode);
5647 TCGv t0;
5648 if (unlikely(ctx->pr)) {
5649 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5650 return;
5651 }
5652 t0 = tcg_temp_new();
5653 gen_addr_reg_index(ctx, t0);
5654 tcg_gen_shri_tl(t0, t0, 28);
5655 tcg_gen_andi_tl(t0, t0, 0xF);
5656 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5657 tcg_temp_free(t0);
5658 if (ra != 0 && ra != rd)
5659 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5660 #endif
5661 }
5662
5663 static void gen_rac(DisasContext *ctx)
5664 {
5665 #if defined(CONFIG_USER_ONLY)
5666 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5667 #else
5668 TCGv t0;
5669 if (unlikely(ctx->pr)) {
5670 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5671 return;
5672 }
5673 t0 = tcg_temp_new();
5674 gen_addr_reg_index(ctx, t0);
5675 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5676 tcg_temp_free(t0);
5677 #endif
5678 }
5679
5680 static void gen_rfsvc(DisasContext *ctx)
5681 {
5682 #if defined(CONFIG_USER_ONLY)
5683 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5684 #else
5685 if (unlikely(ctx->pr)) {
5686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5687 return;
5688 }
5689 gen_helper_rfsvc(cpu_env);
5690 gen_sync_exception(ctx);
5691 #endif
5692 }
5693
5694 /* svc is not implemented for now */
5695
5696 /* POWER2 specific instructions */
5697 /* Quad manipulation (load/store two floats at a time) */
5698
5699 /* lfq */
5700 static void gen_lfq(DisasContext *ctx)
5701 {
5702 int rd = rD(ctx->opcode);
5703 TCGv t0;
5704 gen_set_access_type(ctx, ACCESS_FLOAT);
5705 t0 = tcg_temp_new();
5706 gen_addr_imm_index(ctx, t0, 0);
5707 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5708 gen_addr_add(ctx, t0, t0, 8);
5709 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5710 tcg_temp_free(t0);
5711 }
5712
5713 /* lfqu */
5714 static void gen_lfqu(DisasContext *ctx)
5715 {
5716 int ra = rA(ctx->opcode);
5717 int rd = rD(ctx->opcode);
5718 TCGv t0, t1;
5719 gen_set_access_type(ctx, ACCESS_FLOAT);
5720 t0 = tcg_temp_new();
5721 t1 = tcg_temp_new();
5722 gen_addr_imm_index(ctx, t0, 0);
5723 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5724 gen_addr_add(ctx, t1, t0, 8);
5725 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5726 if (ra != 0)
5727 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5728 tcg_temp_free(t0);
5729 tcg_temp_free(t1);
5730 }
5731
5732 /* lfqux */
5733 static void gen_lfqux(DisasContext *ctx)
5734 {
5735 int ra = rA(ctx->opcode);
5736 int rd = rD(ctx->opcode);
5737 gen_set_access_type(ctx, ACCESS_FLOAT);
5738 TCGv t0, t1;
5739 t0 = tcg_temp_new();
5740 gen_addr_reg_index(ctx, t0);
5741 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5742 t1 = tcg_temp_new();
5743 gen_addr_add(ctx, t1, t0, 8);
5744 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5745 tcg_temp_free(t1);
5746 if (ra != 0)
5747 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5748 tcg_temp_free(t0);
5749 }
5750
5751 /* lfqx */
5752 static void gen_lfqx(DisasContext *ctx)
5753 {
5754 int rd = rD(ctx->opcode);
5755 TCGv t0;
5756 gen_set_access_type(ctx, ACCESS_FLOAT);
5757 t0 = tcg_temp_new();
5758 gen_addr_reg_index(ctx, t0);
5759 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5760 gen_addr_add(ctx, t0, t0, 8);
5761 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5762 tcg_temp_free(t0);
5763 }
5764
5765 /* stfq */
5766 static void gen_stfq(DisasContext *ctx)
5767 {
5768 int rd = rD(ctx->opcode);
5769 TCGv t0;
5770 gen_set_access_type(ctx, ACCESS_FLOAT);
5771 t0 = tcg_temp_new();
5772 gen_addr_imm_index(ctx, t0, 0);
5773 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5774 gen_addr_add(ctx, t0, t0, 8);
5775 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5776 tcg_temp_free(t0);
5777 }
5778
5779 /* stfqu */
5780 static void gen_stfqu(DisasContext *ctx)
5781 {
5782 int ra = rA(ctx->opcode);
5783 int rd = rD(ctx->opcode);
5784 TCGv t0, t1;
5785 gen_set_access_type(ctx, ACCESS_FLOAT);
5786 t0 = tcg_temp_new();
5787 gen_addr_imm_index(ctx, t0, 0);
5788 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5789 t1 = tcg_temp_new();
5790 gen_addr_add(ctx, t1, t0, 8);
5791 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5792 tcg_temp_free(t1);
5793 if (ra != 0)
5794 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5795 tcg_temp_free(t0);
5796 }
5797
5798 /* stfqux */
5799 static void gen_stfqux(DisasContext *ctx)
5800 {
5801 int ra = rA(ctx->opcode);
5802 int rd = rD(ctx->opcode);
5803 TCGv t0, t1;
5804 gen_set_access_type(ctx, ACCESS_FLOAT);
5805 t0 = tcg_temp_new();
5806 gen_addr_reg_index(ctx, t0);
5807 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5808 t1 = tcg_temp_new();
5809 gen_addr_add(ctx, t1, t0, 8);
5810 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5811 tcg_temp_free(t1);
5812 if (ra != 0)
5813 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5814 tcg_temp_free(t0);
5815 }
5816
5817 /* stfqx */
5818 static void gen_stfqx(DisasContext *ctx)
5819 {
5820 int rd = rD(ctx->opcode);
5821 TCGv t0;
5822 gen_set_access_type(ctx, ACCESS_FLOAT);
5823 t0 = tcg_temp_new();
5824 gen_addr_reg_index(ctx, t0);
5825 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5826 gen_addr_add(ctx, t0, t0, 8);
5827 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5828 tcg_temp_free(t0);
5829 }
5830
5831 /* BookE specific instructions */
5832
5833 /* XXX: not implemented on 440 ? */
5834 static void gen_mfapidi(DisasContext *ctx)
5835 {
5836 /* XXX: TODO */
5837 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5838 }
5839
5840 /* XXX: not implemented on 440 ? */
5841 static void gen_tlbiva(DisasContext *ctx)
5842 {
5843 #if defined(CONFIG_USER_ONLY)
5844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5845 #else
5846 TCGv t0;
5847 if (unlikely(ctx->pr)) {
5848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5849 return;
5850 }
5851 t0 = tcg_temp_new();
5852 gen_addr_reg_index(ctx, t0);
5853 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5854 tcg_temp_free(t0);
5855 #endif
5856 }
5857
5858 /* All 405 MAC instructions are translated here */
5859 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5860 int ra, int rb, int rt, int Rc)
5861 {
5862 TCGv t0, t1;
5863
5864 t0 = tcg_temp_local_new();
5865 t1 = tcg_temp_local_new();
5866
5867 switch (opc3 & 0x0D) {
5868 case 0x05:
5869 /* macchw - macchw. - macchwo - macchwo. */
5870 /* macchws - macchws. - macchwso - macchwso. */
5871 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5872 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5873 /* mulchw - mulchw. */
5874 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5875 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5876 tcg_gen_ext16s_tl(t1, t1);
5877 break;
5878 case 0x04:
5879 /* macchwu - macchwu. - macchwuo - macchwuo. */
5880 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5881 /* mulchwu - mulchwu. */
5882 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5883 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5884 tcg_gen_ext16u_tl(t1, t1);
5885 break;
5886 case 0x01:
5887 /* machhw - machhw. - machhwo - machhwo. */
5888 /* machhws - machhws. - machhwso - machhwso. */
5889 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5890 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5891 /* mulhhw - mulhhw. */
5892 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5893 tcg_gen_ext16s_tl(t0, t0);
5894 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5895 tcg_gen_ext16s_tl(t1, t1);
5896 break;
5897 case 0x00:
5898 /* machhwu - machhwu. - machhwuo - machhwuo. */
5899 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5900 /* mulhhwu - mulhhwu. */
5901 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5902 tcg_gen_ext16u_tl(t0, t0);
5903 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5904 tcg_gen_ext16u_tl(t1, t1);
5905 break;
5906 case 0x0D:
5907 /* maclhw - maclhw. - maclhwo - maclhwo. */
5908 /* maclhws - maclhws. - maclhwso - maclhwso. */
5909 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5910 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5911 /* mullhw - mullhw. */
5912 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5913 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5914 break;
5915 case 0x0C:
5916 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5917 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5918 /* mullhwu - mullhwu. */
5919 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5920 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5921 break;
5922 }
5923 if (opc2 & 0x04) {
5924 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5925 tcg_gen_mul_tl(t1, t0, t1);
5926 if (opc2 & 0x02) {
5927 /* nmultiply-and-accumulate (0x0E) */
5928 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5929 } else {
5930 /* multiply-and-accumulate (0x0C) */
5931 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5932 }
5933
5934 if (opc3 & 0x12) {
5935 /* Check overflow and/or saturate */
5936 int l1 = gen_new_label();
5937
5938 if (opc3 & 0x10) {
5939 /* Start with XER OV disabled, the most likely case */
5940 tcg_gen_movi_tl(cpu_ov, 0);
5941 }
5942 if (opc3 & 0x01) {
5943 /* Signed */
5944 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5945 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5946 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5947 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5948 if (opc3 & 0x02) {
5949 /* Saturate */
5950 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5951 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5952 }
5953 } else {
5954 /* Unsigned */
5955 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5956 if (opc3 & 0x02) {
5957 /* Saturate */
5958 tcg_gen_movi_tl(t0, UINT32_MAX);
5959 }
5960 }
5961 if (opc3 & 0x10) {
5962 /* Check overflow */
5963 tcg_gen_movi_tl(cpu_ov, 1);
5964 tcg_gen_movi_tl(cpu_so, 1);
5965 }
5966 gen_set_label(l1);
5967 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5968 }
5969 } else {
5970 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5971 }
5972 tcg_temp_free(t0);
5973 tcg_temp_free(t1);
5974 if (unlikely(Rc) != 0) {
5975 /* Update Rc0 */
5976 gen_set_Rc0(ctx, cpu_gpr[rt]);
5977 }
5978 }
5979
5980 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5981 static void glue(gen_, name)(DisasContext *ctx) \
5982 { \
5983 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5984 rD(ctx->opcode), Rc(ctx->opcode)); \
5985 }
5986
5987 /* macchw - macchw. */
5988 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5989 /* macchwo - macchwo. */
5990 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5991 /* macchws - macchws. */
5992 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5993 /* macchwso - macchwso. */
5994 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5995 /* macchwsu - macchwsu. */
5996 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5997 /* macchwsuo - macchwsuo. */
5998 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5999 /* macchwu - macchwu. */
6000 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6001 /* macchwuo - macchwuo. */
6002 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6003 /* machhw - machhw. */
6004 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6005 /* machhwo - machhwo. */
6006 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6007 /* machhws - machhws. */
6008 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6009 /* machhwso - machhwso. */
6010 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6011 /* machhwsu - machhwsu. */
6012 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6013 /* machhwsuo - machhwsuo. */
6014 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6015 /* machhwu - machhwu. */
6016 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6017 /* machhwuo - machhwuo. */
6018 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6019 /* maclhw - maclhw. */
6020 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6021 /* maclhwo - maclhwo. */
6022 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6023 /* maclhws - maclhws. */
6024 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6025 /* maclhwso - maclhwso. */
6026 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6027 /* maclhwu - maclhwu. */
6028 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6029 /* maclhwuo - maclhwuo. */
6030 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6031 /* maclhwsu - maclhwsu. */
6032 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6033 /* maclhwsuo - maclhwsuo. */
6034 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6035 /* nmacchw - nmacchw. */
6036 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6037 /* nmacchwo - nmacchwo. */
6038 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6039 /* nmacchws - nmacchws. */
6040 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6041 /* nmacchwso - nmacchwso. */
6042 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6043 /* nmachhw - nmachhw. */
6044 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6045 /* nmachhwo - nmachhwo. */
6046 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6047 /* nmachhws - nmachhws. */
6048 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6049 /* nmachhwso - nmachhwso. */
6050 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6051 /* nmaclhw - nmaclhw. */
6052 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6053 /* nmaclhwo - nmaclhwo. */
6054 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6055 /* nmaclhws - nmaclhws. */
6056 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6057 /* nmaclhwso - nmaclhwso. */
6058 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6059
6060 /* mulchw - mulchw. */
6061 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6062 /* mulchwu - mulchwu. */
6063 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6064 /* mulhhw - mulhhw. */
6065 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6066 /* mulhhwu - mulhhwu. */
6067 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6068 /* mullhw - mullhw. */
6069 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6070 /* mullhwu - mullhwu. */
6071 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6072
6073 /* mfdcr */
6074 static void gen_mfdcr(DisasContext *ctx)
6075 {
6076 #if defined(CONFIG_USER_ONLY)
6077 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6078 #else
6079 TCGv dcrn;
6080 if (unlikely(ctx->pr)) {
6081 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6082 return;
6083 }
6084 /* NIP cannot be restored if the memory exception comes from an helper */
6085 gen_update_nip(ctx, ctx->nip - 4);
6086 dcrn = tcg_const_tl(SPR(ctx->opcode));
6087 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6088 tcg_temp_free(dcrn);
6089 #endif
6090 }
6091
6092 /* mtdcr */
6093 static void gen_mtdcr(DisasContext *ctx)
6094 {
6095 #if defined(CONFIG_USER_ONLY)
6096 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6097 #else
6098 TCGv dcrn;
6099 if (unlikely(ctx->pr)) {
6100 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6101 return;
6102 }
6103 /* NIP cannot be restored if the memory exception comes from an helper */
6104 gen_update_nip(ctx, ctx->nip - 4);
6105 dcrn = tcg_const_tl(SPR(ctx->opcode));
6106 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6107 tcg_temp_free(dcrn);
6108 #endif
6109 }
6110
6111 /* mfdcrx */
6112 /* XXX: not implemented on 440 ? */
6113 static void gen_mfdcrx(DisasContext *ctx)
6114 {
6115 #if defined(CONFIG_USER_ONLY)
6116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6117 #else
6118 if (unlikely(ctx->pr)) {
6119 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6120 return;
6121 }
6122 /* NIP cannot be restored if the memory exception comes from an helper */
6123 gen_update_nip(ctx, ctx->nip - 4);
6124 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6125 cpu_gpr[rA(ctx->opcode)]);
6126 /* Note: Rc update flag set leads to undefined state of Rc0 */
6127 #endif
6128 }
6129
6130 /* mtdcrx */
6131 /* XXX: not implemented on 440 ? */
6132 static void gen_mtdcrx(DisasContext *ctx)
6133 {
6134 #if defined(CONFIG_USER_ONLY)
6135 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6136 #else
6137 if (unlikely(ctx->pr)) {
6138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6139 return;
6140 }
6141 /* NIP cannot be restored if the memory exception comes from an helper */
6142 gen_update_nip(ctx, ctx->nip - 4);
6143 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6144 cpu_gpr[rS(ctx->opcode)]);
6145 /* Note: Rc update flag set leads to undefined state of Rc0 */
6146 #endif
6147 }
6148
6149 /* mfdcrux (PPC 460) : user-mode access to DCR */
6150 static void gen_mfdcrux(DisasContext *ctx)
6151 {
6152 /* NIP cannot be restored if the memory exception comes from an helper */
6153 gen_update_nip(ctx, ctx->nip - 4);
6154 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6155 cpu_gpr[rA(ctx->opcode)]);
6156 /* Note: Rc update flag set leads to undefined state of Rc0 */
6157 }
6158
6159 /* mtdcrux (PPC 460) : user-mode access to DCR */
6160 static void gen_mtdcrux(DisasContext *ctx)
6161 {
6162 /* NIP cannot be restored if the memory exception comes from an helper */
6163 gen_update_nip(ctx, ctx->nip - 4);
6164 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6165 cpu_gpr[rS(ctx->opcode)]);
6166 /* Note: Rc update flag set leads to undefined state of Rc0 */
6167 }
6168
6169 /* dccci */
6170 static void gen_dccci(DisasContext *ctx)
6171 {
6172 #if defined(CONFIG_USER_ONLY)
6173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6174 #else
6175 if (unlikely(ctx->pr)) {
6176 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6177 return;
6178 }
6179 /* interpreted as no-op */
6180 #endif
6181 }
6182
6183 /* dcread */
6184 static void gen_dcread(DisasContext *ctx)
6185 {
6186 #if defined(CONFIG_USER_ONLY)
6187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6188 #else
6189 TCGv EA, val;
6190 if (unlikely(ctx->pr)) {
6191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6192 return;
6193 }
6194 gen_set_access_type(ctx, ACCESS_CACHE);
6195 EA = tcg_temp_new();
6196 gen_addr_reg_index(ctx, EA);
6197 val = tcg_temp_new();
6198 gen_qemu_ld32u(ctx, val, EA);
6199 tcg_temp_free(val);
6200 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6201 tcg_temp_free(EA);
6202 #endif
6203 }
6204
6205 /* icbt */
6206 static void gen_icbt_40x(DisasContext *ctx)
6207 {
6208 /* interpreted as no-op */
6209 /* XXX: specification say this is treated as a load by the MMU
6210 * but does not generate any exception
6211 */
6212 }
6213
6214 /* iccci */
6215 static void gen_iccci(DisasContext *ctx)
6216 {
6217 #if defined(CONFIG_USER_ONLY)
6218 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6219 #else
6220 if (unlikely(ctx->pr)) {
6221 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6222 return;
6223 }
6224 /* interpreted as no-op */
6225 #endif
6226 }
6227
6228 /* icread */
6229 static void gen_icread(DisasContext *ctx)
6230 {
6231 #if defined(CONFIG_USER_ONLY)
6232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6233 #else
6234 if (unlikely(ctx->pr)) {
6235 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6236 return;
6237 }
6238 /* interpreted as no-op */
6239 #endif
6240 }
6241
6242 /* rfci (supervisor only) */
6243 static void gen_rfci_40x(DisasContext *ctx)
6244 {
6245 #if defined(CONFIG_USER_ONLY)
6246 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6247 #else
6248 if (unlikely(ctx->pr)) {
6249 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6250 return;
6251 }
6252 /* Restore CPU state */
6253 gen_helper_40x_rfci(cpu_env);
6254 gen_sync_exception(ctx);
6255 #endif
6256 }
6257
6258 static void gen_rfci(DisasContext *ctx)
6259 {
6260 #if defined(CONFIG_USER_ONLY)
6261 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6262 #else
6263 if (unlikely(ctx->pr)) {
6264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6265 return;
6266 }
6267 /* Restore CPU state */
6268 gen_helper_rfci(cpu_env);
6269 gen_sync_exception(ctx);
6270 #endif
6271 }
6272
6273 /* BookE specific */
6274
6275 /* XXX: not implemented on 440 ? */
6276 static void gen_rfdi(DisasContext *ctx)
6277 {
6278 #if defined(CONFIG_USER_ONLY)
6279 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6280 #else
6281 if (unlikely(ctx->pr)) {
6282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6283 return;
6284 }
6285 /* Restore CPU state */
6286 gen_helper_rfdi(cpu_env);
6287 gen_sync_exception(ctx);
6288 #endif
6289 }
6290
6291 /* XXX: not implemented on 440 ? */
6292 static void gen_rfmci(DisasContext *ctx)
6293 {
6294 #if defined(CONFIG_USER_ONLY)
6295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6296 #else
6297 if (unlikely(ctx->pr)) {
6298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6299 return;
6300 }
6301 /* Restore CPU state */
6302 gen_helper_rfmci(cpu_env);
6303 gen_sync_exception(ctx);
6304 #endif
6305 }
6306
6307 /* TLB management - PowerPC 405 implementation */
6308
6309 /* tlbre */
6310 static void gen_tlbre_40x(DisasContext *ctx)
6311 {
6312 #if defined(CONFIG_USER_ONLY)
6313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6314 #else
6315 if (unlikely(ctx->pr)) {
6316 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6317 return;
6318 }
6319 switch (rB(ctx->opcode)) {
6320 case 0:
6321 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6322 cpu_gpr[rA(ctx->opcode)]);
6323 break;
6324 case 1:
6325 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6326 cpu_gpr[rA(ctx->opcode)]);
6327 break;
6328 default:
6329 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6330 break;
6331 }
6332 #endif
6333 }
6334
6335 /* tlbsx - tlbsx. */
6336 static void gen_tlbsx_40x(DisasContext *ctx)
6337 {
6338 #if defined(CONFIG_USER_ONLY)
6339 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6340 #else
6341 TCGv t0;
6342 if (unlikely(ctx->pr)) {
6343 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6344 return;
6345 }
6346 t0 = tcg_temp_new();
6347 gen_addr_reg_index(ctx, t0);
6348 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6349 tcg_temp_free(t0);
6350 if (Rc(ctx->opcode)) {
6351 int l1 = gen_new_label();
6352 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6353 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6354 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6355 gen_set_label(l1);
6356 }
6357 #endif
6358 }
6359
6360 /* tlbwe */
6361 static void gen_tlbwe_40x(DisasContext *ctx)
6362 {
6363 #if defined(CONFIG_USER_ONLY)
6364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6365 #else
6366 if (unlikely(ctx->pr)) {
6367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6368 return;
6369 }
6370 switch (rB(ctx->opcode)) {
6371 case 0:
6372 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6373 cpu_gpr[rS(ctx->opcode)]);
6374 break;
6375 case 1:
6376 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6377 cpu_gpr[rS(ctx->opcode)]);
6378 break;
6379 default:
6380 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6381 break;
6382 }
6383 #endif
6384 }
6385
6386 /* TLB management - PowerPC 440 implementation */
6387
6388 /* tlbre */
6389 static void gen_tlbre_440(DisasContext *ctx)
6390 {
6391 #if defined(CONFIG_USER_ONLY)
6392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6393 #else
6394 if (unlikely(ctx->pr)) {
6395 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6396 return;
6397 }
6398 switch (rB(ctx->opcode)) {
6399 case 0:
6400 case 1:
6401 case 2:
6402 {
6403 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6404 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6405 t0, cpu_gpr[rA(ctx->opcode)]);
6406 tcg_temp_free_i32(t0);
6407 }
6408 break;
6409 default:
6410 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6411 break;
6412 }
6413 #endif
6414 }
6415
6416 /* tlbsx - tlbsx. */
6417 static void gen_tlbsx_440(DisasContext *ctx)
6418 {
6419 #if defined(CONFIG_USER_ONLY)
6420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6421 #else
6422 TCGv t0;
6423 if (unlikely(ctx->pr)) {
6424 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6425 return;
6426 }
6427 t0 = tcg_temp_new();
6428 gen_addr_reg_index(ctx, t0);
6429 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6430 tcg_temp_free(t0);
6431 if (Rc(ctx->opcode)) {
6432 int l1 = gen_new_label();
6433 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6434 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6435 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6436 gen_set_label(l1);
6437 }
6438 #endif
6439 }
6440
6441 /* tlbwe */
6442 static void gen_tlbwe_440(DisasContext *ctx)
6443 {
6444 #if defined(CONFIG_USER_ONLY)
6445 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6446 #else
6447 if (unlikely(ctx->pr)) {
6448 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6449 return;
6450 }
6451 switch (rB(ctx->opcode)) {
6452 case 0:
6453 case 1:
6454 case 2:
6455 {
6456 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6457 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6458 cpu_gpr[rS(ctx->opcode)]);
6459 tcg_temp_free_i32(t0);
6460 }
6461 break;
6462 default:
6463 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6464 break;
6465 }
6466 #endif
6467 }
6468
6469 /* TLB management - PowerPC BookE 2.06 implementation */
6470
6471 /* tlbre */
6472 static void gen_tlbre_booke206(DisasContext *ctx)
6473 {
6474 #if defined(CONFIG_USER_ONLY)
6475 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6476 #else
6477 if (unlikely(ctx->pr)) {
6478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6479 return;
6480 }
6481
6482 gen_helper_booke206_tlbre(cpu_env);
6483 #endif
6484 }
6485
6486 /* tlbsx - tlbsx. */
6487 static void gen_tlbsx_booke206(DisasContext *ctx)
6488 {
6489 #if defined(CONFIG_USER_ONLY)
6490 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6491 #else
6492 TCGv t0;
6493 if (unlikely(ctx->pr)) {
6494 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6495 return;
6496 }
6497
6498 if (rA(ctx->opcode)) {
6499 t0 = tcg_temp_new();
6500 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6501 } else {
6502 t0 = tcg_const_tl(0);
6503 }
6504
6505 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6506 gen_helper_booke206_tlbsx(cpu_env, t0);
6507 tcg_temp_free(t0);
6508 #endif
6509 }
6510
6511 /* tlbwe */
6512 static void gen_tlbwe_booke206(DisasContext *ctx)
6513 {
6514 #if defined(CONFIG_USER_ONLY)
6515 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6516 #else
6517 if (unlikely(ctx->pr)) {
6518 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6519 return;
6520 }
6521 gen_update_nip(ctx, ctx->nip - 4);
6522 gen_helper_booke206_tlbwe(cpu_env);
6523 #endif
6524 }
6525
6526 static void gen_tlbivax_booke206(DisasContext *ctx)
6527 {
6528 #if defined(CONFIG_USER_ONLY)
6529 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6530 #else
6531 TCGv t0;
6532 if (unlikely(ctx->pr)) {
6533 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6534 return;
6535 }
6536
6537 t0 = tcg_temp_new();
6538 gen_addr_reg_index(ctx, t0);
6539
6540 gen_helper_booke206_tlbivax(cpu_env, t0);
6541 tcg_temp_free(t0);
6542 #endif
6543 }
6544
6545 static void gen_tlbilx_booke206(DisasContext *ctx)
6546 {
6547 #if defined(CONFIG_USER_ONLY)
6548 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6549 #else
6550 TCGv t0;
6551 if (unlikely(ctx->pr)) {
6552 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6553 return;
6554 }
6555
6556 t0 = tcg_temp_new();
6557 gen_addr_reg_index(ctx, t0);
6558
6559 switch((ctx->opcode >> 21) & 0x3) {
6560 case 0:
6561 gen_helper_booke206_tlbilx0(cpu_env, t0);
6562 break;
6563 case 1:
6564 gen_helper_booke206_tlbilx1(cpu_env, t0);
6565 break;
6566 case 3:
6567 gen_helper_booke206_tlbilx3(cpu_env, t0);
6568 break;
6569 default:
6570 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6571 break;
6572 }
6573
6574 tcg_temp_free(t0);
6575 #endif
6576 }
6577
6578
6579 /* wrtee */
6580 static void gen_wrtee(DisasContext *ctx)
6581 {
6582 #if defined(CONFIG_USER_ONLY)
6583 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6584 #else
6585 TCGv t0;
6586 if (unlikely(ctx->pr)) {
6587 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6588 return;
6589 }
6590 t0 = tcg_temp_new();
6591 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6592 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6593 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6594 tcg_temp_free(t0);
6595 /* Stop translation to have a chance to raise an exception
6596 * if we just set msr_ee to 1
6597 */
6598 gen_stop_exception(ctx);
6599 #endif
6600 }
6601
6602 /* wrteei */
6603 static void gen_wrteei(DisasContext *ctx)
6604 {
6605 #if defined(CONFIG_USER_ONLY)
6606 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6607 #else
6608 if (unlikely(ctx->pr)) {
6609 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6610 return;
6611 }
6612 if (ctx->opcode & 0x00008000) {
6613 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6614 /* Stop translation to have a chance to raise an exception */
6615 gen_stop_exception(ctx);
6616 } else {
6617 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6618 }
6619 #endif
6620 }
6621
6622 /* PowerPC 440 specific instructions */
6623
6624 /* dlmzb */
6625 static void gen_dlmzb(DisasContext *ctx)
6626 {
6627 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6628 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6629 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6630 tcg_temp_free_i32(t0);
6631 }
6632
6633 /* mbar replaces eieio on 440 */
6634 static void gen_mbar(DisasContext *ctx)
6635 {
6636 /* interpreted as no-op */
6637 }
6638
6639 /* msync replaces sync on 440 */
6640 static void gen_msync_4xx(DisasContext *ctx)
6641 {
6642 /* interpreted as no-op */
6643 }
6644
6645 /* icbt */
6646 static void gen_icbt_440(DisasContext *ctx)
6647 {
6648 /* interpreted as no-op */
6649 /* XXX: specification say this is treated as a load by the MMU
6650 * but does not generate any exception
6651 */
6652 }
6653
6654 /* Embedded.Processor Control */
6655
6656 static void gen_msgclr(DisasContext *ctx)
6657 {
6658 #if defined(CONFIG_USER_ONLY)
6659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6660 #else
6661 if (unlikely(ctx->pr)) {
6662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6663 return;
6664 }
6665
6666 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6667 #endif
6668 }
6669
6670 static void gen_msgsnd(DisasContext *ctx)
6671 {
6672 #if defined(CONFIG_USER_ONLY)
6673 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6674 #else
6675 if (unlikely(ctx->pr)) {
6676 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6677 return;
6678 }
6679
6680 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6681 #endif
6682 }
6683
6684 /*** Altivec vector extension ***/
6685 /* Altivec registers moves */
6686
6687 static inline TCGv_ptr gen_avr_ptr(int reg)
6688 {
6689 TCGv_ptr r = tcg_temp_new_ptr();
6690 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6691 return r;
6692 }
6693
6694 #define GEN_VR_LDX(name, opc2, opc3) \
6695 static void glue(gen_, name)(DisasContext *ctx) \
6696 { \
6697 TCGv EA; \
6698 if (unlikely(!ctx->altivec_enabled)) { \
6699 gen_exception(ctx, POWERPC_EXCP_VPU); \
6700 return; \
6701 } \
6702 gen_set_access_type(ctx, ACCESS_INT); \
6703 EA = tcg_temp_new(); \
6704 gen_addr_reg_index(ctx, EA); \
6705 tcg_gen_andi_tl(EA, EA, ~0xf); \
6706 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6707 64-bit byteswap already. */ \
6708 if (ctx->le_mode) { \
6709 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6710 tcg_gen_addi_tl(EA, EA, 8); \
6711 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6712 } else { \
6713 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6714 tcg_gen_addi_tl(EA, EA, 8); \
6715 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6716 } \
6717 tcg_temp_free(EA); \
6718 }
6719
6720 #define GEN_VR_STX(name, opc2, opc3) \
6721 static void gen_st##name(DisasContext *ctx) \
6722 { \
6723 TCGv EA; \
6724 if (unlikely(!ctx->altivec_enabled)) { \
6725 gen_exception(ctx, POWERPC_EXCP_VPU); \
6726 return; \
6727 } \
6728 gen_set_access_type(ctx, ACCESS_INT); \
6729 EA = tcg_temp_new(); \
6730 gen_addr_reg_index(ctx, EA); \
6731 tcg_gen_andi_tl(EA, EA, ~0xf); \
6732 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6733 64-bit byteswap already. */ \
6734 if (ctx->le_mode) { \
6735 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6736 tcg_gen_addi_tl(EA, EA, 8); \
6737 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6738 } else { \
6739 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6740 tcg_gen_addi_tl(EA, EA, 8); \
6741 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6742 } \
6743 tcg_temp_free(EA); \
6744 }
6745
6746 #define GEN_VR_LVE(name, opc2, opc3) \
6747 static void gen_lve##name(DisasContext *ctx) \
6748 { \
6749 TCGv EA; \
6750 TCGv_ptr rs; \
6751 if (unlikely(!ctx->altivec_enabled)) { \
6752 gen_exception(ctx, POWERPC_EXCP_VPU); \
6753 return; \
6754 } \
6755 gen_set_access_type(ctx, ACCESS_INT); \
6756 EA = tcg_temp_new(); \
6757 gen_addr_reg_index(ctx, EA); \
6758 rs = gen_avr_ptr(rS(ctx->opcode)); \
6759 gen_helper_lve##name(cpu_env, rs, EA); \
6760 tcg_temp_free(EA); \
6761 tcg_temp_free_ptr(rs); \
6762 }
6763
6764 #define GEN_VR_STVE(name, opc2, opc3) \
6765 static void gen_stve##name(DisasContext *ctx) \
6766 { \
6767 TCGv EA; \
6768 TCGv_ptr rs; \
6769 if (unlikely(!ctx->altivec_enabled)) { \
6770 gen_exception(ctx, POWERPC_EXCP_VPU); \
6771 return; \
6772 } \
6773 gen_set_access_type(ctx, ACCESS_INT); \
6774 EA = tcg_temp_new(); \
6775 gen_addr_reg_index(ctx, EA); \
6776 rs = gen_avr_ptr(rS(ctx->opcode)); \
6777 gen_helper_stve##name(cpu_env, rs, EA); \
6778 tcg_temp_free(EA); \
6779 tcg_temp_free_ptr(rs); \
6780 }
6781
6782 GEN_VR_LDX(lvx, 0x07, 0x03);
6783 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6784 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6785
6786 GEN_VR_LVE(bx, 0x07, 0x00);
6787 GEN_VR_LVE(hx, 0x07, 0x01);
6788 GEN_VR_LVE(wx, 0x07, 0x02);
6789
6790 GEN_VR_STX(svx, 0x07, 0x07);
6791 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6792 GEN_VR_STX(svxl, 0x07, 0x0F);
6793
6794 GEN_VR_STVE(bx, 0x07, 0x04);
6795 GEN_VR_STVE(hx, 0x07, 0x05);
6796 GEN_VR_STVE(wx, 0x07, 0x06);
6797
6798 static void gen_lvsl(DisasContext *ctx)
6799 {
6800 TCGv_ptr rd;
6801 TCGv EA;
6802 if (unlikely(!ctx->altivec_enabled)) {
6803 gen_exception(ctx, POWERPC_EXCP_VPU);
6804 return;
6805 }
6806 EA = tcg_temp_new();
6807 gen_addr_reg_index(ctx, EA);
6808 rd = gen_avr_ptr(rD(ctx->opcode));
6809 gen_helper_lvsl(rd, EA);
6810 tcg_temp_free(EA);
6811 tcg_temp_free_ptr(rd);
6812 }
6813
6814 static void gen_lvsr(DisasContext *ctx)
6815 {
6816 TCGv_ptr rd;
6817 TCGv EA;
6818 if (unlikely(!ctx->altivec_enabled)) {
6819 gen_exception(ctx, POWERPC_EXCP_VPU);
6820 return;
6821 }
6822 EA = tcg_temp_new();
6823 gen_addr_reg_index(ctx, EA);
6824 rd = gen_avr_ptr(rD(ctx->opcode));
6825 gen_helper_lvsr(rd, EA);
6826 tcg_temp_free(EA);
6827 tcg_temp_free_ptr(rd);
6828 }
6829
6830 static void gen_mfvscr(DisasContext *ctx)
6831 {
6832 TCGv_i32 t;
6833 if (unlikely(!ctx->altivec_enabled)) {
6834 gen_exception(ctx, POWERPC_EXCP_VPU);
6835 return;
6836 }
6837 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6838 t = tcg_temp_new_i32();
6839 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6840 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6841 tcg_temp_free_i32(t);
6842 }
6843
6844 static void gen_mtvscr(DisasContext *ctx)
6845 {
6846 TCGv_ptr p;
6847 if (unlikely(!ctx->altivec_enabled)) {
6848 gen_exception(ctx, POWERPC_EXCP_VPU);
6849 return;
6850 }
6851 p = gen_avr_ptr(rB(ctx->opcode));
6852 gen_helper_mtvscr(cpu_env, p);
6853 tcg_temp_free_ptr(p);
6854 }
6855
6856 /* Logical operations */
6857 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6858 static void glue(gen_, name)(DisasContext *ctx) \
6859 { \
6860 if (unlikely(!ctx->altivec_enabled)) { \
6861 gen_exception(ctx, POWERPC_EXCP_VPU); \
6862 return; \
6863 } \
6864 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6865 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6866 }
6867
6868 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6869 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6870 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6871 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6872 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6873 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6874 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6875 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6876
6877 #define GEN_VXFORM(name, opc2, opc3) \
6878 static void glue(gen_, name)(DisasContext *ctx) \
6879 { \
6880 TCGv_ptr ra, rb, rd; \
6881 if (unlikely(!ctx->altivec_enabled)) { \
6882 gen_exception(ctx, POWERPC_EXCP_VPU); \
6883 return; \
6884 } \
6885 ra = gen_avr_ptr(rA(ctx->opcode)); \
6886 rb = gen_avr_ptr(rB(ctx->opcode)); \
6887 rd = gen_avr_ptr(rD(ctx->opcode)); \
6888 gen_helper_##name (rd, ra, rb); \
6889 tcg_temp_free_ptr(ra); \
6890 tcg_temp_free_ptr(rb); \
6891 tcg_temp_free_ptr(rd); \
6892 }
6893
6894 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6895 static void glue(gen_, name)(DisasContext *ctx) \
6896 { \
6897 TCGv_ptr ra, rb, rd; \
6898 if (unlikely(!ctx->altivec_enabled)) { \
6899 gen_exception(ctx, POWERPC_EXCP_VPU); \
6900 return; \
6901 } \
6902 ra = gen_avr_ptr(rA(ctx->opcode)); \
6903 rb = gen_avr_ptr(rB(ctx->opcode)); \
6904 rd = gen_avr_ptr(rD(ctx->opcode)); \
6905 gen_helper_##name(cpu_env, rd, ra, rb); \
6906 tcg_temp_free_ptr(ra); \
6907 tcg_temp_free_ptr(rb); \
6908 tcg_temp_free_ptr(rd); \
6909 }
6910
6911 #define GEN_VXFORM3(name, opc2, opc3) \
6912 static void glue(gen_, name)(DisasContext *ctx) \
6913 { \
6914 TCGv_ptr ra, rb, rc, rd; \
6915 if (unlikely(!ctx->altivec_enabled)) { \
6916 gen_exception(ctx, POWERPC_EXCP_VPU); \
6917 return; \
6918 } \
6919 ra = gen_avr_ptr(rA(ctx->opcode)); \
6920 rb = gen_avr_ptr(rB(ctx->opcode)); \
6921 rc = gen_avr_ptr(rC(ctx->opcode)); \
6922 rd = gen_avr_ptr(rD(ctx->opcode)); \
6923 gen_helper_##name(rd, ra, rb, rc); \
6924 tcg_temp_free_ptr(ra); \
6925 tcg_temp_free_ptr(rb); \
6926 tcg_temp_free_ptr(rc); \
6927 tcg_temp_free_ptr(rd); \
6928 }
6929
6930 /*
6931 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6932 * an opcode bit. In general, these pairs come from different
6933 * versions of the ISA, so we must also support a pair of flags for
6934 * each instruction.
6935 */
6936 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6937 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6938 { \
6939 if ((Rc(ctx->opcode) == 0) && \
6940 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6941 gen_##name0(ctx); \
6942 } else if ((Rc(ctx->opcode) == 1) && \
6943 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6944 gen_##name1(ctx); \
6945 } else { \
6946 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6947 } \
6948 }
6949
6950 GEN_VXFORM(vaddubm, 0, 0);
6951 GEN_VXFORM(vadduhm, 0, 1);
6952 GEN_VXFORM(vadduwm, 0, 2);
6953 GEN_VXFORM(vaddudm, 0, 3);
6954 GEN_VXFORM(vsububm, 0, 16);
6955 GEN_VXFORM(vsubuhm, 0, 17);
6956 GEN_VXFORM(vsubuwm, 0, 18);
6957 GEN_VXFORM(vsubudm, 0, 19);
6958 GEN_VXFORM(vmaxub, 1, 0);
6959 GEN_VXFORM(vmaxuh, 1, 1);
6960 GEN_VXFORM(vmaxuw, 1, 2);
6961 GEN_VXFORM(vmaxud, 1, 3);
6962 GEN_VXFORM(vmaxsb, 1, 4);
6963 GEN_VXFORM(vmaxsh, 1, 5);
6964 GEN_VXFORM(vmaxsw, 1, 6);
6965 GEN_VXFORM(vmaxsd, 1, 7);
6966 GEN_VXFORM(vminub, 1, 8);
6967 GEN_VXFORM(vminuh, 1, 9);
6968 GEN_VXFORM(vminuw, 1, 10);
6969 GEN_VXFORM(vminud, 1, 11);
6970 GEN_VXFORM(vminsb, 1, 12);
6971 GEN_VXFORM(vminsh, 1, 13);
6972 GEN_VXFORM(vminsw, 1, 14);
6973 GEN_VXFORM(vminsd, 1, 15);
6974 GEN_VXFORM(vavgub, 1, 16);
6975 GEN_VXFORM(vavguh, 1, 17);
6976 GEN_VXFORM(vavguw, 1, 18);
6977 GEN_VXFORM(vavgsb, 1, 20);
6978 GEN_VXFORM(vavgsh, 1, 21);
6979 GEN_VXFORM(vavgsw, 1, 22);
6980 GEN_VXFORM(vmrghb, 6, 0);
6981 GEN_VXFORM(vmrghh, 6, 1);
6982 GEN_VXFORM(vmrghw, 6, 2);
6983 GEN_VXFORM(vmrglb, 6, 4);
6984 GEN_VXFORM(vmrglh, 6, 5);
6985 GEN_VXFORM(vmrglw, 6, 6);
6986
6987 static void gen_vmrgew(DisasContext *ctx)
6988 {
6989 TCGv_i64 tmp;
6990 int VT, VA, VB;
6991 if (unlikely(!ctx->altivec_enabled)) {
6992 gen_exception(ctx, POWERPC_EXCP_VPU);
6993 return;
6994 }
6995 VT = rD(ctx->opcode);
6996 VA = rA(ctx->opcode);
6997 VB = rB(ctx->opcode);
6998 tmp = tcg_temp_new_i64();
6999 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7000 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7001 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7002 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7003 tcg_temp_free_i64(tmp);
7004 }
7005
7006 static void gen_vmrgow(DisasContext *ctx)
7007 {
7008 int VT, VA, VB;
7009 if (unlikely(!ctx->altivec_enabled)) {
7010 gen_exception(ctx, POWERPC_EXCP_VPU);
7011 return;
7012 }
7013 VT = rD(ctx->opcode);
7014 VA = rA(ctx->opcode);
7015 VB = rB(ctx->opcode);
7016
7017 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7018 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7019 }
7020
7021 GEN_VXFORM(vmuloub, 4, 0);
7022 GEN_VXFORM(vmulouh, 4, 1);
7023 GEN_VXFORM(vmulouw, 4, 2);
7024 GEN_VXFORM(vmuluwm, 4, 2);
7025 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7026 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7027 GEN_VXFORM(vmulosb, 4, 4);
7028 GEN_VXFORM(vmulosh, 4, 5);
7029 GEN_VXFORM(vmulosw, 4, 6);
7030 GEN_VXFORM(vmuleub, 4, 8);
7031 GEN_VXFORM(vmuleuh, 4, 9);
7032 GEN_VXFORM(vmuleuw, 4, 10);
7033 GEN_VXFORM(vmulesb, 4, 12);
7034 GEN_VXFORM(vmulesh, 4, 13);
7035 GEN_VXFORM(vmulesw, 4, 14);
7036 GEN_VXFORM(vslb, 2, 4);
7037 GEN_VXFORM(vslh, 2, 5);
7038 GEN_VXFORM(vslw, 2, 6);
7039 GEN_VXFORM(vsld, 2, 23);
7040 GEN_VXFORM(vsrb, 2, 8);
7041 GEN_VXFORM(vsrh, 2, 9);
7042 GEN_VXFORM(vsrw, 2, 10);
7043 GEN_VXFORM(vsrd, 2, 27);
7044 GEN_VXFORM(vsrab, 2, 12);
7045 GEN_VXFORM(vsrah, 2, 13);
7046 GEN_VXFORM(vsraw, 2, 14);
7047 GEN_VXFORM(vsrad, 2, 15);
7048 GEN_VXFORM(vslo, 6, 16);
7049 GEN_VXFORM(vsro, 6, 17);
7050 GEN_VXFORM(vaddcuw, 0, 6);
7051 GEN_VXFORM(vsubcuw, 0, 22);
7052 GEN_VXFORM_ENV(vaddubs, 0, 8);
7053 GEN_VXFORM_ENV(vadduhs, 0, 9);
7054 GEN_VXFORM_ENV(vadduws, 0, 10);
7055 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7056 GEN_VXFORM_ENV(vaddshs, 0, 13);
7057 GEN_VXFORM_ENV(vaddsws, 0, 14);
7058 GEN_VXFORM_ENV(vsububs, 0, 24);
7059 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7060 GEN_VXFORM_ENV(vsubuws, 0, 26);
7061 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7062 GEN_VXFORM_ENV(vsubshs, 0, 29);
7063 GEN_VXFORM_ENV(vsubsws, 0, 30);
7064 GEN_VXFORM(vadduqm, 0, 4);
7065 GEN_VXFORM(vaddcuq, 0, 5);
7066 GEN_VXFORM3(vaddeuqm, 30, 0);
7067 GEN_VXFORM3(vaddecuq, 30, 0);
7068 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7069 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7070 GEN_VXFORM(vsubuqm, 0, 20);
7071 GEN_VXFORM(vsubcuq, 0, 21);
7072 GEN_VXFORM3(vsubeuqm, 31, 0);
7073 GEN_VXFORM3(vsubecuq, 31, 0);
7074 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7075 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7076 GEN_VXFORM(vrlb, 2, 0);
7077 GEN_VXFORM(vrlh, 2, 1);
7078 GEN_VXFORM(vrlw, 2, 2);
7079 GEN_VXFORM(vrld, 2, 3);
7080 GEN_VXFORM(vsl, 2, 7);
7081 GEN_VXFORM(vsr, 2, 11);
7082 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7083 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7084 GEN_VXFORM_ENV(vpkudum, 7, 17);
7085 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7086 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7087 GEN_VXFORM_ENV(vpkudus, 7, 19);
7088 GEN_VXFORM_ENV(vpkshus, 7, 4);
7089 GEN_VXFORM_ENV(vpkswus, 7, 5);
7090 GEN_VXFORM_ENV(vpksdus, 7, 21);
7091 GEN_VXFORM_ENV(vpkshss, 7, 6);
7092 GEN_VXFORM_ENV(vpkswss, 7, 7);
7093 GEN_VXFORM_ENV(vpksdss, 7, 23);
7094 GEN_VXFORM(vpkpx, 7, 12);
7095 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7096 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7097 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7098 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7099 GEN_VXFORM_ENV(vsumsws, 4, 30);
7100 GEN_VXFORM_ENV(vaddfp, 5, 0);
7101 GEN_VXFORM_ENV(vsubfp, 5, 1);
7102 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7103 GEN_VXFORM_ENV(vminfp, 5, 17);
7104
7105 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7106 static void glue(gen_, name)(DisasContext *ctx) \
7107 { \
7108 TCGv_ptr ra, rb, rd; \
7109 if (unlikely(!ctx->altivec_enabled)) { \
7110 gen_exception(ctx, POWERPC_EXCP_VPU); \
7111 return; \
7112 } \
7113 ra = gen_avr_ptr(rA(ctx->opcode)); \
7114 rb = gen_avr_ptr(rB(ctx->opcode)); \
7115 rd = gen_avr_ptr(rD(ctx->opcode)); \
7116 gen_helper_##opname(cpu_env, rd, ra, rb); \
7117 tcg_temp_free_ptr(ra); \
7118 tcg_temp_free_ptr(rb); \
7119 tcg_temp_free_ptr(rd); \
7120 }
7121
7122 #define GEN_VXRFORM(name, opc2, opc3) \
7123 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7124 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7125
7126 /*
7127 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7128 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7129 * come from different versions of the ISA, so we must also support a
7130 * pair of flags for each instruction.
7131 */
7132 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7133 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7134 { \
7135 if ((Rc(ctx->opcode) == 0) && \
7136 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7137 if (Rc21(ctx->opcode) == 0) { \
7138 gen_##name0(ctx); \
7139 } else { \
7140 gen_##name0##_(ctx); \
7141 } \
7142 } else if ((Rc(ctx->opcode) == 1) && \
7143 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7144 if (Rc21(ctx->opcode) == 0) { \
7145 gen_##name1(ctx); \
7146 } else { \
7147 gen_##name1##_(ctx); \
7148 } \
7149 } else { \
7150 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7151 } \
7152 }
7153
7154 GEN_VXRFORM(vcmpequb, 3, 0)
7155 GEN_VXRFORM(vcmpequh, 3, 1)
7156 GEN_VXRFORM(vcmpequw, 3, 2)
7157 GEN_VXRFORM(vcmpequd, 3, 3)
7158 GEN_VXRFORM(vcmpgtsb, 3, 12)
7159 GEN_VXRFORM(vcmpgtsh, 3, 13)
7160 GEN_VXRFORM(vcmpgtsw, 3, 14)
7161 GEN_VXRFORM(vcmpgtsd, 3, 15)
7162 GEN_VXRFORM(vcmpgtub, 3, 8)
7163 GEN_VXRFORM(vcmpgtuh, 3, 9)
7164 GEN_VXRFORM(vcmpgtuw, 3, 10)
7165 GEN_VXRFORM(vcmpgtud, 3, 11)
7166 GEN_VXRFORM(vcmpeqfp, 3, 3)
7167 GEN_VXRFORM(vcmpgefp, 3, 7)
7168 GEN_VXRFORM(vcmpgtfp, 3, 11)
7169 GEN_VXRFORM(vcmpbfp, 3, 15)
7170
7171 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7172 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7173 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7174 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7175 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7176 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7177
7178 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7179 static void glue(gen_, name)(DisasContext *ctx) \
7180 { \
7181 TCGv_ptr rd; \
7182 TCGv_i32 simm; \
7183 if (unlikely(!ctx->altivec_enabled)) { \
7184 gen_exception(ctx, POWERPC_EXCP_VPU); \
7185 return; \
7186 } \
7187 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7188 rd = gen_avr_ptr(rD(ctx->opcode)); \
7189 gen_helper_##name (rd, simm); \
7190 tcg_temp_free_i32(simm); \
7191 tcg_temp_free_ptr(rd); \
7192 }
7193
7194 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7195 GEN_VXFORM_SIMM(vspltish, 6, 13);
7196 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7197
7198 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7199 static void glue(gen_, name)(DisasContext *ctx) \
7200 { \
7201 TCGv_ptr rb, rd; \
7202 if (unlikely(!ctx->altivec_enabled)) { \
7203 gen_exception(ctx, POWERPC_EXCP_VPU); \
7204 return; \
7205 } \
7206 rb = gen_avr_ptr(rB(ctx->opcode)); \
7207 rd = gen_avr_ptr(rD(ctx->opcode)); \
7208 gen_helper_##name (rd, rb); \
7209 tcg_temp_free_ptr(rb); \
7210 tcg_temp_free_ptr(rd); \
7211 }
7212
7213 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7214 static void glue(gen_, name)(DisasContext *ctx) \
7215 { \
7216 TCGv_ptr rb, rd; \
7217 \
7218 if (unlikely(!ctx->altivec_enabled)) { \
7219 gen_exception(ctx, POWERPC_EXCP_VPU); \
7220 return; \
7221 } \
7222 rb = gen_avr_ptr(rB(ctx->opcode)); \
7223 rd = gen_avr_ptr(rD(ctx->opcode)); \
7224 gen_helper_##name(cpu_env, rd, rb); \
7225 tcg_temp_free_ptr(rb); \
7226 tcg_temp_free_ptr(rd); \
7227 }
7228
7229 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7230 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7231 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7232 GEN_VXFORM_NOA(vupklsb, 7, 10);
7233 GEN_VXFORM_NOA(vupklsh, 7, 11);
7234 GEN_VXFORM_NOA(vupklsw, 7, 27);
7235 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7236 GEN_VXFORM_NOA(vupklpx, 7, 15);
7237 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7238 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7239 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7240 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7241 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7242 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7243 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7244 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7245
7246 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7247 static void glue(gen_, name)(DisasContext *ctx) \
7248 { \
7249 TCGv_ptr rd; \
7250 TCGv_i32 simm; \
7251 if (unlikely(!ctx->altivec_enabled)) { \
7252 gen_exception(ctx, POWERPC_EXCP_VPU); \
7253 return; \
7254 } \
7255 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7256 rd = gen_avr_ptr(rD(ctx->opcode)); \
7257 gen_helper_##name (rd, simm); \
7258 tcg_temp_free_i32(simm); \
7259 tcg_temp_free_ptr(rd); \
7260 }
7261
7262 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7263 static void glue(gen_, name)(DisasContext *ctx) \
7264 { \
7265 TCGv_ptr rb, rd; \
7266 TCGv_i32 uimm; \
7267 if (unlikely(!ctx->altivec_enabled)) { \
7268 gen_exception(ctx, POWERPC_EXCP_VPU); \
7269 return; \
7270 } \
7271 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7272 rb = gen_avr_ptr(rB(ctx->opcode)); \
7273 rd = gen_avr_ptr(rD(ctx->opcode)); \
7274 gen_helper_##name (rd, rb, uimm); \
7275 tcg_temp_free_i32(uimm); \
7276 tcg_temp_free_ptr(rb); \
7277 tcg_temp_free_ptr(rd); \
7278 }
7279
7280 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7281 static void glue(gen_, name)(DisasContext *ctx) \
7282 { \
7283 TCGv_ptr rb, rd; \
7284 TCGv_i32 uimm; \
7285 \
7286 if (unlikely(!ctx->altivec_enabled)) { \
7287 gen_exception(ctx, POWERPC_EXCP_VPU); \
7288 return; \
7289 } \
7290 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7291 rb = gen_avr_ptr(rB(ctx->opcode)); \
7292 rd = gen_avr_ptr(rD(ctx->opcode)); \
7293 gen_helper_##name(cpu_env, rd, rb, uimm); \
7294 tcg_temp_free_i32(uimm); \
7295 tcg_temp_free_ptr(rb); \
7296 tcg_temp_free_ptr(rd); \
7297 }
7298
7299 GEN_VXFORM_UIMM(vspltb, 6, 8);
7300 GEN_VXFORM_UIMM(vsplth, 6, 9);
7301 GEN_VXFORM_UIMM(vspltw, 6, 10);
7302 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7303 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7304 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7305 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7306
7307 static void gen_vsldoi(DisasContext *ctx)
7308 {
7309 TCGv_ptr ra, rb, rd;
7310 TCGv_i32 sh;
7311 if (unlikely(!ctx->altivec_enabled)) {
7312 gen_exception(ctx, POWERPC_EXCP_VPU);
7313 return;
7314 }
7315 ra = gen_avr_ptr(rA(ctx->opcode));
7316 rb = gen_avr_ptr(rB(ctx->opcode));
7317 rd = gen_avr_ptr(rD(ctx->opcode));
7318 sh = tcg_const_i32(VSH(ctx->opcode));
7319 gen_helper_vsldoi (rd, ra, rb, sh);
7320 tcg_temp_free_ptr(ra);
7321 tcg_temp_free_ptr(rb);
7322 tcg_temp_free_ptr(rd);
7323 tcg_temp_free_i32(sh);
7324 }
7325
7326 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7327 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7328 { \
7329 TCGv_ptr ra, rb, rc, rd; \
7330 if (unlikely(!ctx->altivec_enabled)) { \
7331 gen_exception(ctx, POWERPC_EXCP_VPU); \
7332 return; \
7333 } \
7334 ra = gen_avr_ptr(rA(ctx->opcode)); \
7335 rb = gen_avr_ptr(rB(ctx->opcode)); \
7336 rc = gen_avr_ptr(rC(ctx->opcode)); \
7337 rd = gen_avr_ptr(rD(ctx->opcode)); \
7338 if (Rc(ctx->opcode)) { \
7339 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7340 } else { \
7341 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7342 } \
7343 tcg_temp_free_ptr(ra); \
7344 tcg_temp_free_ptr(rb); \
7345 tcg_temp_free_ptr(rc); \
7346 tcg_temp_free_ptr(rd); \
7347 }
7348
7349 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7350
7351 static void gen_vmladduhm(DisasContext *ctx)
7352 {
7353 TCGv_ptr ra, rb, rc, rd;
7354 if (unlikely(!ctx->altivec_enabled)) {
7355 gen_exception(ctx, POWERPC_EXCP_VPU);
7356 return;
7357 }
7358 ra = gen_avr_ptr(rA(ctx->opcode));
7359 rb = gen_avr_ptr(rB(ctx->opcode));
7360 rc = gen_avr_ptr(rC(ctx->opcode));
7361 rd = gen_avr_ptr(rD(ctx->opcode));
7362 gen_helper_vmladduhm(rd, ra, rb, rc);
7363 tcg_temp_free_ptr(ra);
7364 tcg_temp_free_ptr(rb);
7365 tcg_temp_free_ptr(rc);
7366 tcg_temp_free_ptr(rd);
7367 }
7368
7369 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7370 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7371 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7372 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7373 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7374
7375 GEN_VXFORM_NOA(vclzb, 1, 28)
7376 GEN_VXFORM_NOA(vclzh, 1, 29)
7377 GEN_VXFORM_NOA(vclzw, 1, 30)
7378 GEN_VXFORM_NOA(vclzd, 1, 31)
7379 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7380 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7381 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7382 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7383 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7384 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7385 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7386 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7387 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7388 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7389 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7390 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7391 GEN_VXFORM(vbpermq, 6, 21);
7392 GEN_VXFORM_NOA(vgbbd, 6, 20);
7393 GEN_VXFORM(vpmsumb, 4, 16)
7394 GEN_VXFORM(vpmsumh, 4, 17)
7395 GEN_VXFORM(vpmsumw, 4, 18)
7396 GEN_VXFORM(vpmsumd, 4, 19)
7397
7398 #define GEN_BCD(op) \
7399 static void gen_##op(DisasContext *ctx) \
7400 { \
7401 TCGv_ptr ra, rb, rd; \
7402 TCGv_i32 ps; \
7403 \
7404 if (unlikely(!ctx->altivec_enabled)) { \
7405 gen_exception(ctx, POWERPC_EXCP_VPU); \
7406 return; \
7407 } \
7408 \
7409 ra = gen_avr_ptr(rA(ctx->opcode)); \
7410 rb = gen_avr_ptr(rB(ctx->opcode)); \
7411 rd = gen_avr_ptr(rD(ctx->opcode)); \
7412 \
7413 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7414 \
7415 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7416 \
7417 tcg_temp_free_ptr(ra); \
7418 tcg_temp_free_ptr(rb); \
7419 tcg_temp_free_ptr(rd); \
7420 tcg_temp_free_i32(ps); \
7421 }
7422
7423 GEN_BCD(bcdadd)
7424 GEN_BCD(bcdsub)
7425
7426 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7427 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7428 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7429 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7430 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7431 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7432 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7433 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7434
7435 static void gen_vsbox(DisasContext *ctx)
7436 {
7437 TCGv_ptr ra, rd;
7438 if (unlikely(!ctx->altivec_enabled)) {
7439 gen_exception(ctx, POWERPC_EXCP_VPU);
7440 return;
7441 }
7442 ra = gen_avr_ptr(rA(ctx->opcode));
7443 rd = gen_avr_ptr(rD(ctx->opcode));
7444 gen_helper_vsbox(rd, ra);
7445 tcg_temp_free_ptr(ra);
7446 tcg_temp_free_ptr(rd);
7447 }
7448
7449 GEN_VXFORM(vcipher, 4, 20)
7450 GEN_VXFORM(vcipherlast, 4, 20)
7451 GEN_VXFORM(vncipher, 4, 21)
7452 GEN_VXFORM(vncipherlast, 4, 21)
7453
7454 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7455 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7456 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7457 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7458
7459 #define VSHASIGMA(op) \
7460 static void gen_##op(DisasContext *ctx) \
7461 { \
7462 TCGv_ptr ra, rd; \
7463 TCGv_i32 st_six; \
7464 if (unlikely(!ctx->altivec_enabled)) { \
7465 gen_exception(ctx, POWERPC_EXCP_VPU); \
7466 return; \
7467 } \
7468 ra = gen_avr_ptr(rA(ctx->opcode)); \
7469 rd = gen_avr_ptr(rD(ctx->opcode)); \
7470 st_six = tcg_const_i32(rB(ctx->opcode)); \
7471 gen_helper_##op(rd, ra, st_six); \
7472 tcg_temp_free_ptr(ra); \
7473 tcg_temp_free_ptr(rd); \
7474 tcg_temp_free_i32(st_six); \
7475 }
7476
7477 VSHASIGMA(vshasigmaw)
7478 VSHASIGMA(vshasigmad)
7479
7480 GEN_VXFORM3(vpermxor, 22, 0xFF)
7481 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7482 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7483
7484 /*** VSX extension ***/
7485
7486 static inline TCGv_i64 cpu_vsrh(int n)
7487 {
7488 if (n < 32) {
7489 return cpu_fpr[n];
7490 } else {
7491 return cpu_avrh[n-32];
7492 }
7493 }
7494
7495 static inline TCGv_i64 cpu_vsrl(int n)
7496 {
7497 if (n < 32) {
7498 return cpu_vsr[n];
7499 } else {
7500 return cpu_avrl[n-32];
7501 }
7502 }
7503
7504 #define VSX_LOAD_SCALAR(name, operation) \
7505 static void gen_##name(DisasContext *ctx) \
7506 { \
7507 TCGv EA; \
7508 if (unlikely(!ctx->vsx_enabled)) { \
7509 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7510 return; \
7511 } \
7512 gen_set_access_type(ctx, ACCESS_INT); \
7513 EA = tcg_temp_new(); \
7514 gen_addr_reg_index(ctx, EA); \
7515 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7516 /* NOTE: cpu_vsrl is undefined */ \
7517 tcg_temp_free(EA); \
7518 }
7519
7520 VSX_LOAD_SCALAR(lxsdx, ld64)
7521 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7522 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7523 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7524
7525 static void gen_lxvd2x(DisasContext *ctx)
7526 {
7527 TCGv EA;
7528 if (unlikely(!ctx->vsx_enabled)) {
7529 gen_exception(ctx, POWERPC_EXCP_VSXU);
7530 return;
7531 }
7532 gen_set_access_type(ctx, ACCESS_INT);
7533 EA = tcg_temp_new();
7534 gen_addr_reg_index(ctx, EA);
7535 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7536 tcg_gen_addi_tl(EA, EA, 8);
7537 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7538 tcg_temp_free(EA);
7539 }
7540
7541 static void gen_lxvdsx(DisasContext *ctx)
7542 {
7543 TCGv EA;
7544 if (unlikely(!ctx->vsx_enabled)) {
7545 gen_exception(ctx, POWERPC_EXCP_VSXU);
7546 return;
7547 }
7548 gen_set_access_type(ctx, ACCESS_INT);
7549 EA = tcg_temp_new();
7550 gen_addr_reg_index(ctx, EA);
7551 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7552 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7553 tcg_temp_free(EA);
7554 }
7555
7556 static void gen_lxvw4x(DisasContext *ctx)
7557 {
7558 TCGv EA;
7559 TCGv_i64 tmp;
7560 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7561 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7562 if (unlikely(!ctx->vsx_enabled)) {
7563 gen_exception(ctx, POWERPC_EXCP_VSXU);
7564 return;
7565 }
7566 gen_set_access_type(ctx, ACCESS_INT);
7567 EA = tcg_temp_new();
7568 tmp = tcg_temp_new_i64();
7569
7570 gen_addr_reg_index(ctx, EA);
7571 gen_qemu_ld32u_i64(ctx, tmp, EA);
7572 tcg_gen_addi_tl(EA, EA, 4);
7573 gen_qemu_ld32u_i64(ctx, xth, EA);
7574 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7575
7576 tcg_gen_addi_tl(EA, EA, 4);
7577 gen_qemu_ld32u_i64(ctx, tmp, EA);
7578 tcg_gen_addi_tl(EA, EA, 4);
7579 gen_qemu_ld32u_i64(ctx, xtl, EA);
7580 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7581
7582 tcg_temp_free(EA);
7583 tcg_temp_free_i64(tmp);
7584 }
7585
7586 #define VSX_STORE_SCALAR(name, operation) \
7587 static void gen_##name(DisasContext *ctx) \
7588 { \
7589 TCGv EA; \
7590 if (unlikely(!ctx->vsx_enabled)) { \
7591 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7592 return; \
7593 } \
7594 gen_set_access_type(ctx, ACCESS_INT); \
7595 EA = tcg_temp_new(); \
7596 gen_addr_reg_index(ctx, EA); \
7597 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7598 tcg_temp_free(EA); \
7599 }
7600
7601 VSX_STORE_SCALAR(stxsdx, st64)
7602 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7603 VSX_STORE_SCALAR(stxsspx, st32fs)
7604
7605 static void gen_stxvd2x(DisasContext *ctx)
7606 {
7607 TCGv EA;
7608 if (unlikely(!ctx->vsx_enabled)) {
7609 gen_exception(ctx, POWERPC_EXCP_VSXU);
7610 return;
7611 }
7612 gen_set_access_type(ctx, ACCESS_INT);
7613 EA = tcg_temp_new();
7614 gen_addr_reg_index(ctx, EA);
7615 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7616 tcg_gen_addi_tl(EA, EA, 8);
7617 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7618 tcg_temp_free(EA);
7619 }
7620
7621 static void gen_stxvw4x(DisasContext *ctx)
7622 {
7623 TCGv_i64 tmp;
7624 TCGv EA;
7625 if (unlikely(!ctx->vsx_enabled)) {
7626 gen_exception(ctx, POWERPC_EXCP_VSXU);
7627 return;
7628 }
7629 gen_set_access_type(ctx, ACCESS_INT);
7630 EA = tcg_temp_new();
7631 gen_addr_reg_index(ctx, EA);
7632 tmp = tcg_temp_new_i64();
7633
7634 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7635 gen_qemu_st32_i64(ctx, tmp, EA);
7636 tcg_gen_addi_tl(EA, EA, 4);
7637 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7638
7639 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7640 tcg_gen_addi_tl(EA, EA, 4);
7641 gen_qemu_st32_i64(ctx, tmp, EA);
7642 tcg_gen_addi_tl(EA, EA, 4);
7643 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7644
7645 tcg_temp_free(EA);
7646 tcg_temp_free_i64(tmp);
7647 }
7648
7649 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7650 static void gen_##name(DisasContext *ctx) \
7651 { \
7652 if (xS(ctx->opcode) < 32) { \
7653 if (unlikely(!ctx->fpu_enabled)) { \
7654 gen_exception(ctx, POWERPC_EXCP_FPU); \
7655 return; \
7656 } \
7657 } else { \
7658 if (unlikely(!ctx->altivec_enabled)) { \
7659 gen_exception(ctx, POWERPC_EXCP_VPU); \
7660 return; \
7661 } \
7662 } \
7663 TCGv_i64 tmp = tcg_temp_new_i64(); \
7664 tcg_gen_##tcgop1(tmp, source); \
7665 tcg_gen_##tcgop2(target, tmp); \
7666 tcg_temp_free_i64(tmp); \
7667 }
7668
7669
7670 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7671 cpu_vsrh(xS(ctx->opcode)))
7672 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7673 cpu_gpr[rA(ctx->opcode)])
7674 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7675 cpu_gpr[rA(ctx->opcode)])
7676
7677 #if defined(TARGET_PPC64)
7678 #define MV_VSRD(name, target, source) \
7679 static void gen_##name(DisasContext *ctx) \
7680 { \
7681 if (xS(ctx->opcode) < 32) { \
7682 if (unlikely(!ctx->fpu_enabled)) { \
7683 gen_exception(ctx, POWERPC_EXCP_FPU); \
7684 return; \
7685 } \
7686 } else { \
7687 if (unlikely(!ctx->altivec_enabled)) { \
7688 gen_exception(ctx, POWERPC_EXCP_VPU); \
7689 return; \
7690 } \
7691 } \
7692 tcg_gen_mov_i64(target, source); \
7693 }
7694
7695 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7696 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7697
7698 #endif
7699
7700 static void gen_xxpermdi(DisasContext *ctx)
7701 {
7702 if (unlikely(!ctx->vsx_enabled)) {
7703 gen_exception(ctx, POWERPC_EXCP_VSXU);
7704 return;
7705 }
7706
7707 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7708 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7709 TCGv_i64 xh, xl;
7710
7711 xh = tcg_temp_new_i64();
7712 xl = tcg_temp_new_i64();
7713
7714 if ((DM(ctx->opcode) & 2) == 0) {
7715 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7716 } else {
7717 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7718 }
7719 if ((DM(ctx->opcode) & 1) == 0) {
7720 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7721 } else {
7722 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7723 }
7724
7725 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7726 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7727
7728 tcg_temp_free_i64(xh);
7729 tcg_temp_free_i64(xl);
7730 } else {
7731 if ((DM(ctx->opcode) & 2) == 0) {
7732 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7733 } else {
7734 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7735 }
7736 if ((DM(ctx->opcode) & 1) == 0) {
7737 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7738 } else {
7739 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7740 }
7741 }
7742 }
7743
7744 #define OP_ABS 1
7745 #define OP_NABS 2
7746 #define OP_NEG 3
7747 #define OP_CPSGN 4
7748 #define SGN_MASK_DP 0x8000000000000000ull
7749 #define SGN_MASK_SP 0x8000000080000000ull
7750
7751 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7752 static void glue(gen_, name)(DisasContext * ctx) \
7753 { \
7754 TCGv_i64 xb, sgm; \
7755 if (unlikely(!ctx->vsx_enabled)) { \
7756 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7757 return; \
7758 } \
7759 xb = tcg_temp_new_i64(); \
7760 sgm = tcg_temp_new_i64(); \
7761 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7762 tcg_gen_movi_i64(sgm, sgn_mask); \
7763 switch (op) { \
7764 case OP_ABS: { \
7765 tcg_gen_andc_i64(xb, xb, sgm); \
7766 break; \
7767 } \
7768 case OP_NABS: { \
7769 tcg_gen_or_i64(xb, xb, sgm); \
7770 break; \
7771 } \
7772 case OP_NEG: { \
7773 tcg_gen_xor_i64(xb, xb, sgm); \
7774 break; \
7775 } \
7776 case OP_CPSGN: { \
7777 TCGv_i64 xa = tcg_temp_new_i64(); \
7778 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7779 tcg_gen_and_i64(xa, xa, sgm); \
7780 tcg_gen_andc_i64(xb, xb, sgm); \
7781 tcg_gen_or_i64(xb, xb, xa); \
7782 tcg_temp_free_i64(xa); \
7783 break; \
7784 } \
7785 } \
7786 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7787 tcg_temp_free_i64(xb); \
7788 tcg_temp_free_i64(sgm); \
7789 }
7790
7791 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7792 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7793 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7794 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7795
7796 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7797 static void glue(gen_, name)(DisasContext * ctx) \
7798 { \
7799 TCGv_i64 xbh, xbl, sgm; \
7800 if (unlikely(!ctx->vsx_enabled)) { \
7801 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7802 return; \
7803 } \
7804 xbh = tcg_temp_new_i64(); \
7805 xbl = tcg_temp_new_i64(); \
7806 sgm = tcg_temp_new_i64(); \
7807 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7808 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7809 tcg_gen_movi_i64(sgm, sgn_mask); \
7810 switch (op) { \
7811 case OP_ABS: { \
7812 tcg_gen_andc_i64(xbh, xbh, sgm); \
7813 tcg_gen_andc_i64(xbl, xbl, sgm); \
7814 break; \
7815 } \
7816 case OP_NABS: { \
7817 tcg_gen_or_i64(xbh, xbh, sgm); \
7818 tcg_gen_or_i64(xbl, xbl, sgm); \
7819 break; \
7820 } \
7821 case OP_NEG: { \
7822 tcg_gen_xor_i64(xbh, xbh, sgm); \
7823 tcg_gen_xor_i64(xbl, xbl, sgm); \
7824 break; \
7825 } \
7826 case OP_CPSGN: { \
7827 TCGv_i64 xah = tcg_temp_new_i64(); \
7828 TCGv_i64 xal = tcg_temp_new_i64(); \
7829 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7830 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7831 tcg_gen_and_i64(xah, xah, sgm); \
7832 tcg_gen_and_i64(xal, xal, sgm); \
7833 tcg_gen_andc_i64(xbh, xbh, sgm); \
7834 tcg_gen_andc_i64(xbl, xbl, sgm); \
7835 tcg_gen_or_i64(xbh, xbh, xah); \
7836 tcg_gen_or_i64(xbl, xbl, xal); \
7837 tcg_temp_free_i64(xah); \
7838 tcg_temp_free_i64(xal); \
7839 break; \
7840 } \
7841 } \
7842 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7843 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7844 tcg_temp_free_i64(xbh); \
7845 tcg_temp_free_i64(xbl); \
7846 tcg_temp_free_i64(sgm); \
7847 }
7848
7849 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7850 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7851 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7852 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7853 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7854 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7855 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7856 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7857
7858 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7859 static void gen_##name(DisasContext * ctx) \
7860 { \
7861 TCGv_i32 opc; \
7862 if (unlikely(!ctx->vsx_enabled)) { \
7863 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7864 return; \
7865 } \
7866 /* NIP cannot be restored if the memory exception comes from an helper */ \
7867 gen_update_nip(ctx, ctx->nip - 4); \
7868 opc = tcg_const_i32(ctx->opcode); \
7869 gen_helper_##name(cpu_env, opc); \
7870 tcg_temp_free_i32(opc); \
7871 }
7872
7873 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7874 static void gen_##name(DisasContext * ctx) \
7875 { \
7876 if (unlikely(!ctx->vsx_enabled)) { \
7877 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7878 return; \
7879 } \
7880 /* NIP cannot be restored if the exception comes */ \
7881 /* from a helper. */ \
7882 gen_update_nip(ctx, ctx->nip - 4); \
7883 \
7884 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7885 cpu_vsrh(xB(ctx->opcode))); \
7886 }
7887
7888 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7889 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7890 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7891 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7892 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7893 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7894 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7895 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7896 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7897 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7898 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7899 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7900 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7901 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7902 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7903 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7904 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7905 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7906 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7907 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7908 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7909 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7910 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7911 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7912 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7913 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7914 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7915 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7916 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7917 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7918 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7919 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7920 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7921 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7922 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7923 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7924 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7925
7926 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7927 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7928 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7929 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7930 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7931 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7932 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7933 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7934 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7935 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7936 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7937 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7938 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7939 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7940 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7941 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7942 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7943
7944 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7945 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7946 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7947 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7948 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7949 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7951 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7952 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7953 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7954 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7955 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7958 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7959 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7963 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7964 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7965 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7977 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7978 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7979 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7980
7981 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7982 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7983 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7984 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7985 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7986 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7987 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7988 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7989 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7990 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7991 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7992 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7993 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7994 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7995 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7996 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8001 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8014 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8015 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8016 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8017
8018 #define VSX_LOGICAL(name, tcg_op) \
8019 static void glue(gen_, name)(DisasContext * ctx) \
8020 { \
8021 if (unlikely(!ctx->vsx_enabled)) { \
8022 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8023 return; \
8024 } \
8025 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8026 cpu_vsrh(xB(ctx->opcode))); \
8027 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8028 cpu_vsrl(xB(ctx->opcode))); \
8029 }
8030
8031 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8032 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8033 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8034 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8035 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8036 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8037 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8038 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8039
8040 #define VSX_XXMRG(name, high) \
8041 static void glue(gen_, name)(DisasContext * ctx) \
8042 { \
8043 TCGv_i64 a0, a1, b0, b1; \
8044 if (unlikely(!ctx->vsx_enabled)) { \
8045 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8046 return; \
8047 } \
8048 a0 = tcg_temp_new_i64(); \
8049 a1 = tcg_temp_new_i64(); \
8050 b0 = tcg_temp_new_i64(); \
8051 b1 = tcg_temp_new_i64(); \
8052 if (high) { \
8053 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8054 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8055 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8056 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8057 } else { \
8058 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8059 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8060 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8061 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8062 } \
8063 tcg_gen_shri_i64(a0, a0, 32); \
8064 tcg_gen_shri_i64(b0, b0, 32); \
8065 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8066 b0, a0, 32, 32); \
8067 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8068 b1, a1, 32, 32); \
8069 tcg_temp_free_i64(a0); \
8070 tcg_temp_free_i64(a1); \
8071 tcg_temp_free_i64(b0); \
8072 tcg_temp_free_i64(b1); \
8073 }
8074
8075 VSX_XXMRG(xxmrghw, 1)
8076 VSX_XXMRG(xxmrglw, 0)
8077
8078 static void gen_xxsel(DisasContext * ctx)
8079 {
8080 TCGv_i64 a, b, c;
8081 if (unlikely(!ctx->vsx_enabled)) {
8082 gen_exception(ctx, POWERPC_EXCP_VSXU);
8083 return;
8084 }
8085 a = tcg_temp_new_i64();
8086 b = tcg_temp_new_i64();
8087 c = tcg_temp_new_i64();
8088
8089 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8090 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8091 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8092
8093 tcg_gen_and_i64(b, b, c);
8094 tcg_gen_andc_i64(a, a, c);
8095 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8096
8097 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8098 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8099 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8100
8101 tcg_gen_and_i64(b, b, c);
8102 tcg_gen_andc_i64(a, a, c);
8103 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8104
8105 tcg_temp_free_i64(a);
8106 tcg_temp_free_i64(b);
8107 tcg_temp_free_i64(c);
8108 }
8109
8110 static void gen_xxspltw(DisasContext *ctx)
8111 {
8112 TCGv_i64 b, b2;
8113 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8114 cpu_vsrl(xB(ctx->opcode)) :
8115 cpu_vsrh(xB(ctx->opcode));
8116
8117 if (unlikely(!ctx->vsx_enabled)) {
8118 gen_exception(ctx, POWERPC_EXCP_VSXU);
8119 return;
8120 }
8121
8122 b = tcg_temp_new_i64();
8123 b2 = tcg_temp_new_i64();
8124
8125 if (UIM(ctx->opcode) & 1) {
8126 tcg_gen_ext32u_i64(b, vsr);
8127 } else {
8128 tcg_gen_shri_i64(b, vsr, 32);
8129 }
8130
8131 tcg_gen_shli_i64(b2, b, 32);
8132 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8133 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8134
8135 tcg_temp_free_i64(b);
8136 tcg_temp_free_i64(b2);
8137 }
8138
8139 static void gen_xxsldwi(DisasContext *ctx)
8140 {
8141 TCGv_i64 xth, xtl;
8142 if (unlikely(!ctx->vsx_enabled)) {
8143 gen_exception(ctx, POWERPC_EXCP_VSXU);
8144 return;
8145 }
8146 xth = tcg_temp_new_i64();
8147 xtl = tcg_temp_new_i64();
8148
8149 switch (SHW(ctx->opcode)) {
8150 case 0: {
8151 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8152 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8153 break;
8154 }
8155 case 1: {
8156 TCGv_i64 t0 = tcg_temp_new_i64();
8157 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8158 tcg_gen_shli_i64(xth, xth, 32);
8159 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8160 tcg_gen_shri_i64(t0, t0, 32);
8161 tcg_gen_or_i64(xth, xth, t0);
8162 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8163 tcg_gen_shli_i64(xtl, xtl, 32);
8164 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8165 tcg_gen_shri_i64(t0, t0, 32);
8166 tcg_gen_or_i64(xtl, xtl, t0);
8167 tcg_temp_free_i64(t0);
8168 break;
8169 }
8170 case 2: {
8171 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8172 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8173 break;
8174 }
8175 case 3: {
8176 TCGv_i64 t0 = tcg_temp_new_i64();
8177 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8178 tcg_gen_shli_i64(xth, xth, 32);
8179 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8180 tcg_gen_shri_i64(t0, t0, 32);
8181 tcg_gen_or_i64(xth, xth, t0);
8182 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8183 tcg_gen_shli_i64(xtl, xtl, 32);
8184 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8185 tcg_gen_shri_i64(t0, t0, 32);
8186 tcg_gen_or_i64(xtl, xtl, t0);
8187 tcg_temp_free_i64(t0);
8188 break;
8189 }
8190 }
8191
8192 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8193 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8194
8195 tcg_temp_free_i64(xth);
8196 tcg_temp_free_i64(xtl);
8197 }
8198
8199 /*** Decimal Floating Point ***/
8200
8201 static inline TCGv_ptr gen_fprp_ptr(int reg)
8202 {
8203 TCGv_ptr r = tcg_temp_new_ptr();
8204 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8205 return r;
8206 }
8207
8208 #if defined(TARGET_PPC64)
8209 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
8210 {
8211 TCGv_i32 tmp = tcg_temp_new_i32();
8212 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
8213 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
8214 tcg_temp_free_i32(tmp);
8215 }
8216 #else
8217 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
8218 {
8219 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
8220 }
8221 #endif
8222
8223 #define GEN_DFP_T_A_B_Rc(name) \
8224 static void gen_##name(DisasContext *ctx) \
8225 { \
8226 TCGv_ptr rd, ra, rb; \
8227 if (unlikely(!ctx->fpu_enabled)) { \
8228 gen_exception(ctx, POWERPC_EXCP_FPU); \
8229 return; \
8230 } \
8231 gen_update_nip(ctx, ctx->nip - 4); \
8232 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8233 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8234 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8235 gen_helper_##name(cpu_env, rd, ra, rb); \
8236 if (unlikely(Rc(ctx->opcode) != 0)) { \
8237 gen_set_cr1_from_fpscr(ctx); \
8238 } \
8239 tcg_temp_free_ptr(rd); \
8240 tcg_temp_free_ptr(ra); \
8241 tcg_temp_free_ptr(rb); \
8242 }
8243
8244 #define GEN_DFP_BF_A_B(name) \
8245 static void gen_##name(DisasContext *ctx) \
8246 { \
8247 TCGv_ptr ra, rb; \
8248 if (unlikely(!ctx->fpu_enabled)) { \
8249 gen_exception(ctx, POWERPC_EXCP_FPU); \
8250 return; \
8251 } \
8252 gen_update_nip(ctx, ctx->nip - 4); \
8253 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8254 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8255 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8256 cpu_env, ra, rb); \
8257 tcg_temp_free_ptr(ra); \
8258 tcg_temp_free_ptr(rb); \
8259 }
8260
8261 #define GEN_DFP_BF_A_DCM(name) \
8262 static void gen_##name(DisasContext *ctx) \
8263 { \
8264 TCGv_ptr ra; \
8265 TCGv_i32 dcm; \
8266 if (unlikely(!ctx->fpu_enabled)) { \
8267 gen_exception(ctx, POWERPC_EXCP_FPU); \
8268 return; \
8269 } \
8270 gen_update_nip(ctx, ctx->nip - 4); \
8271 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8272 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8273 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8274 cpu_env, ra, dcm); \
8275 tcg_temp_free_ptr(ra); \
8276 tcg_temp_free_i32(dcm); \
8277 }
8278
8279 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8280 static void gen_##name(DisasContext *ctx) \
8281 { \
8282 TCGv_ptr rt, rb; \
8283 TCGv_i32 u32_1, u32_2; \
8284 if (unlikely(!ctx->fpu_enabled)) { \
8285 gen_exception(ctx, POWERPC_EXCP_FPU); \
8286 return; \
8287 } \
8288 gen_update_nip(ctx, ctx->nip - 4); \
8289 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8290 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8291 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8292 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8293 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8294 if (unlikely(Rc(ctx->opcode) != 0)) { \
8295 gen_set_cr1_from_fpscr(ctx); \
8296 } \
8297 tcg_temp_free_ptr(rt); \
8298 tcg_temp_free_ptr(rb); \
8299 tcg_temp_free_i32(u32_1); \
8300 tcg_temp_free_i32(u32_2); \
8301 }
8302
8303 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8304 static void gen_##name(DisasContext *ctx) \
8305 { \
8306 TCGv_ptr rt, ra, rb; \
8307 TCGv_i32 i32; \
8308 if (unlikely(!ctx->fpu_enabled)) { \
8309 gen_exception(ctx, POWERPC_EXCP_FPU); \
8310 return; \
8311 } \
8312 gen_update_nip(ctx, ctx->nip - 4); \
8313 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8314 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8315 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8316 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8317 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8318 if (unlikely(Rc(ctx->opcode) != 0)) { \
8319 gen_set_cr1_from_fpscr(ctx); \
8320 } \
8321 tcg_temp_free_ptr(rt); \
8322 tcg_temp_free_ptr(rb); \
8323 tcg_temp_free_ptr(ra); \
8324 tcg_temp_free_i32(i32); \
8325 }
8326
8327 #define GEN_DFP_T_B_Rc(name) \
8328 static void gen_##name(DisasContext *ctx) \
8329 { \
8330 TCGv_ptr rt, rb; \
8331 if (unlikely(!ctx->fpu_enabled)) { \
8332 gen_exception(ctx, POWERPC_EXCP_FPU); \
8333 return; \
8334 } \
8335 gen_update_nip(ctx, ctx->nip - 4); \
8336 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8337 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8338 gen_helper_##name(cpu_env, rt, rb); \
8339 if (unlikely(Rc(ctx->opcode) != 0)) { \
8340 gen_set_cr1_from_fpscr(ctx); \
8341 } \
8342 tcg_temp_free_ptr(rt); \
8343 tcg_temp_free_ptr(rb); \
8344 }
8345
8346 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8347 static void gen_##name(DisasContext *ctx) \
8348 { \
8349 TCGv_ptr rt, rs; \
8350 TCGv_i32 i32; \
8351 if (unlikely(!ctx->fpu_enabled)) { \
8352 gen_exception(ctx, POWERPC_EXCP_FPU); \
8353 return; \
8354 } \
8355 gen_update_nip(ctx, ctx->nip - 4); \
8356 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8357 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8358 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8359 gen_helper_##name(cpu_env, rt, rs, i32); \
8360 if (unlikely(Rc(ctx->opcode) != 0)) { \
8361 gen_set_cr1_from_fpscr(ctx); \
8362 } \
8363 tcg_temp_free_ptr(rt); \
8364 tcg_temp_free_ptr(rs); \
8365 tcg_temp_free_i32(i32); \
8366 }
8367
8368 GEN_DFP_T_A_B_Rc(dadd)
8369 GEN_DFP_T_A_B_Rc(daddq)
8370 GEN_DFP_T_A_B_Rc(dsub)
8371 GEN_DFP_T_A_B_Rc(dsubq)
8372 GEN_DFP_T_A_B_Rc(dmul)
8373 GEN_DFP_T_A_B_Rc(dmulq)
8374 GEN_DFP_T_A_B_Rc(ddiv)
8375 GEN_DFP_T_A_B_Rc(ddivq)
8376 GEN_DFP_BF_A_B(dcmpu)
8377 GEN_DFP_BF_A_B(dcmpuq)
8378 GEN_DFP_BF_A_B(dcmpo)
8379 GEN_DFP_BF_A_B(dcmpoq)
8380 GEN_DFP_BF_A_DCM(dtstdc)
8381 GEN_DFP_BF_A_DCM(dtstdcq)
8382 GEN_DFP_BF_A_DCM(dtstdg)
8383 GEN_DFP_BF_A_DCM(dtstdgq)
8384 GEN_DFP_BF_A_B(dtstex)
8385 GEN_DFP_BF_A_B(dtstexq)
8386 GEN_DFP_BF_A_B(dtstsf)
8387 GEN_DFP_BF_A_B(dtstsfq)
8388 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8389 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8390 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8391 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8392 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8393 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8394 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8395 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8396 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8397 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8398 GEN_DFP_T_B_Rc(dctdp)
8399 GEN_DFP_T_B_Rc(dctqpq)
8400 GEN_DFP_T_B_Rc(drsp)
8401 GEN_DFP_T_B_Rc(drdpq)
8402 GEN_DFP_T_B_Rc(dcffix)
8403 GEN_DFP_T_B_Rc(dcffixq)
8404 GEN_DFP_T_B_Rc(dctfix)
8405 GEN_DFP_T_B_Rc(dctfixq)
8406 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8407 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8408 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8409 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8410 GEN_DFP_T_B_Rc(dxex)
8411 GEN_DFP_T_B_Rc(dxexq)
8412 GEN_DFP_T_A_B_Rc(diex)
8413 GEN_DFP_T_A_B_Rc(diexq)
8414 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8415 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8416 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8417 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8418
8419 /*** SPE extension ***/
8420 /* Register moves */
8421
8422 static inline void gen_evmra(DisasContext *ctx)
8423 {
8424
8425 if (unlikely(!ctx->spe_enabled)) {
8426 gen_exception(ctx, POWERPC_EXCP_SPEU);
8427 return;
8428 }
8429
8430 TCGv_i64 tmp = tcg_temp_new_i64();
8431
8432 /* tmp := rA_lo + rA_hi << 32 */
8433 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8434
8435 /* spe_acc := tmp */
8436 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8437 tcg_temp_free_i64(tmp);
8438
8439 /* rD := rA */
8440 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8441 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8442 }
8443
8444 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8445 {
8446 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8447 }
8448
8449 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8450 {
8451 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8452 }
8453
8454 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8455 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8456 { \
8457 if (Rc(ctx->opcode)) \
8458 gen_##name1(ctx); \
8459 else \
8460 gen_##name0(ctx); \
8461 }
8462
8463 /* Handler for undefined SPE opcodes */
8464 static inline void gen_speundef(DisasContext *ctx)
8465 {
8466 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8467 }
8468
8469 /* SPE logic */
8470 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8471 static inline void gen_##name(DisasContext *ctx) \
8472 { \
8473 if (unlikely(!ctx->spe_enabled)) { \
8474 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8475 return; \
8476 } \
8477 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8478 cpu_gpr[rB(ctx->opcode)]); \
8479 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8480 cpu_gprh[rB(ctx->opcode)]); \
8481 }
8482
8483 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8484 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8485 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8486 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8487 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8488 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8489 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8490 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8491
8492 /* SPE logic immediate */
8493 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8494 static inline void gen_##name(DisasContext *ctx) \
8495 { \
8496 TCGv_i32 t0; \
8497 if (unlikely(!ctx->spe_enabled)) { \
8498 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8499 return; \
8500 } \
8501 t0 = tcg_temp_new_i32(); \
8502 \
8503 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8504 tcg_opi(t0, t0, rB(ctx->opcode)); \
8505 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8506 \
8507 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8508 tcg_opi(t0, t0, rB(ctx->opcode)); \
8509 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8510 \
8511 tcg_temp_free_i32(t0); \
8512 }
8513 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8514 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8515 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8516 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8517
8518 /* SPE arithmetic */
8519 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8520 static inline void gen_##name(DisasContext *ctx) \
8521 { \
8522 TCGv_i32 t0; \
8523 if (unlikely(!ctx->spe_enabled)) { \
8524 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8525 return; \
8526 } \
8527 t0 = tcg_temp_new_i32(); \
8528 \
8529 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8530 tcg_op(t0, t0); \
8531 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8532 \
8533 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8534 tcg_op(t0, t0); \
8535 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8536 \
8537 tcg_temp_free_i32(t0); \
8538 }
8539
8540 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8541 {
8542 int l1 = gen_new_label();
8543 int l2 = gen_new_label();
8544
8545 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8546 tcg_gen_neg_i32(ret, arg1);
8547 tcg_gen_br(l2);
8548 gen_set_label(l1);
8549 tcg_gen_mov_i32(ret, arg1);
8550 gen_set_label(l2);
8551 }
8552 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8553 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8554 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8555 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8556 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8557 {
8558 tcg_gen_addi_i32(ret, arg1, 0x8000);
8559 tcg_gen_ext16u_i32(ret, ret);
8560 }
8561 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8562 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8563 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8564
8565 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8566 static inline void gen_##name(DisasContext *ctx) \
8567 { \
8568 TCGv_i32 t0, t1; \
8569 if (unlikely(!ctx->spe_enabled)) { \
8570 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8571 return; \
8572 } \
8573 t0 = tcg_temp_new_i32(); \
8574 t1 = tcg_temp_new_i32(); \
8575 \
8576 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8577 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8578 tcg_op(t0, t0, t1); \
8579 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8580 \
8581 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8582 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8583 tcg_op(t0, t0, t1); \
8584 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8585 \
8586 tcg_temp_free_i32(t0); \
8587 tcg_temp_free_i32(t1); \
8588 }
8589
8590 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8591 {
8592 TCGv_i32 t0;
8593 int l1, l2;
8594
8595 l1 = gen_new_label();
8596 l2 = gen_new_label();
8597 t0 = tcg_temp_local_new_i32();
8598 /* No error here: 6 bits are used */
8599 tcg_gen_andi_i32(t0, arg2, 0x3F);
8600 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8601 tcg_gen_shr_i32(ret, arg1, t0);
8602 tcg_gen_br(l2);
8603 gen_set_label(l1);
8604 tcg_gen_movi_i32(ret, 0);
8605 gen_set_label(l2);
8606 tcg_temp_free_i32(t0);
8607 }
8608 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8609 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8610 {
8611 TCGv_i32 t0;
8612 int l1, l2;
8613
8614 l1 = gen_new_label();
8615 l2 = gen_new_label();
8616 t0 = tcg_temp_local_new_i32();
8617 /* No error here: 6 bits are used */
8618 tcg_gen_andi_i32(t0, arg2, 0x3F);
8619 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8620 tcg_gen_sar_i32(ret, arg1, t0);
8621 tcg_gen_br(l2);
8622 gen_set_label(l1);
8623 tcg_gen_movi_i32(ret, 0);
8624 gen_set_label(l2);
8625 tcg_temp_free_i32(t0);
8626 }
8627 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8628 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8629 {
8630 TCGv_i32 t0;
8631 int l1, l2;
8632
8633 l1 = gen_new_label();
8634 l2 = gen_new_label();
8635 t0 = tcg_temp_local_new_i32();
8636 /* No error here: 6 bits are used */
8637 tcg_gen_andi_i32(t0, arg2, 0x3F);
8638 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8639 tcg_gen_shl_i32(ret, arg1, t0);
8640 tcg_gen_br(l2);
8641 gen_set_label(l1);
8642 tcg_gen_movi_i32(ret, 0);
8643 gen_set_label(l2);
8644 tcg_temp_free_i32(t0);
8645 }
8646 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8647 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8648 {
8649 TCGv_i32 t0 = tcg_temp_new_i32();
8650 tcg_gen_andi_i32(t0, arg2, 0x1F);
8651 tcg_gen_rotl_i32(ret, arg1, t0);
8652 tcg_temp_free_i32(t0);
8653 }
8654 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8655 static inline void gen_evmergehi(DisasContext *ctx)
8656 {
8657 if (unlikely(!ctx->spe_enabled)) {
8658 gen_exception(ctx, POWERPC_EXCP_SPEU);
8659 return;
8660 }
8661 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8662 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8663 }
8664 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8665 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8666 {
8667 tcg_gen_sub_i32(ret, arg2, arg1);
8668 }
8669 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8670
8671 /* SPE arithmetic immediate */
8672 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8673 static inline void gen_##name(DisasContext *ctx) \
8674 { \
8675 TCGv_i32 t0; \
8676 if (unlikely(!ctx->spe_enabled)) { \
8677 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8678 return; \
8679 } \
8680 t0 = tcg_temp_new_i32(); \
8681 \
8682 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8683 tcg_op(t0, t0, rA(ctx->opcode)); \
8684 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8685 \
8686 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8687 tcg_op(t0, t0, rA(ctx->opcode)); \
8688 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8689 \
8690 tcg_temp_free_i32(t0); \
8691 }
8692 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8693 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8694
8695 /* SPE comparison */
8696 #define GEN_SPEOP_COMP(name, tcg_cond) \
8697 static inline void gen_##name(DisasContext *ctx) \
8698 { \
8699 if (unlikely(!ctx->spe_enabled)) { \
8700 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8701 return; \
8702 } \
8703 int l1 = gen_new_label(); \
8704 int l2 = gen_new_label(); \
8705 int l3 = gen_new_label(); \
8706 int l4 = gen_new_label(); \
8707 \
8708 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8709 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8710 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8711 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8712 \
8713 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8714 cpu_gpr[rB(ctx->opcode)], l1); \
8715 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8716 tcg_gen_br(l2); \
8717 gen_set_label(l1); \
8718 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8719 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8720 gen_set_label(l2); \
8721 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8722 cpu_gprh[rB(ctx->opcode)], l3); \
8723 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8724 ~(CRF_CH | CRF_CH_AND_CL)); \
8725 tcg_gen_br(l4); \
8726 gen_set_label(l3); \
8727 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8728 CRF_CH | CRF_CH_OR_CL); \
8729 gen_set_label(l4); \
8730 }
8731 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8732 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8733 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8734 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8735 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8736
8737 /* SPE misc */
8738 static inline void gen_brinc(DisasContext *ctx)
8739 {
8740 /* Note: brinc is usable even if SPE is disabled */
8741 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8742 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8743 }
8744 static inline void gen_evmergelo(DisasContext *ctx)
8745 {
8746 if (unlikely(!ctx->spe_enabled)) {
8747 gen_exception(ctx, POWERPC_EXCP_SPEU);
8748 return;
8749 }
8750 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8751 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8752 }
8753 static inline void gen_evmergehilo(DisasContext *ctx)
8754 {
8755 if (unlikely(!ctx->spe_enabled)) {
8756 gen_exception(ctx, POWERPC_EXCP_SPEU);
8757 return;
8758 }
8759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8760 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8761 }
8762 static inline void gen_evmergelohi(DisasContext *ctx)
8763 {
8764 if (unlikely(!ctx->spe_enabled)) {
8765 gen_exception(ctx, POWERPC_EXCP_SPEU);
8766 return;
8767 }
8768 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8769 TCGv tmp = tcg_temp_new();
8770 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8771 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8772 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8773 tcg_temp_free(tmp);
8774 } else {
8775 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8776 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8777 }
8778 }
8779 static inline void gen_evsplati(DisasContext *ctx)
8780 {
8781 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8782
8783 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8784 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8785 }
8786 static inline void gen_evsplatfi(DisasContext *ctx)
8787 {
8788 uint64_t imm = rA(ctx->opcode) << 27;
8789
8790 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8791 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8792 }
8793
8794 static inline void gen_evsel(DisasContext *ctx)
8795 {
8796 int l1 = gen_new_label();
8797 int l2 = gen_new_label();
8798 int l3 = gen_new_label();
8799 int l4 = gen_new_label();
8800 TCGv_i32 t0 = tcg_temp_local_new_i32();
8801 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8802 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8803 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8804 tcg_gen_br(l2);
8805 gen_set_label(l1);
8806 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8807 gen_set_label(l2);
8808 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8809 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8810 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8811 tcg_gen_br(l4);
8812 gen_set_label(l3);
8813 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8814 gen_set_label(l4);
8815 tcg_temp_free_i32(t0);
8816 }
8817
8818 static void gen_evsel0(DisasContext *ctx)
8819 {
8820 gen_evsel(ctx);
8821 }
8822
8823 static void gen_evsel1(DisasContext *ctx)
8824 {
8825 gen_evsel(ctx);
8826 }
8827
8828 static void gen_evsel2(DisasContext *ctx)
8829 {
8830 gen_evsel(ctx);
8831 }
8832
8833 static void gen_evsel3(DisasContext *ctx)
8834 {
8835 gen_evsel(ctx);
8836 }
8837
8838 /* Multiply */
8839
8840 static inline void gen_evmwumi(DisasContext *ctx)
8841 {
8842 TCGv_i64 t0, t1;
8843
8844 if (unlikely(!ctx->spe_enabled)) {
8845 gen_exception(ctx, POWERPC_EXCP_SPEU);
8846 return;
8847 }
8848
8849 t0 = tcg_temp_new_i64();
8850 t1 = tcg_temp_new_i64();
8851
8852 /* t0 := rA; t1 := rB */
8853 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8854 tcg_gen_ext32u_i64(t0, t0);
8855 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8856 tcg_gen_ext32u_i64(t1, t1);
8857
8858 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8859
8860 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8861
8862 tcg_temp_free_i64(t0);
8863 tcg_temp_free_i64(t1);
8864 }
8865
8866 static inline void gen_evmwumia(DisasContext *ctx)
8867 {
8868 TCGv_i64 tmp;
8869
8870 if (unlikely(!ctx->spe_enabled)) {
8871 gen_exception(ctx, POWERPC_EXCP_SPEU);
8872 return;
8873 }
8874
8875 gen_evmwumi(ctx); /* rD := rA * rB */
8876
8877 tmp = tcg_temp_new_i64();
8878
8879 /* acc := rD */
8880 gen_load_gpr64(tmp, rD(ctx->opcode));
8881 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8882 tcg_temp_free_i64(tmp);
8883 }
8884
8885 static inline void gen_evmwumiaa(DisasContext *ctx)
8886 {
8887 TCGv_i64 acc;
8888 TCGv_i64 tmp;
8889
8890 if (unlikely(!ctx->spe_enabled)) {
8891 gen_exception(ctx, POWERPC_EXCP_SPEU);
8892 return;
8893 }
8894
8895 gen_evmwumi(ctx); /* rD := rA * rB */
8896
8897 acc = tcg_temp_new_i64();
8898 tmp = tcg_temp_new_i64();
8899
8900 /* tmp := rD */
8901 gen_load_gpr64(tmp, rD(ctx->opcode));
8902
8903 /* Load acc */
8904 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8905
8906 /* acc := tmp + acc */
8907 tcg_gen_add_i64(acc, acc, tmp);
8908
8909 /* Store acc */
8910 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8911
8912 /* rD := acc */
8913 gen_store_gpr64(rD(ctx->opcode), acc);
8914
8915 tcg_temp_free_i64(acc);
8916 tcg_temp_free_i64(tmp);
8917 }
8918
8919 static inline void gen_evmwsmi(DisasContext *ctx)
8920 {
8921 TCGv_i64 t0, t1;
8922
8923 if (unlikely(!ctx->spe_enabled)) {
8924 gen_exception(ctx, POWERPC_EXCP_SPEU);
8925 return;
8926 }
8927
8928 t0 = tcg_temp_new_i64();
8929 t1 = tcg_temp_new_i64();
8930
8931 /* t0 := rA; t1 := rB */
8932 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8933 tcg_gen_ext32s_i64(t0, t0);
8934 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8935 tcg_gen_ext32s_i64(t1, t1);
8936
8937 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8938
8939 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8940
8941 tcg_temp_free_i64(t0);
8942 tcg_temp_free_i64(t1);
8943 }
8944
8945 static inline void gen_evmwsmia(DisasContext *ctx)
8946 {
8947 TCGv_i64 tmp;
8948
8949 gen_evmwsmi(ctx); /* rD := rA * rB */
8950
8951 tmp = tcg_temp_new_i64();
8952
8953 /* acc := rD */
8954 gen_load_gpr64(tmp, rD(ctx->opcode));
8955 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8956
8957 tcg_temp_free_i64(tmp);
8958 }
8959
8960 static inline void gen_evmwsmiaa(DisasContext *ctx)
8961 {
8962 TCGv_i64 acc = tcg_temp_new_i64();
8963 TCGv_i64 tmp = tcg_temp_new_i64();
8964
8965 gen_evmwsmi(ctx); /* rD := rA * rB */
8966
8967 acc = tcg_temp_new_i64();
8968 tmp = tcg_temp_new_i64();
8969
8970 /* tmp := rD */
8971 gen_load_gpr64(tmp, rD(ctx->opcode));
8972
8973 /* Load acc */
8974 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8975
8976 /* acc := tmp + acc */
8977 tcg_gen_add_i64(acc, acc, tmp);
8978
8979 /* Store acc */
8980 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8981
8982 /* rD := acc */
8983 gen_store_gpr64(rD(ctx->opcode), acc);
8984
8985 tcg_temp_free_i64(acc);
8986 tcg_temp_free_i64(tmp);
8987 }
8988
8989 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8990 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8991 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8992 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8993 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8994 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8995 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8996 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8997 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8998 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8999 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9000 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9001 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9002 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9003 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9004 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9005 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9006 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9007 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9008 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9009 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9010 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9011 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9012 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9013 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9014 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9015 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9016 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9017 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9018
9019 /* SPE load and stores */
9020 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9021 {
9022 target_ulong uimm = rB(ctx->opcode);
9023
9024 if (rA(ctx->opcode) == 0) {
9025 tcg_gen_movi_tl(EA, uimm << sh);
9026 } else {
9027 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9028 if (NARROW_MODE(ctx)) {
9029 tcg_gen_ext32u_tl(EA, EA);
9030 }
9031 }
9032 }
9033
9034 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9035 {
9036 TCGv_i64 t0 = tcg_temp_new_i64();
9037 gen_qemu_ld64(ctx, t0, addr);
9038 gen_store_gpr64(rD(ctx->opcode), t0);
9039 tcg_temp_free_i64(t0);
9040 }
9041
9042 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9043 {
9044 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9045 gen_addr_add(ctx, addr, addr, 4);
9046 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9047 }
9048
9049 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9050 {
9051 TCGv t0 = tcg_temp_new();
9052 gen_qemu_ld16u(ctx, t0, addr);
9053 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9054 gen_addr_add(ctx, addr, addr, 2);
9055 gen_qemu_ld16u(ctx, t0, addr);
9056 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9057 gen_addr_add(ctx, addr, addr, 2);
9058 gen_qemu_ld16u(ctx, t0, addr);
9059 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9060 gen_addr_add(ctx, addr, addr, 2);
9061 gen_qemu_ld16u(ctx, t0, addr);
9062 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9063 tcg_temp_free(t0);
9064 }
9065
9066 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9067 {
9068 TCGv t0 = tcg_temp_new();
9069 gen_qemu_ld16u(ctx, t0, addr);
9070 tcg_gen_shli_tl(t0, t0, 16);
9071 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9072 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9073 tcg_temp_free(t0);
9074 }
9075
9076 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9077 {
9078 TCGv t0 = tcg_temp_new();
9079 gen_qemu_ld16u(ctx, t0, addr);
9080 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9081 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9082 tcg_temp_free(t0);
9083 }
9084
9085 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9086 {
9087 TCGv t0 = tcg_temp_new();
9088 gen_qemu_ld16s(ctx, t0, addr);
9089 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9090 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9091 tcg_temp_free(t0);
9092 }
9093
9094 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9095 {
9096 TCGv t0 = tcg_temp_new();
9097 gen_qemu_ld16u(ctx, t0, addr);
9098 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9099 gen_addr_add(ctx, addr, addr, 2);
9100 gen_qemu_ld16u(ctx, t0, addr);
9101 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9102 tcg_temp_free(t0);
9103 }
9104
9105 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9106 {
9107 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9108 gen_addr_add(ctx, addr, addr, 2);
9109 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9110 }
9111
9112 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9113 {
9114 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9115 gen_addr_add(ctx, addr, addr, 2);
9116 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9117 }
9118
9119 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9120 {
9121 TCGv t0 = tcg_temp_new();
9122 gen_qemu_ld32u(ctx, t0, addr);
9123 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9124 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9125 tcg_temp_free(t0);
9126 }
9127
9128 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9129 {
9130 TCGv t0 = tcg_temp_new();
9131 gen_qemu_ld16u(ctx, t0, addr);
9132 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9133 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9134 gen_addr_add(ctx, addr, addr, 2);
9135 gen_qemu_ld16u(ctx, t0, addr);
9136 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9137 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9138 tcg_temp_free(t0);
9139 }
9140
9141 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9142 {
9143 TCGv_i64 t0 = tcg_temp_new_i64();
9144 gen_load_gpr64(t0, rS(ctx->opcode));
9145 gen_qemu_st64(ctx, t0, addr);
9146 tcg_temp_free_i64(t0);
9147 }
9148
9149 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9150 {
9151 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9152 gen_addr_add(ctx, addr, addr, 4);
9153 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9154 }
9155
9156 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9157 {
9158 TCGv t0 = tcg_temp_new();
9159 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9160 gen_qemu_st16(ctx, t0, addr);
9161 gen_addr_add(ctx, addr, addr, 2);
9162 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9163 gen_addr_add(ctx, addr, addr, 2);
9164 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9165 gen_qemu_st16(ctx, t0, addr);
9166 tcg_temp_free(t0);
9167 gen_addr_add(ctx, addr, addr, 2);
9168 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9169 }
9170
9171 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9172 {
9173 TCGv t0 = tcg_temp_new();
9174 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9175 gen_qemu_st16(ctx, t0, addr);
9176 gen_addr_add(ctx, addr, addr, 2);
9177 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9178 gen_qemu_st16(ctx, t0, addr);
9179 tcg_temp_free(t0);
9180 }
9181
9182 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9183 {
9184 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9185 gen_addr_add(ctx, addr, addr, 2);
9186 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9187 }
9188
9189 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9190 {
9191 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9192 }
9193
9194 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9195 {
9196 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9197 }
9198
9199 #define GEN_SPEOP_LDST(name, opc2, sh) \
9200 static void glue(gen_, name)(DisasContext *ctx) \
9201 { \
9202 TCGv t0; \
9203 if (unlikely(!ctx->spe_enabled)) { \
9204 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9205 return; \
9206 } \
9207 gen_set_access_type(ctx, ACCESS_INT); \
9208 t0 = tcg_temp_new(); \
9209 if (Rc(ctx->opcode)) { \
9210 gen_addr_spe_imm_index(ctx, t0, sh); \
9211 } else { \
9212 gen_addr_reg_index(ctx, t0); \
9213 } \
9214 gen_op_##name(ctx, t0); \
9215 tcg_temp_free(t0); \
9216 }
9217
9218 GEN_SPEOP_LDST(evldd, 0x00, 3);
9219 GEN_SPEOP_LDST(evldw, 0x01, 3);
9220 GEN_SPEOP_LDST(evldh, 0x02, 3);
9221 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9222 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9223 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9224 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9225 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9226 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9227 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9228 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9229
9230 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9231 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9232 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9233 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9234 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9235 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9236 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9237
9238 /* Multiply and add - TODO */
9239 #if 0
9240 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9241 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9242 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9243 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9244 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9245 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9246 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9247 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9248 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9249 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9250 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9251 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9252
9253 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9254 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9255 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9256 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9257 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9258 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9259 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9260 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9261 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9262 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9263 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9264 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9265
9266 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9267 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9268 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9269 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9270 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9271
9272 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9273 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9274 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9275 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9276 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9277 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9278 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9279 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9280 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9281 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9282 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9283 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9284
9285 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9286 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9287 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9288 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9289
9290 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9291 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9292 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9293 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9294 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9295 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9296 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9297 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9298 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9299 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9300 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9301 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9302
9303 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9304 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9305 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9306 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9307 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9308 #endif
9309
9310 /*** SPE floating-point extension ***/
9311 #define GEN_SPEFPUOP_CONV_32_32(name) \
9312 static inline void gen_##name(DisasContext *ctx) \
9313 { \
9314 TCGv_i32 t0 = tcg_temp_new_i32(); \
9315 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9316 gen_helper_##name(t0, cpu_env, t0); \
9317 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9318 tcg_temp_free_i32(t0); \
9319 }
9320 #define GEN_SPEFPUOP_CONV_32_64(name) \
9321 static inline void gen_##name(DisasContext *ctx) \
9322 { \
9323 TCGv_i64 t0 = tcg_temp_new_i64(); \
9324 TCGv_i32 t1 = tcg_temp_new_i32(); \
9325 gen_load_gpr64(t0, rB(ctx->opcode)); \
9326 gen_helper_##name(t1, cpu_env, t0); \
9327 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9328 tcg_temp_free_i64(t0); \
9329 tcg_temp_free_i32(t1); \
9330 }
9331 #define GEN_SPEFPUOP_CONV_64_32(name) \
9332 static inline void gen_##name(DisasContext *ctx) \
9333 { \
9334 TCGv_i64 t0 = tcg_temp_new_i64(); \
9335 TCGv_i32 t1 = tcg_temp_new_i32(); \
9336 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9337 gen_helper_##name(t0, cpu_env, t1); \
9338 gen_store_gpr64(rD(ctx->opcode), t0); \
9339 tcg_temp_free_i64(t0); \
9340 tcg_temp_free_i32(t1); \
9341 }
9342 #define GEN_SPEFPUOP_CONV_64_64(name) \
9343 static inline void gen_##name(DisasContext *ctx) \
9344 { \
9345 TCGv_i64 t0 = tcg_temp_new_i64(); \
9346 gen_load_gpr64(t0, rB(ctx->opcode)); \
9347 gen_helper_##name(t0, cpu_env, t0); \
9348 gen_store_gpr64(rD(ctx->opcode), t0); \
9349 tcg_temp_free_i64(t0); \
9350 }
9351 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9352 static inline void gen_##name(DisasContext *ctx) \
9353 { \
9354 TCGv_i32 t0, t1; \
9355 if (unlikely(!ctx->spe_enabled)) { \
9356 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9357 return; \
9358 } \
9359 t0 = tcg_temp_new_i32(); \
9360 t1 = tcg_temp_new_i32(); \
9361 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9362 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9363 gen_helper_##name(t0, cpu_env, t0, t1); \
9364 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9365 \
9366 tcg_temp_free_i32(t0); \
9367 tcg_temp_free_i32(t1); \
9368 }
9369 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9370 static inline void gen_##name(DisasContext *ctx) \
9371 { \
9372 TCGv_i64 t0, t1; \
9373 if (unlikely(!ctx->spe_enabled)) { \
9374 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9375 return; \
9376 } \
9377 t0 = tcg_temp_new_i64(); \
9378 t1 = tcg_temp_new_i64(); \
9379 gen_load_gpr64(t0, rA(ctx->opcode)); \
9380 gen_load_gpr64(t1, rB(ctx->opcode)); \
9381 gen_helper_##name(t0, cpu_env, t0, t1); \
9382 gen_store_gpr64(rD(ctx->opcode), t0); \
9383 tcg_temp_free_i64(t0); \
9384 tcg_temp_free_i64(t1); \
9385 }
9386 #define GEN_SPEFPUOP_COMP_32(name) \
9387 static inline void gen_##name(DisasContext *ctx) \
9388 { \
9389 TCGv_i32 t0, t1; \
9390 if (unlikely(!ctx->spe_enabled)) { \
9391 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9392 return; \
9393 } \
9394 t0 = tcg_temp_new_i32(); \
9395 t1 = tcg_temp_new_i32(); \
9396 \
9397 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9398 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9399 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9400 \
9401 tcg_temp_free_i32(t0); \
9402 tcg_temp_free_i32(t1); \
9403 }
9404 #define GEN_SPEFPUOP_COMP_64(name) \
9405 static inline void gen_##name(DisasContext *ctx) \
9406 { \
9407 TCGv_i64 t0, t1; \
9408 if (unlikely(!ctx->spe_enabled)) { \
9409 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9410 return; \
9411 } \
9412 t0 = tcg_temp_new_i64(); \
9413 t1 = tcg_temp_new_i64(); \
9414 gen_load_gpr64(t0, rA(ctx->opcode)); \
9415 gen_load_gpr64(t1, rB(ctx->opcode)); \
9416 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9417 tcg_temp_free_i64(t0); \
9418 tcg_temp_free_i64(t1); \
9419 }
9420
9421 /* Single precision floating-point vectors operations */
9422 /* Arithmetic */
9423 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9424 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9425 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9426 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9427 static inline void gen_evfsabs(DisasContext *ctx)
9428 {
9429 if (unlikely(!ctx->spe_enabled)) {
9430 gen_exception(ctx, POWERPC_EXCP_SPEU);
9431 return;
9432 }
9433 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9434 ~0x80000000);
9435 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9436 ~0x80000000);
9437 }
9438 static inline void gen_evfsnabs(DisasContext *ctx)
9439 {
9440 if (unlikely(!ctx->spe_enabled)) {
9441 gen_exception(ctx, POWERPC_EXCP_SPEU);
9442 return;
9443 }
9444 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9445 0x80000000);
9446 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9447 0x80000000);
9448 }
9449 static inline void gen_evfsneg(DisasContext *ctx)
9450 {
9451 if (unlikely(!ctx->spe_enabled)) {
9452 gen_exception(ctx, POWERPC_EXCP_SPEU);
9453 return;
9454 }
9455 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9456 0x80000000);
9457 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9458 0x80000000);
9459 }
9460
9461 /* Conversion */
9462 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9463 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9464 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9465 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9466 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9467 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9468 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9469 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9470 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9471 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9472
9473 /* Comparison */
9474 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9475 GEN_SPEFPUOP_COMP_64(evfscmplt);
9476 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9477 GEN_SPEFPUOP_COMP_64(evfststgt);
9478 GEN_SPEFPUOP_COMP_64(evfststlt);
9479 GEN_SPEFPUOP_COMP_64(evfststeq);
9480
9481 /* Opcodes definitions */
9482 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9483 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9484 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9485 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9486 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9487 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9488 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9489 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9490 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9491 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9492 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9493 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9494 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9495 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9496
9497 /* Single precision floating-point operations */
9498 /* Arithmetic */
9499 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9500 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9501 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9502 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9503 static inline void gen_efsabs(DisasContext *ctx)
9504 {
9505 if (unlikely(!ctx->spe_enabled)) {
9506 gen_exception(ctx, POWERPC_EXCP_SPEU);
9507 return;
9508 }
9509 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9510 }
9511 static inline void gen_efsnabs(DisasContext *ctx)
9512 {
9513 if (unlikely(!ctx->spe_enabled)) {
9514 gen_exception(ctx, POWERPC_EXCP_SPEU);
9515 return;
9516 }
9517 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9518 }
9519 static inline void gen_efsneg(DisasContext *ctx)
9520 {
9521 if (unlikely(!ctx->spe_enabled)) {
9522 gen_exception(ctx, POWERPC_EXCP_SPEU);
9523 return;
9524 }
9525 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9526 }
9527
9528 /* Conversion */
9529 GEN_SPEFPUOP_CONV_32_32(efscfui);
9530 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9531 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9532 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9533 GEN_SPEFPUOP_CONV_32_32(efsctui);
9534 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9535 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9536 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9537 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9538 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9539 GEN_SPEFPUOP_CONV_32_64(efscfd);
9540
9541 /* Comparison */
9542 GEN_SPEFPUOP_COMP_32(efscmpgt);
9543 GEN_SPEFPUOP_COMP_32(efscmplt);
9544 GEN_SPEFPUOP_COMP_32(efscmpeq);
9545 GEN_SPEFPUOP_COMP_32(efststgt);
9546 GEN_SPEFPUOP_COMP_32(efststlt);
9547 GEN_SPEFPUOP_COMP_32(efststeq);
9548
9549 /* Opcodes definitions */
9550 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9551 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9552 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9553 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9554 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9555 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9556 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9557 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9558 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9559 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9560 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9561 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9562 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9563 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9564
9565 /* Double precision floating-point operations */
9566 /* Arithmetic */
9567 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9568 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9569 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9570 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9571 static inline void gen_efdabs(DisasContext *ctx)
9572 {
9573 if (unlikely(!ctx->spe_enabled)) {
9574 gen_exception(ctx, POWERPC_EXCP_SPEU);
9575 return;
9576 }
9577 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9578 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9579 ~0x80000000);
9580 }
9581 static inline void gen_efdnabs(DisasContext *ctx)
9582 {
9583 if (unlikely(!ctx->spe_enabled)) {
9584 gen_exception(ctx, POWERPC_EXCP_SPEU);
9585 return;
9586 }
9587 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9588 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9589 0x80000000);
9590 }
9591 static inline void gen_efdneg(DisasContext *ctx)
9592 {
9593 if (unlikely(!ctx->spe_enabled)) {
9594 gen_exception(ctx, POWERPC_EXCP_SPEU);
9595 return;
9596 }
9597 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9598 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9599 0x80000000);
9600 }
9601
9602 /* Conversion */
9603 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9604 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9605 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9606 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9607 GEN_SPEFPUOP_CONV_32_64(efdctui);
9608 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9609 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9610 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9611 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9612 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9613 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9614 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9615 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9616 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9617 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9618
9619 /* Comparison */
9620 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9621 GEN_SPEFPUOP_COMP_64(efdcmplt);
9622 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9623 GEN_SPEFPUOP_COMP_64(efdtstgt);
9624 GEN_SPEFPUOP_COMP_64(efdtstlt);
9625 GEN_SPEFPUOP_COMP_64(efdtsteq);
9626
9627 /* Opcodes definitions */
9628 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9629 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9630 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9631 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9632 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9633 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9634 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9635 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9636 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9637 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9638 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9639 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9640 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9641 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9642 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9643 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9644
9645 static opcode_t opcodes[] = {
9646 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9647 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9648 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9649 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9650 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9651 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9652 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9653 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9654 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9655 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9656 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9657 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9658 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9659 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9660 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9661 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9662 #if defined(TARGET_PPC64)
9663 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9664 #endif
9665 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9666 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9667 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9668 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9669 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9670 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9671 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9672 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9673 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9674 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9675 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9676 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9677 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9678 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9679 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9680 #if defined(TARGET_PPC64)
9681 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9682 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9683 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9684 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9685 #endif
9686 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9687 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9688 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9689 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9690 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9691 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9692 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9693 #if defined(TARGET_PPC64)
9694 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9695 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9696 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9697 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9698 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9699 #endif
9700 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9701 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9702 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9703 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9704 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9705 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9706 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9707 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9708 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9709 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9710 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9711 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9712 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9713 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9714 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9715 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9716 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9717 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9718 #if defined(TARGET_PPC64)
9719 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9720 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9721 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9722 #endif
9723 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9724 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9725 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9726 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9727 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9728 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9729 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9730 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9731 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9732 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9733 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9734 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9735 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9736 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9737 #if defined(TARGET_PPC64)
9738 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9739 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9740 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9741 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9742 #endif
9743 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9744 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9745 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9746 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9747 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9748 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9749 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9750 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9751 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9752 #if defined(TARGET_PPC64)
9753 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9754 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9755 #endif
9756 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9757 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9758 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9759 #if defined(TARGET_PPC64)
9760 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9761 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9762 #endif
9763 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9764 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9765 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9766 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9767 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9768 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9769 #if defined(TARGET_PPC64)
9770 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9771 #endif
9772 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9773 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9774 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9775 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9776 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9777 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9778 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9779 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9780 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9781 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9782 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9783 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9784 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9785 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9786 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9787 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9788 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9789 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9790 #if defined(TARGET_PPC64)
9791 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9792 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9793 PPC_SEGMENT_64B),
9794 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9795 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9796 PPC_SEGMENT_64B),
9797 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9798 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9799 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9800 #endif
9801 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9802 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9803 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9804 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9805 #if defined(TARGET_PPC64)
9806 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9807 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9808 #endif
9809 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9810 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9811 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9812 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9813 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9814 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9815 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9816 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9817 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9818 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9819 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9820 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9821 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9822 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9823 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9824 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9825 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9826 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9827 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9828 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9829 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9830 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9831 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9832 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9833 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9834 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9835 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9836 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9837 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9838 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9839 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9840 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9841 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9842 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9843 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9844 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9845 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9846 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9847 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9848 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9849 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9850 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9851 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9852 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9853 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9854 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9855 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9856 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9857 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9858 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9859 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9860 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9861 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9862 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9863 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9864 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9865 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9866 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9867 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9868 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9869 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9870 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9871 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9872 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9873 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9874 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9875 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9876 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9877 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9878 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9879 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9880 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9881 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9882 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9883 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9884 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9885 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9886 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9887 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9888 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9889 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9890 PPC_NONE, PPC2_BOOKE206),
9891 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9892 PPC_NONE, PPC2_BOOKE206),
9893 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9894 PPC_NONE, PPC2_BOOKE206),
9895 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9896 PPC_NONE, PPC2_BOOKE206),
9897 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9898 PPC_NONE, PPC2_BOOKE206),
9899 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9900 PPC_NONE, PPC2_PRCNTL),
9901 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9902 PPC_NONE, PPC2_PRCNTL),
9903 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9904 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9905 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9906 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9907 PPC_BOOKE, PPC2_BOOKE206),
9908 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9909 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9910 PPC_BOOKE, PPC2_BOOKE206),
9911 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9912 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9913 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9914 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9915 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9916 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9917 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9918 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9919 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9920
9921 #undef GEN_INT_ARITH_ADD
9922 #undef GEN_INT_ARITH_ADD_CONST
9923 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9924 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9925 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9926 add_ca, compute_ca, compute_ov) \
9927 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9928 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9929 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9930 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9931 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9932 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9933 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9934 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9935 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9936 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9937 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9938
9939 #undef GEN_INT_ARITH_DIVW
9940 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9941 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9942 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9943 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9944 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9945 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9946 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9947 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9948 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9949 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9950
9951 #if defined(TARGET_PPC64)
9952 #undef GEN_INT_ARITH_DIVD
9953 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9954 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9955 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9956 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9957 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9958 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9959
9960 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9961 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9962 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9963 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9964
9965 #undef GEN_INT_ARITH_MUL_HELPER
9966 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9967 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9968 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9969 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9970 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9971 #endif
9972
9973 #undef GEN_INT_ARITH_SUBF
9974 #undef GEN_INT_ARITH_SUBF_CONST
9975 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9976 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9977 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9978 add_ca, compute_ca, compute_ov) \
9979 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9980 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9981 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9982 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9983 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9984 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9985 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9986 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9987 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9988 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9989 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9990
9991 #undef GEN_LOGICAL1
9992 #undef GEN_LOGICAL2
9993 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9994 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9995 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9996 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9997 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9998 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9999 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10000 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10001 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10002 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10003 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10004 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10005 #if defined(TARGET_PPC64)
10006 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10007 #endif
10008
10009 #if defined(TARGET_PPC64)
10010 #undef GEN_PPC64_R2
10011 #undef GEN_PPC64_R4
10012 #define GEN_PPC64_R2(name, opc1, opc2) \
10013 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10014 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10015 PPC_64B)
10016 #define GEN_PPC64_R4(name, opc1, opc2) \
10017 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10018 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10019 PPC_64B), \
10020 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10021 PPC_64B), \
10022 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10023 PPC_64B)
10024 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10025 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10026 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10027 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10028 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10029 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10030 #endif
10031
10032 #undef _GEN_FLOAT_ACB
10033 #undef GEN_FLOAT_ACB
10034 #undef _GEN_FLOAT_AB
10035 #undef GEN_FLOAT_AB
10036 #undef _GEN_FLOAT_AC
10037 #undef GEN_FLOAT_AC
10038 #undef GEN_FLOAT_B
10039 #undef GEN_FLOAT_BS
10040 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10041 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10042 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10043 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10044 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10045 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10046 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10047 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10048 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10049 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10050 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10051 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10052 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10053 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10054 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10055 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10056 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10057 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10058 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10059
10060 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10061 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10062 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10063 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10064 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10065 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10066 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10067 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10068 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10069 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10070 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10071 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10072 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10073 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10074 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10075 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10076 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10077 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10078 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10079 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10080 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10081 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10082 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10083 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10084 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10085 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10086 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10087 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10088 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10089 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10090 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10091
10092 #undef GEN_LD
10093 #undef GEN_LDU
10094 #undef GEN_LDUX
10095 #undef GEN_LDX_E
10096 #undef GEN_LDS
10097 #define GEN_LD(name, ldop, opc, type) \
10098 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10099 #define GEN_LDU(name, ldop, opc, type) \
10100 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10101 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10102 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10103 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10104 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10105 #define GEN_LDS(name, ldop, op, type) \
10106 GEN_LD(name, ldop, op | 0x20, type) \
10107 GEN_LDU(name, ldop, op | 0x21, type) \
10108 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10109 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10110
10111 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10112 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10113 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10114 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10115 #if defined(TARGET_PPC64)
10116 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10117 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10118 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10119 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10120 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10121 #endif
10122 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10123 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10124
10125 #undef GEN_ST
10126 #undef GEN_STU
10127 #undef GEN_STUX
10128 #undef GEN_STX_E
10129 #undef GEN_STS
10130 #define GEN_ST(name, stop, opc, type) \
10131 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10132 #define GEN_STU(name, stop, opc, type) \
10133 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10134 #define GEN_STUX(name, stop, opc2, opc3, type) \
10135 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10136 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10137 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10138 #define GEN_STS(name, stop, op, type) \
10139 GEN_ST(name, stop, op | 0x20, type) \
10140 GEN_STU(name, stop, op | 0x21, type) \
10141 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10142 GEN_STX(name, stop, 0x17, op | 0x00, type)
10143
10144 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10145 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10146 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10147 #if defined(TARGET_PPC64)
10148 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10149 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10150 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10151 #endif
10152 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10153 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10154
10155 #undef GEN_LDF
10156 #undef GEN_LDUF
10157 #undef GEN_LDUXF
10158 #undef GEN_LDXF
10159 #undef GEN_LDFS
10160 #define GEN_LDF(name, ldop, opc, type) \
10161 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10162 #define GEN_LDUF(name, ldop, opc, type) \
10163 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10164 #define GEN_LDUXF(name, ldop, opc, type) \
10165 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10166 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10167 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10168 #define GEN_LDFS(name, ldop, op, type) \
10169 GEN_LDF(name, ldop, op | 0x20, type) \
10170 GEN_LDUF(name, ldop, op | 0x21, type) \
10171 GEN_LDUXF(name, ldop, op | 0x01, type) \
10172 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10173
10174 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10175 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10176 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10177 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10178 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10179 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10180
10181 #undef GEN_STF
10182 #undef GEN_STUF
10183 #undef GEN_STUXF
10184 #undef GEN_STXF
10185 #undef GEN_STFS
10186 #define GEN_STF(name, stop, opc, type) \
10187 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10188 #define GEN_STUF(name, stop, opc, type) \
10189 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10190 #define GEN_STUXF(name, stop, opc, type) \
10191 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10192 #define GEN_STXF(name, stop, opc2, opc3, type) \
10193 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10194 #define GEN_STFS(name, stop, op, type) \
10195 GEN_STF(name, stop, op | 0x20, type) \
10196 GEN_STUF(name, stop, op | 0x21, type) \
10197 GEN_STUXF(name, stop, op | 0x01, type) \
10198 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10199
10200 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10201 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10202 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10203 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10204 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10205
10206 #undef GEN_CRLOGIC
10207 #define GEN_CRLOGIC(name, tcg_op, opc) \
10208 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10209 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10210 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10211 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10212 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10213 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10214 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10215 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10216 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10217
10218 #undef GEN_MAC_HANDLER
10219 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10220 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10221 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10222 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10223 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10224 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10225 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10226 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10227 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10228 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10229 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10230 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10231 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10232 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10233 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10234 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10235 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10236 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10237 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10238 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10239 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10240 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10241 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10242 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10243 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10244 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10245 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10246 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10247 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10248 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10249 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10250 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10251 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10252 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10253 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10254 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10255 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10256 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10257 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10258 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10259 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10260 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10261 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10262 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10263
10264 #undef GEN_VR_LDX
10265 #undef GEN_VR_STX
10266 #undef GEN_VR_LVE
10267 #undef GEN_VR_STVE
10268 #define GEN_VR_LDX(name, opc2, opc3) \
10269 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10270 #define GEN_VR_STX(name, opc2, opc3) \
10271 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10272 #define GEN_VR_LVE(name, opc2, opc3) \
10273 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10274 #define GEN_VR_STVE(name, opc2, opc3) \
10275 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10276 GEN_VR_LDX(lvx, 0x07, 0x03),
10277 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10278 GEN_VR_LVE(bx, 0x07, 0x00),
10279 GEN_VR_LVE(hx, 0x07, 0x01),
10280 GEN_VR_LVE(wx, 0x07, 0x02),
10281 GEN_VR_STX(svx, 0x07, 0x07),
10282 GEN_VR_STX(svxl, 0x07, 0x0F),
10283 GEN_VR_STVE(bx, 0x07, 0x04),
10284 GEN_VR_STVE(hx, 0x07, 0x05),
10285 GEN_VR_STVE(wx, 0x07, 0x06),
10286
10287 #undef GEN_VX_LOGICAL
10288 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10289 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10290
10291 #undef GEN_VX_LOGICAL_207
10292 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10293 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10294
10295 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10296 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10297 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10298 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10299 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10300 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10301 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10302 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10303
10304 #undef GEN_VXFORM
10305 #define GEN_VXFORM(name, opc2, opc3) \
10306 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10307
10308 #undef GEN_VXFORM_207
10309 #define GEN_VXFORM_207(name, opc2, opc3) \
10310 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10311
10312 #undef GEN_VXFORM_DUAL
10313 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10314 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10315
10316 #undef GEN_VXRFORM_DUAL
10317 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10318 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10319 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10320
10321 GEN_VXFORM(vaddubm, 0, 0),
10322 GEN_VXFORM(vadduhm, 0, 1),
10323 GEN_VXFORM(vadduwm, 0, 2),
10324 GEN_VXFORM_207(vaddudm, 0, 3),
10325 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10326 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10327 GEN_VXFORM(vsubuwm, 0, 18),
10328 GEN_VXFORM_207(vsubudm, 0, 19),
10329 GEN_VXFORM(vmaxub, 1, 0),
10330 GEN_VXFORM(vmaxuh, 1, 1),
10331 GEN_VXFORM(vmaxuw, 1, 2),
10332 GEN_VXFORM_207(vmaxud, 1, 3),
10333 GEN_VXFORM(vmaxsb, 1, 4),
10334 GEN_VXFORM(vmaxsh, 1, 5),
10335 GEN_VXFORM(vmaxsw, 1, 6),
10336 GEN_VXFORM_207(vmaxsd, 1, 7),
10337 GEN_VXFORM(vminub, 1, 8),
10338 GEN_VXFORM(vminuh, 1, 9),
10339 GEN_VXFORM(vminuw, 1, 10),
10340 GEN_VXFORM_207(vminud, 1, 11),
10341 GEN_VXFORM(vminsb, 1, 12),
10342 GEN_VXFORM(vminsh, 1, 13),
10343 GEN_VXFORM(vminsw, 1, 14),
10344 GEN_VXFORM_207(vminsd, 1, 15),
10345 GEN_VXFORM(vavgub, 1, 16),
10346 GEN_VXFORM(vavguh, 1, 17),
10347 GEN_VXFORM(vavguw, 1, 18),
10348 GEN_VXFORM(vavgsb, 1, 20),
10349 GEN_VXFORM(vavgsh, 1, 21),
10350 GEN_VXFORM(vavgsw, 1, 22),
10351 GEN_VXFORM(vmrghb, 6, 0),
10352 GEN_VXFORM(vmrghh, 6, 1),
10353 GEN_VXFORM(vmrghw, 6, 2),
10354 GEN_VXFORM(vmrglb, 6, 4),
10355 GEN_VXFORM(vmrglh, 6, 5),
10356 GEN_VXFORM(vmrglw, 6, 6),
10357 GEN_VXFORM_207(vmrgew, 6, 30),
10358 GEN_VXFORM_207(vmrgow, 6, 26),
10359 GEN_VXFORM(vmuloub, 4, 0),
10360 GEN_VXFORM(vmulouh, 4, 1),
10361 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10362 GEN_VXFORM(vmulosb, 4, 4),
10363 GEN_VXFORM(vmulosh, 4, 5),
10364 GEN_VXFORM_207(vmulosw, 4, 6),
10365 GEN_VXFORM(vmuleub, 4, 8),
10366 GEN_VXFORM(vmuleuh, 4, 9),
10367 GEN_VXFORM_207(vmuleuw, 4, 10),
10368 GEN_VXFORM(vmulesb, 4, 12),
10369 GEN_VXFORM(vmulesh, 4, 13),
10370 GEN_VXFORM_207(vmulesw, 4, 14),
10371 GEN_VXFORM(vslb, 2, 4),
10372 GEN_VXFORM(vslh, 2, 5),
10373 GEN_VXFORM(vslw, 2, 6),
10374 GEN_VXFORM_207(vsld, 2, 23),
10375 GEN_VXFORM(vsrb, 2, 8),
10376 GEN_VXFORM(vsrh, 2, 9),
10377 GEN_VXFORM(vsrw, 2, 10),
10378 GEN_VXFORM_207(vsrd, 2, 27),
10379 GEN_VXFORM(vsrab, 2, 12),
10380 GEN_VXFORM(vsrah, 2, 13),
10381 GEN_VXFORM(vsraw, 2, 14),
10382 GEN_VXFORM_207(vsrad, 2, 15),
10383 GEN_VXFORM(vslo, 6, 16),
10384 GEN_VXFORM(vsro, 6, 17),
10385 GEN_VXFORM(vaddcuw, 0, 6),
10386 GEN_VXFORM(vsubcuw, 0, 22),
10387 GEN_VXFORM(vaddubs, 0, 8),
10388 GEN_VXFORM(vadduhs, 0, 9),
10389 GEN_VXFORM(vadduws, 0, 10),
10390 GEN_VXFORM(vaddsbs, 0, 12),
10391 GEN_VXFORM(vaddshs, 0, 13),
10392 GEN_VXFORM(vaddsws, 0, 14),
10393 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10394 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10395 GEN_VXFORM(vsubuws, 0, 26),
10396 GEN_VXFORM(vsubsbs, 0, 28),
10397 GEN_VXFORM(vsubshs, 0, 29),
10398 GEN_VXFORM(vsubsws, 0, 30),
10399 GEN_VXFORM_207(vadduqm, 0, 4),
10400 GEN_VXFORM_207(vaddcuq, 0, 5),
10401 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10402 GEN_VXFORM_207(vsubuqm, 0, 20),
10403 GEN_VXFORM_207(vsubcuq, 0, 21),
10404 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10405 GEN_VXFORM(vrlb, 2, 0),
10406 GEN_VXFORM(vrlh, 2, 1),
10407 GEN_VXFORM(vrlw, 2, 2),
10408 GEN_VXFORM_207(vrld, 2, 3),
10409 GEN_VXFORM(vsl, 2, 7),
10410 GEN_VXFORM(vsr, 2, 11),
10411 GEN_VXFORM(vpkuhum, 7, 0),
10412 GEN_VXFORM(vpkuwum, 7, 1),
10413 GEN_VXFORM_207(vpkudum, 7, 17),
10414 GEN_VXFORM(vpkuhus, 7, 2),
10415 GEN_VXFORM(vpkuwus, 7, 3),
10416 GEN_VXFORM_207(vpkudus, 7, 19),
10417 GEN_VXFORM(vpkshus, 7, 4),
10418 GEN_VXFORM(vpkswus, 7, 5),
10419 GEN_VXFORM_207(vpksdus, 7, 21),
10420 GEN_VXFORM(vpkshss, 7, 6),
10421 GEN_VXFORM(vpkswss, 7, 7),
10422 GEN_VXFORM_207(vpksdss, 7, 23),
10423 GEN_VXFORM(vpkpx, 7, 12),
10424 GEN_VXFORM(vsum4ubs, 4, 24),
10425 GEN_VXFORM(vsum4sbs, 4, 28),
10426 GEN_VXFORM(vsum4shs, 4, 25),
10427 GEN_VXFORM(vsum2sws, 4, 26),
10428 GEN_VXFORM(vsumsws, 4, 30),
10429 GEN_VXFORM(vaddfp, 5, 0),
10430 GEN_VXFORM(vsubfp, 5, 1),
10431 GEN_VXFORM(vmaxfp, 5, 16),
10432 GEN_VXFORM(vminfp, 5, 17),
10433
10434 #undef GEN_VXRFORM1
10435 #undef GEN_VXRFORM
10436 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10437 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10438 #define GEN_VXRFORM(name, opc2, opc3) \
10439 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10440 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10441 GEN_VXRFORM(vcmpequb, 3, 0)
10442 GEN_VXRFORM(vcmpequh, 3, 1)
10443 GEN_VXRFORM(vcmpequw, 3, 2)
10444 GEN_VXRFORM(vcmpgtsb, 3, 12)
10445 GEN_VXRFORM(vcmpgtsh, 3, 13)
10446 GEN_VXRFORM(vcmpgtsw, 3, 14)
10447 GEN_VXRFORM(vcmpgtub, 3, 8)
10448 GEN_VXRFORM(vcmpgtuh, 3, 9)
10449 GEN_VXRFORM(vcmpgtuw, 3, 10)
10450 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10451 GEN_VXRFORM(vcmpgefp, 3, 7)
10452 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10453 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10454
10455 #undef GEN_VXFORM_SIMM
10456 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10457 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10458 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10459 GEN_VXFORM_SIMM(vspltish, 6, 13),
10460 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10461
10462 #undef GEN_VXFORM_NOA
10463 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10464 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10465 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10466 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10467 GEN_VXFORM_207(vupkhsw, 7, 25),
10468 GEN_VXFORM_NOA(vupklsb, 7, 10),
10469 GEN_VXFORM_NOA(vupklsh, 7, 11),
10470 GEN_VXFORM_207(vupklsw, 7, 27),
10471 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10472 GEN_VXFORM_NOA(vupklpx, 7, 15),
10473 GEN_VXFORM_NOA(vrefp, 5, 4),
10474 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10475 GEN_VXFORM_NOA(vexptefp, 5, 6),
10476 GEN_VXFORM_NOA(vlogefp, 5, 7),
10477 GEN_VXFORM_NOA(vrfim, 5, 11),
10478 GEN_VXFORM_NOA(vrfin, 5, 8),
10479 GEN_VXFORM_NOA(vrfip, 5, 10),
10480 GEN_VXFORM_NOA(vrfiz, 5, 9),
10481
10482 #undef GEN_VXFORM_UIMM
10483 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10484 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10485 GEN_VXFORM_UIMM(vspltb, 6, 8),
10486 GEN_VXFORM_UIMM(vsplth, 6, 9),
10487 GEN_VXFORM_UIMM(vspltw, 6, 10),
10488 GEN_VXFORM_UIMM(vcfux, 5, 12),
10489 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10490 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10491 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10492
10493 #undef GEN_VAFORM_PAIRED
10494 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10495 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10496 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10497 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10498 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10499 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10500 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10501 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10502
10503 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10504 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10505 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10506 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10507
10508 GEN_VXFORM_207(vbpermq, 6, 21),
10509 GEN_VXFORM_207(vgbbd, 6, 20),
10510 GEN_VXFORM_207(vpmsumb, 4, 16),
10511 GEN_VXFORM_207(vpmsumh, 4, 17),
10512 GEN_VXFORM_207(vpmsumw, 4, 18),
10513 GEN_VXFORM_207(vpmsumd, 4, 19),
10514
10515 GEN_VXFORM_207(vsbox, 4, 23),
10516
10517 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10518 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10519
10520 GEN_VXFORM_207(vshasigmaw, 1, 26),
10521 GEN_VXFORM_207(vshasigmad, 1, 27),
10522
10523 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10524
10525 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10526 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10527 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10528 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10529 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10530 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10531 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10532
10533 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10534 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10535 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10536 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10537 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10538
10539 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10540 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10541 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10542 #if defined(TARGET_PPC64)
10543 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10544 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10545 #endif
10546
10547 #undef GEN_XX2FORM
10548 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10549 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10550 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10551
10552 #undef GEN_XX3FORM
10553 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10554 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10555 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10556 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10557 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10558
10559 #undef GEN_XX3_RC_FORM
10560 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10561 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10562 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10563 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10564 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10565 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10566 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10567 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10568 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10569
10570 #undef GEN_XX3FORM_DM
10571 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10572 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10573 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10574 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10575 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10576 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10577 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10578 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10579 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10580 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10581 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10582 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10583 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10584 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10585 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10586 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10587 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10588
10589 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10590 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10591 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10592 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10593
10594 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10595 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10596 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10597 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10598 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10599 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10600 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10601 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10602
10603 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10604 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10605 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10606 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10607 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10608 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10609 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10610 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10611 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10612 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10613 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10614 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10615 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10616 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10617 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10618 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10619 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10620 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10621 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10622 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10623 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10624 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10625 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10626 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10627 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10628 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10629 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10630 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10631 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10632 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10633 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10634 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10635 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10636 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10637 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10638 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10639
10640 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10641 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10642 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10643 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10644 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10645 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10646 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10647 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10648 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10649 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10650 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10651 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10652 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10653 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10654 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10655 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10656 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10657 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10658
10659 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10660 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10661 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10662 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10663 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10664 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10665 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10666 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10667 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10668 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10669 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10670 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10671 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10672 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10673 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10674 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10675 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10676 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10677 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10678 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10679 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10680 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10681 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10682 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10683 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10684 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10685 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10686 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10687 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10688 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10689 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10690 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10691 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10692 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10693 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10694 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10695
10696 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10697 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10698 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10699 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10700 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10701 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10702 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10703 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10704 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10705 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10706 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10707 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10708 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10709 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10710 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10711 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10712 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10713 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10714 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10715 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10716 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10717 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10718 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10719 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10720 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10721 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10722 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10723 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10724 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10725 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10726 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10727 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10728 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10729 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10730 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10731 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10732
10733 #undef VSX_LOGICAL
10734 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10735 GEN_XX3FORM(name, opc2, opc3, fl2)
10736
10737 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10738 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10739 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10740 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10741 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10742 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10743 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10744 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10745 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10746 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10747 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10748 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10749
10750 #define GEN_XXSEL_ROW(opc3) \
10751 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10752 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10753 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10754 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10755 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10756 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10757 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10758 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10759
10760 GEN_XXSEL_ROW(0x00)
10761 GEN_XXSEL_ROW(0x01)
10762 GEN_XXSEL_ROW(0x02)
10763 GEN_XXSEL_ROW(0x03)
10764 GEN_XXSEL_ROW(0x04)
10765 GEN_XXSEL_ROW(0x05)
10766 GEN_XXSEL_ROW(0x06)
10767 GEN_XXSEL_ROW(0x07)
10768 GEN_XXSEL_ROW(0x08)
10769 GEN_XXSEL_ROW(0x09)
10770 GEN_XXSEL_ROW(0x0A)
10771 GEN_XXSEL_ROW(0x0B)
10772 GEN_XXSEL_ROW(0x0C)
10773 GEN_XXSEL_ROW(0x0D)
10774 GEN_XXSEL_ROW(0x0E)
10775 GEN_XXSEL_ROW(0x0F)
10776 GEN_XXSEL_ROW(0x10)
10777 GEN_XXSEL_ROW(0x11)
10778 GEN_XXSEL_ROW(0x12)
10779 GEN_XXSEL_ROW(0x13)
10780 GEN_XXSEL_ROW(0x14)
10781 GEN_XXSEL_ROW(0x15)
10782 GEN_XXSEL_ROW(0x16)
10783 GEN_XXSEL_ROW(0x17)
10784 GEN_XXSEL_ROW(0x18)
10785 GEN_XXSEL_ROW(0x19)
10786 GEN_XXSEL_ROW(0x1A)
10787 GEN_XXSEL_ROW(0x1B)
10788 GEN_XXSEL_ROW(0x1C)
10789 GEN_XXSEL_ROW(0x1D)
10790 GEN_XXSEL_ROW(0x1E)
10791 GEN_XXSEL_ROW(0x1F)
10792
10793 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10794
10795 #undef GEN_DFP_T_A_B_Rc
10796 #undef GEN_DFP_BF_A_B
10797 #undef GEN_DFP_BF_A_DCM
10798 #undef GEN_DFP_T_B_U32_U32_Rc
10799 #undef GEN_DFP_T_A_B_I32_Rc
10800 #undef GEN_DFP_T_B_Rc
10801 #undef GEN_DFP_T_FPR_I32_Rc
10802
10803 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10804 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10805
10806 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10807 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10808 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10809
10810 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10811 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10812 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10813 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10814 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10815
10816 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10817 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10818
10819 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10820 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10821 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10822
10823 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10824 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10825 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10826 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10827 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10828
10829 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10830 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10831
10832 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10833 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10834
10835 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10836 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10837
10838 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10839 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10840
10841 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10842 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10843
10844 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10845 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10846
10847 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10848 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10849
10850 #define GEN_DFP_BF_A_B(name, op1, op2) \
10851 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10852
10853 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10854 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10855
10856 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10857 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10858
10859 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10860 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10861
10862 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10863 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10864
10865 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10866 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10867
10868 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10869 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10870
10871 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10872 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10873
10874 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10875 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10876
10877 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10878 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10879
10880 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
10881 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
10882
10883 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
10884 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
10885
10886 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
10887 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
10888
10889 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
10890 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
10891
10892 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
10893 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
10894
10895 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
10896 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
10897
10898 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
10899 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
10900
10901 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
10902 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
10903
10904 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
10905 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
10906 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
10907 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
10908 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
10909 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
10910 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
10911 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
10912 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
10913 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
10914 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
10915 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
10916 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
10917 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
10918 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
10919 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
10920 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
10921 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
10922 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
10923 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
10924 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
10925 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
10926 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
10927 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
10928 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
10929 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
10930 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
10931 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
10932 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
10933 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
10934 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
10935 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
10936 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
10937 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
10938 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
10939 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
10940 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
10941 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
10942 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
10943 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
10944 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
10945 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
10946 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
10947 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
10948 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
10949 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
10950 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
10951 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
10952 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
10953 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
10954
10955 #undef GEN_SPE
10956 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10957 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10958 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10959 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10960 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10961 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10962 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10963 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10964 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10965 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10966 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10967 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10968 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10969 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10970 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10971 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10972 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10973 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10974 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10975 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10976 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10977 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10978 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10979 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10980 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10981 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10982 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10983 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10984 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10985 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10986 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10987
10988 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10989 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10990 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10991 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10992 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10993 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10994 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10995 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10996 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10997 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10998 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10999 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11000 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11001 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11002
11003 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11004 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11005 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11006 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11007 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11008 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11009 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11010 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11011 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11012 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11013 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11014 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11015 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11016 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11017
11018 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11019 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11020 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11021 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11022 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11023 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11024 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11025 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11026 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11027 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11028 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11029 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11030 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11031 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11032 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11033 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11034
11035 #undef GEN_SPEOP_LDST
11036 #define GEN_SPEOP_LDST(name, opc2, sh) \
11037 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11038 GEN_SPEOP_LDST(evldd, 0x00, 3),
11039 GEN_SPEOP_LDST(evldw, 0x01, 3),
11040 GEN_SPEOP_LDST(evldh, 0x02, 3),
11041 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11042 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11043 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11044 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11045 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11046 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11047 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11048 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11049
11050 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11051 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11052 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11053 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11054 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11055 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11056 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11057 };
11058
11059 #include "helper_regs.h"
11060 #include "translate_init.c"
11061
11062 /*****************************************************************************/
11063 /* Misc PowerPC helpers */
11064 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11065 int flags)
11066 {
11067 #define RGPL 4
11068 #define RFPL 4
11069
11070 PowerPCCPU *cpu = POWERPC_CPU(cs);
11071 CPUPPCState *env = &cpu->env;
11072 int i;
11073
11074 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11075 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
11076 env->nip, env->lr, env->ctr, cpu_read_xer(env));
11077 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11078 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11079 env->hflags, env->mmu_idx);
11080 #if !defined(NO_TIMER_DUMP)
11081 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11082 #if !defined(CONFIG_USER_ONLY)
11083 " DECR %08" PRIu32
11084 #endif
11085 "\n",
11086 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11087 #if !defined(CONFIG_USER_ONLY)
11088 , cpu_ppc_load_decr(env)
11089 #endif
11090 );
11091 #endif
11092 for (i = 0; i < 32; i++) {
11093 if ((i & (RGPL - 1)) == 0)
11094 cpu_fprintf(f, "GPR%02d", i);
11095 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11096 if ((i & (RGPL - 1)) == (RGPL - 1))
11097 cpu_fprintf(f, "\n");
11098 }
11099 cpu_fprintf(f, "CR ");
11100 for (i = 0; i < 8; i++)
11101 cpu_fprintf(f, "%01x", env->crf[i]);
11102 cpu_fprintf(f, " [");
11103 for (i = 0; i < 8; i++) {
11104 char a = '-';
11105 if (env->crf[i] & 0x08)
11106 a = 'L';
11107 else if (env->crf[i] & 0x04)
11108 a = 'G';
11109 else if (env->crf[i] & 0x02)
11110 a = 'E';
11111 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11112 }
11113 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11114 env->reserve_addr);
11115 for (i = 0; i < 32; i++) {
11116 if ((i & (RFPL - 1)) == 0)
11117 cpu_fprintf(f, "FPR%02d", i);
11118 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11119 if ((i & (RFPL - 1)) == (RFPL - 1))
11120 cpu_fprintf(f, "\n");
11121 }
11122 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11123 #if !defined(CONFIG_USER_ONLY)
11124 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11125 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11126 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11127 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11128
11129 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11130 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11131 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11132 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11133
11134 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11135 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11136 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11137 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11138
11139 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11140 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11141 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11142 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11143 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11144
11145 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11146 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11147 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11148 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11149
11150 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11151 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11152 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11153 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11154
11155 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11156 " EPR " TARGET_FMT_lx "\n",
11157 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11158 env->spr[SPR_BOOKE_EPR]);
11159
11160 /* FSL-specific */
11161 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11162 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11163 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11164 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11165
11166 /*
11167 * IVORs are left out as they are large and do not change often --
11168 * they can be read with "p $ivor0", "p $ivor1", etc.
11169 */
11170 }
11171
11172 #if defined(TARGET_PPC64)
11173 if (env->flags & POWERPC_FLAG_CFAR) {
11174 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11175 }
11176 #endif
11177
11178 switch (env->mmu_model) {
11179 case POWERPC_MMU_32B:
11180 case POWERPC_MMU_601:
11181 case POWERPC_MMU_SOFT_6xx:
11182 case POWERPC_MMU_SOFT_74xx:
11183 #if defined(TARGET_PPC64)
11184 case POWERPC_MMU_64B:
11185 case POWERPC_MMU_2_06:
11186 case POWERPC_MMU_2_06a:
11187 case POWERPC_MMU_2_06d:
11188 #endif
11189 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11190 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11191 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11192 break;
11193 case POWERPC_MMU_BOOKE206:
11194 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11195 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11196 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11197 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11198
11199 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11200 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11201 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11202 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11203
11204 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11205 " TLB1CFG " TARGET_FMT_lx "\n",
11206 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11207 env->spr[SPR_BOOKE_TLB1CFG]);
11208 break;
11209 default:
11210 break;
11211 }
11212 #endif
11213
11214 #undef RGPL
11215 #undef RFPL
11216 }
11217
11218 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11219 fprintf_function cpu_fprintf, int flags)
11220 {
11221 #if defined(DO_PPC_STATISTICS)
11222 PowerPCCPU *cpu = POWERPC_CPU(cs);
11223 opc_handler_t **t1, **t2, **t3, *handler;
11224 int op1, op2, op3;
11225
11226 t1 = cpu->env.opcodes;
11227 for (op1 = 0; op1 < 64; op1++) {
11228 handler = t1[op1];
11229 if (is_indirect_opcode(handler)) {
11230 t2 = ind_table(handler);
11231 for (op2 = 0; op2 < 32; op2++) {
11232 handler = t2[op2];
11233 if (is_indirect_opcode(handler)) {
11234 t3 = ind_table(handler);
11235 for (op3 = 0; op3 < 32; op3++) {
11236 handler = t3[op3];
11237 if (handler->count == 0)
11238 continue;
11239 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11240 "%016" PRIx64 " %" PRId64 "\n",
11241 op1, op2, op3, op1, (op3 << 5) | op2,
11242 handler->oname,
11243 handler->count, handler->count);
11244 }
11245 } else {
11246 if (handler->count == 0)
11247 continue;
11248 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11249 "%016" PRIx64 " %" PRId64 "\n",
11250 op1, op2, op1, op2, handler->oname,
11251 handler->count, handler->count);
11252 }
11253 }
11254 } else {
11255 if (handler->count == 0)
11256 continue;
11257 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11258 " %" PRId64 "\n",
11259 op1, op1, handler->oname,
11260 handler->count, handler->count);
11261 }
11262 }
11263 #endif
11264 }
11265
11266 /*****************************************************************************/
11267 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11268 TranslationBlock *tb,
11269 bool search_pc)
11270 {
11271 CPUState *cs = CPU(cpu);
11272 CPUPPCState *env = &cpu->env;
11273 DisasContext ctx, *ctxp = &ctx;
11274 opc_handler_t **table, *handler;
11275 target_ulong pc_start;
11276 uint16_t *gen_opc_end;
11277 CPUBreakpoint *bp;
11278 int j, lj = -1;
11279 int num_insns;
11280 int max_insns;
11281
11282 pc_start = tb->pc;
11283 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
11284 ctx.nip = pc_start;
11285 ctx.tb = tb;
11286 ctx.exception = POWERPC_EXCP_NONE;
11287 ctx.spr_cb = env->spr_cb;
11288 ctx.pr = msr_pr;
11289 ctx.hv = !msr_pr && msr_hv;
11290 ctx.mem_idx = env->mmu_idx;
11291 ctx.insns_flags = env->insns_flags;
11292 ctx.insns_flags2 = env->insns_flags2;
11293 ctx.access_type = -1;
11294 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11295 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11296 #if defined(TARGET_PPC64)
11297 ctx.sf_mode = msr_is_64bit(env, env->msr);
11298 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11299 #endif
11300 ctx.fpu_enabled = msr_fp;
11301 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11302 ctx.spe_enabled = msr_spe;
11303 else
11304 ctx.spe_enabled = 0;
11305 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11306 ctx.altivec_enabled = msr_vr;
11307 else
11308 ctx.altivec_enabled = 0;
11309 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11310 ctx.vsx_enabled = msr_vsx;
11311 } else {
11312 ctx.vsx_enabled = 0;
11313 }
11314 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11315 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11316 else
11317 ctx.singlestep_enabled = 0;
11318 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11319 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11320 if (unlikely(cs->singlestep_enabled)) {
11321 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11322 }
11323 #if defined (DO_SINGLE_STEP) && 0
11324 /* Single step trace mode */
11325 msr_se = 1;
11326 #endif
11327 num_insns = 0;
11328 max_insns = tb->cflags & CF_COUNT_MASK;
11329 if (max_insns == 0)
11330 max_insns = CF_COUNT_MASK;
11331
11332 gen_tb_start();
11333 tcg_clear_temp_count();
11334 /* Set env in case of segfault during code fetch */
11335 while (ctx.exception == POWERPC_EXCP_NONE
11336 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
11337 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11338 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11339 if (bp->pc == ctx.nip) {
11340 gen_debug_exception(ctxp);
11341 break;
11342 }
11343 }
11344 }
11345 if (unlikely(search_pc)) {
11346 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11347 if (lj < j) {
11348 lj++;
11349 while (lj < j)
11350 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11351 }
11352 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11353 tcg_ctx.gen_opc_instr_start[lj] = 1;
11354 tcg_ctx.gen_opc_icount[lj] = num_insns;
11355 }
11356 LOG_DISAS("----------------\n");
11357 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11358 ctx.nip, ctx.mem_idx, (int)msr_ir);
11359 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11360 gen_io_start();
11361 if (unlikely(need_byteswap(&ctx))) {
11362 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11363 } else {
11364 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11365 }
11366 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11367 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11368 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11369 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11370 tcg_gen_debug_insn_start(ctx.nip);
11371 }
11372 ctx.nip += 4;
11373 table = env->opcodes;
11374 num_insns++;
11375 handler = table[opc1(ctx.opcode)];
11376 if (is_indirect_opcode(handler)) {
11377 table = ind_table(handler);
11378 handler = table[opc2(ctx.opcode)];
11379 if (is_indirect_opcode(handler)) {
11380 table = ind_table(handler);
11381 handler = table[opc3(ctx.opcode)];
11382 }
11383 }
11384 /* Is opcode *REALLY* valid ? */
11385 if (unlikely(handler->handler == &gen_invalid)) {
11386 if (qemu_log_enabled()) {
11387 qemu_log("invalid/unsupported opcode: "
11388 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11389 opc1(ctx.opcode), opc2(ctx.opcode),
11390 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11391 }
11392 } else {
11393 uint32_t inval;
11394
11395 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11396 inval = handler->inval2;
11397 } else {
11398 inval = handler->inval1;
11399 }
11400
11401 if (unlikely((ctx.opcode & inval) != 0)) {
11402 if (qemu_log_enabled()) {
11403 qemu_log("invalid bits: %08x for opcode: "
11404 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11405 ctx.opcode & inval, opc1(ctx.opcode),
11406 opc2(ctx.opcode), opc3(ctx.opcode),
11407 ctx.opcode, ctx.nip - 4);
11408 }
11409 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11410 break;
11411 }
11412 }
11413 (*(handler->handler))(&ctx);
11414 #if defined(DO_PPC_STATISTICS)
11415 handler->count++;
11416 #endif
11417 /* Check trace mode exceptions */
11418 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11419 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11420 ctx.exception != POWERPC_SYSCALL &&
11421 ctx.exception != POWERPC_EXCP_TRAP &&
11422 ctx.exception != POWERPC_EXCP_BRANCH)) {
11423 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11424 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11425 (cs->singlestep_enabled) ||
11426 singlestep ||
11427 num_insns >= max_insns)) {
11428 /* if we reach a page boundary or are single stepping, stop
11429 * generation
11430 */
11431 break;
11432 }
11433 if (tcg_check_temp_count()) {
11434 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11435 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11436 ctx.opcode);
11437 exit(1);
11438 }
11439 }
11440 if (tb->cflags & CF_LAST_IO)
11441 gen_io_end();
11442 if (ctx.exception == POWERPC_EXCP_NONE) {
11443 gen_goto_tb(&ctx, 0, ctx.nip);
11444 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11445 if (unlikely(cs->singlestep_enabled)) {
11446 gen_debug_exception(ctxp);
11447 }
11448 /* Generate the return instruction */
11449 tcg_gen_exit_tb(0);
11450 }
11451 gen_tb_end(tb, num_insns);
11452 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11453 if (unlikely(search_pc)) {
11454 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11455 lj++;
11456 while (lj <= j)
11457 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11458 } else {
11459 tb->size = ctx.nip - pc_start;
11460 tb->icount = num_insns;
11461 }
11462 #if defined(DEBUG_DISAS)
11463 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11464 int flags;
11465 flags = env->bfd_mach;
11466 flags |= ctx.le_mode << 16;
11467 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11468 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11469 qemu_log("\n");
11470 }
11471 #endif
11472 }
11473
11474 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11475 {
11476 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11477 }
11478
11479 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11480 {
11481 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11482 }
11483
11484 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11485 {
11486 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11487 }
AR7 emulation for QEMU