2 * CFI parallel flash with Intel command set emulation
4 * Copyright (c) 2006 Thorsten Zitterell
5 * Copyright (c) 2005 Jocelyn Mayer
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
30 * It does not support timings
31 * It does not support flash interleaving
32 * It does not implement software data protection as found in many real chips
33 * It does not implement erase suspend/resume commands
34 * It does not implement multiple sectors erase
36 * It does not implement much more ...
39 #include "qemu/osdep.h"
41 #include "hw/block/block.h"
42 #include "hw/block/flash.h"
43 #include "sysemu/block-backend.h"
44 #include "qapi/error.h"
45 #include "qemu/timer.h"
46 #include "qemu/bitops.h"
47 #include "qemu/error-report.h"
48 #include "qemu/host-utils.h"
50 #include "qemu/module.h"
51 #include "qemu/option.h"
52 #include "hw/sysbus.h"
53 #include "sysemu/blockdev.h"
54 #include "sysemu/sysemu.h"
57 /* #define PFLASH_DEBUG */
59 #define DPRINTF(fmt, ...) \
61 fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \
64 #define DPRINTF(fmt, ...) do { } while (0)
68 #define PFLASH_SECURE 1
72 SysBusDevice parent_obj
;
79 uint8_t device_width
; /* If 0, device width not specified. */
80 uint8_t max_device_width
; /* max device width in bytes */
82 uint8_t wcycle
; /* if 0, the flash is read normally */
90 uint8_t cfi_table
[0x52];
92 unsigned int writeblock_size
;
97 VMChangeStateEntry
*vmstate
;
98 bool old_multiple_chip_handling
;
101 static int pflash_post_load(void *opaque
, int version_id
);
103 static const VMStateDescription vmstate_pflash
= {
104 .name
= "pflash_cfi01",
106 .minimum_version_id
= 1,
107 .post_load
= pflash_post_load
,
108 .fields
= (VMStateField
[]) {
109 VMSTATE_UINT8(wcycle
, PFlashCFI01
),
110 VMSTATE_UINT8(cmd
, PFlashCFI01
),
111 VMSTATE_UINT8(status
, PFlashCFI01
),
112 VMSTATE_UINT64(counter
, PFlashCFI01
),
113 VMSTATE_END_OF_LIST()
117 static void pflash_timer (void *opaque
)
119 PFlashCFI01
*pfl
= opaque
;
121 trace_pflash_timer_expired(pfl
->cmd
);
124 memory_region_rom_device_set_romd(&pfl
->mem
, true);
129 /* Perform a CFI query based on the bank width of the flash.
130 * If this code is called we know we have a device_width set for
133 static uint32_t pflash_cfi_query(PFlashCFI01
*pfl
, hwaddr offset
)
139 /* Adjust incoming offset to match expected device-width
140 * addressing. CFI query addresses are always specified in terms of
141 * the maximum supported width of the device. This means that x8
142 * devices and x8/x16 devices in x8 mode behave differently. For
143 * devices that are not used at their max width, we will be
144 * provided with addresses that use higher address bits than
145 * expected (based on the max width), so we will shift them lower
146 * so that they will match the addresses used when
147 * device_width==max_device_width.
149 boff
= offset
>> (ctz32(pfl
->bank_width
) +
150 ctz32(pfl
->max_device_width
) - ctz32(pfl
->device_width
));
152 if (boff
>= sizeof(pfl
->cfi_table
)) {
155 /* Now we will construct the CFI response generated by a single
156 * device, then replicate that for all devices that make up the
157 * bus. For wide parts used in x8 mode, CFI query responses
158 * are different than native byte-wide parts.
160 resp
= pfl
->cfi_table
[boff
];
161 if (pfl
->device_width
!= pfl
->max_device_width
) {
162 /* The only case currently supported is x8 mode for a
165 if (pfl
->device_width
!= 1 || pfl
->bank_width
> 4) {
166 DPRINTF("%s: Unsupported device configuration: "
167 "device_width=%d, max_device_width=%d\n",
168 __func__
, pfl
->device_width
,
169 pfl
->max_device_width
);
172 /* CFI query data is repeated, rather than zero padded for
173 * wide devices used in x8 mode.
175 for (i
= 1; i
< pfl
->max_device_width
; i
++) {
176 resp
= deposit32(resp
, 8 * i
, 8, pfl
->cfi_table
[boff
]);
179 /* Replicate responses for each device in bank. */
180 if (pfl
->device_width
< pfl
->bank_width
) {
181 for (i
= pfl
->device_width
;
182 i
< pfl
->bank_width
; i
+= pfl
->device_width
) {
183 resp
= deposit32(resp
, 8 * i
, 8 * pfl
->device_width
, resp
);
192 /* Perform a device id query based on the bank width of the flash. */
193 static uint32_t pflash_devid_query(PFlashCFI01
*pfl
, hwaddr offset
)
199 /* Adjust incoming offset to match expected device-width
200 * addressing. Device ID read addresses are always specified in
201 * terms of the maximum supported width of the device. This means
202 * that x8 devices and x8/x16 devices in x8 mode behave
203 * differently. For devices that are not used at their max width,
204 * we will be provided with addresses that use higher address bits
205 * than expected (based on the max width), so we will shift them
206 * lower so that they will match the addresses used when
207 * device_width==max_device_width.
209 boff
= offset
>> (ctz32(pfl
->bank_width
) +
210 ctz32(pfl
->max_device_width
) - ctz32(pfl
->device_width
));
212 /* Mask off upper bits which may be used in to query block
213 * or sector lock status at other addresses.
214 * Offsets 2/3 are block lock status, is not emulated.
216 switch (boff
& 0xFF) {
219 trace_pflash_manufacturer_id(resp
);
223 trace_pflash_device_id(resp
);
226 trace_pflash_device_info(offset
);
230 /* Replicate responses for each device in bank. */
231 if (pfl
->device_width
< pfl
->bank_width
) {
232 for (i
= pfl
->device_width
;
233 i
< pfl
->bank_width
; i
+= pfl
->device_width
) {
234 resp
= deposit32(resp
, 8 * i
, 8 * pfl
->device_width
, resp
);
241 static uint32_t pflash_data_read(PFlashCFI01
*pfl
, hwaddr offset
,
254 ret
= p
[offset
] << 8;
255 ret
|= p
[offset
+ 1];
258 ret
|= p
[offset
+ 1] << 8;
263 ret
= p
[offset
] << 24;
264 ret
|= p
[offset
+ 1] << 16;
265 ret
|= p
[offset
+ 2] << 8;
266 ret
|= p
[offset
+ 3];
269 ret
|= p
[offset
+ 1] << 8;
270 ret
|= p
[offset
+ 2] << 16;
271 ret
|= p
[offset
+ 3] << 24;
275 DPRINTF("BUG in %s\n", __func__
);
278 trace_pflash_data_read(offset
, width
<< 1, ret
);
282 static uint32_t pflash_read(PFlashCFI01
*pfl
, hwaddr offset
,
291 /* This should never happen : reset state & treat it as a read */
292 DPRINTF("%s: unknown command state: %x\n", __func__
, pfl
->cmd
);
295 /* fall through to read code */
297 /* Flash area read */
298 ret
= pflash_data_read(pfl
, offset
, width
, be
);
300 case 0x10: /* Single byte program */
301 case 0x20: /* Block erase */
302 case 0x28: /* Block erase */
303 case 0x40: /* single byte program */
304 case 0x50: /* Clear status register */
305 case 0x60: /* Block /un)lock */
306 case 0x70: /* Status Register */
307 case 0xe8: /* Write block */
308 /* Status register read. Return status from each device in
312 if (pfl
->device_width
&& width
> pfl
->device_width
) {
313 int shift
= pfl
->device_width
* 8;
314 while (shift
+ pfl
->device_width
* 8 <= width
* 8) {
315 ret
|= pfl
->status
<< shift
;
316 shift
+= pfl
->device_width
* 8;
318 } else if (!pfl
->device_width
&& width
> 2) {
319 /* Handle 32 bit flash cases where device width is not
320 * set. (Existing behavior before device width added.)
322 ret
|= pfl
->status
<< 16;
324 DPRINTF("%s: status %x\n", __func__
, ret
);
327 if (!pfl
->device_width
) {
328 /* Preserve old behavior if device width not specified */
329 boff
= offset
& 0xFF;
330 if (pfl
->bank_width
== 2) {
332 } else if (pfl
->bank_width
== 4) {
338 ret
= pfl
->ident0
<< 8 | pfl
->ident1
;
339 trace_pflash_manufacturer_id(ret
);
342 ret
= pfl
->ident2
<< 8 | pfl
->ident3
;
343 trace_pflash_device_id(ret
);
346 trace_pflash_device_info(boff
);
351 /* If we have a read larger than the bank_width, combine multiple
352 * manufacturer/device ID queries into a single response.
355 for (i
= 0; i
< width
; i
+= pfl
->bank_width
) {
356 ret
= deposit32(ret
, i
* 8, pfl
->bank_width
* 8,
357 pflash_devid_query(pfl
,
358 offset
+ i
* pfl
->bank_width
));
362 case 0x98: /* Query mode */
363 if (!pfl
->device_width
) {
364 /* Preserve old behavior if device width not specified */
365 boff
= offset
& 0xFF;
366 if (pfl
->bank_width
== 2) {
368 } else if (pfl
->bank_width
== 4) {
372 if (boff
< sizeof(pfl
->cfi_table
)) {
373 ret
= pfl
->cfi_table
[boff
];
378 /* If we have a read larger than the bank_width, combine multiple
379 * CFI queries into a single response.
382 for (i
= 0; i
< width
; i
+= pfl
->bank_width
) {
383 ret
= deposit32(ret
, i
* 8, pfl
->bank_width
* 8,
384 pflash_cfi_query(pfl
,
385 offset
+ i
* pfl
->bank_width
));
391 trace_pflash_io_read(offset
, width
, width
<< 1, ret
, pfl
->cmd
, pfl
->wcycle
);
396 /* update flash content on disk */
397 static void pflash_update(PFlashCFI01
*pfl
, int offset
,
402 offset_end
= offset
+ size
;
403 /* widen to sector boundaries */
404 offset
= QEMU_ALIGN_DOWN(offset
, BDRV_SECTOR_SIZE
);
405 offset_end
= QEMU_ALIGN_UP(offset_end
, BDRV_SECTOR_SIZE
);
406 blk_pwrite(pfl
->blk
, offset
, pfl
->storage
+ offset
,
407 offset_end
- offset
, 0);
411 static inline void pflash_data_write(PFlashCFI01
*pfl
, hwaddr offset
,
412 uint32_t value
, int width
, int be
)
414 uint8_t *p
= pfl
->storage
;
416 trace_pflash_data_write(offset
, width
<< 1, value
, pfl
->counter
);
423 p
[offset
] = value
>> 8;
424 p
[offset
+ 1] = value
;
427 p
[offset
+ 1] = value
>> 8;
432 p
[offset
] = value
>> 24;
433 p
[offset
+ 1] = value
>> 16;
434 p
[offset
+ 2] = value
>> 8;
435 p
[offset
+ 3] = value
;
438 p
[offset
+ 1] = value
>> 8;
439 p
[offset
+ 2] = value
>> 16;
440 p
[offset
+ 3] = value
>> 24;
447 static void pflash_write(PFlashCFI01
*pfl
, hwaddr offset
,
448 uint32_t value
, int width
, int be
)
455 trace_pflash_io_write(offset
, width
, width
<< 1, value
, pfl
->wcycle
);
457 /* Set the device in I/O access mode */
458 memory_region_rom_device_set_romd(&pfl
->mem
, false);
461 switch (pfl
->wcycle
) {
467 case 0x10: /* Single Byte Program */
468 case 0x40: /* Single Byte Program */
469 DPRINTF("%s: Single Byte Program\n", __func__
);
471 case 0x20: /* Block erase */
473 offset
&= ~(pfl
->sector_len
- 1);
475 DPRINTF("%s: block erase at " TARGET_FMT_plx
" bytes %x\n",
476 __func__
, offset
, (unsigned)pfl
->sector_len
);
479 memset(p
+ offset
, 0xff, pfl
->sector_len
);
480 pflash_update(pfl
, offset
, pfl
->sector_len
);
482 pfl
->status
|= 0x20; /* Block erase error */
484 pfl
->status
|= 0x80; /* Ready! */
486 case 0x50: /* Clear status bits */
487 DPRINTF("%s: Clear status bits\n", __func__
);
490 case 0x60: /* Block (un)lock */
491 DPRINTF("%s: Block unlock\n", __func__
);
493 case 0x70: /* Status Register */
494 DPRINTF("%s: Read status register\n", __func__
);
497 case 0x90: /* Read Device ID */
498 DPRINTF("%s: Read Device information\n", __func__
);
501 case 0x98: /* CFI query */
502 DPRINTF("%s: CFI query\n", __func__
);
504 case 0xe8: /* Write to buffer */
505 DPRINTF("%s: Write to buffer\n", __func__
);
506 /* FIXME should save @offset, @width for case 1+ */
507 qemu_log_mask(LOG_UNIMP
,
508 "%s: Write to buffer emulation is flawed\n",
510 pfl
->status
|= 0x80; /* Ready! */
512 case 0xf0: /* Probe for AMD flash */
513 DPRINTF("%s: Probe for AMD flash\n", __func__
);
515 case 0xff: /* Read array mode */
516 DPRINTF("%s: Read array mode\n", __func__
);
526 case 0x10: /* Single Byte Program */
527 case 0x40: /* Single Byte Program */
528 DPRINTF("%s: Single Byte Program\n", __func__
);
530 pflash_data_write(pfl
, offset
, value
, width
, be
);
531 pflash_update(pfl
, offset
, width
);
533 pfl
->status
|= 0x10; /* Programming error */
535 pfl
->status
|= 0x80; /* Ready! */
538 case 0x20: /* Block erase */
540 if (cmd
== 0xd0) { /* confirm */
543 } else if (cmd
== 0xff) { /* read array mode */
550 /* Mask writeblock size based on device width, or bank width if
551 * device width not specified.
553 /* FIXME check @offset, @width */
554 if (pfl
->device_width
) {
555 value
= extract32(value
, 0, pfl
->device_width
* 8);
557 value
= extract32(value
, 0, pfl
->bank_width
* 8);
559 DPRINTF("%s: block write of %x bytes\n", __func__
, value
);
560 pfl
->counter
= value
;
567 } else if (cmd
== 0x01) {
570 } else if (cmd
== 0xff) {
573 DPRINTF("%s: Unknown (un)locking command\n", __func__
);
581 DPRINTF("%s: leaving query mode\n", __func__
);
590 case 0xe8: /* Block write */
591 /* FIXME check @offset, @width */
594 * FIXME writing straight to memory is *wrong*. We
595 * should write to a buffer, and flush it to memory
596 * only on confirm command (see below).
598 pflash_data_write(pfl
, offset
, value
, width
, be
);
600 pfl
->status
|= 0x10; /* Programming error */
606 hwaddr mask
= pfl
->writeblock_size
- 1;
609 DPRINTF("%s: block write finished\n", __func__
);
612 /* Flush the entire write buffer onto backing storage. */
613 /* FIXME premature! */
614 pflash_update(pfl
, offset
& mask
, pfl
->writeblock_size
);
616 pfl
->status
|= 0x10; /* Programming error */
626 case 3: /* Confirm mode */
628 case 0xe8: /* Block write */
630 /* FIXME this is where we should write out the buffer */
634 qemu_log_mask(LOG_UNIMP
,
635 "%s: Aborting write to buffer not implemented,"
636 " the data is already written to storage!\n"
637 "Flash device reset into READ mode.\n",
647 /* Should never happen */
648 DPRINTF("%s: invalid write state\n", __func__
);
654 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented flash cmd sequence "
655 "(offset " TARGET_FMT_plx
", wcycle 0x%x cmd 0x%x value 0x%x)"
656 "\n", __func__
, offset
, pfl
->wcycle
, pfl
->cmd
, value
);
659 trace_pflash_reset();
660 memory_region_rom_device_set_romd(&pfl
->mem
, true);
666 static MemTxResult
pflash_mem_read_with_attrs(void *opaque
, hwaddr addr
, uint64_t *value
,
667 unsigned len
, MemTxAttrs attrs
)
669 PFlashCFI01
*pfl
= opaque
;
670 bool be
= !!(pfl
->features
& (1 << PFLASH_BE
));
672 if ((pfl
->features
& (1 << PFLASH_SECURE
)) && !attrs
.secure
) {
673 *value
= pflash_data_read(opaque
, addr
, len
, be
);
675 *value
= pflash_read(opaque
, addr
, len
, be
);
680 static MemTxResult
pflash_mem_write_with_attrs(void *opaque
, hwaddr addr
, uint64_t value
,
681 unsigned len
, MemTxAttrs attrs
)
683 PFlashCFI01
*pfl
= opaque
;
684 bool be
= !!(pfl
->features
& (1 << PFLASH_BE
));
686 if ((pfl
->features
& (1 << PFLASH_SECURE
)) && !attrs
.secure
) {
689 pflash_write(opaque
, addr
, value
, len
, be
);
694 static const MemoryRegionOps pflash_cfi01_ops
= {
695 .read_with_attrs
= pflash_mem_read_with_attrs
,
696 .write_with_attrs
= pflash_mem_write_with_attrs
,
697 .endianness
= DEVICE_NATIVE_ENDIAN
,
700 static void pflash_cfi01_realize(DeviceState
*dev
, Error
**errp
)
702 PFlashCFI01
*pfl
= PFLASH_CFI01(dev
);
705 uint64_t blocks_per_device
, sector_len_per_device
, device_len
;
707 Error
*local_err
= NULL
;
709 if (pfl
->sector_len
== 0) {
710 error_setg(errp
, "attribute \"sector-length\" not specified or zero.");
713 if (pfl
->nb_blocs
== 0) {
714 error_setg(errp
, "attribute \"num-blocks\" not specified or zero.");
717 if (pfl
->name
== NULL
) {
718 error_setg(errp
, "attribute \"name\" not specified.");
722 total_len
= pfl
->sector_len
* pfl
->nb_blocs
;
724 /* These are only used to expose the parameters of each device
725 * in the cfi_table[].
727 num_devices
= pfl
->device_width
? (pfl
->bank_width
/ pfl
->device_width
) : 1;
728 if (pfl
->old_multiple_chip_handling
) {
729 blocks_per_device
= pfl
->nb_blocs
/ num_devices
;
730 sector_len_per_device
= pfl
->sector_len
;
732 blocks_per_device
= pfl
->nb_blocs
;
733 sector_len_per_device
= pfl
->sector_len
/ num_devices
;
735 device_len
= sector_len_per_device
* blocks_per_device
;
737 memory_region_init_rom_device(
738 &pfl
->mem
, OBJECT(dev
),
741 pfl
->name
, total_len
, &local_err
);
743 error_propagate(errp
, local_err
);
747 pfl
->storage
= memory_region_get_ram_ptr(&pfl
->mem
);
748 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &pfl
->mem
);
752 pfl
->ro
= blk_is_read_only(pfl
->blk
);
753 perm
= BLK_PERM_CONSISTENT_READ
| (pfl
->ro
? 0 : BLK_PERM_WRITE
);
754 ret
= blk_set_perm(pfl
->blk
, perm
, BLK_PERM_ALL
, errp
);
763 if (!blk_check_size_and_read_all(pfl
->blk
, pfl
->storage
, total_len
,
765 vmstate_unregister_ram(&pfl
->mem
, DEVICE(pfl
));
770 /* Default to devices being used at their maximum device width. This was
771 * assumed before the device_width support was added.
773 if (!pfl
->max_device_width
) {
774 pfl
->max_device_width
= pfl
->device_width
;
777 pfl
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, pflash_timer
, pfl
);
780 pfl
->status
= 0x80; /* WSM ready */
781 /* Hardcoded CFI table */
782 /* Standard "QRY" string */
783 pfl
->cfi_table
[0x10] = 'Q';
784 pfl
->cfi_table
[0x11] = 'R';
785 pfl
->cfi_table
[0x12] = 'Y';
786 /* Command set (Intel) */
787 pfl
->cfi_table
[0x13] = 0x01;
788 pfl
->cfi_table
[0x14] = 0x00;
789 /* Primary extended table address (none) */
790 pfl
->cfi_table
[0x15] = 0x31;
791 pfl
->cfi_table
[0x16] = 0x00;
792 /* Alternate command set (none) */
793 pfl
->cfi_table
[0x17] = 0x00;
794 pfl
->cfi_table
[0x18] = 0x00;
795 /* Alternate extended table (none) */
796 pfl
->cfi_table
[0x19] = 0x00;
797 pfl
->cfi_table
[0x1A] = 0x00;
799 pfl
->cfi_table
[0x1B] = 0x45;
801 pfl
->cfi_table
[0x1C] = 0x55;
802 /* Vpp min (no Vpp pin) */
803 pfl
->cfi_table
[0x1D] = 0x00;
804 /* Vpp max (no Vpp pin) */
805 pfl
->cfi_table
[0x1E] = 0x00;
807 pfl
->cfi_table
[0x1F] = 0x07;
808 /* Timeout for min size buffer write */
809 pfl
->cfi_table
[0x20] = 0x07;
810 /* Typical timeout for block erase */
811 pfl
->cfi_table
[0x21] = 0x0a;
812 /* Typical timeout for full chip erase (4096 ms) */
813 pfl
->cfi_table
[0x22] = 0x00;
815 pfl
->cfi_table
[0x23] = 0x04;
816 /* Max timeout for buffer write */
817 pfl
->cfi_table
[0x24] = 0x04;
818 /* Max timeout for block erase */
819 pfl
->cfi_table
[0x25] = 0x04;
820 /* Max timeout for chip erase */
821 pfl
->cfi_table
[0x26] = 0x00;
823 pfl
->cfi_table
[0x27] = ctz32(device_len
); /* + 1; */
824 /* Flash device interface (8 & 16 bits) */
825 pfl
->cfi_table
[0x28] = 0x02;
826 pfl
->cfi_table
[0x29] = 0x00;
827 /* Max number of bytes in multi-bytes write */
828 if (pfl
->bank_width
== 1) {
829 pfl
->cfi_table
[0x2A] = 0x08;
831 pfl
->cfi_table
[0x2A] = 0x0B;
833 pfl
->writeblock_size
= 1 << pfl
->cfi_table
[0x2A];
834 if (!pfl
->old_multiple_chip_handling
&& num_devices
> 1) {
835 pfl
->writeblock_size
*= num_devices
;
838 pfl
->cfi_table
[0x2B] = 0x00;
839 /* Number of erase block regions (uniform) */
840 pfl
->cfi_table
[0x2C] = 0x01;
841 /* Erase block region 1 */
842 pfl
->cfi_table
[0x2D] = blocks_per_device
- 1;
843 pfl
->cfi_table
[0x2E] = (blocks_per_device
- 1) >> 8;
844 pfl
->cfi_table
[0x2F] = sector_len_per_device
>> 8;
845 pfl
->cfi_table
[0x30] = sector_len_per_device
>> 16;
848 pfl
->cfi_table
[0x31] = 'P';
849 pfl
->cfi_table
[0x32] = 'R';
850 pfl
->cfi_table
[0x33] = 'I';
852 pfl
->cfi_table
[0x34] = '1';
853 pfl
->cfi_table
[0x35] = '0';
855 pfl
->cfi_table
[0x36] = 0x00;
856 pfl
->cfi_table
[0x37] = 0x00;
857 pfl
->cfi_table
[0x38] = 0x00;
858 pfl
->cfi_table
[0x39] = 0x00;
860 pfl
->cfi_table
[0x3a] = 0x00;
862 pfl
->cfi_table
[0x3b] = 0x00;
863 pfl
->cfi_table
[0x3c] = 0x00;
865 pfl
->cfi_table
[0x3f] = 0x01; /* Number of protection fields */
868 static void pflash_cfi01_system_reset(DeviceState
*dev
)
870 PFlashCFI01
*pfl
= PFLASH_CFI01(dev
);
873 * The command 0x00 is not assigned by the CFI open standard,
874 * but QEMU historically uses it for the READ_ARRAY command (0xff).
878 memory_region_rom_device_set_romd(&pfl
->mem
, true);
880 * The WSM ready timer occurs at most 150ns after system reset.
881 * This model deliberately ignores this delay.
886 static Property pflash_cfi01_properties
[] = {
887 DEFINE_PROP_DRIVE("drive", PFlashCFI01
, blk
),
888 /* num-blocks is the number of blocks actually visible to the guest,
889 * ie the total size of the device divided by the sector length.
890 * If we're emulating flash devices wired in parallel the actual
891 * number of blocks per indvidual device will differ.
893 DEFINE_PROP_UINT32("num-blocks", PFlashCFI01
, nb_blocs
, 0),
894 DEFINE_PROP_UINT64("sector-length", PFlashCFI01
, sector_len
, 0),
895 /* width here is the overall width of this QEMU device in bytes.
896 * The QEMU device may be emulating a number of flash devices
897 * wired up in parallel; the width of each individual flash
898 * device should be specified via device-width. If the individual
899 * devices have a maximum width which is greater than the width
900 * they are being used for, this maximum width should be set via
901 * max-device-width (which otherwise defaults to device-width).
902 * So for instance a 32-bit wide QEMU flash device made from four
903 * 16-bit flash devices used in 8-bit wide mode would be configured
904 * with width = 4, device-width = 1, max-device-width = 2.
906 * If device-width is not specified we default to backwards
907 * compatible behaviour which is a bad emulation of two
908 * 16 bit devices making up a 32 bit wide QEMU device. This
909 * is deprecated for new uses of this device.
911 DEFINE_PROP_UINT8("width", PFlashCFI01
, bank_width
, 0),
912 DEFINE_PROP_UINT8("device-width", PFlashCFI01
, device_width
, 0),
913 DEFINE_PROP_UINT8("max-device-width", PFlashCFI01
, max_device_width
, 0),
914 DEFINE_PROP_BIT("big-endian", PFlashCFI01
, features
, PFLASH_BE
, 0),
915 DEFINE_PROP_BIT("secure", PFlashCFI01
, features
, PFLASH_SECURE
, 0),
916 DEFINE_PROP_UINT16("id0", PFlashCFI01
, ident0
, 0),
917 DEFINE_PROP_UINT16("id1", PFlashCFI01
, ident1
, 0),
918 DEFINE_PROP_UINT16("id2", PFlashCFI01
, ident2
, 0),
919 DEFINE_PROP_UINT16("id3", PFlashCFI01
, ident3
, 0),
920 DEFINE_PROP_STRING("name", PFlashCFI01
, name
),
921 DEFINE_PROP_BOOL("old-multiple-chip-handling", PFlashCFI01
,
922 old_multiple_chip_handling
, false),
923 DEFINE_PROP_END_OF_LIST(),
926 static void pflash_cfi01_class_init(ObjectClass
*klass
, void *data
)
928 DeviceClass
*dc
= DEVICE_CLASS(klass
);
930 dc
->reset
= pflash_cfi01_system_reset
;
931 dc
->realize
= pflash_cfi01_realize
;
932 dc
->props
= pflash_cfi01_properties
;
933 dc
->vmsd
= &vmstate_pflash
;
934 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
938 static const TypeInfo pflash_cfi01_info
= {
939 .name
= TYPE_PFLASH_CFI01
,
940 .parent
= TYPE_SYS_BUS_DEVICE
,
941 .instance_size
= sizeof(PFlashCFI01
),
942 .class_init
= pflash_cfi01_class_init
,
945 static void pflash_cfi01_register_types(void)
947 type_register_static(&pflash_cfi01_info
);
950 type_init(pflash_cfi01_register_types
)
952 PFlashCFI01
*pflash_cfi01_register(hwaddr base
,
958 uint16_t id0
, uint16_t id1
,
959 uint16_t id2
, uint16_t id3
,
962 DeviceState
*dev
= qdev_create(NULL
, TYPE_PFLASH_CFI01
);
965 qdev_prop_set_drive(dev
, "drive", blk
, &error_abort
);
967 assert(size
% sector_len
== 0);
968 qdev_prop_set_uint32(dev
, "num-blocks", size
/ sector_len
);
969 qdev_prop_set_uint64(dev
, "sector-length", sector_len
);
970 qdev_prop_set_uint8(dev
, "width", bank_width
);
971 qdev_prop_set_bit(dev
, "big-endian", !!be
);
972 qdev_prop_set_uint16(dev
, "id0", id0
);
973 qdev_prop_set_uint16(dev
, "id1", id1
);
974 qdev_prop_set_uint16(dev
, "id2", id2
);
975 qdev_prop_set_uint16(dev
, "id3", id3
);
976 qdev_prop_set_string(dev
, "name", name
);
977 qdev_init_nofail(dev
);
979 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
980 return PFLASH_CFI01(dev
);
983 BlockBackend
*pflash_cfi01_get_blk(PFlashCFI01
*fl
)
988 MemoryRegion
*pflash_cfi01_get_memory(PFlashCFI01
*fl
)
994 * Handle -drive if=pflash for machines that use properties.
995 * If @dinfo is null, do nothing.
996 * Else if @fl's property "drive" is already set, fatal error.
997 * Else set it to the BlockBackend with @dinfo.
999 void pflash_cfi01_legacy_drive(PFlashCFI01
*fl
, DriveInfo
*dinfo
)
1007 loc_push_none(&loc
);
1008 qemu_opts_loc_restore(dinfo
->opts
);
1010 error_report("clashes with -machine");
1013 qdev_prop_set_drive(DEVICE(fl
), "drive",
1014 blk_by_legacy_dinfo(dinfo
), &error_fatal
);
1018 static void postload_update_cb(void *opaque
, int running
, RunState state
)
1020 PFlashCFI01
*pfl
= opaque
;
1022 /* This is called after bdrv_invalidate_cache_all. */
1023 qemu_del_vm_change_state_handler(pfl
->vmstate
);
1024 pfl
->vmstate
= NULL
;
1026 DPRINTF("%s: updating bdrv for %s\n", __func__
, pfl
->name
);
1027 pflash_update(pfl
, 0, pfl
->sector_len
* pfl
->nb_blocs
);
1030 static int pflash_post_load(void *opaque
, int version_id
)
1032 PFlashCFI01
*pfl
= opaque
;
1035 pfl
->vmstate
= qemu_add_vm_change_state_handler(postload_update_cb
,