hw/riscv/virt.c

   1 /*
   2  * QEMU RISC-V VirtIO Board
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * RISC-V machine with 16550a UART and VirtIO MMIO
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/units.h"
  23 #include "qemu/log.h"
  24 #include "qemu/error-report.h"
  25 #include "qapi/error.h"
  26 #include "hw/boards.h"
  27 #include "hw/loader.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/qdev-properties.h"
  30 #include "hw/char/serial.h"
  31 #include "target/riscv/cpu.h"
  32 #include "hw/riscv/riscv_hart.h"
  33 #include "hw/riscv/sifive_plic.h"
  34 #include "hw/riscv/sifive_clint.h"
  35 #include "hw/riscv/sifive_test.h"
  36 #include "hw/riscv/virt.h"
  37 #include "hw/riscv/boot.h"
  38 #include "chardev/char.h"
  39 #include "sysemu/arch_init.h"
  40 #include "sysemu/device_tree.h"
  41 #include "sysemu/sysemu.h"
  42 #include "hw/pci/pci.h"
  43 #include "hw/pci-host/gpex.h"
  44
  45 #if defined(TARGET_RISCV32)
  46 # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
  47 #else
  48 # define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin"
  49 #endif
  50
  51 static const struct MemmapEntry {
  52     hwaddr base;
  53     hwaddr size;
  54 } virt_memmap[] = {
  55     [VIRT_DEBUG] =       {        0x0,         0x100 },
  56     [VIRT_MROM] =        {     0x1000,        0xf000 },
  57     [VIRT_TEST] =        {   0x100000,        0x1000 },
  58     [VIRT_RTC] =         {   0x101000,        0x1000 },
  59     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
  60     [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
  61     [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
  62     [VIRT_UART0] =       { 0x10000000,         0x100 },
  63     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
  64     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
  65     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
  66     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
  67     [VIRT_DRAM] =        { 0x80000000,           0x0 },
  68 };
  69
  70 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
  71
  72 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
  73                                        const char *name,
  74                                        const char *alias_prop_name)
  75 {
  76     /*
  77      * Create a single flash device.  We use the same parameters as
  78      * the flash devices on the ARM virt board.
  79      */
  80     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
  81
  82     qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
  83     qdev_prop_set_uint8(dev, "width", 4);
  84     qdev_prop_set_uint8(dev, "device-width", 2);
  85     qdev_prop_set_bit(dev, "big-endian", false);
  86     qdev_prop_set_uint16(dev, "id0", 0x89);
  87     qdev_prop_set_uint16(dev, "id1", 0x18);
  88     qdev_prop_set_uint16(dev, "id2", 0x00);
  89     qdev_prop_set_uint16(dev, "id3", 0x00);
  90     qdev_prop_set_string(dev, "name", name);
  91
  92     object_property_add_child(OBJECT(s), name, OBJECT(dev));
  93     object_property_add_alias(OBJECT(s), alias_prop_name,
  94                               OBJECT(dev), "drive");
  95
  96     return PFLASH_CFI01(dev);
  97 }
  98
  99 static void virt_flash_create(RISCVVirtState *s)
 100 {
 101     s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
 102     s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
 103 }
 104
 105 static void virt_flash_map1(PFlashCFI01 *flash,
 106                             hwaddr base, hwaddr size,
 107                             MemoryRegion *sysmem)
 108 {
 109     DeviceState *dev = DEVICE(flash);
 110
 111     assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
 112     assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
 113     qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
 114     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 115
 116     memory_region_add_subregion(sysmem, base,
 117                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
 118                                                        0));
 119 }
 120
 121 static void virt_flash_map(RISCVVirtState *s,
 122                            MemoryRegion *sysmem)
 123 {
 124     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
 125     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 126
 127     virt_flash_map1(s->flash[0], flashbase, flashsize,
 128                     sysmem);
 129     virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
 130                     sysmem);
 131 }
 132
 133 static void create_pcie_irq_map(void *fdt, char *nodename,
 134                                 uint32_t plic_phandle)
 135 {
 136     int pin, dev;
 137     uint32_t
 138         full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
 139     uint32_t *irq_map = full_irq_map;
 140
 141     /* This code creates a standard swizzle of interrupts such that
 142      * each device's first interrupt is based on it's PCI_SLOT number.
 143      * (See pci_swizzle_map_irq_fn())
 144      *
 145      * We only need one entry per interrupt in the table (not one per
 146      * possible slot) seeing the interrupt-map-mask will allow the table
 147      * to wrap to any number of devices.
 148      */
 149     for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
 150         int devfn = dev * 0x8;
 151
 152         for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
 153             int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
 154             int i = 0;
 155
 156             irq_map[i] = cpu_to_be32(devfn << 8);
 157
 158             i += FDT_PCI_ADDR_CELLS;
 159             irq_map[i] = cpu_to_be32(pin + 1);
 160
 161             i += FDT_PCI_INT_CELLS;
 162             irq_map[i++] = cpu_to_be32(plic_phandle);
 163
 164             i += FDT_PLIC_ADDR_CELLS;
 165             irq_map[i] = cpu_to_be32(irq_nr);
 166
 167             irq_map += FDT_INT_MAP_WIDTH;
 168         }
 169     }
 170
 171     qemu_fdt_setprop(fdt, nodename, "interrupt-map",
 172                      full_irq_map, sizeof(full_irq_map));
 173
 174     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
 175                            0x1800, 0, 0, 0x7);
 176 }
 177
 178 static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 179     uint64_t mem_size, const char *cmdline)
 180 {
 181     void *fdt;
 182     int cpu, i;
 183     uint32_t *cells;
 184     char *nodename;
 185     uint32_t plic_phandle, test_phandle, phandle = 1;
 186     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
 187     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 188
 189     fdt = s->fdt = create_device_tree(&s->fdt_size);
 190     if (!fdt) {
 191         error_report("create_device_tree() failed");
 192         exit(1);
 193     }
 194
 195     qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
 196     qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
 197     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 198     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 199
 200     qemu_fdt_add_subnode(fdt, "/soc");
 201     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 202     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
 203     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 204     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 205
 206     nodename = g_strdup_printf("/memory@%lx",
 207         (long)memmap[VIRT_DRAM].base);
 208     qemu_fdt_add_subnode(fdt, nodename);
 209     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 210         memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
 211         mem_size >> 32, mem_size);
 212     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 213     g_free(nodename);
 214
 215     qemu_fdt_add_subnode(fdt, "/cpus");
 216     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 217                           SIFIVE_CLINT_TIMEBASE_FREQ);
 218     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 219     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 220
 221     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 222         int cpu_phandle = phandle++;
 223         int intc_phandle;
 224         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 225         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 226         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 227         qemu_fdt_add_subnode(fdt, nodename);
 228 #if defined(TARGET_RISCV32)
 229         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
 230 #else
 231         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 232 #endif
 233         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 234         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 235         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 236         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 237         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 238         qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
 239         intc_phandle = phandle++;
 240         qemu_fdt_add_subnode(fdt, intc);
 241         qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
 242         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 243         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 244         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 245         g_free(isa);
 246         g_free(intc);
 247         g_free(nodename);
 248     }
 249
 250     /* Add cpu-topology node */
 251     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
 252     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
 253     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 254         char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
 255                                               cpu);
 256         char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 257         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
 258         qemu_fdt_add_subnode(fdt, core_nodename);
 259         qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
 260         g_free(core_nodename);
 261         g_free(cpu_nodename);
 262     }
 263
 264     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 265     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 266         nodename =
 267             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 268         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 269         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 270         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 271         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 272         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 273         g_free(nodename);
 274     }
 275     nodename = g_strdup_printf("/soc/clint@%lx",
 276         (long)memmap[VIRT_CLINT].base);
 277     qemu_fdt_add_subnode(fdt, nodename);
 278     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 279     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 280         0x0, memmap[VIRT_CLINT].base,
 281         0x0, memmap[VIRT_CLINT].size);
 282     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 283         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 284     g_free(cells);
 285     g_free(nodename);
 286
 287     plic_phandle = phandle++;
 288     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 289     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 290         nodename =
 291             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 292         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 293         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 294         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 295         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 296         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 297         g_free(nodename);
 298     }
 299     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 300         (long)memmap[VIRT_PLIC].base);
 301     qemu_fdt_add_subnode(fdt, nodename);
 302     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
 303                           FDT_PLIC_ADDR_CELLS);
 304     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
 305                           FDT_PLIC_INT_CELLS);
 306     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 307     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 308     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 309         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 310     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 311         0x0, memmap[VIRT_PLIC].base,
 312         0x0, memmap[VIRT_PLIC].size);
 313     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
 314     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 315     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 316     g_free(cells);
 317     g_free(nodename);
 318
 319     for (i = 0; i < VIRTIO_COUNT; i++) {
 320         nodename = g_strdup_printf("/virtio_mmio@%lx",
 321             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
 322         qemu_fdt_add_subnode(fdt, nodename);
 323         qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
 324         qemu_fdt_setprop_cells(fdt, nodename, "reg",
 325             0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 326             0x0, memmap[VIRT_VIRTIO].size);
 327         qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 328         qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
 329         g_free(nodename);
 330     }
 331
 332     nodename = g_strdup_printf("/soc/pci@%lx",
 333         (long) memmap[VIRT_PCIE_ECAM].base);
 334     qemu_fdt_add_subnode(fdt, nodename);
 335     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
 336                           FDT_PCI_ADDR_CELLS);
 337     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
 338                           FDT_PCI_INT_CELLS);
 339     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
 340     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 341                             "pci-host-ecam-generic");
 342     qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
 343     qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
 344     qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
 345                            memmap[VIRT_PCIE_ECAM].size /
 346                                PCIE_MMCFG_SIZE_MIN - 1);
 347     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
 348     qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
 349                            0, memmap[VIRT_PCIE_ECAM].size);
 350     qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
 351         1, FDT_PCI_RANGE_IOPORT, 2, 0,
 352         2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
 353         1, FDT_PCI_RANGE_MMIO,
 354         2, memmap[VIRT_PCIE_MMIO].base,
 355         2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
 356     create_pcie_irq_map(fdt, nodename, plic_phandle);
 357     g_free(nodename);
 358
 359     test_phandle = phandle++;
 360     nodename = g_strdup_printf("/test@%lx",
 361         (long)memmap[VIRT_TEST].base);
 362     qemu_fdt_add_subnode(fdt, nodename);
 363     {
 364         const char compat[] = "sifive,test1\0sifive,test0\0syscon";
 365         qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compat));
 366     }
 367     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 368         0x0, memmap[VIRT_TEST].base,
 369         0x0, memmap[VIRT_TEST].size);
 370     qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle);
 371     test_phandle = qemu_fdt_get_phandle(fdt, nodename);
 372     g_free(nodename);
 373
 374     nodename = g_strdup_printf("/reboot");
 375     qemu_fdt_add_subnode(fdt, nodename);
 376     qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
 377     qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
 378     qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
 379     qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
 380     g_free(nodename);
 381
 382     nodename = g_strdup_printf("/poweroff");
 383     qemu_fdt_add_subnode(fdt, nodename);
 384     qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
 385     qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
 386     qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
 387     qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
 388     g_free(nodename);
 389
 390     nodename = g_strdup_printf("/uart@%lx",
 391         (long)memmap[VIRT_UART0].base);
 392     qemu_fdt_add_subnode(fdt, nodename);
 393     qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
 394     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 395         0x0, memmap[VIRT_UART0].base,
 396         0x0, memmap[VIRT_UART0].size);
 397     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
 398     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 399     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
 400
 401     qemu_fdt_add_subnode(fdt, "/chosen");
 402     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 403     if (cmdline) {
 404         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 405     }
 406     g_free(nodename);
 407
 408     nodename = g_strdup_printf("/rtc@%lx",
 409         (long)memmap[VIRT_RTC].base);
 410     qemu_fdt_add_subnode(fdt, nodename);
 411     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 412         "google,goldfish-rtc");
 413     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 414         0x0, memmap[VIRT_RTC].base,
 415         0x0, memmap[VIRT_RTC].size);
 416     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 417     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ);
 418     g_free(nodename);
 419
 420     nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
 421     qemu_fdt_add_subnode(s->fdt, nodename);
 422     qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash");
 423     qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
 424                                  2, flashbase, 2, flashsize,
 425                                  2, flashbase + flashsize, 2, flashsize);
 426     qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4);
 427     g_free(nodename);
 428 }
 429
 430
 431 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
 432                                           hwaddr ecam_base, hwaddr ecam_size,
 433                                           hwaddr mmio_base, hwaddr mmio_size,
 434                                           hwaddr pio_base,
 435                                           DeviceState *plic, bool link_up)
 436 {
 437     DeviceState *dev;
 438     MemoryRegion *ecam_alias, *ecam_reg;
 439     MemoryRegion *mmio_alias, *mmio_reg;
 440     qemu_irq irq;
 441     int i;
 442
 443     dev = qdev_new(TYPE_GPEX_HOST);
 444
 445     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 446
 447     ecam_alias = g_new0(MemoryRegion, 1);
 448     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 449     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
 450                              ecam_reg, 0, ecam_size);
 451     memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
 452
 453     mmio_alias = g_new0(MemoryRegion, 1);
 454     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
 455     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
 456                              mmio_reg, mmio_base, mmio_size);
 457     memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
 458
 459     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
 460
 461     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 462         irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
 463
 464         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
 465         gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
 466     }
 467
 468     return dev;
 469 }
 470
 471 static void virt_machine_init(MachineState *machine)
 472 {
 473     const struct MemmapEntry *memmap = virt_memmap;
 474     RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
 475     MemoryRegion *system_memory = get_system_memory();
 476     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 477     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 478     char *plic_hart_config;
 479     size_t plic_hart_config_len;
 480     target_ulong start_addr = memmap[VIRT_DRAM].base;
 481     uint32_t fdt_load_addr;
 482     uint64_t kernel_entry;
 483     int i;
 484     unsigned int smp_cpus = machine->smp.cpus;
 485
 486     /* Initialize SOC */
 487     object_initialize_child(OBJECT(machine), "soc", &s->soc,
 488                             TYPE_RISCV_HART_ARRAY);
 489     object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
 490                             &error_abort);
 491     object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
 492                             &error_abort);
 493     sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
 494
 495     /* register system main memory (actual RAM) */
 496     memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
 497                            machine->ram_size, &error_fatal);
 498     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
 499         main_mem);
 500
 501     /* create device tree */
 502     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 503
 504     /* boot rom */
 505     memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
 506                            memmap[VIRT_MROM].size, &error_fatal);
 507     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
 508                                 mask_rom);
 509
 510     riscv_find_and_load_firmware(machine, BIOS_FILENAME,
 511                                  memmap[VIRT_DRAM].base, NULL);
 512
 513     if (machine->kernel_filename) {
 514         kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL);
 515
 516         if (machine->initrd_filename) {
 517             hwaddr start;
 518             hwaddr end = riscv_load_initrd(machine->initrd_filename,
 519                                            machine->ram_size, kernel_entry,
 520                                            &start);
 521             qemu_fdt_setprop_cell(s->fdt, "/chosen",
 522                                   "linux,initrd-start", start);
 523             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 524                                   end);
 525         }
 526     } else {
 527        /*
 528         * If dynamic firmware is used, it doesn't know where is the next mode
 529         * if kernel argument is not set.
 530         */
 531         kernel_entry = 0;
 532     }
 533
 534     if (drive_get(IF_PFLASH, 0, 0)) {
 535         /*
 536          * Pflash was supplied, let's overwrite the address we jump to after
 537          * reset to the base of the flash.
 538          */
 539         start_addr = virt_memmap[VIRT_FLASH].base;
 540     }
 541
 542     /* Compute the fdt load address in dram */
 543     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
 544                                    machine->ram_size, s->fdt);
 545     /* load the reset vector */
 546     riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
 547                               virt_memmap[VIRT_MROM].size, kernel_entry,
 548                               fdt_load_addr, s->fdt);
 549
 550     /* create PLIC hart topology configuration string */
 551     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
 552     plic_hart_config = g_malloc0(plic_hart_config_len);
 553     for (i = 0; i < smp_cpus; i++) {
 554         if (i != 0) {
 555             strncat(plic_hart_config, ",", plic_hart_config_len);
 556         }
 557         strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
 558         plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
 559     }
 560
 561     /* MMIO */
 562     s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
 563         plic_hart_config,
 564         VIRT_PLIC_NUM_SOURCES,
 565         VIRT_PLIC_NUM_PRIORITIES,
 566         VIRT_PLIC_PRIORITY_BASE,
 567         VIRT_PLIC_PENDING_BASE,
 568         VIRT_PLIC_ENABLE_BASE,
 569         VIRT_PLIC_ENABLE_STRIDE,
 570         VIRT_PLIC_CONTEXT_BASE,
 571         VIRT_PLIC_CONTEXT_STRIDE,
 572         memmap[VIRT_PLIC].size);
 573     sifive_clint_create(memmap[VIRT_CLINT].base,
 574         memmap[VIRT_CLINT].size, smp_cpus,
 575         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
 576     sifive_test_create(memmap[VIRT_TEST].base);
 577
 578     for (i = 0; i < VIRTIO_COUNT; i++) {
 579         sysbus_create_simple("virtio-mmio",
 580             memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 581             qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
 582     }
 583
 584     gpex_pcie_init(system_memory,
 585                          memmap[VIRT_PCIE_ECAM].base,
 586                          memmap[VIRT_PCIE_ECAM].size,
 587                          memmap[VIRT_PCIE_MMIO].base,
 588                          memmap[VIRT_PCIE_MMIO].size,
 589                          memmap[VIRT_PCIE_PIO].base,
 590                          DEVICE(s->plic), true);
 591
 592     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
 593         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
 594         serial_hd(0), DEVICE_LITTLE_ENDIAN);
 595
 596     sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
 597         qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ));
 598
 599     virt_flash_create(s);
 600
 601     for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
 602         /* Map legacy -drive if=pflash to machine properties */
 603         pflash_cfi01_legacy_drive(s->flash[i],
 604                                   drive_get(IF_PFLASH, 0, i));
 605     }
 606     virt_flash_map(s, system_memory);
 607
 608     g_free(plic_hart_config);
 609 }
 610
 611 static void virt_machine_instance_init(Object *obj)
 612 {
 613 }
 614
 615 static void virt_machine_class_init(ObjectClass *oc, void *data)
 616 {
 617     MachineClass *mc = MACHINE_CLASS(oc);
 618
 619     mc->desc = "RISC-V VirtIO board";
 620     mc->init = virt_machine_init;
 621     mc->max_cpus = 8;
 622     mc->default_cpu_type = VIRT_CPU;
 623     mc->pci_allow_0_address = true;
 624 }
 625
 626 static const TypeInfo virt_machine_typeinfo = {
 627     .name       = MACHINE_TYPE_NAME("virt"),
 628     .parent     = TYPE_MACHINE,
 629     .class_init = virt_machine_class_init,
 630     .instance_init = virt_machine_instance_init,
 631     .instance_size = sizeof(RISCVVirtState),
 632 };
 633
 634 static void virt_machine_init_register_types(void)
 635 {
 636     type_register_static(&virt_machine_typeinfo);
 637 }
 638
 639 type_init(virt_machine_init_register_types)