hw/riscv/sifive_test.c

   1 /*
   2  * QEMU SiFive Test Finisher
   3  *
   4  * Copyright (c) 2018 SiFive, Inc.
   5  *
   6  * Test finisher memory mapped device used to exit simulation
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/sysbus.h"
  23 #include "qapi/error.h"
  24 #include "qemu/log.h"
  25 #include "qemu/module.h"
  26 #include "sysemu/runstate.h"
  27 #include "hw/hw.h"
  28 #include "hw/riscv/sifive_test.h"
  29
  30 static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
  31 {
  32     return 0;
  33 }
  34
  35 static void sifive_test_write(void *opaque, hwaddr addr,
  36            uint64_t val64, unsigned int size)
  37 {
  38     if (addr == 0) {
  39         int status = val64 & 0xffff;
  40         int code = (val64 >> 16) & 0xffff;
  41         switch (status) {
  42         case FINISHER_FAIL:
  43             exit(code);
  44         case FINISHER_PASS:
  45             exit(0);
  46         case FINISHER_RESET:
  47             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
  48             return;
  49         default:
  50             break;
  51         }
  52     }
  53     qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
  54                   __func__, (int)addr, val64);
  55 }
  56
  57 static const MemoryRegionOps sifive_test_ops = {
  58     .read = sifive_test_read,
  59     .write = sifive_test_write,
  60     .endianness = DEVICE_NATIVE_ENDIAN,
  61     .valid = {
  62         .min_access_size = 4,
  63         .max_access_size = 4
  64     }
  65 };
  66
  67 static void sifive_test_init(Object *obj)
  68 {
  69     SiFiveTestState *s = SIFIVE_TEST(obj);
  70
  71     memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s,
  72                           TYPE_SIFIVE_TEST, 0x1000);
  73     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
  74 }
  75
  76 static const TypeInfo sifive_test_info = {
  77     .name          = TYPE_SIFIVE_TEST,
  78     .parent        = TYPE_SYS_BUS_DEVICE,
  79     .instance_size = sizeof(SiFiveTestState),
  80     .instance_init = sifive_test_init,
  81 };
  82
  83 static void sifive_test_register_types(void)
  84 {
  85     type_register_static(&sifive_test_info);
  86 }
  87
  88 type_init(sifive_test_register_types)
  89
  90
  91 /*
  92  * Create Test device.
  93  */
  94 DeviceState *sifive_test_create(hwaddr addr)
  95 {
  96     DeviceState *dev = qdev_new(TYPE_SIFIVE_TEST);
  97     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
  98     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
  99     return dev;
 100 }