hw/usb/hcd-xhci.h

   1 /*
   2  * USB xHCI controller emulation
   3  *
   4  * Copyright (c) 2011 Securiforest
   5  * Date: 2011-05-11 ;  Author: Hector Martin <hector@marcansoft.com>
   6  * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef HW_USB_HCD_XHCI_H
  23 #define HW_USB_HCD_XHCI_H
  24 #include "qom/object.h"
  25
  26 #define TYPE_XHCI "base-xhci"
  27 #define TYPE_NEC_XHCI "nec-usb-xhci"
  28 #define TYPE_QEMU_XHCI "qemu-xhci"
  29
  30 typedef struct XHCIState XHCIState;
  31 DECLARE_INSTANCE_CHECKER(XHCIState, XHCI,
  32                          TYPE_XHCI)
  33
  34 #define MAXPORTS_2 15
  35 #define MAXPORTS_3 15
  36
  37 #define MAXPORTS (MAXPORTS_2 + MAXPORTS_3)
  38 #define MAXSLOTS 64
  39 #define MAXINTRS 16
  40
  41 /* Very pessimistic, let's hope it's enough for all cases */
  42 #define EV_QUEUE (((3 * 24) + 16) * MAXSLOTS)
  43
  44 typedef struct XHCIStreamContext XHCIStreamContext;
  45 typedef struct XHCIEPContext XHCIEPContext;
  46
  47 enum xhci_flags {
  48     XHCI_FLAG_SS_FIRST = 1,
  49     XHCI_FLAG_FORCE_PCIE_ENDCAP,
  50     XHCI_FLAG_ENABLE_STREAMS,
  51 };
  52
  53 typedef enum TRBType {
  54     TRB_RESERVED = 0,
  55     TR_NORMAL,
  56     TR_SETUP,
  57     TR_DATA,
  58     TR_STATUS,
  59     TR_ISOCH,
  60     TR_LINK,
  61     TR_EVDATA,
  62     TR_NOOP,
  63     CR_ENABLE_SLOT,
  64     CR_DISABLE_SLOT,
  65     CR_ADDRESS_DEVICE,
  66     CR_CONFIGURE_ENDPOINT,
  67     CR_EVALUATE_CONTEXT,
  68     CR_RESET_ENDPOINT,
  69     CR_STOP_ENDPOINT,
  70     CR_SET_TR_DEQUEUE,
  71     CR_RESET_DEVICE,
  72     CR_FORCE_EVENT,
  73     CR_NEGOTIATE_BW,
  74     CR_SET_LATENCY_TOLERANCE,
  75     CR_GET_PORT_BANDWIDTH,
  76     CR_FORCE_HEADER,
  77     CR_NOOP,
  78     ER_TRANSFER = 32,
  79     ER_COMMAND_COMPLETE,
  80     ER_PORT_STATUS_CHANGE,
  81     ER_BANDWIDTH_REQUEST,
  82     ER_DOORBELL,
  83     ER_HOST_CONTROLLER,
  84     ER_DEVICE_NOTIFICATION,
  85     ER_MFINDEX_WRAP,
  86     /* vendor specific bits */
  87     CR_VENDOR_NEC_FIRMWARE_REVISION  = 49,
  88     CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
  89 } TRBType;
  90
  91 typedef enum TRBCCode {
  92     CC_INVALID = 0,
  93     CC_SUCCESS,
  94     CC_DATA_BUFFER_ERROR,
  95     CC_BABBLE_DETECTED,
  96     CC_USB_TRANSACTION_ERROR,
  97     CC_TRB_ERROR,
  98     CC_STALL_ERROR,
  99     CC_RESOURCE_ERROR,
 100     CC_BANDWIDTH_ERROR,
 101     CC_NO_SLOTS_ERROR,
 102     CC_INVALID_STREAM_TYPE_ERROR,
 103     CC_SLOT_NOT_ENABLED_ERROR,
 104     CC_EP_NOT_ENABLED_ERROR,
 105     CC_SHORT_PACKET,
 106     CC_RING_UNDERRUN,
 107     CC_RING_OVERRUN,
 108     CC_VF_ER_FULL,
 109     CC_PARAMETER_ERROR,
 110     CC_BANDWIDTH_OVERRUN,
 111     CC_CONTEXT_STATE_ERROR,
 112     CC_NO_PING_RESPONSE_ERROR,
 113     CC_EVENT_RING_FULL_ERROR,
 114     CC_INCOMPATIBLE_DEVICE_ERROR,
 115     CC_MISSED_SERVICE_ERROR,
 116     CC_COMMAND_RING_STOPPED,
 117     CC_COMMAND_ABORTED,
 118     CC_STOPPED,
 119     CC_STOPPED_LENGTH_INVALID,
 120     CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
 121     CC_ISOCH_BUFFER_OVERRUN = 31,
 122     CC_EVENT_LOST_ERROR,
 123     CC_UNDEFINED_ERROR,
 124     CC_INVALID_STREAM_ID_ERROR,
 125     CC_SECONDARY_BANDWIDTH_ERROR,
 126     CC_SPLIT_TRANSACTION_ERROR
 127 } TRBCCode;
 128
 129 typedef struct XHCIRing {
 130     dma_addr_t dequeue;
 131     bool ccs;
 132 } XHCIRing;
 133
 134 typedef struct XHCIPort {
 135     XHCIState *xhci;
 136     uint32_t portsc;
 137     uint32_t portnr;
 138     USBPort  *uport;
 139     uint32_t speedmask;
 140     char name[16];
 141     MemoryRegion mem;
 142 } XHCIPort;
 143
 144 typedef struct XHCISlot {
 145     bool enabled;
 146     bool addressed;
 147     uint16_t intr;
 148     dma_addr_t ctx;
 149     USBPort *uport;
 150     XHCIEPContext *eps[31];
 151 } XHCISlot;
 152
 153 typedef struct XHCIEvent {
 154     TRBType type;
 155     TRBCCode ccode;
 156     uint64_t ptr;
 157     uint32_t length;
 158     uint32_t flags;
 159     uint8_t slotid;
 160     uint8_t epid;
 161 } XHCIEvent;
 162
 163 typedef struct XHCIInterrupter {
 164     uint32_t iman;
 165     uint32_t imod;
 166     uint32_t erstsz;
 167     uint32_t erstba_low;
 168     uint32_t erstba_high;
 169     uint32_t erdp_low;
 170     uint32_t erdp_high;
 171
 172     bool msix_used, er_pcs;
 173
 174     dma_addr_t er_start;
 175     uint32_t er_size;
 176     unsigned int er_ep_idx;
 177
 178     /* kept for live migration compat only */
 179     bool er_full_unused;
 180     XHCIEvent ev_buffer[EV_QUEUE];
 181     unsigned int ev_buffer_put;
 182     unsigned int ev_buffer_get;
 183
 184 } XHCIInterrupter;
 185
 186 struct XHCIState {
 187     /*< private >*/
 188     PCIDevice parent_obj;
 189     /*< public >*/
 190
 191     USBBus bus;
 192     MemoryRegion mem;
 193     MemoryRegion mem_cap;
 194     MemoryRegion mem_oper;
 195     MemoryRegion mem_runtime;
 196     MemoryRegion mem_doorbell;
 197
 198     /* properties */
 199     uint32_t numports_2;
 200     uint32_t numports_3;
 201     uint32_t numintrs;
 202     uint32_t numslots;
 203     uint32_t flags;
 204     uint32_t max_pstreams_mask;
 205     OnOffAuto msi;
 206     OnOffAuto msix;
 207
 208     /* Operational Registers */
 209     uint32_t usbcmd;
 210     uint32_t usbsts;
 211     uint32_t dnctrl;
 212     uint32_t crcr_low;
 213     uint32_t crcr_high;
 214     uint32_t dcbaap_low;
 215     uint32_t dcbaap_high;
 216     uint32_t config;
 217
 218     USBPort  uports[MAX_CONST(MAXPORTS_2, MAXPORTS_3)];
 219     XHCIPort ports[MAXPORTS];
 220     XHCISlot slots[MAXSLOTS];
 221     uint32_t numports;
 222
 223     /* Runtime Registers */
 224     int64_t mfindex_start;
 225     QEMUTimer *mfwrap_timer;
 226     XHCIInterrupter intr[MAXINTRS];
 227
 228     XHCIRing cmd_ring;
 229
 230     bool nec_quirks;
 231 };
 232
 233 #endif