hw/timer/milkymist-sysctl.c

   1 /*
   2  *  QEMU model of the Milkymist System Controller.
   3  *
   4  *  Copyright (c) 2010-2012 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/sysctl.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/irq.h"
  26 #include "hw/sysbus.h"
  27 #include "migration/vmstate.h"
  28 #include "trace.h"
  29 #include "qemu/timer.h"
  30 #include "sysemu/runstate.h"
  31 #include "hw/ptimer.h"
  32 #include "hw/qdev-properties.h"
  33 #include "qemu/error-report.h"
  34 #include "qemu/module.h"
  35 #include "qom/object.h"
  36
  37 enum {
  38     CTRL_ENABLE      = (1<<0),
  39     CTRL_AUTORESTART = (1<<1),
  40 };
  41
  42 enum {
  43     ICAP_READY       = (1<<0),
  44 };
  45
  46 enum {
  47     R_GPIO_IN         = 0,
  48     R_GPIO_OUT,
  49     R_GPIO_INTEN,
  50     R_TIMER0_CONTROL  = 4,
  51     R_TIMER0_COMPARE,
  52     R_TIMER0_COUNTER,
  53     R_TIMER1_CONTROL  = 8,
  54     R_TIMER1_COMPARE,
  55     R_TIMER1_COUNTER,
  56     R_ICAP = 16,
  57     R_DBG_SCRATCHPAD  = 20,
  58     R_DBG_WRITE_LOCK,
  59     R_CLK_FREQUENCY   = 29,
  60     R_CAPABILITIES,
  61     R_SYSTEM_ID,
  62     R_MAX
  63 };
  64
  65 #define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
  66 typedef struct MilkymistSysctlState MilkymistSysctlState;
  67 DECLARE_INSTANCE_CHECKER(MilkymistSysctlState, MILKYMIST_SYSCTL,
  68                          TYPE_MILKYMIST_SYSCTL)
  69
  70 struct MilkymistSysctlState {
  71     SysBusDevice parent_obj;
  72
  73     MemoryRegion regs_region;
  74
  75     ptimer_state *ptimer0;
  76     ptimer_state *ptimer1;
  77
  78     uint32_t freq_hz;
  79     uint32_t capabilities;
  80     uint32_t systemid;
  81     uint32_t strappings;
  82
  83     uint32_t regs[R_MAX];
  84
  85     qemu_irq gpio_irq;
  86     qemu_irq timer0_irq;
  87     qemu_irq timer1_irq;
  88 };
  89
  90 static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
  91 {
  92     trace_milkymist_sysctl_icap_write(value);
  93     switch (value & 0xffff) {
  94     case 0x000e:
  95         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
  96         break;
  97     }
  98 }
  99
 100 static uint64_t sysctl_read(void *opaque, hwaddr addr,
 101                             unsigned size)
 102 {
 103     MilkymistSysctlState *s = opaque;
 104     uint32_t r = 0;
 105
 106     addr >>= 2;
 107     switch (addr) {
 108     case R_TIMER0_COUNTER:
 109         r = (uint32_t)ptimer_get_count(s->ptimer0);
 110         /* milkymist timer counts up */
 111         r = s->regs[R_TIMER0_COMPARE] - r;
 112         break;
 113     case R_TIMER1_COUNTER:
 114         r = (uint32_t)ptimer_get_count(s->ptimer1);
 115         /* milkymist timer counts up */
 116         r = s->regs[R_TIMER1_COMPARE] - r;
 117         break;
 118     case R_GPIO_IN:
 119     case R_GPIO_OUT:
 120     case R_GPIO_INTEN:
 121     case R_TIMER0_CONTROL:
 122     case R_TIMER0_COMPARE:
 123     case R_TIMER1_CONTROL:
 124     case R_TIMER1_COMPARE:
 125     case R_ICAP:
 126     case R_DBG_SCRATCHPAD:
 127     case R_DBG_WRITE_LOCK:
 128     case R_CLK_FREQUENCY:
 129     case R_CAPABILITIES:
 130     case R_SYSTEM_ID:
 131         r = s->regs[addr];
 132         break;
 133
 134     default:
 135         error_report("milkymist_sysctl: read access to unknown register 0x"
 136                 TARGET_FMT_plx, addr << 2);
 137         break;
 138     }
 139
 140     trace_milkymist_sysctl_memory_read(addr << 2, r);
 141
 142     return r;
 143 }
 144
 145 static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
 146                          unsigned size)
 147 {
 148     MilkymistSysctlState *s = opaque;
 149
 150     trace_milkymist_sysctl_memory_write(addr, value);
 151
 152     addr >>= 2;
 153     switch (addr) {
 154     case R_GPIO_OUT:
 155     case R_GPIO_INTEN:
 156     case R_TIMER0_COUNTER:
 157     case R_TIMER1_COUNTER:
 158     case R_DBG_SCRATCHPAD:
 159         s->regs[addr] = value;
 160         break;
 161     case R_TIMER0_COMPARE:
 162         ptimer_transaction_begin(s->ptimer0);
 163         ptimer_set_limit(s->ptimer0, value, 0);
 164         s->regs[addr] = value;
 165         ptimer_transaction_commit(s->ptimer0);
 166         break;
 167     case R_TIMER1_COMPARE:
 168         ptimer_transaction_begin(s->ptimer1);
 169         ptimer_set_limit(s->ptimer1, value, 0);
 170         s->regs[addr] = value;
 171         ptimer_transaction_commit(s->ptimer1);
 172         break;
 173     case R_TIMER0_CONTROL:
 174         ptimer_transaction_begin(s->ptimer0);
 175         s->regs[addr] = value;
 176         if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
 177             trace_milkymist_sysctl_start_timer0();
 178             ptimer_set_count(s->ptimer0,
 179                     s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
 180             ptimer_run(s->ptimer0, 0);
 181         } else {
 182             trace_milkymist_sysctl_stop_timer0();
 183             ptimer_stop(s->ptimer0);
 184         }
 185         ptimer_transaction_commit(s->ptimer0);
 186         break;
 187     case R_TIMER1_CONTROL:
 188         ptimer_transaction_begin(s->ptimer1);
 189         s->regs[addr] = value;
 190         if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
 191             trace_milkymist_sysctl_start_timer1();
 192             ptimer_set_count(s->ptimer1,
 193                     s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
 194             ptimer_run(s->ptimer1, 0);
 195         } else {
 196             trace_milkymist_sysctl_stop_timer1();
 197             ptimer_stop(s->ptimer1);
 198         }
 199         ptimer_transaction_commit(s->ptimer1);
 200         break;
 201     case R_ICAP:
 202         sysctl_icap_write(s, value);
 203         break;
 204     case R_DBG_WRITE_LOCK:
 205         s->regs[addr] = 1;
 206         break;
 207     case R_SYSTEM_ID:
 208         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 209         break;
 210
 211     case R_GPIO_IN:
 212     case R_CLK_FREQUENCY:
 213     case R_CAPABILITIES:
 214         error_report("milkymist_sysctl: write to read-only register 0x"
 215                 TARGET_FMT_plx, addr << 2);
 216         break;
 217
 218     default:
 219         error_report("milkymist_sysctl: write access to unknown register 0x"
 220                 TARGET_FMT_plx, addr << 2);
 221         break;
 222     }
 223 }
 224
 225 static const MemoryRegionOps sysctl_mmio_ops = {
 226     .read = sysctl_read,
 227     .write = sysctl_write,
 228     .valid = {
 229         .min_access_size = 4,
 230         .max_access_size = 4,
 231     },
 232     .endianness = DEVICE_NATIVE_ENDIAN,
 233 };
 234
 235 static void timer0_hit(void *opaque)
 236 {
 237     MilkymistSysctlState *s = opaque;
 238
 239     if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
 240         s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
 241         trace_milkymist_sysctl_stop_timer0();
 242         ptimer_stop(s->ptimer0);
 243     }
 244
 245     trace_milkymist_sysctl_pulse_irq_timer0();
 246     qemu_irq_pulse(s->timer0_irq);
 247 }
 248
 249 static void timer1_hit(void *opaque)
 250 {
 251     MilkymistSysctlState *s = opaque;
 252
 253     if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
 254         s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
 255         trace_milkymist_sysctl_stop_timer1();
 256         ptimer_stop(s->ptimer1);
 257     }
 258
 259     trace_milkymist_sysctl_pulse_irq_timer1();
 260     qemu_irq_pulse(s->timer1_irq);
 261 }
 262
 263 static void milkymist_sysctl_reset(DeviceState *d)
 264 {
 265     MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
 266     int i;
 267
 268     for (i = 0; i < R_MAX; i++) {
 269         s->regs[i] = 0;
 270     }
 271
 272     ptimer_transaction_begin(s->ptimer0);
 273     ptimer_stop(s->ptimer0);
 274     ptimer_transaction_commit(s->ptimer0);
 275     ptimer_transaction_begin(s->ptimer1);
 276     ptimer_stop(s->ptimer1);
 277     ptimer_transaction_commit(s->ptimer1);
 278
 279     /* defaults */
 280     s->regs[R_ICAP] = ICAP_READY;
 281     s->regs[R_SYSTEM_ID] = s->systemid;
 282     s->regs[R_CLK_FREQUENCY] = s->freq_hz;
 283     s->regs[R_CAPABILITIES] = s->capabilities;
 284     s->regs[R_GPIO_IN] = s->strappings;
 285 }
 286
 287 static void milkymist_sysctl_init(Object *obj)
 288 {
 289     MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj);
 290     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 291
 292     sysbus_init_irq(dev, &s->gpio_irq);
 293     sysbus_init_irq(dev, &s->timer0_irq);
 294     sysbus_init_irq(dev, &s->timer1_irq);
 295
 296     memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s,
 297             "milkymist-sysctl", R_MAX * 4);
 298     sysbus_init_mmio(dev, &s->regs_region);
 299 }
 300
 301 static void milkymist_sysctl_realize(DeviceState *dev, Error **errp)
 302 {
 303     MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);
 304
 305     s->ptimer0 = ptimer_init(timer0_hit, s, PTIMER_POLICY_DEFAULT);
 306     s->ptimer1 = ptimer_init(timer1_hit, s, PTIMER_POLICY_DEFAULT);
 307
 308     ptimer_transaction_begin(s->ptimer0);
 309     ptimer_set_freq(s->ptimer0, s->freq_hz);
 310     ptimer_transaction_commit(s->ptimer0);
 311     ptimer_transaction_begin(s->ptimer1);
 312     ptimer_set_freq(s->ptimer1, s->freq_hz);
 313     ptimer_transaction_commit(s->ptimer1);
 314 }
 315
 316 static const VMStateDescription vmstate_milkymist_sysctl = {
 317     .name = "milkymist-sysctl",
 318     .version_id = 1,
 319     .minimum_version_id = 1,
 320     .fields = (VMStateField[]) {
 321         VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
 322         VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
 323         VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
 324         VMSTATE_END_OF_LIST()
 325     }
 326 };
 327
 328 static Property milkymist_sysctl_properties[] = {
 329     DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
 330     freq_hz, 80000000),
 331     DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
 332     capabilities, 0x00000000),
 333     DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
 334     systemid, 0x10014d31),
 335     DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
 336     strappings, 0x00000001),
 337     DEFINE_PROP_END_OF_LIST(),
 338 };
 339
 340 static void milkymist_sysctl_class_init(ObjectClass *klass, void *data)
 341 {
 342     DeviceClass *dc = DEVICE_CLASS(klass);
 343
 344     dc->realize = milkymist_sysctl_realize;
 345     dc->reset = milkymist_sysctl_reset;
 346     dc->vmsd = &vmstate_milkymist_sysctl;
 347     device_class_set_props(dc, milkymist_sysctl_properties);
 348 }
 349
 350 static const TypeInfo milkymist_sysctl_info = {
 351     .name          = TYPE_MILKYMIST_SYSCTL,
 352     .parent        = TYPE_SYS_BUS_DEVICE,
 353     .instance_size = sizeof(MilkymistSysctlState),
 354     .instance_init = milkymist_sysctl_init,
 355     .class_init    = milkymist_sysctl_class_init,
 356 };
 357
 358 static void milkymist_sysctl_register_types(void)
 359 {
 360     type_register_static(&milkymist_sysctl_info);
 361 }
 362
 363 type_init(milkymist_sysctl_register_types)