hw/timer/lm32_timer.c

   1 /*
   2  *  QEMU model of the LatticeMico32 timer block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32timer.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/irq.h"
  26 #include "hw/sysbus.h"
  27 #include "migration/vmstate.h"
  28 #include "trace.h"
  29 #include "qemu/timer.h"
  30 #include "hw/ptimer.h"
  31 #include "hw/qdev-properties.h"
  32 #include "qemu/error-report.h"
  33 #include "qemu/module.h"
  34 #include "qom/object.h"
  35
  36 #define DEFAULT_FREQUENCY (50*1000000)
  37
  38 enum {
  39     R_SR = 0,
  40     R_CR,
  41     R_PERIOD,
  42     R_SNAPSHOT,
  43     R_MAX
  44 };
  45
  46 enum {
  47     SR_TO    = (1 << 0),
  48     SR_RUN   = (1 << 1),
  49 };
  50
  51 enum {
  52     CR_ITO   = (1 << 0),
  53     CR_CONT  = (1 << 1),
  54     CR_START = (1 << 2),
  55     CR_STOP  = (1 << 3),
  56 };
  57
  58 #define TYPE_LM32_TIMER "lm32-timer"
  59 typedef struct LM32TimerState LM32TimerState;
  60 DECLARE_INSTANCE_CHECKER(LM32TimerState, LM32_TIMER,
  61                          TYPE_LM32_TIMER)
  62
  63 struct LM32TimerState {
  64     SysBusDevice parent_obj;
  65
  66     MemoryRegion iomem;
  67
  68     ptimer_state *ptimer;
  69
  70     qemu_irq irq;
  71     uint32_t freq_hz;
  72
  73     uint32_t regs[R_MAX];
  74 };
  75
  76 static void timer_update_irq(LM32TimerState *s)
  77 {
  78     int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO);
  79
  80     trace_lm32_timer_irq_state(state);
  81     qemu_set_irq(s->irq, state);
  82 }
  83
  84 static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
  85 {
  86     LM32TimerState *s = opaque;
  87     uint32_t r = 0;
  88
  89     addr >>= 2;
  90     switch (addr) {
  91     case R_SR:
  92     case R_CR:
  93     case R_PERIOD:
  94         r = s->regs[addr];
  95         break;
  96     case R_SNAPSHOT:
  97         r = (uint32_t)ptimer_get_count(s->ptimer);
  98         break;
  99     default:
 100         error_report("lm32_timer: read access to unknown register 0x"
 101                 TARGET_FMT_plx, addr << 2);
 102         break;
 103     }
 104
 105     trace_lm32_timer_memory_read(addr << 2, r);
 106     return r;
 107 }
 108
 109 static void timer_write(void *opaque, hwaddr addr,
 110                         uint64_t value, unsigned size)
 111 {
 112     LM32TimerState *s = opaque;
 113
 114     trace_lm32_timer_memory_write(addr, value);
 115
 116     addr >>= 2;
 117     switch (addr) {
 118     case R_SR:
 119         s->regs[R_SR] &= ~SR_TO;
 120         break;
 121     case R_CR:
 122         ptimer_transaction_begin(s->ptimer);
 123         s->regs[R_CR] = value;
 124         if (s->regs[R_CR] & CR_START) {
 125             ptimer_run(s->ptimer, 1);
 126         }
 127         if (s->regs[R_CR] & CR_STOP) {
 128             ptimer_stop(s->ptimer);
 129         }
 130         ptimer_transaction_commit(s->ptimer);
 131         break;
 132     case R_PERIOD:
 133         s->regs[R_PERIOD] = value;
 134         ptimer_transaction_begin(s->ptimer);
 135         ptimer_set_count(s->ptimer, value);
 136         ptimer_transaction_commit(s->ptimer);
 137         break;
 138     case R_SNAPSHOT:
 139         error_report("lm32_timer: write access to read only register 0x"
 140                 TARGET_FMT_plx, addr << 2);
 141         break;
 142     default:
 143         error_report("lm32_timer: write access to unknown register 0x"
 144                 TARGET_FMT_plx, addr << 2);
 145         break;
 146     }
 147     timer_update_irq(s);
 148 }
 149
 150 static const MemoryRegionOps timer_ops = {
 151     .read = timer_read,
 152     .write = timer_write,
 153     .endianness = DEVICE_NATIVE_ENDIAN,
 154     .valid = {
 155         .min_access_size = 4,
 156         .max_access_size = 4,
 157     },
 158 };
 159
 160 static void timer_hit(void *opaque)
 161 {
 162     LM32TimerState *s = opaque;
 163
 164     trace_lm32_timer_hit();
 165
 166     s->regs[R_SR] |= SR_TO;
 167
 168     if (s->regs[R_CR] & CR_CONT) {
 169         ptimer_set_count(s->ptimer, s->regs[R_PERIOD]);
 170         ptimer_run(s->ptimer, 1);
 171     }
 172     timer_update_irq(s);
 173 }
 174
 175 static void timer_reset(DeviceState *d)
 176 {
 177     LM32TimerState *s = LM32_TIMER(d);
 178     int i;
 179
 180     for (i = 0; i < R_MAX; i++) {
 181         s->regs[i] = 0;
 182     }
 183     ptimer_transaction_begin(s->ptimer);
 184     ptimer_stop(s->ptimer);
 185     ptimer_transaction_commit(s->ptimer);
 186 }
 187
 188 static void lm32_timer_init(Object *obj)
 189 {
 190     LM32TimerState *s = LM32_TIMER(obj);
 191     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 192
 193     sysbus_init_irq(dev, &s->irq);
 194
 195     memory_region_init_io(&s->iomem, obj, &timer_ops, s,
 196                           "timer", R_MAX * 4);
 197     sysbus_init_mmio(dev, &s->iomem);
 198 }
 199
 200 static void lm32_timer_realize(DeviceState *dev, Error **errp)
 201 {
 202     LM32TimerState *s = LM32_TIMER(dev);
 203
 204     s->ptimer = ptimer_init(timer_hit, s, PTIMER_POLICY_DEFAULT);
 205
 206     ptimer_transaction_begin(s->ptimer);
 207     ptimer_set_freq(s->ptimer, s->freq_hz);
 208     ptimer_transaction_commit(s->ptimer);
 209 }
 210
 211 static const VMStateDescription vmstate_lm32_timer = {
 212     .name = "lm32-timer",
 213     .version_id = 1,
 214     .minimum_version_id = 1,
 215     .fields = (VMStateField[]) {
 216         VMSTATE_PTIMER(ptimer, LM32TimerState),
 217         VMSTATE_UINT32(freq_hz, LM32TimerState),
 218         VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX),
 219         VMSTATE_END_OF_LIST()
 220     }
 221 };
 222
 223 static Property lm32_timer_properties[] = {
 224     DEFINE_PROP_UINT32("frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY),
 225     DEFINE_PROP_END_OF_LIST(),
 226 };
 227
 228 static void lm32_timer_class_init(ObjectClass *klass, void *data)
 229 {
 230     DeviceClass *dc = DEVICE_CLASS(klass);
 231
 232     dc->realize = lm32_timer_realize;
 233     dc->reset = timer_reset;
 234     dc->vmsd = &vmstate_lm32_timer;
 235     device_class_set_props(dc, lm32_timer_properties);
 236 }
 237
 238 static const TypeInfo lm32_timer_info = {
 239     .name          = TYPE_LM32_TIMER,
 240     .parent        = TYPE_SYS_BUS_DEVICE,
 241     .instance_size = sizeof(LM32TimerState),
 242     .instance_init = lm32_timer_init,
 243     .class_init    = lm32_timer_class_init,
 244 };
 245
 246 static void lm32_timer_register_types(void)
 247 {
 248     type_register_static(&lm32_timer_info);
 249 }
 250
 251 type_init(lm32_timer_register_types)