hw/timer/arm_timer.c

   1 /*
   2  * ARM PrimeCell Timer modules.
   3  *
   4  * Copyright (c) 2005-2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/sysbus.h"
  12 #include "migration/vmstate.h"
  13 #include "qemu/timer.h"
  14 #include "hw/irq.h"
  15 #include "hw/ptimer.h"
  16 #include "hw/qdev-properties.h"
  17 #include "qemu/module.h"
  18 #include "qemu/log.h"
  19 #include "qom/object.h"
  20
  21 /* Common timer implementation.  */
  22
  23 #define TIMER_CTRL_ONESHOT      (1 << 0)
  24 #define TIMER_CTRL_32BIT        (1 << 1)
  25 #define TIMER_CTRL_DIV1         (0 << 2)
  26 #define TIMER_CTRL_DIV16        (1 << 2)
  27 #define TIMER_CTRL_DIV256       (2 << 2)
  28 #define TIMER_CTRL_IE           (1 << 5)
  29 #define TIMER_CTRL_PERIODIC     (1 << 6)
  30 #define TIMER_CTRL_ENABLE       (1 << 7)
  31
  32 typedef struct {
  33     ptimer_state *timer;
  34     uint32_t control;
  35     uint32_t limit;
  36     int freq;
  37     int int_level;
  38     qemu_irq irq;
  39 } arm_timer_state;
  40
  41 /* Check all active timers, and schedule the next timer interrupt.  */
  42
  43 static void arm_timer_update(arm_timer_state *s)
  44 {
  45     /* Update interrupts.  */
  46     if (s->int_level && (s->control & TIMER_CTRL_IE)) {
  47         qemu_irq_raise(s->irq);
  48     } else {
  49         qemu_irq_lower(s->irq);
  50     }
  51 }
  52
  53 static uint32_t arm_timer_read(void *opaque, hwaddr offset)
  54 {
  55     arm_timer_state *s = (arm_timer_state *)opaque;
  56
  57     switch (offset >> 2) {
  58     case 0: /* TimerLoad */
  59     case 6: /* TimerBGLoad */
  60         return s->limit;
  61     case 1: /* TimerValue */
  62         return ptimer_get_count(s->timer);
  63     case 2: /* TimerControl */
  64         return s->control;
  65     case 4: /* TimerRIS */
  66         return s->int_level;
  67     case 5: /* TimerMIS */
  68         if ((s->control & TIMER_CTRL_IE) == 0)
  69             return 0;
  70         return s->int_level;
  71     default:
  72         qemu_log_mask(LOG_GUEST_ERROR,
  73                       "%s: Bad offset %x\n", __func__, (int)offset);
  74         return 0;
  75     }
  76 }
  77
  78 /*
  79  * Reset the timer limit after settings have changed.
  80  * May only be called from inside a ptimer transaction block.
  81  */
  82 static void arm_timer_recalibrate(arm_timer_state *s, int reload)
  83 {
  84     uint32_t limit;
  85
  86     if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
  87         /* Free running.  */
  88         if (s->control & TIMER_CTRL_32BIT)
  89             limit = 0xffffffff;
  90         else
  91             limit = 0xffff;
  92     } else {
  93           /* Periodic.  */
  94           limit = s->limit;
  95     }
  96     ptimer_set_limit(s->timer, limit, reload);
  97 }
  98
  99 static void arm_timer_write(void *opaque, hwaddr offset,
 100                             uint32_t value)
 101 {
 102     arm_timer_state *s = (arm_timer_state *)opaque;
 103     int freq;
 104
 105     switch (offset >> 2) {
 106     case 0: /* TimerLoad */
 107         s->limit = value;
 108         ptimer_transaction_begin(s->timer);
 109         arm_timer_recalibrate(s, 1);
 110         ptimer_transaction_commit(s->timer);
 111         break;
 112     case 1: /* TimerValue */
 113         /* ??? Linux seems to want to write to this readonly register.
 114            Ignore it.  */
 115         break;
 116     case 2: /* TimerControl */
 117         ptimer_transaction_begin(s->timer);
 118         if (s->control & TIMER_CTRL_ENABLE) {
 119             /* Pause the timer if it is running.  This may cause some
 120                inaccuracy dure to rounding, but avoids a whole lot of other
 121                messyness.  */
 122             ptimer_stop(s->timer);
 123         }
 124         s->control = value;
 125         freq = s->freq;
 126         /* ??? Need to recalculate expiry time after changing divisor.  */
 127         switch ((value >> 2) & 3) {
 128         case 1: freq >>= 4; break;
 129         case 2: freq >>= 8; break;
 130         }
 131         arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
 132         ptimer_set_freq(s->timer, freq);
 133         if (s->control & TIMER_CTRL_ENABLE) {
 134             /* Restart the timer if still enabled.  */
 135             ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
 136         }
 137         ptimer_transaction_commit(s->timer);
 138         break;
 139     case 3: /* TimerIntClr */
 140         s->int_level = 0;
 141         break;
 142     case 6: /* TimerBGLoad */
 143         s->limit = value;
 144         ptimer_transaction_begin(s->timer);
 145         arm_timer_recalibrate(s, 0);
 146         ptimer_transaction_commit(s->timer);
 147         break;
 148     default:
 149         qemu_log_mask(LOG_GUEST_ERROR,
 150                       "%s: Bad offset %x\n", __func__, (int)offset);
 151     }
 152     arm_timer_update(s);
 153 }
 154
 155 static void arm_timer_tick(void *opaque)
 156 {
 157     arm_timer_state *s = (arm_timer_state *)opaque;
 158     s->int_level = 1;
 159     arm_timer_update(s);
 160 }
 161
 162 static const VMStateDescription vmstate_arm_timer = {
 163     .name = "arm_timer",
 164     .version_id = 1,
 165     .minimum_version_id = 1,
 166     .fields = (VMStateField[]) {
 167         VMSTATE_UINT32(control, arm_timer_state),
 168         VMSTATE_UINT32(limit, arm_timer_state),
 169         VMSTATE_INT32(int_level, arm_timer_state),
 170         VMSTATE_PTIMER(timer, arm_timer_state),
 171         VMSTATE_END_OF_LIST()
 172     }
 173 };
 174
 175 static arm_timer_state *arm_timer_init(uint32_t freq)
 176 {
 177     arm_timer_state *s;
 178
 179     s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
 180     s->freq = freq;
 181     s->control = TIMER_CTRL_IE;
 182
 183     s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_DEFAULT);
 184     vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s);
 185     return s;
 186 }
 187
 188 /* ARM PrimeCell SP804 dual timer module.
 189  * Docs at
 190  * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
 191 */
 192
 193 #define TYPE_SP804 "sp804"
 194 typedef struct SP804State SP804State;
 195 DECLARE_INSTANCE_CHECKER(SP804State, SP804,
 196                          TYPE_SP804)
 197
 198 struct SP804State {
 199     SysBusDevice parent_obj;
 200
 201     MemoryRegion iomem;
 202     arm_timer_state *timer[2];
 203     uint32_t freq0, freq1;
 204     int level[2];
 205     qemu_irq irq;
 206 };
 207
 208 static const uint8_t sp804_ids[] = {
 209     /* Timer ID */
 210     0x04, 0x18, 0x14, 0,
 211     /* PrimeCell ID */
 212     0xd, 0xf0, 0x05, 0xb1
 213 };
 214
 215 /* Merge the IRQs from the two component devices.  */
 216 static void sp804_set_irq(void *opaque, int irq, int level)
 217 {
 218     SP804State *s = (SP804State *)opaque;
 219
 220     s->level[irq] = level;
 221     qemu_set_irq(s->irq, s->level[0] || s->level[1]);
 222 }
 223
 224 static uint64_t sp804_read(void *opaque, hwaddr offset,
 225                            unsigned size)
 226 {
 227     SP804State *s = (SP804State *)opaque;
 228
 229     if (offset < 0x20) {
 230         return arm_timer_read(s->timer[0], offset);
 231     }
 232     if (offset < 0x40) {
 233         return arm_timer_read(s->timer[1], offset - 0x20);
 234     }
 235
 236     /* TimerPeriphID */
 237     if (offset >= 0xfe0 && offset <= 0xffc) {
 238         return sp804_ids[(offset - 0xfe0) >> 2];
 239     }
 240
 241     switch (offset) {
 242     /* Integration Test control registers, which we won't support */
 243     case 0xf00: /* TimerITCR */
 244     case 0xf04: /* TimerITOP (strictly write only but..) */
 245         qemu_log_mask(LOG_UNIMP,
 246                       "%s: integration test registers unimplemented\n",
 247                       __func__);
 248         return 0;
 249     }
 250
 251     qemu_log_mask(LOG_GUEST_ERROR,
 252                   "%s: Bad offset %x\n", __func__, (int)offset);
 253     return 0;
 254 }
 255
 256 static void sp804_write(void *opaque, hwaddr offset,
 257                         uint64_t value, unsigned size)
 258 {
 259     SP804State *s = (SP804State *)opaque;
 260
 261     if (offset < 0x20) {
 262         arm_timer_write(s->timer[0], offset, value);
 263         return;
 264     }
 265
 266     if (offset < 0x40) {
 267         arm_timer_write(s->timer[1], offset - 0x20, value);
 268         return;
 269     }
 270
 271     /* Technically we could be writing to the Test Registers, but not likely */
 272     qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n",
 273                   __func__, (int)offset);
 274 }
 275
 276 static const MemoryRegionOps sp804_ops = {
 277     .read = sp804_read,
 278     .write = sp804_write,
 279     .endianness = DEVICE_NATIVE_ENDIAN,
 280 };
 281
 282 static const VMStateDescription vmstate_sp804 = {
 283     .name = "sp804",
 284     .version_id = 1,
 285     .minimum_version_id = 1,
 286     .fields = (VMStateField[]) {
 287         VMSTATE_INT32_ARRAY(level, SP804State, 2),
 288         VMSTATE_END_OF_LIST()
 289     }
 290 };
 291
 292 static void sp804_init(Object *obj)
 293 {
 294     SP804State *s = SP804(obj);
 295     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 296
 297     sysbus_init_irq(sbd, &s->irq);
 298     memory_region_init_io(&s->iomem, obj, &sp804_ops, s,
 299                           "sp804", 0x1000);
 300     sysbus_init_mmio(sbd, &s->iomem);
 301 }
 302
 303 static void sp804_realize(DeviceState *dev, Error **errp)
 304 {
 305     SP804State *s = SP804(dev);
 306
 307     s->timer[0] = arm_timer_init(s->freq0);
 308     s->timer[1] = arm_timer_init(s->freq1);
 309     s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0);
 310     s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1);
 311 }
 312
 313 /* Integrator/CP timer module.  */
 314
 315 #define TYPE_INTEGRATOR_PIT "integrator_pit"
 316 typedef struct icp_pit_state icp_pit_state;
 317 DECLARE_INSTANCE_CHECKER(icp_pit_state, INTEGRATOR_PIT,
 318                          TYPE_INTEGRATOR_PIT)
 319
 320 struct icp_pit_state {
 321     SysBusDevice parent_obj;
 322
 323     MemoryRegion iomem;
 324     arm_timer_state *timer[3];
 325 };
 326
 327 static uint64_t icp_pit_read(void *opaque, hwaddr offset,
 328                              unsigned size)
 329 {
 330     icp_pit_state *s = (icp_pit_state *)opaque;
 331     int n;
 332
 333     /* ??? Don't know the PrimeCell ID for this device.  */
 334     n = offset >> 8;
 335     if (n > 2) {
 336         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
 337         return 0;
 338     }
 339
 340     return arm_timer_read(s->timer[n], offset & 0xff);
 341 }
 342
 343 static void icp_pit_write(void *opaque, hwaddr offset,
 344                           uint64_t value, unsigned size)
 345 {
 346     icp_pit_state *s = (icp_pit_state *)opaque;
 347     int n;
 348
 349     n = offset >> 8;
 350     if (n > 2) {
 351         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
 352         return;
 353     }
 354
 355     arm_timer_write(s->timer[n], offset & 0xff, value);
 356 }
 357
 358 static const MemoryRegionOps icp_pit_ops = {
 359     .read = icp_pit_read,
 360     .write = icp_pit_write,
 361     .endianness = DEVICE_NATIVE_ENDIAN,
 362 };
 363
 364 static void icp_pit_init(Object *obj)
 365 {
 366     icp_pit_state *s = INTEGRATOR_PIT(obj);
 367     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 368
 369     /* Timer 0 runs at the system clock speed (40MHz).  */
 370     s->timer[0] = arm_timer_init(40000000);
 371     /* The other two timers run at 1MHz.  */
 372     s->timer[1] = arm_timer_init(1000000);
 373     s->timer[2] = arm_timer_init(1000000);
 374
 375     sysbus_init_irq(dev, &s->timer[0]->irq);
 376     sysbus_init_irq(dev, &s->timer[1]->irq);
 377     sysbus_init_irq(dev, &s->timer[2]->irq);
 378
 379     memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s,
 380                           "icp_pit", 0x1000);
 381     sysbus_init_mmio(dev, &s->iomem);
 382     /* This device has no state to save/restore.  The component timers will
 383        save themselves.  */
 384 }
 385
 386 static const TypeInfo icp_pit_info = {
 387     .name          = TYPE_INTEGRATOR_PIT,
 388     .parent        = TYPE_SYS_BUS_DEVICE,
 389     .instance_size = sizeof(icp_pit_state),
 390     .instance_init = icp_pit_init,
 391 };
 392
 393 static Property sp804_properties[] = {
 394     DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000),
 395     DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000),
 396     DEFINE_PROP_END_OF_LIST(),
 397 };
 398
 399 static void sp804_class_init(ObjectClass *klass, void *data)
 400 {
 401     DeviceClass *k = DEVICE_CLASS(klass);
 402
 403     k->realize = sp804_realize;
 404     device_class_set_props(k, sp804_properties);
 405     k->vmsd = &vmstate_sp804;
 406 }
 407
 408 static const TypeInfo sp804_info = {
 409     .name          = TYPE_SP804,
 410     .parent        = TYPE_SYS_BUS_DEVICE,
 411     .instance_size = sizeof(SP804State),
 412     .instance_init = sp804_init,
 413     .class_init    = sp804_class_init,
 414 };
 415
 416 static void arm_timer_register_types(void)
 417 {
 418     type_register_static(&icp_pit_info);
 419     type_register_static(&sp804_info);
 420 }
 421
 422 type_init(arm_timer_register_types)