hw/pci-host/i440fx.c

   1 /*
   2  * QEMU i440FX PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qemu/range.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/pci/pci_host.h"
  31 #include "hw/pci-host/i440fx.h"
  32 #include "hw/qdev-properties.h"
  33 #include "hw/sysbus.h"
  34 #include "qapi/error.h"
  35 #include "migration/vmstate.h"
  36 #include "qapi/visitor.h"
  37 #include "qemu/error-report.h"
  38 #include "qom/object.h"
  39
  40 /*
  41  * I440FX chipset data sheet.
  42  * https://wiki.qemu.org/File:29054901.pdf
  43  */
  44
  45 typedef struct I440FXState I440FXState;
  46 DECLARE_INSTANCE_CHECKER(I440FXState, I440FX_PCI_HOST_BRIDGE,
  47                          TYPE_I440FX_PCI_HOST_BRIDGE)
  48
  49 struct I440FXState {
  50     PCIHostState parent_obj;
  51     Range pci_hole;
  52     uint64_t pci_hole64_size;
  53     bool pci_hole64_fix;
  54     uint32_t short_root_bus;
  55 };
  56
  57 #define I440FX_PAM      0x59
  58 #define I440FX_PAM_SIZE 7
  59 #define I440FX_SMRAM    0x72
  60
  61 /* Keep it 2G to comply with older win32 guests */
  62 #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
  63
  64 /* Older coreboot versions (4.0 and older) read a config register that doesn't
  65  * exist in real hardware, to get the RAM size from QEMU.
  66  */
  67 #define I440FX_COREBOOT_RAM_SIZE 0x57
  68
  69 static void i440fx_update_memory_mappings(PCII440FXState *d)
  70 {
  71     int i;
  72     PCIDevice *pd = PCI_DEVICE(d);
  73
  74     memory_region_transaction_begin();
  75     for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
  76         pam_update(&d->pam_regions[i], i,
  77                    pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
  78     }
  79     memory_region_set_enabled(&d->smram_region,
  80                               !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
  81     memory_region_set_enabled(&d->smram,
  82                               pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
  83     memory_region_transaction_commit();
  84 }
  85
  86
  87 static void i440fx_write_config(PCIDevice *dev,
  88                                 uint32_t address, uint32_t val, int len)
  89 {
  90     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
  91
  92     /* XXX: implement SMRAM.D_LOCK */
  93     pci_default_write_config(dev, address, val, len);
  94     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
  95         range_covers_byte(address, len, I440FX_SMRAM)) {
  96         i440fx_update_memory_mappings(d);
  97     }
  98 }
  99
 100 static int i440fx_post_load(void *opaque, int version_id)
 101 {
 102     PCII440FXState *d = opaque;
 103
 104     i440fx_update_memory_mappings(d);
 105     return 0;
 106 }
 107
 108 static const VMStateDescription vmstate_i440fx = {
 109     .name = "I440FX",
 110     .version_id = 3,
 111     .minimum_version_id = 3,
 112     .post_load = i440fx_post_load,
 113     .fields = (VMStateField[]) {
 114         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
 115         /* Used to be smm_enabled, which was basically always zero because
 116          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
 117          */
 118         VMSTATE_UNUSED(1),
 119         VMSTATE_END_OF_LIST()
 120     }
 121 };
 122
 123 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
 124                                               const char *name, void *opaque,
 125                                               Error **errp)
 126 {
 127     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 128     uint64_t val64;
 129     uint32_t value;
 130
 131     val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
 132     value = val64;
 133     assert(value == val64);
 134     visit_type_uint32(v, name, &value, errp);
 135 }
 136
 137 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
 138                                             const char *name, void *opaque,
 139                                             Error **errp)
 140 {
 141     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 142     uint64_t val64;
 143     uint32_t value;
 144
 145     val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
 146     value = val64;
 147     assert(value == val64);
 148     visit_type_uint32(v, name, &value, errp);
 149 }
 150
 151 /*
 152  * The 64bit PCI hole start is set by the Guest firmware
 153  * as the address of the first 64bit PCI MEM resource.
 154  * If no PCI device has resources on the 64bit area,
 155  * the 64bit PCI hole will start after "over 4G RAM" and the
 156  * reserved space for memory hotplug if any.
 157  */
 158 static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
 159 {
 160     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 161     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 162     Range w64;
 163     uint64_t value;
 164
 165     pci_bus_get_w64_range(h->bus, &w64);
 166     value = range_is_empty(&w64) ? 0 : range_lob(&w64);
 167     if (!value && s->pci_hole64_fix) {
 168         value = pc_pci_hole64_start();
 169     }
 170     return value;
 171 }
 172
 173 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
 174                                                 const char *name,
 175                                                 void *opaque, Error **errp)
 176 {
 177     uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
 178
 179     visit_type_uint64(v, name, &hole64_start, errp);
 180 }
 181
 182 /*
 183  * The 64bit PCI hole end is set by the Guest firmware
 184  * as the address of the last 64bit PCI MEM resource.
 185  * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
 186  * that can be configured by the user.
 187  */
 188 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
 189                                               const char *name, void *opaque,
 190                                               Error **errp)
 191 {
 192     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 193     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 194     uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
 195     Range w64;
 196     uint64_t value, hole64_end;
 197
 198     pci_bus_get_w64_range(h->bus, &w64);
 199     value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
 200     hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
 201     if (s->pci_hole64_fix && value < hole64_end) {
 202         value = hole64_end;
 203     }
 204     visit_type_uint64(v, name, &value, errp);
 205 }
 206
 207 static void i440fx_pcihost_initfn(Object *obj)
 208 {
 209     PCIHostState *s = PCI_HOST_BRIDGE(obj);
 210
 211     memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
 212                           "pci-conf-idx", 4);
 213     memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
 214                           "pci-conf-data", 4);
 215
 216     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
 217                         i440fx_pcihost_get_pci_hole_start,
 218                         NULL, NULL, NULL);
 219
 220     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
 221                         i440fx_pcihost_get_pci_hole_end,
 222                         NULL, NULL, NULL);
 223
 224     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
 225                         i440fx_pcihost_get_pci_hole64_start,
 226                         NULL, NULL, NULL);
 227
 228     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
 229                         i440fx_pcihost_get_pci_hole64_end,
 230                         NULL, NULL, NULL);
 231 }
 232
 233 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
 234 {
 235     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 236     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 237
 238     sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
 239     sysbus_init_ioports(sbd, 0xcf8, 4);
 240
 241     sysbus_add_io(sbd, 0xcfc, &s->data_mem);
 242     sysbus_init_ioports(sbd, 0xcfc, 4);
 243
 244     /* register i440fx 0xcf8 port as coalesced pio */
 245     memory_region_set_flush_coalesced(&s->data_mem);
 246     memory_region_add_coalescing(&s->conf_mem, 0, 4);
 247 }
 248
 249 static void i440fx_realize(PCIDevice *dev, Error **errp)
 250 {
 251     dev->config[I440FX_SMRAM] = 0x02;
 252
 253     if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
 254         warn_report("i440fx doesn't support emulated iommu");
 255     }
 256 }
 257
 258 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 259                     PCII440FXState **pi440fx_state,
 260                     MemoryRegion *address_space_mem,
 261                     MemoryRegion *address_space_io,
 262                     ram_addr_t ram_size,
 263                     ram_addr_t below_4g_mem_size,
 264                     ram_addr_t above_4g_mem_size,
 265                     MemoryRegion *pci_address_space,
 266                     MemoryRegion *ram_memory)
 267 {
 268     DeviceState *dev;
 269     PCIBus *b;
 270     PCIDevice *d;
 271     PCIHostState *s;
 272     PCII440FXState *f;
 273     unsigned i;
 274     I440FXState *i440fx;
 275
 276     dev = qdev_new(host_type);
 277     s = PCI_HOST_BRIDGE(dev);
 278     b = pci_root_bus_new(dev, NULL, pci_address_space,
 279                          address_space_io, 0, TYPE_PCI_BUS);
 280     s->bus = b;
 281     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev));
 282     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 283
 284     d = pci_create_simple(b, 0, pci_type);
 285     *pi440fx_state = I440FX_PCI_DEVICE(d);
 286     f = *pi440fx_state;
 287     f->system_memory = address_space_mem;
 288     f->pci_address_space = pci_address_space;
 289     f->ram_memory = ram_memory;
 290
 291     i440fx = I440FX_PCI_HOST_BRIDGE(dev);
 292     range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
 293                      IO_APIC_DEFAULT_ADDRESS - 1);
 294
 295     /* setup pci memory mapping */
 296     pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
 297                            f->pci_address_space);
 298
 299     /* if *disabled* show SMRAM to all CPUs */
 300     memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 301                              f->pci_address_space, 0xa0000, 0x20000);
 302     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 303                                         &f->smram_region, 1);
 304     memory_region_set_enabled(&f->smram_region, true);
 305
 306     /* smram, as seen by SMM CPUs */
 307     memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB);
 308     memory_region_set_enabled(&f->smram, true);
 309     memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
 310                              f->ram_memory, 0xa0000, 0x20000);
 311     memory_region_set_enabled(&f->low_smram, true);
 312     memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
 313     object_property_add_const_link(qdev_get_machine(), "smram",
 314                                    OBJECT(&f->smram));
 315
 316     init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 317              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 318     for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
 319         init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 320                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 321                  PAM_EXPAN_SIZE);
 322     }
 323
 324     ram_size = ram_size / 8 / 1024 / 1024;
 325     if (ram_size > 255) {
 326         ram_size = 255;
 327     }
 328     d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
 329
 330     i440fx_update_memory_mappings(f);
 331
 332     return b;
 333 }
 334
 335 PCIBus *find_i440fx(void)
 336 {
 337     PCIHostState *s = OBJECT_CHECK(PCIHostState,
 338                                    object_resolve_path("/machine/i440fx", NULL),
 339                                    TYPE_PCI_HOST_BRIDGE);
 340     return s ? s->bus : NULL;
 341 }
 342
 343 static void i440fx_class_init(ObjectClass *klass, void *data)
 344 {
 345     DeviceClass *dc = DEVICE_CLASS(klass);
 346     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 347
 348     k->realize = i440fx_realize;
 349     k->config_write = i440fx_write_config;
 350     k->vendor_id = PCI_VENDOR_ID_INTEL;
 351     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 352     k->revision = 0x02;
 353     k->class_id = PCI_CLASS_BRIDGE_HOST;
 354     dc->desc = "Host bridge";
 355     dc->vmsd = &vmstate_i440fx;
 356     /*
 357      * PCI-facing part of the host bridge, not usable without the
 358      * host-facing part, which can't be device_add'ed, yet.
 359      */
 360     dc->user_creatable = false;
 361     dc->hotpluggable   = false;
 362 }
 363
 364 static const TypeInfo i440fx_info = {
 365     .name          = TYPE_I440FX_PCI_DEVICE,
 366     .parent        = TYPE_PCI_DEVICE,
 367     .instance_size = sizeof(PCII440FXState),
 368     .class_init    = i440fx_class_init,
 369     .interfaces = (InterfaceInfo[]) {
 370         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 371         { },
 372     },
 373 };
 374
 375 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 376                                                 PCIBus *rootbus)
 377 {
 378     I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
 379
 380     /* For backwards compat with old device paths */
 381     if (s->short_root_bus) {
 382         return "0000";
 383     }
 384     return "0000:00";
 385 }
 386
 387 static Property i440fx_props[] = {
 388     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
 389                      pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
 390     DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
 391     DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
 392     DEFINE_PROP_END_OF_LIST(),
 393 };
 394
 395 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 396 {
 397     DeviceClass *dc = DEVICE_CLASS(klass);
 398     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 399
 400     hc->root_bus_path = i440fx_pcihost_root_bus_path;
 401     dc->realize = i440fx_pcihost_realize;
 402     dc->fw_name = "pci";
 403     device_class_set_props(dc, i440fx_props);
 404     /* Reason: needs to be wired up by pc_init1 */
 405     dc->user_creatable = false;
 406 }
 407
 408 static const TypeInfo i440fx_pcihost_info = {
 409     .name          = TYPE_I440FX_PCI_HOST_BRIDGE,
 410     .parent        = TYPE_PCI_HOST_BRIDGE,
 411     .instance_size = sizeof(I440FXState),
 412     .instance_init = i440fx_pcihost_initfn,
 413     .class_init    = i440fx_pcihost_class_init,
 414 };
 415
 416 static void i440fx_register_types(void)
 417 {
 418     type_register_static(&i440fx_info);
 419     type_register_static(&i440fx_pcihost_info);
 420 }
 421
 422 type_init(i440fx_register_types)