2 * OneNAND flash memories emulation.
4 * Copyright (C) 2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
24 #include "hw/block/flash.h"
26 #include "hw/qdev-properties.h"
27 #include "sysemu/block-backend.h"
28 #include "exec/memory.h"
29 #include "hw/sysbus.h"
30 #include "migration/vmstate.h"
31 #include "qemu/error-report.h"
33 #include "qemu/module.h"
34 #include "qom/object.h"
36 /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
40 #define BLOCK_SHIFT (PAGE_SHIFT + 6)
42 #define TYPE_ONE_NAND "onenand"
43 typedef struct OneNANDState OneNANDState
;
44 DECLARE_INSTANCE_CHECKER(OneNANDState
, ONE_NAND
,
48 SysBusDevice parent_obj
;
60 BlockBackend
*blk_cur
;
65 MemoryRegion mapped_ram
;
66 uint8_t current_direction
;
70 MemoryRegion container
;
96 ONEN_BUF_DEST_BLOCK
= 2,
97 ONEN_BUF_DEST_PAGE
= 3,
102 ONEN_ERR_CMD
= 1 << 10,
103 ONEN_ERR_ERASE
= 1 << 11,
104 ONEN_ERR_PROG
= 1 << 12,
105 ONEN_ERR_LOAD
= 1 << 13,
109 ONEN_INT_RESET
= 1 << 4,
110 ONEN_INT_ERASE
= 1 << 5,
111 ONEN_INT_PROG
= 1 << 6,
112 ONEN_INT_LOAD
= 1 << 7,
117 ONEN_LOCK_LOCKTIGHTEN
= 1 << 0,
118 ONEN_LOCK_LOCKED
= 1 << 1,
119 ONEN_LOCK_UNLOCKED
= 1 << 2,
122 static void onenand_mem_setup(OneNANDState
*s
)
124 /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
125 * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
126 * write boot commands. Also take note of the BWPS bit. */
127 memory_region_init(&s
->container
, OBJECT(s
), "onenand",
128 0x10000 << s
->shift
);
129 memory_region_add_subregion(&s
->container
, 0, &s
->iomem
);
130 memory_region_init_alias(&s
->mapped_ram
, OBJECT(s
), "onenand-mapped-ram",
131 &s
->ram
, 0x0200 << s
->shift
,
133 memory_region_add_subregion_overlap(&s
->container
,
139 static void onenand_intr_update(OneNANDState
*s
)
141 qemu_set_irq(s
->intr
, ((s
->intstatus
>> 15) ^ (~s
->config
[0] >> 6)) & 1);
144 static int onenand_pre_save(void *opaque
)
146 OneNANDState
*s
= opaque
;
147 if (s
->current
== s
->otp
) {
148 s
->current_direction
= 1;
149 } else if (s
->current
== s
->image
) {
150 s
->current_direction
= 2;
152 s
->current_direction
= 0;
158 static int onenand_post_load(void *opaque
, int version_id
)
160 OneNANDState
*s
= opaque
;
161 switch (s
->current_direction
) {
168 s
->current
= s
->image
;
173 onenand_intr_update(s
);
177 static const VMStateDescription vmstate_onenand
= {
180 .minimum_version_id
= 1,
181 .pre_save
= onenand_pre_save
,
182 .post_load
= onenand_post_load
,
183 .fields
= (VMStateField
[]) {
184 VMSTATE_UINT8(current_direction
, OneNANDState
),
185 VMSTATE_INT32(cycle
, OneNANDState
),
186 VMSTATE_INT32(otpmode
, OneNANDState
),
187 VMSTATE_UINT16_ARRAY(addr
, OneNANDState
, 8),
188 VMSTATE_UINT16_ARRAY(unladdr
, OneNANDState
, 8),
189 VMSTATE_INT32(bufaddr
, OneNANDState
),
190 VMSTATE_INT32(count
, OneNANDState
),
191 VMSTATE_UINT16(command
, OneNANDState
),
192 VMSTATE_UINT16_ARRAY(config
, OneNANDState
, 2),
193 VMSTATE_UINT16(status
, OneNANDState
),
194 VMSTATE_UINT16(intstatus
, OneNANDState
),
195 VMSTATE_UINT16(wpstatus
, OneNANDState
),
196 VMSTATE_INT32(secs_cur
, OneNANDState
),
197 VMSTATE_PARTIAL_VBUFFER(blockwp
, OneNANDState
, blocks
),
198 VMSTATE_UINT8(ecc
.cp
, OneNANDState
),
199 VMSTATE_UINT16_ARRAY(ecc
.lp
, OneNANDState
, 2),
200 VMSTATE_UINT16(ecc
.count
, OneNANDState
),
201 VMSTATE_BUFFER_POINTER_UNSAFE(otp
, OneNANDState
, 0,
202 ((64 + 2) << PAGE_SHIFT
)),
203 VMSTATE_END_OF_LIST()
207 /* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
208 static void onenand_reset(OneNANDState
*s
, int cold
)
210 memset(&s
->addr
, 0, sizeof(s
->addr
));
214 s
->config
[0] = 0x40c0;
215 s
->config
[1] = 0x0000;
216 onenand_intr_update(s
);
217 qemu_irq_raise(s
->rdy
);
219 s
->intstatus
= cold
? 0x8080 : 0x8010;
222 s
->wpstatus
= 0x0002;
226 s
->current
= s
->image
;
227 s
->secs_cur
= s
->secs
;
230 /* Lock the whole flash */
231 memset(s
->blockwp
, ONEN_LOCK_LOCKED
, s
->blocks
);
233 if (s
->blk_cur
&& blk_pread(s
->blk_cur
, 0, s
->boot
[0],
234 8 << BDRV_SECTOR_BITS
) < 0) {
235 hw_error("%s: Loading the BootRAM failed.\n", __func__
);
240 static void onenand_system_reset(DeviceState
*dev
)
242 OneNANDState
*s
= ONE_NAND(dev
);
247 static inline int onenand_load_main(OneNANDState
*s
, int sec
, int secn
,
250 assert(UINT32_MAX
>> BDRV_SECTOR_BITS
> sec
);
251 assert(UINT32_MAX
>> BDRV_SECTOR_BITS
> secn
);
253 return blk_pread(s
->blk_cur
, sec
<< BDRV_SECTOR_BITS
, dest
,
254 secn
<< BDRV_SECTOR_BITS
) < 0;
255 } else if (sec
+ secn
> s
->secs_cur
) {
259 memcpy(dest
, s
->current
+ (sec
<< 9), secn
<< 9);
264 static inline int onenand_prog_main(OneNANDState
*s
, int sec
, int secn
,
270 uint32_t size
= secn
<< BDRV_SECTOR_BITS
;
271 uint32_t offset
= sec
<< BDRV_SECTOR_BITS
;
272 assert(UINT32_MAX
>> BDRV_SECTOR_BITS
> sec
);
273 assert(UINT32_MAX
>> BDRV_SECTOR_BITS
> secn
);
274 const uint8_t *sp
= (const uint8_t *)src
;
278 if (!dp
|| blk_pread(s
->blk_cur
, offset
, dp
, size
) < 0) {
282 if (sec
+ secn
> s
->secs_cur
) {
285 dp
= (uint8_t *)s
->current
+ offset
;
290 for (i
= 0; i
< size
; i
++) {
294 result
= blk_pwrite(s
->blk_cur
, offset
, dp
, size
, 0) < 0;
297 if (dp
&& s
->blk_cur
) {
305 static inline int onenand_load_spare(OneNANDState
*s
, int sec
, int secn
,
311 uint32_t offset
= (s
->secs_cur
+ (sec
>> 5)) << BDRV_SECTOR_BITS
;
312 if (blk_pread(s
->blk_cur
, offset
, buf
, BDRV_SECTOR_SIZE
) < 0) {
315 memcpy(dest
, buf
+ ((sec
& 31) << 4), secn
<< 4);
316 } else if (sec
+ secn
> s
->secs_cur
) {
319 memcpy(dest
, s
->current
+ (s
->secs_cur
<< 9) + (sec
<< 4), secn
<< 4);
325 static inline int onenand_prog_spare(OneNANDState
*s
, int sec
, int secn
,
330 const uint8_t *sp
= (const uint8_t *)src
;
331 uint8_t *dp
= 0, *dpp
= 0;
332 uint32_t offset
= (s
->secs_cur
+ (sec
>> 5)) << BDRV_SECTOR_BITS
;
333 assert(UINT32_MAX
>> BDRV_SECTOR_BITS
> s
->secs_cur
+ (sec
>> 5));
337 || blk_pread(s
->blk_cur
, offset
, dp
, BDRV_SECTOR_SIZE
) < 0) {
340 dpp
= dp
+ ((sec
& 31) << 4);
343 if (sec
+ secn
> s
->secs_cur
) {
346 dpp
= s
->current
+ (s
->secs_cur
<< 9) + (sec
<< 4);
351 for (i
= 0; i
< (secn
<< 4); i
++) {
355 result
= blk_pwrite(s
->blk_cur
, offset
, dp
,
356 BDRV_SECTOR_SIZE
, 0) < 0;
364 static inline int onenand_erase(OneNANDState
*s
, int sec
, int num
)
366 uint8_t *blankbuf
, *tmpbuf
;
368 blankbuf
= g_malloc(512);
369 tmpbuf
= g_malloc(512);
370 memset(blankbuf
, 0xff, 512);
371 for (; num
> 0; num
--, sec
++) {
373 int erasesec
= s
->secs_cur
+ (sec
>> 5);
374 if (blk_pwrite(s
->blk_cur
, sec
<< BDRV_SECTOR_BITS
, blankbuf
,
375 BDRV_SECTOR_SIZE
, 0) < 0) {
378 if (blk_pread(s
->blk_cur
, erasesec
<< BDRV_SECTOR_BITS
, tmpbuf
,
379 BDRV_SECTOR_SIZE
) < 0) {
382 memcpy(tmpbuf
+ ((sec
& 31) << 4), blankbuf
, 1 << 4);
383 if (blk_pwrite(s
->blk_cur
, erasesec
<< BDRV_SECTOR_BITS
, tmpbuf
,
384 BDRV_SECTOR_SIZE
, 0) < 0) {
388 if (sec
+ 1 > s
->secs_cur
) {
391 memcpy(s
->current
+ (sec
<< 9), blankbuf
, 512);
392 memcpy(s
->current
+ (s
->secs_cur
<< 9) + (sec
<< 4),
407 static void onenand_command(OneNANDState
*s
)
412 #define SETADDR(block, page) \
413 sec = (s->addr[page] & 3) + \
414 ((((s->addr[page] >> 2) & 0x3f) + \
415 (((s->addr[block] & 0xfff) | \
416 (s->addr[block] >> 15 ? \
417 s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9));
419 buf = (s->bufaddr & 8) ? \
420 s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \
421 buf += (s->bufaddr & 3) << 9;
423 buf = (s->bufaddr & 8) ? \
424 s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
425 buf += (s->bufaddr & 3) << 4;
427 switch (s
->command
) {
428 case 0x00: /* Load single/multiple sector data unit into buffer */
429 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
432 if (onenand_load_main(s
, sec
, s
->count
, buf
))
433 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_LOAD
;
437 if (onenand_load_spare(s
, sec
, s
->count
, buf
))
438 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_LOAD
;
441 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
442 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
443 * then we need two split the read/write into two chunks.
445 s
->intstatus
|= ONEN_INT
| ONEN_INT_LOAD
;
447 case 0x13: /* Load single/multiple spare sector into buffer */
448 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
451 if (onenand_load_spare(s
, sec
, s
->count
, buf
))
452 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_LOAD
;
454 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
455 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
456 * then we need two split the read/write into two chunks.
458 s
->intstatus
|= ONEN_INT
| ONEN_INT_LOAD
;
460 case 0x80: /* Program single/multiple sector data unit from buffer */
461 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
464 if (onenand_prog_main(s
, sec
, s
->count
, buf
))
465 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
469 if (onenand_prog_spare(s
, sec
, s
->count
, buf
))
470 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
473 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
474 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
475 * then we need two split the read/write into two chunks.
477 s
->intstatus
|= ONEN_INT
| ONEN_INT_PROG
;
479 case 0x1a: /* Program single/multiple spare area sector from buffer */
480 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
483 if (onenand_prog_spare(s
, sec
, s
->count
, buf
))
484 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
486 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
487 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
488 * then we need two split the read/write into two chunks.
490 s
->intstatus
|= ONEN_INT
| ONEN_INT_PROG
;
492 case 0x1b: /* Copy-back program */
495 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
496 if (onenand_load_main(s
, sec
, s
->count
, buf
))
497 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
499 SETADDR(ONEN_BUF_DEST_BLOCK
, ONEN_BUF_DEST_PAGE
)
500 if (onenand_prog_main(s
, sec
, s
->count
, buf
))
501 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
503 /* TODO: spare areas */
505 s
->intstatus
|= ONEN_INT
| ONEN_INT_PROG
;
508 case 0x23: /* Unlock NAND array block(s) */
509 s
->intstatus
|= ONEN_INT
;
511 /* XXX the previous (?) area should be locked automatically */
512 for (b
= s
->unladdr
[0]; b
<= s
->unladdr
[1]; b
++) {
513 if (b
>= s
->blocks
) {
514 s
->status
|= ONEN_ERR_CMD
;
517 if (s
->blockwp
[b
] == ONEN_LOCK_LOCKTIGHTEN
)
520 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_UNLOCKED
;
523 case 0x27: /* Unlock All NAND array blocks */
524 s
->intstatus
|= ONEN_INT
;
526 for (b
= 0; b
< s
->blocks
; b
++) {
527 if (s
->blockwp
[b
] == ONEN_LOCK_LOCKTIGHTEN
)
530 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_UNLOCKED
;
534 case 0x2a: /* Lock NAND array block(s) */
535 s
->intstatus
|= ONEN_INT
;
537 for (b
= s
->unladdr
[0]; b
<= s
->unladdr
[1]; b
++) {
538 if (b
>= s
->blocks
) {
539 s
->status
|= ONEN_ERR_CMD
;
542 if (s
->blockwp
[b
] == ONEN_LOCK_LOCKTIGHTEN
)
545 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_LOCKED
;
548 case 0x2c: /* Lock-tight NAND array block(s) */
549 s
->intstatus
|= ONEN_INT
;
551 for (b
= s
->unladdr
[0]; b
<= s
->unladdr
[1]; b
++) {
552 if (b
>= s
->blocks
) {
553 s
->status
|= ONEN_ERR_CMD
;
556 if (s
->blockwp
[b
] == ONEN_LOCK_UNLOCKED
)
559 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_LOCKTIGHTEN
;
563 case 0x71: /* Erase-Verify-Read */
564 s
->intstatus
|= ONEN_INT
;
566 case 0x95: /* Multi-block erase */
567 qemu_irq_pulse(s
->intr
);
569 case 0x94: /* Block erase */
570 sec
= ((s
->addr
[ONEN_BUF_BLOCK
] & 0xfff) |
571 (s
->addr
[ONEN_BUF_BLOCK
] >> 15 ? s
->density_mask
: 0))
572 << (BLOCK_SHIFT
- 9);
573 if (onenand_erase(s
, sec
, 1 << (BLOCK_SHIFT
- 9)))
574 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_ERASE
;
576 s
->intstatus
|= ONEN_INT
| ONEN_INT_ERASE
;
578 case 0xb0: /* Erase suspend */
580 case 0x30: /* Erase resume */
581 s
->intstatus
|= ONEN_INT
| ONEN_INT_ERASE
;
584 case 0xf0: /* Reset NAND Flash core */
587 case 0xf3: /* Reset OneNAND */
591 case 0x65: /* OTP Access */
592 s
->intstatus
|= ONEN_INT
;
595 s
->secs_cur
= 1 << (BLOCK_SHIFT
- 9);
596 s
->addr
[ONEN_BUF_BLOCK
] = 0;
601 s
->status
|= ONEN_ERR_CMD
;
602 s
->intstatus
|= ONEN_INT
;
603 qemu_log_mask(LOG_GUEST_ERROR
, "unknown OneNAND command %x\n",
607 onenand_intr_update(s
);
610 static uint64_t onenand_read(void *opaque
, hwaddr addr
,
613 OneNANDState
*s
= (OneNANDState
*) opaque
;
614 int offset
= addr
>> s
->shift
;
617 case 0x0000 ... 0xbffe:
618 return lduw_le_p(s
->boot
[0] + addr
);
620 case 0xf000: /* Manufacturer ID */
622 case 0xf001: /* Device ID */
624 case 0xf002: /* Version ID */
626 /* TODO: get the following values from a real chip! */
627 case 0xf003: /* Data Buffer size */
628 return 1 << PAGE_SHIFT
;
629 case 0xf004: /* Boot Buffer size */
631 case 0xf005: /* Amount of buffers */
633 case 0xf006: /* Technology */
636 case 0xf100 ... 0xf107: /* Start addresses */
637 return s
->addr
[offset
- 0xf100];
639 case 0xf200: /* Start buffer */
640 return (s
->bufaddr
<< 8) | ((s
->count
- 1) & (1 << (PAGE_SHIFT
- 10)));
642 case 0xf220: /* Command */
644 case 0xf221: /* System Configuration 1 */
645 return s
->config
[0] & 0xffe0;
646 case 0xf222: /* System Configuration 2 */
649 case 0xf240: /* Controller Status */
651 case 0xf241: /* Interrupt */
653 case 0xf24c: /* Unlock Start Block Address */
654 return s
->unladdr
[0];
655 case 0xf24d: /* Unlock End Block Address */
656 return s
->unladdr
[1];
657 case 0xf24e: /* Write Protection Status */
660 case 0xff00: /* ECC Status */
662 case 0xff01: /* ECC Result of main area data */
663 case 0xff02: /* ECC Result of spare area data */
664 case 0xff03: /* ECC Result of main area data */
665 case 0xff04: /* ECC Result of spare area data */
666 qemu_log_mask(LOG_UNIMP
,
667 "onenand: ECC result registers unimplemented\n");
671 qemu_log_mask(LOG_GUEST_ERROR
, "read of unknown OneNAND register 0x%x\n",
676 static void onenand_write(void *opaque
, hwaddr addr
,
677 uint64_t value
, unsigned size
)
679 OneNANDState
*s
= (OneNANDState
*) opaque
;
680 int offset
= addr
>> s
->shift
;
684 case 0x0000 ... 0x01ff:
685 case 0x8000 ... 0x800f:
689 if (value
== 0x0000) {
690 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
691 onenand_load_main(s
, sec
,
692 1 << (PAGE_SHIFT
- 9), s
->data
[0][0]);
693 s
->addr
[ONEN_BUF_PAGE
] += 4;
694 s
->addr
[ONEN_BUF_PAGE
] &= 0xff;
700 case 0x00f0: /* Reset OneNAND */
704 case 0x00e0: /* Load Data into Buffer */
708 case 0x0090: /* Read Identification Data */
709 memset(s
->boot
[0], 0, 3 << s
->shift
);
710 s
->boot
[0][0 << s
->shift
] = s
->id
.man
& 0xff;
711 s
->boot
[0][1 << s
->shift
] = s
->id
.dev
& 0xff;
712 s
->boot
[0][2 << s
->shift
] = s
->wpstatus
& 0xff;
716 qemu_log_mask(LOG_GUEST_ERROR
,
717 "unknown OneNAND boot command %" PRIx64
"\n",
722 case 0xf100 ... 0xf107: /* Start addresses */
723 s
->addr
[offset
- 0xf100] = value
;
726 case 0xf200: /* Start buffer */
727 s
->bufaddr
= (value
>> 8) & 0xf;
728 if (PAGE_SHIFT
== 11)
729 s
->count
= (value
& 3) ?: 4;
730 else if (PAGE_SHIFT
== 10)
731 s
->count
= (value
& 1) ?: 2;
734 case 0xf220: /* Command */
735 if (s
->intstatus
& (1 << 15))
740 case 0xf221: /* System Configuration 1 */
741 s
->config
[0] = value
;
742 onenand_intr_update(s
);
743 qemu_set_irq(s
->rdy
, (s
->config
[0] >> 7) & 1);
745 case 0xf222: /* System Configuration 2 */
746 s
->config
[1] = value
;
749 case 0xf241: /* Interrupt */
750 s
->intstatus
&= value
;
751 if ((1 << 15) & ~s
->intstatus
)
752 s
->status
&= ~(ONEN_ERR_CMD
| ONEN_ERR_ERASE
|
753 ONEN_ERR_PROG
| ONEN_ERR_LOAD
);
754 onenand_intr_update(s
);
756 case 0xf24c: /* Unlock Start Block Address */
757 s
->unladdr
[0] = value
& (s
->blocks
- 1);
758 /* For some reason we have to set the end address to by default
759 * be same as start because the software forgets to write anything
761 s
->unladdr
[1] = value
& (s
->blocks
- 1);
763 case 0xf24d: /* Unlock End Block Address */
764 s
->unladdr
[1] = value
& (s
->blocks
- 1);
768 qemu_log_mask(LOG_GUEST_ERROR
,
769 "write to unknown OneNAND register 0x%x\n",
774 static const MemoryRegionOps onenand_ops
= {
775 .read
= onenand_read
,
776 .write
= onenand_write
,
777 .endianness
= DEVICE_NATIVE_ENDIAN
,
780 static void onenand_realize(DeviceState
*dev
, Error
**errp
)
782 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
783 OneNANDState
*s
= ONE_NAND(dev
);
784 uint32_t size
= 1 << (24 + ((s
->id
.dev
>> 4) & 7));
786 Error
*local_err
= NULL
;
788 s
->base
= (hwaddr
)-1;
790 s
->blocks
= size
>> BLOCK_SHIFT
;
792 s
->blockwp
= g_malloc(s
->blocks
);
793 s
->density_mask
= (s
->id
.dev
& 0x08)
794 ? (1 << (6 + ((s
->id
.dev
>> 4) & 7))) : 0;
795 memory_region_init_io(&s
->iomem
, OBJECT(s
), &onenand_ops
, s
, "onenand",
796 0x10000 << s
->shift
);
798 s
->image
= memset(g_malloc(size
+ (size
>> 5)),
799 0xff, size
+ (size
>> 5));
801 if (blk_is_read_only(s
->blk
)) {
802 error_setg(errp
, "Can't use a read-only drive");
805 blk_set_perm(s
->blk
, BLK_PERM_CONSISTENT_READ
| BLK_PERM_WRITE
,
806 BLK_PERM_ALL
, &local_err
);
808 error_propagate(errp
, local_err
);
813 s
->otp
= memset(g_malloc((64 + 2) << PAGE_SHIFT
),
814 0xff, (64 + 2) << PAGE_SHIFT
);
815 memory_region_init_ram_nomigrate(&s
->ram
, OBJECT(s
), "onenand.ram",
816 0xc000 << s
->shift
, &error_fatal
);
817 vmstate_register_ram_global(&s
->ram
);
818 ram
= memory_region_get_ram_ptr(&s
->ram
);
819 s
->boot
[0] = ram
+ (0x0000 << s
->shift
);
820 s
->boot
[1] = ram
+ (0x8000 << s
->shift
);
821 s
->data
[0][0] = ram
+ ((0x0200 + (0 << (PAGE_SHIFT
- 1))) << s
->shift
);
822 s
->data
[0][1] = ram
+ ((0x8010 + (0 << (PAGE_SHIFT
- 6))) << s
->shift
);
823 s
->data
[1][0] = ram
+ ((0x0200 + (1 << (PAGE_SHIFT
- 1))) << s
->shift
);
824 s
->data
[1][1] = ram
+ ((0x8010 + (1 << (PAGE_SHIFT
- 6))) << s
->shift
);
825 onenand_mem_setup(s
);
826 sysbus_init_irq(sbd
, &s
->intr
);
827 sysbus_init_mmio(sbd
, &s
->container
);
828 vmstate_register(VMSTATE_IF(dev
),
829 ((s
->shift
& 0x7f) << 24)
830 | ((s
->id
.man
& 0xff) << 16)
831 | ((s
->id
.dev
& 0xff) << 8)
832 | (s
->id
.ver
& 0xff),
833 &vmstate_onenand
, s
);
836 static Property onenand_properties
[] = {
837 DEFINE_PROP_UINT16("manufacturer_id", OneNANDState
, id
.man
, 0),
838 DEFINE_PROP_UINT16("device_id", OneNANDState
, id
.dev
, 0),
839 DEFINE_PROP_UINT16("version_id", OneNANDState
, id
.ver
, 0),
840 DEFINE_PROP_INT32("shift", OneNANDState
, shift
, 0),
841 DEFINE_PROP_DRIVE("drive", OneNANDState
, blk
),
842 DEFINE_PROP_END_OF_LIST(),
845 static void onenand_class_init(ObjectClass
*klass
, void *data
)
847 DeviceClass
*dc
= DEVICE_CLASS(klass
);
849 dc
->realize
= onenand_realize
;
850 dc
->reset
= onenand_system_reset
;
851 device_class_set_props(dc
, onenand_properties
);
854 static const TypeInfo onenand_info
= {
855 .name
= TYPE_ONE_NAND
,
856 .parent
= TYPE_SYS_BUS_DEVICE
,
857 .instance_size
= sizeof(OneNANDState
),
858 .class_init
= onenand_class_init
,
861 static void onenand_register_types(void)
863 type_register_static(&onenand_info
);
866 void *onenand_raw_otp(DeviceState
*onenand_device
)
868 OneNANDState
*s
= ONE_NAND(onenand_device
);
873 type_init(onenand_register_types
)