2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
38 #include "hw/fw-path-provider.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "migration/blocker.h"
50 #include "mmu-hash64.h"
51 #include "mmu-book3s-v3.h"
52 #include "cpu-models.h"
53 #include "hw/core/cpu.h"
55 #include "hw/boards.h"
56 #include "hw/ppc/ppc.h"
57 #include "hw/loader.h"
59 #include "hw/ppc/fdt.h"
60 #include "hw/ppc/spapr.h"
61 #include "hw/ppc/spapr_vio.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/pci-host/spapr.h"
64 #include "hw/pci/msi.h"
66 #include "hw/pci/pci.h"
67 #include "hw/scsi/scsi.h"
68 #include "hw/virtio/virtio-scsi.h"
69 #include "hw/virtio/vhost-scsi-common.h"
71 #include "exec/address-spaces.h"
72 #include "exec/ram_addr.h"
74 #include "qemu/config-file.h"
75 #include "qemu/error-report.h"
78 #include "hw/intc/intc.h"
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
83 #include "hw/ppc/spapr_nvdimm.h"
84 #include "hw/ppc/spapr_numa.h"
86 #include "monitor/monitor.h"
90 /* SLOF memory layout:
92 * SLOF raw image loaded at 0, copies its romfs right below the flat
93 * device-tree, then position SLOF itself 31M below that
95 * So we set FW_OVERHEAD to 40MB which should account for all of that
98 * We load our kernel at 4M, leaving space for SLOF initial image
100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
101 #define FW_MAX_SIZE 0x400000
102 #define FW_FILE_NAME "slof.bin"
103 #define FW_OVERHEAD 0x2800000
104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
106 #define MIN_RMA_SLOF (128 * MiB)
108 #define PHANDLE_INTC 0x00001111
110 /* These two functions implement the VCPU id numbering: one to compute them
111 * all and one to identify thread 0 of a VCORE. Any change to the first one
112 * is likely to have an impact on the second one, so let's keep them close.
114 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
116 MachineState
*ms
= MACHINE(spapr
);
117 unsigned int smp_threads
= ms
->smp
.threads
;
121 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
123 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
127 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
132 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
133 * and newer QEMUs don't even have them. In both cases, we don't want
134 * to send anything on the wire.
139 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
140 .name
= "icp/server",
142 .minimum_version_id
= 1,
143 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
144 .fields
= (VMStateField
[]) {
145 VMSTATE_UNUSED(4), /* uint32_t xirr */
146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
147 VMSTATE_UNUSED(1), /* uint8_t mfrr */
148 VMSTATE_END_OF_LIST()
152 static void pre_2_10_vmstate_register_dummy_icp(int i
)
154 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
155 (void *)(uintptr_t) i
);
158 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
160 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
161 (void *)(uintptr_t) i
);
164 int spapr_max_server_number(SpaprMachineState
*spapr
)
166 MachineState
*ms
= MACHINE(spapr
);
169 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
172 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
176 uint32_t servers_prop
[smt_threads
];
177 uint32_t gservers_prop
[smt_threads
* 2];
178 int index
= spapr_get_vcpu_id(cpu
);
180 if (cpu
->compat_pvr
) {
181 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
187 /* Build interrupt servers and gservers properties */
188 for (i
= 0; i
< smt_threads
; i
++) {
189 servers_prop
[i
] = cpu_to_be32(index
+ i
);
190 /* Hack, direct the group queues back to cpu 0 */
191 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
192 gservers_prop
[i
*2 + 1] = 0;
194 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
195 servers_prop
, sizeof(servers_prop
));
199 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
200 gservers_prop
, sizeof(gservers_prop
));
205 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
207 int index
= spapr_get_vcpu_id(cpu
);
208 uint32_t associativity
[] = {cpu_to_be32(0x5),
212 cpu_to_be32(cpu
->node_id
),
215 /* Advertise NUMA via ibm,associativity */
216 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
217 sizeof(associativity
));
220 static void spapr_dt_pa_features(SpaprMachineState
*spapr
,
222 void *fdt
, int offset
)
224 uint8_t pa_features_206
[] = { 6, 0,
225 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
226 uint8_t pa_features_207
[] = { 24, 0,
227 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
228 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
229 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
230 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
231 uint8_t pa_features_300
[] = { 66, 0,
232 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
233 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
234 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
236 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
238 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
239 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
241 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
242 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
243 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
244 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
245 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
246 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
247 /* 42: PM, 44: PC RA, 46: SC vec'd */
248 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
249 /* 48: SIMD, 50: QP BFP, 52: String */
250 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
251 /* 54: DecFP, 56: DecI, 58: SHA */
252 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
253 /* 60: NM atomic, 62: RNG */
254 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
256 uint8_t *pa_features
= NULL
;
259 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
260 pa_features
= pa_features_206
;
261 pa_size
= sizeof(pa_features_206
);
263 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
264 pa_features
= pa_features_207
;
265 pa_size
= sizeof(pa_features_207
);
267 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
268 pa_features
= pa_features_300
;
269 pa_size
= sizeof(pa_features_300
);
275 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
277 * Note: we keep CI large pages off by default because a 64K capable
278 * guest provisioned with large pages might otherwise try to map a qemu
279 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
280 * even if that qemu runs on a 4k host.
281 * We dd this bit back here if we are confident this is not an issue
283 pa_features
[3] |= 0x20;
285 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
286 pa_features
[24] |= 0x80; /* Transactional memory support */
288 if (spapr
->cas_pre_isa3_guest
&& pa_size
> 40) {
289 /* Workaround for broken kernels that attempt (guest) radix
290 * mode when they can't handle it, if they see the radix bit set
291 * in pa-features. So hide it from them. */
292 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
295 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
298 static hwaddr
spapr_node0_size(MachineState
*machine
)
300 if (machine
->numa_state
->num_nodes
) {
302 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
303 if (machine
->numa_state
->nodes
[i
].node_mem
) {
304 return MIN(pow2floor(machine
->numa_state
->nodes
[i
].node_mem
),
309 return machine
->ram_size
;
312 static void add_str(GString
*s
, const gchar
*s1
)
314 g_string_append_len(s
, s1
, strlen(s1
) + 1);
317 static int spapr_dt_memory_node(void *fdt
, int nodeid
, hwaddr start
,
320 uint32_t associativity
[] = {
321 cpu_to_be32(0x4), /* length */
322 cpu_to_be32(0x0), cpu_to_be32(0x0),
323 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
326 uint64_t mem_reg_property
[2];
329 mem_reg_property
[0] = cpu_to_be64(start
);
330 mem_reg_property
[1] = cpu_to_be64(size
);
332 sprintf(mem_name
, "memory@%" HWADDR_PRIx
, start
);
333 off
= fdt_add_subnode(fdt
, 0, mem_name
);
335 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
336 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
337 sizeof(mem_reg_property
))));
338 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
339 sizeof(associativity
))));
343 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
345 MemoryDeviceInfoList
*info
;
347 for (info
= list
; info
; info
= info
->next
) {
348 MemoryDeviceInfo
*value
= info
->value
;
350 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
351 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
353 if (addr
>= pcdimm_info
->addr
&&
354 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
355 return pcdimm_info
->node
;
363 struct sPAPRDrconfCellV2
{
371 typedef struct DrconfCellQueue
{
372 struct sPAPRDrconfCellV2 cell
;
373 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
376 static DrconfCellQueue
*
377 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
378 uint32_t drc_index
, uint32_t aa_index
,
381 DrconfCellQueue
*elem
;
383 elem
= g_malloc0(sizeof(*elem
));
384 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
385 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
386 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
387 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
388 elem
->cell
.flags
= cpu_to_be32(flags
);
393 static int spapr_dt_dynamic_memory_v2(SpaprMachineState
*spapr
, void *fdt
,
394 int offset
, MemoryDeviceInfoList
*dimms
)
396 MachineState
*machine
= MACHINE(spapr
);
397 uint8_t *int_buf
, *cur_index
;
399 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
400 uint64_t addr
, cur_addr
, size
;
401 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
402 uint64_t mem_end
= machine
->device_memory
->base
+
403 memory_region_size(&machine
->device_memory
->mr
);
404 uint32_t node
, buf_len
, nr_entries
= 0;
406 DrconfCellQueue
*elem
, *next
;
407 MemoryDeviceInfoList
*info
;
408 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
409 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
411 /* Entry to cover RAM and the gap area */
412 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
413 SPAPR_LMB_FLAGS_RESERVED
|
414 SPAPR_LMB_FLAGS_DRC_INVALID
);
415 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
418 cur_addr
= machine
->device_memory
->base
;
419 for (info
= dimms
; info
; info
= info
->next
) {
420 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
427 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
428 * area is marked hotpluggable in the next iteration for the bigger
429 * chunk including the NVDIMM occupied area.
431 if (info
->value
->type
== MEMORY_DEVICE_INFO_KIND_NVDIMM
)
434 /* Entry for hot-pluggable area */
435 if (cur_addr
< addr
) {
436 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
438 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
439 cur_addr
, spapr_drc_index(drc
), -1, 0);
440 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
445 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
447 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
448 spapr_drc_index(drc
), node
,
449 (SPAPR_LMB_FLAGS_ASSIGNED
|
450 SPAPR_LMB_FLAGS_HOTREMOVABLE
));
451 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
453 cur_addr
= addr
+ size
;
456 /* Entry for remaining hotpluggable area */
457 if (cur_addr
< mem_end
) {
458 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
460 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
461 cur_addr
, spapr_drc_index(drc
), -1, 0);
462 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
466 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
467 int_buf
= cur_index
= g_malloc0(buf_len
);
468 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
469 cur_index
+= sizeof(nr_entries
);
471 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
472 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
473 cur_index
+= sizeof(elem
->cell
);
474 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
478 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
486 static int spapr_dt_dynamic_memory(SpaprMachineState
*spapr
, void *fdt
,
487 int offset
, MemoryDeviceInfoList
*dimms
)
489 MachineState
*machine
= MACHINE(spapr
);
491 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
492 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
493 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
494 memory_region_size(&machine
->device_memory
->mr
)) /
496 uint32_t *int_buf
, *cur_index
, buf_len
;
499 * Allocate enough buffer size to fit in ibm,dynamic-memory
501 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
502 cur_index
= int_buf
= g_malloc0(buf_len
);
503 int_buf
[0] = cpu_to_be32(nr_lmbs
);
505 for (i
= 0; i
< nr_lmbs
; i
++) {
506 uint64_t addr
= i
* lmb_size
;
507 uint32_t *dynamic_memory
= cur_index
;
509 if (i
>= device_lmb_start
) {
512 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
515 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
516 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
517 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
518 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
519 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
520 if (memory_region_present(get_system_memory(), addr
)) {
521 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
523 dynamic_memory
[5] = cpu_to_be32(0);
527 * LMB information for RMA, boot time RAM and gap b/n RAM and
528 * device memory region -- all these are marked as reserved
529 * and as having no valid DRC.
531 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
532 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
533 dynamic_memory
[2] = cpu_to_be32(0);
534 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
535 dynamic_memory
[4] = cpu_to_be32(-1);
536 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
537 SPAPR_LMB_FLAGS_DRC_INVALID
);
540 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
542 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
551 * Adds ibm,dynamic-reconfiguration-memory node.
552 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
553 * of this device tree node.
555 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState
*spapr
,
558 MachineState
*machine
= MACHINE(spapr
);
559 int nb_numa_nodes
= machine
->numa_state
->num_nodes
;
561 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
562 uint32_t prop_lmb_size
[] = {cpu_to_be32(lmb_size
>> 32),
563 cpu_to_be32(lmb_size
& 0xffffffff)};
564 uint32_t *int_buf
, *cur_index
, buf_len
;
565 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
566 MemoryDeviceInfoList
*dimms
= NULL
;
569 * Don't create the node if there is no device memory
571 if (machine
->ram_size
== machine
->maxram_size
) {
575 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
577 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
578 sizeof(prop_lmb_size
));
583 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
588 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
593 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
594 dimms
= qmp_memory_device_list();
595 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
596 ret
= spapr_dt_dynamic_memory_v2(spapr
, fdt
, offset
, dimms
);
598 ret
= spapr_dt_dynamic_memory(spapr
, fdt
, offset
, dimms
);
600 qapi_free_MemoryDeviceInfoList(dimms
);
606 /* ibm,associativity-lookup-arrays */
607 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
608 cur_index
= int_buf
= g_malloc0(buf_len
);
609 int_buf
[0] = cpu_to_be32(nr_nodes
);
610 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
612 for (i
= 0; i
< nr_nodes
; i
++) {
613 uint32_t associativity
[] = {
619 memcpy(cur_index
, associativity
, sizeof(associativity
));
622 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
623 (cur_index
- int_buf
) * sizeof(uint32_t));
629 static int spapr_dt_memory(SpaprMachineState
*spapr
, void *fdt
)
631 MachineState
*machine
= MACHINE(spapr
);
632 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
633 hwaddr mem_start
, node_size
;
634 int i
, nb_nodes
= machine
->numa_state
->num_nodes
;
635 NodeInfo
*nodes
= machine
->numa_state
->nodes
;
637 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
638 if (!nodes
[i
].node_mem
) {
641 if (mem_start
>= machine
->ram_size
) {
644 node_size
= nodes
[i
].node_mem
;
645 if (node_size
> machine
->ram_size
- mem_start
) {
646 node_size
= machine
->ram_size
- mem_start
;
650 /* spapr_machine_init() checks for rma_size <= node0_size
652 spapr_dt_memory_node(fdt
, i
, 0, spapr
->rma_size
);
653 mem_start
+= spapr
->rma_size
;
654 node_size
-= spapr
->rma_size
;
656 for ( ; node_size
; ) {
657 hwaddr sizetmp
= pow2floor(node_size
);
659 /* mem_start != 0 here */
660 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
661 sizetmp
= 1ULL << ctzl(mem_start
);
664 spapr_dt_memory_node(fdt
, i
, mem_start
, sizetmp
);
665 node_size
-= sizetmp
;
666 mem_start
+= sizetmp
;
670 /* Generate ibm,dynamic-reconfiguration-memory node if required */
671 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRCONF_MEMORY
)) {
674 g_assert(smc
->dr_lmb_enabled
);
675 ret
= spapr_dt_dynamic_reconfiguration_memory(spapr
, fdt
);
684 static void spapr_dt_cpu(CPUState
*cs
, void *fdt
, int offset
,
685 SpaprMachineState
*spapr
)
687 MachineState
*ms
= MACHINE(spapr
);
688 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
689 CPUPPCState
*env
= &cpu
->env
;
690 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
691 int index
= spapr_get_vcpu_id(cpu
);
692 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
693 0xffffffff, 0xffffffff};
694 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
695 : SPAPR_TIMEBASE_FREQ
;
696 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
697 uint32_t page_sizes_prop
[64];
698 size_t page_sizes_prop_size
;
699 unsigned int smp_threads
= ms
->smp
.threads
;
700 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
701 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
702 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
705 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
708 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
710 drc_index
= spapr_drc_index(drc
);
711 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
714 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
715 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
717 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
718 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
719 env
->dcache_line_size
)));
720 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
721 env
->dcache_line_size
)));
722 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
723 env
->icache_line_size
)));
724 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
725 env
->icache_line_size
)));
727 if (pcc
->l1_dcache_size
) {
728 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
729 pcc
->l1_dcache_size
)));
731 warn_report("Unknown L1 dcache size for cpu");
733 if (pcc
->l1_icache_size
) {
734 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
735 pcc
->l1_icache_size
)));
737 warn_report("Unknown L1 icache size for cpu");
740 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
741 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
742 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
743 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
744 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
745 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
747 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
748 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
750 if (env
->spr_cb
[SPR_SPURR
].oea_read
) {
751 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
754 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
755 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
756 segs
, sizeof(segs
))));
759 /* Advertise VSX (vector extensions) if available
760 * 1 == VMX / Altivec available
763 * Only CPUs for which we create core types in spapr_cpu_core.c
764 * are possible, and all of those have VMX */
765 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
766 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
768 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
771 /* Advertise DFP (Decimal Floating Point) if available
772 * 0 / no property == no DFP
773 * 1 == DFP available */
774 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
775 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
778 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
779 sizeof(page_sizes_prop
));
780 if (page_sizes_prop_size
) {
781 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
782 page_sizes_prop
, page_sizes_prop_size
)));
785 spapr_dt_pa_features(spapr
, cpu
, fdt
, offset
);
787 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
788 cs
->cpu_index
/ vcpus_per_socket
)));
790 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
791 pft_size_prop
, sizeof(pft_size_prop
))));
793 if (ms
->numa_state
->num_nodes
> 1) {
794 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
797 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
799 if (pcc
->radix_page_info
) {
800 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
801 radix_AP_encodings
[i
] =
802 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
804 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
806 pcc
->radix_page_info
->count
*
807 sizeof(radix_AP_encodings
[0]))));
811 * We set this property to let the guest know that it can use the large
812 * decrementer and its width in bits.
814 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
815 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
816 pcc
->lrg_decr_bits
)));
819 static void spapr_dt_cpus(void *fdt
, SpaprMachineState
*spapr
)
828 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
830 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
831 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
834 * We walk the CPUs in reverse order to ensure that CPU DT nodes
835 * created by fdt_add_subnode() end up in the right order in FDT
836 * for the guest kernel the enumerate the CPUs correctly.
838 * The CPU list cannot be traversed in reverse order, so we need
844 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
848 for (i
= n_cpus
- 1; i
>= 0; i
--) {
849 CPUState
*cs
= rev
[i
];
850 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
851 int index
= spapr_get_vcpu_id(cpu
);
852 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
855 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
859 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
860 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
863 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
869 static int spapr_dt_rng(void *fdt
)
874 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
878 ret
= fdt_setprop_string(fdt
, node
, "device_type",
879 "ibm,platform-facilities");
880 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
881 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
883 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
887 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
892 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
894 MachineState
*ms
= MACHINE(spapr
);
896 GString
*hypertas
= g_string_sized_new(256);
897 GString
*qemu_hypertas
= g_string_sized_new(256);
898 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
899 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
900 uint32_t lrdr_capacity
[] = {
901 cpu_to_be32(max_device_addr
>> 32),
902 cpu_to_be32(max_device_addr
& 0xffffffff),
903 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
>> 32),
904 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
& 0xffffffff),
905 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
908 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
911 add_str(hypertas
, "hcall-pft");
912 add_str(hypertas
, "hcall-term");
913 add_str(hypertas
, "hcall-dabr");
914 add_str(hypertas
, "hcall-interrupt");
915 add_str(hypertas
, "hcall-tce");
916 add_str(hypertas
, "hcall-vio");
917 add_str(hypertas
, "hcall-splpar");
918 add_str(hypertas
, "hcall-join");
919 add_str(hypertas
, "hcall-bulk");
920 add_str(hypertas
, "hcall-set-mode");
921 add_str(hypertas
, "hcall-sprg0");
922 add_str(hypertas
, "hcall-copy");
923 add_str(hypertas
, "hcall-debug");
924 add_str(hypertas
, "hcall-vphn");
925 add_str(qemu_hypertas
, "hcall-memop1");
927 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
928 add_str(hypertas
, "hcall-multi-tce");
931 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
932 add_str(hypertas
, "hcall-hpt-resize");
935 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
936 hypertas
->str
, hypertas
->len
));
937 g_string_free(hypertas
, TRUE
);
938 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
939 qemu_hypertas
->str
, qemu_hypertas
->len
));
940 g_string_free(qemu_hypertas
, TRUE
);
942 spapr_numa_write_rtas_dt(spapr
, fdt
, rtas
);
945 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
946 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
948 * The system reset requirements are driven by existing Linux and PowerVM
949 * implementation which (contrary to PAPR) saves r3 in the error log
950 * structure like machine check, so Linux expects to find the saved r3
951 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
952 * does not look at the error value).
954 * System reset interrupts are not subject to interlock like machine
955 * check, so this memory area could be corrupted if the sreset is
956 * interrupted by a machine check (or vice versa) if it was shared. To
957 * prevent this, system reset uses per-CPU areas for the sreset save
958 * area. A system reset that interrupts a system reset handler could
959 * still overwrite this area, but Linux doesn't try to recover in that
962 * The extra 8 bytes is required because Linux's FWNMI error log check
965 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-size", RTAS_ERROR_LOG_MAX
+
966 ms
->smp
.max_cpus
* sizeof(uint64_t)*2 + sizeof(uint64_t)));
967 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
968 RTAS_ERROR_LOG_MAX
));
969 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
970 RTAS_EVENT_SCAN_RATE
));
972 g_assert(msi_nonbroken
);
973 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
976 * According to PAPR, rtas ibm,os-term does not guarantee a return
977 * back to the guest cpu.
979 * While an additional ibm,extended-os-term property indicates
980 * that rtas call return will always occur. Set this property.
982 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
984 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
985 lrdr_capacity
, sizeof(lrdr_capacity
)));
987 spapr_dt_rtas_tokens(fdt
, rtas
);
991 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
992 * and the XIVE features that the guest may request and thus the valid
993 * values for bytes 23..26 of option vector 5:
995 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
998 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1001 23, 0x00, /* XICS / XIVE mode */
1002 24, 0x00, /* Hash/Radix, filled in below. */
1003 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1004 26, 0x40, /* Radix options: GTSE == yes. */
1007 if (spapr
->irq
->xics
&& spapr
->irq
->xive
) {
1008 val
[1] = SPAPR_OV5_XIVE_BOTH
;
1009 } else if (spapr
->irq
->xive
) {
1010 val
[1] = SPAPR_OV5_XIVE_EXPLOIT
;
1012 assert(spapr
->irq
->xics
);
1013 val
[1] = SPAPR_OV5_XIVE_LEGACY
;
1016 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1017 first_ppc_cpu
->compat_pvr
)) {
1019 * If we're in a pre POWER9 compat mode then the guest should
1020 * do hash and use the legacy interrupt mode
1022 val
[1] = SPAPR_OV5_XIVE_LEGACY
; /* XICS */
1023 val
[3] = 0x00; /* Hash */
1024 } else if (kvm_enabled()) {
1025 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1026 val
[3] = 0x80; /* OV5_MMU_BOTH */
1027 } else if (kvmppc_has_cap_mmu_radix()) {
1028 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1030 val
[3] = 0x00; /* Hash */
1033 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1036 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1040 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
, bool reset
)
1042 MachineState
*machine
= MACHINE(spapr
);
1043 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1046 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1049 const char *boot_device
= machine
->boot_order
;
1050 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1052 char *bootlist
= get_boot_devices_list(&cb
);
1054 if (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0]) {
1055 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs",
1056 machine
->kernel_cmdline
));
1059 if (spapr
->initrd_size
) {
1060 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1061 spapr
->initrd_base
));
1062 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1063 spapr
->initrd_base
+ spapr
->initrd_size
));
1066 if (spapr
->kernel_size
) {
1067 uint64_t kprop
[2] = { cpu_to_be64(spapr
->kernel_addr
),
1068 cpu_to_be64(spapr
->kernel_size
) };
1070 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1071 &kprop
, sizeof(kprop
)));
1072 if (spapr
->kernel_le
) {
1073 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1077 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1079 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1080 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1081 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1083 if (cb
&& bootlist
) {
1086 for (i
= 0; i
< cb
; i
++) {
1087 if (bootlist
[i
] == '\n') {
1091 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1094 if (boot_device
&& strlen(boot_device
)) {
1095 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1098 if (!spapr
->has_graphics
&& stdout_path
) {
1100 * "linux,stdout-path" and "stdout" properties are
1101 * deprecated by linux kernel. New platforms should only
1102 * use the "stdout-path" property. Set the new property
1103 * and continue using older property to remain compatible
1104 * with the existing firmware.
1106 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1107 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1111 * We can deal with BAR reallocation just fine, advertise it
1114 if (smc
->linux_pci_probe
) {
1115 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,pci-probe-only", 0));
1118 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1120 g_free(stdout_path
);
1124 _FDT(spapr_dt_ovec(fdt
, chosen
, spapr
->ov5_cas
, "ibm,architecture-vec-5"));
1127 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1129 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1130 * KVM to work under pHyp with some guest co-operation */
1132 uint8_t hypercall
[16];
1134 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1135 /* indicate KVM hypercall interface */
1136 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1137 if (kvmppc_has_cap_fixup_hcalls()) {
1139 * Older KVM versions with older guest kernels were broken
1140 * with the magic page, don't allow the guest to map it.
1142 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1143 sizeof(hypercall
))) {
1144 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1145 hypercall
, sizeof(hypercall
)));
1150 void *spapr_build_fdt(SpaprMachineState
*spapr
, bool reset
, size_t space
)
1152 MachineState
*machine
= MACHINE(spapr
);
1153 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1154 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1160 fdt
= g_malloc0(space
);
1161 _FDT((fdt_create_empty_tree(fdt
, space
)));
1164 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1165 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1166 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1168 /* Guest UUID & Name*/
1169 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1170 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1171 if (qemu_uuid_set
) {
1172 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1176 if (qemu_get_vm_name()) {
1177 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1178 qemu_get_vm_name()));
1181 /* Host Model & Serial Number */
1182 if (spapr
->host_model
) {
1183 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1184 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1185 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1189 if (spapr
->host_serial
) {
1190 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1191 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1192 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1196 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1197 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1199 /* /interrupt controller */
1200 spapr_irq_dt(spapr
, spapr_max_server_number(spapr
), fdt
, PHANDLE_INTC
);
1202 ret
= spapr_dt_memory(spapr
, fdt
);
1204 error_report("couldn't setup memory nodes in fdt");
1209 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1211 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1212 ret
= spapr_dt_rng(fdt
);
1214 error_report("could not set up rng device in the fdt");
1219 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1220 ret
= spapr_dt_phb(spapr
, phb
, PHANDLE_INTC
, fdt
, NULL
);
1222 error_report("couldn't setup PCI devices in fdt");
1227 spapr_dt_cpus(fdt
, spapr
);
1229 if (smc
->dr_lmb_enabled
) {
1230 _FDT(spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1233 if (mc
->has_hotpluggable_cpus
) {
1234 int offset
= fdt_path_offset(fdt
, "/cpus");
1235 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1237 error_report("Couldn't set up CPU DR device tree properties");
1242 /* /event-sources */
1243 spapr_dt_events(spapr
, fdt
);
1246 spapr_dt_rtas(spapr
, fdt
);
1249 spapr_dt_chosen(spapr
, fdt
, reset
);
1252 if (kvm_enabled()) {
1253 spapr_dt_hypervisor(spapr
, fdt
);
1256 /* Build memory reserve map */
1258 if (spapr
->kernel_size
) {
1259 _FDT((fdt_add_mem_rsv(fdt
, spapr
->kernel_addr
,
1260 spapr
->kernel_size
)));
1262 if (spapr
->initrd_size
) {
1263 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
,
1264 spapr
->initrd_size
)));
1268 if (smc
->dr_phb_enabled
) {
1269 ret
= spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_PHB
);
1271 error_report("Couldn't set up PHB DR device tree properties");
1276 /* NVDIMM devices */
1277 if (mc
->nvdimm_supported
) {
1278 spapr_dt_persistent_memory(fdt
);
1284 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1286 SpaprMachineState
*spapr
= opaque
;
1288 return (addr
& 0x0fffffff) + spapr
->kernel_addr
;
1291 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1294 CPUPPCState
*env
= &cpu
->env
;
1296 /* The TCG path should also be holding the BQL at this point */
1297 g_assert(qemu_mutex_iothread_locked());
1300 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1301 env
->gpr
[3] = H_PRIVILEGE
;
1303 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1307 struct LPCRSyncState
{
1312 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1314 struct LPCRSyncState
*s
= arg
.host_ptr
;
1315 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1316 CPUPPCState
*env
= &cpu
->env
;
1319 cpu_synchronize_state(cs
);
1320 lpcr
= env
->spr
[SPR_LPCR
];
1323 ppc_store_lpcr(cpu
, lpcr
);
1326 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1329 struct LPCRSyncState s
= {
1334 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1338 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1340 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1342 /* Copy PATE1:GR into PATE0:HR */
1343 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1344 entry
->dw1
= spapr
->patb_entry
;
1347 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1348 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1349 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1350 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1351 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1354 * Get the fd to access the kernel htab, re-opening it if necessary
1356 static int get_htab_fd(SpaprMachineState
*spapr
)
1358 Error
*local_err
= NULL
;
1360 if (spapr
->htab_fd
>= 0) {
1361 return spapr
->htab_fd
;
1364 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1365 if (spapr
->htab_fd
< 0) {
1366 error_report_err(local_err
);
1369 return spapr
->htab_fd
;
1372 void close_htab_fd(SpaprMachineState
*spapr
)
1374 if (spapr
->htab_fd
>= 0) {
1375 close(spapr
->htab_fd
);
1377 spapr
->htab_fd
= -1;
1380 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1382 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1384 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1387 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1389 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1391 assert(kvm_enabled());
1397 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1400 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1403 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1404 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1408 * HTAB is controlled by KVM. Fetch into temporary buffer
1410 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1411 kvmppc_read_hptes(hptes
, ptex
, n
);
1416 * HTAB is controlled by QEMU. Just point to the internally
1419 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1422 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1423 const ppc_hash_pte64_t
*hptes
,
1426 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1429 g_free((void *)hptes
);
1432 /* Nothing to do for qemu managed HPT */
1435 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1436 uint64_t pte0
, uint64_t pte1
)
1438 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1439 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1442 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1444 if (pte0
& HPTE64_V_VALID
) {
1445 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1447 * When setting valid, we write PTE1 first. This ensures
1448 * proper synchronization with the reading code in
1449 * ppc_hash64_pteg_search()
1452 stq_p(spapr
->htab
+ offset
, pte0
);
1454 stq_p(spapr
->htab
+ offset
, pte0
);
1456 * When clearing it we set PTE0 first. This ensures proper
1457 * synchronization with the reading code in
1458 * ppc_hash64_pteg_search()
1461 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1466 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1469 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
1470 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1473 /* There should always be a hash table when this is called */
1474 error_report("spapr_hpte_set_c called with no hash table !");
1478 /* The HW performs a non-atomic byte update */
1479 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1482 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1485 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 14;
1486 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1489 /* There should always be a hash table when this is called */
1490 error_report("spapr_hpte_set_r called with no hash table !");
1494 /* The HW performs a non-atomic byte update */
1495 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1498 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1502 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1503 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1504 * that's much more than is needed for Linux guests */
1505 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1506 shift
= MAX(shift
, 18); /* Minimum architected size */
1507 shift
= MIN(shift
, 46); /* Maximum architected size */
1511 void spapr_free_hpt(SpaprMachineState
*spapr
)
1513 g_free(spapr
->htab
);
1515 spapr
->htab_shift
= 0;
1516 close_htab_fd(spapr
);
1519 void spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
,
1524 /* Clean up any HPT info from a previous boot */
1525 spapr_free_hpt(spapr
);
1527 rc
= kvmppc_reset_htab(shift
);
1529 /* kernel-side HPT needed, but couldn't allocate one */
1530 error_setg_errno(errp
, errno
,
1531 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1533 /* This is almost certainly fatal, but if the caller really
1534 * wants to carry on with shift == 0, it's welcome to try */
1535 } else if (rc
> 0) {
1536 /* kernel-side HPT allocated */
1539 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1543 spapr
->htab_shift
= shift
;
1546 /* kernel-side HPT not needed, allocate in userspace instead */
1547 size_t size
= 1ULL << shift
;
1550 spapr
->htab
= qemu_memalign(size
, size
);
1552 error_setg_errno(errp
, errno
,
1553 "Could not allocate HPT of order %d", shift
);
1557 memset(spapr
->htab
, 0, size
);
1558 spapr
->htab_shift
= shift
;
1560 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1561 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1564 /* We're setting up a hash table, so that means we're not radix */
1565 spapr
->patb_entry
= 0;
1566 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1569 void spapr_setup_hpt(SpaprMachineState
*spapr
)
1573 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
) {
1574 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1576 uint64_t current_ram_size
;
1578 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1579 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1581 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1583 if (kvm_enabled()) {
1584 hwaddr vrma_limit
= kvmppc_vrma_limit(spapr
->htab_shift
);
1586 /* Check our RMA fits in the possible VRMA */
1587 if (vrma_limit
< spapr
->rma_size
) {
1588 error_report("Unable to create %" HWADDR_PRIu
1589 "MiB RMA (VRMA only allows %" HWADDR_PRIu
"MiB",
1590 spapr
->rma_size
/ MiB
, vrma_limit
/ MiB
);
1596 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1599 (SpaprDrc
*) object_dynamic_cast(child
,
1600 TYPE_SPAPR_DR_CONNECTOR
);
1603 spapr_drc_reset(drc
);
1609 static void spapr_machine_reset(MachineState
*machine
)
1611 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1612 PowerPCCPU
*first_ppc_cpu
;
1617 kvmppc_svm_off(&error_fatal
);
1618 spapr_caps_apply(spapr
);
1620 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1621 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1622 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1623 spapr
->max_compat_pvr
)) {
1625 * If using KVM with radix mode available, VCPUs can be started
1626 * without a HPT because KVM will start them in radix mode.
1627 * Set the GR bit in PATE so that we know there is no HPT.
1629 spapr
->patb_entry
= PATE1_GR
;
1630 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1632 spapr_setup_hpt(spapr
);
1635 qemu_devices_reset();
1637 spapr_ovec_cleanup(spapr
->ov5_cas
);
1638 spapr
->ov5_cas
= spapr_ovec_new();
1640 ppc_set_compat_all(spapr
->max_compat_pvr
, &error_fatal
);
1643 * This is fixing some of the default configuration of the XIVE
1644 * devices. To be called after the reset of the machine devices.
1646 spapr_irq_reset(spapr
, &error_fatal
);
1649 * There is no CAS under qtest. Simulate one to please the code that
1650 * depends on spapr->ov5_cas. This is especially needed to test device
1651 * unplug, so we do that before resetting the DRCs.
1653 if (qtest_enabled()) {
1654 spapr_ovec_cleanup(spapr
->ov5_cas
);
1655 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1658 /* DRC reset may cause a device to be unplugged. This will cause troubles
1659 * if this device is used by another device (eg, a running vhost backend
1660 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1661 * situations, we reset DRCs after all devices have been reset.
1663 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1665 spapr_clear_pending_events(spapr
);
1668 * We place the device tree and RTAS just below either the top of the RMA,
1669 * or just below 2GB, whichever is lower, so that it can be
1670 * processed with 32-bit real mode code if necessary
1672 fdt_addr
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FDT_MAX_SIZE
;
1674 fdt
= spapr_build_fdt(spapr
, true, FDT_MAX_SIZE
);
1678 /* Should only fail if we've built a corrupted tree */
1682 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1683 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1684 g_free(spapr
->fdt_blob
);
1685 spapr
->fdt_size
= fdt_totalsize(fdt
);
1686 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1687 spapr
->fdt_blob
= fdt
;
1689 /* Set up the entry state */
1690 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, 0, fdt_addr
, 0);
1691 first_ppc_cpu
->env
.gpr
[5] = 0;
1693 spapr
->fwnmi_system_reset_addr
= -1;
1694 spapr
->fwnmi_machine_check_addr
= -1;
1695 spapr
->fwnmi_machine_check_interlock
= -1;
1697 /* Signal all vCPUs waiting on this condition */
1698 qemu_cond_broadcast(&spapr
->fwnmi_machine_check_interlock_cond
);
1700 migrate_del_blocker(spapr
->fwnmi_migration_blocker
);
1703 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1705 DeviceState
*dev
= qdev_new("spapr-nvram");
1706 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1709 qdev_prop_set_drive_err(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1713 qdev_realize_and_unref(dev
, &spapr
->vio_bus
->bus
, &error_fatal
);
1715 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1718 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1720 object_initialize_child_with_props(OBJECT(spapr
), "rtc", &spapr
->rtc
,
1721 sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1722 &error_fatal
, NULL
);
1723 qdev_realize(DEVICE(&spapr
->rtc
), NULL
, &error_fatal
);
1724 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1728 /* Returns whether we want to use VGA or not */
1729 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1731 switch (vga_interface_type
) {
1739 return pci_vga_init(pci_bus
) != NULL
;
1742 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1747 static int spapr_pre_load(void *opaque
)
1751 rc
= spapr_caps_pre_load(opaque
);
1759 static int spapr_post_load(void *opaque
, int version_id
)
1761 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1764 err
= spapr_caps_post_migration(spapr
);
1770 * In earlier versions, there was no separate qdev for the PAPR
1771 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1772 * So when migrating from those versions, poke the incoming offset
1773 * value into the RTC device
1775 if (version_id
< 3) {
1776 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1782 if (kvm_enabled() && spapr
->patb_entry
) {
1783 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1784 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1785 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1788 * Update LPCR:HR and UPRT as they may not be set properly in
1791 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1792 LPCR_HR
| LPCR_UPRT
);
1794 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1796 error_report("Process table config unsupported by the host");
1801 err
= spapr_irq_post_load(spapr
, version_id
);
1809 static int spapr_pre_save(void *opaque
)
1813 rc
= spapr_caps_pre_save(opaque
);
1821 static bool version_before_3(void *opaque
, int version_id
)
1823 return version_id
< 3;
1826 static bool spapr_pending_events_needed(void *opaque
)
1828 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1829 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1832 static const VMStateDescription vmstate_spapr_event_entry
= {
1833 .name
= "spapr_event_log_entry",
1835 .minimum_version_id
= 1,
1836 .fields
= (VMStateField
[]) {
1837 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1838 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1839 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1840 NULL
, extended_length
),
1841 VMSTATE_END_OF_LIST()
1845 static const VMStateDescription vmstate_spapr_pending_events
= {
1846 .name
= "spapr_pending_events",
1848 .minimum_version_id
= 1,
1849 .needed
= spapr_pending_events_needed
,
1850 .fields
= (VMStateField
[]) {
1851 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1852 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1853 VMSTATE_END_OF_LIST()
1857 static bool spapr_ov5_cas_needed(void *opaque
)
1859 SpaprMachineState
*spapr
= opaque
;
1860 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1863 /* Prior to the introduction of SpaprOptionVector, we had two option
1864 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1865 * Both of these options encode machine topology into the device-tree
1866 * in such a way that the now-booted OS should still be able to interact
1867 * appropriately with QEMU regardless of what options were actually
1868 * negotiatied on the source side.
1870 * As such, we can avoid migrating the CAS-negotiated options if these
1871 * are the only options available on the current machine/platform.
1872 * Since these are the only options available for pseries-2.7 and
1873 * earlier, this allows us to maintain old->new/new->old migration
1876 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1877 * via default pseries-2.8 machines and explicit command-line parameters.
1878 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1879 * of the actual CAS-negotiated values to continue working properly. For
1880 * example, availability of memory unplug depends on knowing whether
1881 * OV5_HP_EVT was negotiated via CAS.
1883 * Thus, for any cases where the set of available CAS-negotiatable
1884 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1885 * include the CAS-negotiated options in the migration stream, unless
1886 * if they affect boot time behaviour only.
1888 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1889 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1890 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1892 /* We need extra information if we have any bits outside the mask
1894 cas_needed
= !spapr_ovec_subset(spapr
->ov5
, ov5_mask
);
1896 spapr_ovec_cleanup(ov5_mask
);
1901 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1902 .name
= "spapr_option_vector_ov5_cas",
1904 .minimum_version_id
= 1,
1905 .needed
= spapr_ov5_cas_needed
,
1906 .fields
= (VMStateField
[]) {
1907 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
1908 vmstate_spapr_ovec
, SpaprOptionVector
),
1909 VMSTATE_END_OF_LIST()
1913 static bool spapr_patb_entry_needed(void *opaque
)
1915 SpaprMachineState
*spapr
= opaque
;
1917 return !!spapr
->patb_entry
;
1920 static const VMStateDescription vmstate_spapr_patb_entry
= {
1921 .name
= "spapr_patb_entry",
1923 .minimum_version_id
= 1,
1924 .needed
= spapr_patb_entry_needed
,
1925 .fields
= (VMStateField
[]) {
1926 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
1927 VMSTATE_END_OF_LIST()
1931 static bool spapr_irq_map_needed(void *opaque
)
1933 SpaprMachineState
*spapr
= opaque
;
1935 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1938 static const VMStateDescription vmstate_spapr_irq_map
= {
1939 .name
= "spapr_irq_map",
1941 .minimum_version_id
= 1,
1942 .needed
= spapr_irq_map_needed
,
1943 .fields
= (VMStateField
[]) {
1944 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
1945 VMSTATE_END_OF_LIST()
1949 static bool spapr_dtb_needed(void *opaque
)
1951 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
1953 return smc
->update_dt_enabled
;
1956 static int spapr_dtb_pre_load(void *opaque
)
1958 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1960 g_free(spapr
->fdt_blob
);
1961 spapr
->fdt_blob
= NULL
;
1962 spapr
->fdt_size
= 0;
1967 static const VMStateDescription vmstate_spapr_dtb
= {
1968 .name
= "spapr_dtb",
1970 .minimum_version_id
= 1,
1971 .needed
= spapr_dtb_needed
,
1972 .pre_load
= spapr_dtb_pre_load
,
1973 .fields
= (VMStateField
[]) {
1974 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
1975 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
1976 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
1978 VMSTATE_END_OF_LIST()
1982 static bool spapr_fwnmi_needed(void *opaque
)
1984 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1986 return spapr
->fwnmi_machine_check_addr
!= -1;
1989 static int spapr_fwnmi_pre_save(void *opaque
)
1991 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1994 * Check if machine check handling is in progress and print a
1997 if (spapr
->fwnmi_machine_check_interlock
!= -1) {
1998 warn_report("A machine check is being handled during migration. The"
1999 "handler may run and log hardware error on the destination");
2005 static const VMStateDescription vmstate_spapr_fwnmi
= {
2006 .name
= "spapr_fwnmi",
2008 .minimum_version_id
= 1,
2009 .needed
= spapr_fwnmi_needed
,
2010 .pre_save
= spapr_fwnmi_pre_save
,
2011 .fields
= (VMStateField
[]) {
2012 VMSTATE_UINT64(fwnmi_system_reset_addr
, SpaprMachineState
),
2013 VMSTATE_UINT64(fwnmi_machine_check_addr
, SpaprMachineState
),
2014 VMSTATE_INT32(fwnmi_machine_check_interlock
, SpaprMachineState
),
2015 VMSTATE_END_OF_LIST()
2019 static const VMStateDescription vmstate_spapr
= {
2022 .minimum_version_id
= 1,
2023 .pre_load
= spapr_pre_load
,
2024 .post_load
= spapr_post_load
,
2025 .pre_save
= spapr_pre_save
,
2026 .fields
= (VMStateField
[]) {
2027 /* used to be @next_irq */
2028 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2031 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
2033 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
2034 VMSTATE_END_OF_LIST()
2036 .subsections
= (const VMStateDescription
*[]) {
2037 &vmstate_spapr_ov5_cas
,
2038 &vmstate_spapr_patb_entry
,
2039 &vmstate_spapr_pending_events
,
2040 &vmstate_spapr_cap_htm
,
2041 &vmstate_spapr_cap_vsx
,
2042 &vmstate_spapr_cap_dfp
,
2043 &vmstate_spapr_cap_cfpc
,
2044 &vmstate_spapr_cap_sbbc
,
2045 &vmstate_spapr_cap_ibs
,
2046 &vmstate_spapr_cap_hpt_maxpagesize
,
2047 &vmstate_spapr_irq_map
,
2048 &vmstate_spapr_cap_nested_kvm_hv
,
2050 &vmstate_spapr_cap_large_decr
,
2051 &vmstate_spapr_cap_ccf_assist
,
2052 &vmstate_spapr_cap_fwnmi
,
2053 &vmstate_spapr_fwnmi
,
2058 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2060 SpaprMachineState
*spapr
= opaque
;
2062 /* "Iteration" header */
2063 if (!spapr
->htab_shift
) {
2064 qemu_put_be32(f
, -1);
2066 qemu_put_be32(f
, spapr
->htab_shift
);
2070 spapr
->htab_save_index
= 0;
2071 spapr
->htab_first_pass
= true;
2073 if (spapr
->htab_shift
) {
2074 assert(kvm_enabled());
2082 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2083 int chunkstart
, int n_valid
, int n_invalid
)
2085 qemu_put_be32(f
, chunkstart
);
2086 qemu_put_be16(f
, n_valid
);
2087 qemu_put_be16(f
, n_invalid
);
2088 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2089 HASH_PTE_SIZE_64
* n_valid
);
2092 static void htab_save_end_marker(QEMUFile
*f
)
2094 qemu_put_be32(f
, 0);
2095 qemu_put_be16(f
, 0);
2096 qemu_put_be16(f
, 0);
2099 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2102 bool has_timeout
= max_ns
!= -1;
2103 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2104 int index
= spapr
->htab_save_index
;
2105 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2107 assert(spapr
->htab_first_pass
);
2112 /* Consume invalid HPTEs */
2113 while ((index
< htabslots
)
2114 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2115 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2119 /* Consume valid HPTEs */
2121 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2122 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2123 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2127 if (index
> chunkstart
) {
2128 int n_valid
= index
- chunkstart
;
2130 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2133 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2137 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2139 if (index
>= htabslots
) {
2140 assert(index
== htabslots
);
2142 spapr
->htab_first_pass
= false;
2144 spapr
->htab_save_index
= index
;
2147 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2150 bool final
= max_ns
< 0;
2151 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2152 int examined
= 0, sent
= 0;
2153 int index
= spapr
->htab_save_index
;
2154 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2156 assert(!spapr
->htab_first_pass
);
2159 int chunkstart
, invalidstart
;
2161 /* Consume non-dirty HPTEs */
2162 while ((index
< htabslots
)
2163 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2169 /* Consume valid dirty HPTEs */
2170 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2171 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2172 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2173 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2178 invalidstart
= index
;
2179 /* Consume invalid dirty HPTEs */
2180 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2181 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2182 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2183 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2188 if (index
> chunkstart
) {
2189 int n_valid
= invalidstart
- chunkstart
;
2190 int n_invalid
= index
- invalidstart
;
2192 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2193 sent
+= index
- chunkstart
;
2195 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2200 if (examined
>= htabslots
) {
2204 if (index
>= htabslots
) {
2205 assert(index
== htabslots
);
2208 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2210 if (index
>= htabslots
) {
2211 assert(index
== htabslots
);
2215 spapr
->htab_save_index
= index
;
2217 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2220 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2221 #define MAX_KVM_BUF_SIZE 2048
2223 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2225 SpaprMachineState
*spapr
= opaque
;
2229 /* Iteration header */
2230 if (!spapr
->htab_shift
) {
2231 qemu_put_be32(f
, -1);
2234 qemu_put_be32(f
, 0);
2238 assert(kvm_enabled());
2240 fd
= get_htab_fd(spapr
);
2245 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2249 } else if (spapr
->htab_first_pass
) {
2250 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2252 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2255 htab_save_end_marker(f
);
2260 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2262 SpaprMachineState
*spapr
= opaque
;
2265 /* Iteration header */
2266 if (!spapr
->htab_shift
) {
2267 qemu_put_be32(f
, -1);
2270 qemu_put_be32(f
, 0);
2276 assert(kvm_enabled());
2278 fd
= get_htab_fd(spapr
);
2283 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2288 if (spapr
->htab_first_pass
) {
2289 htab_save_first_pass(f
, spapr
, -1);
2291 htab_save_later_pass(f
, spapr
, -1);
2295 htab_save_end_marker(f
);
2300 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2302 SpaprMachineState
*spapr
= opaque
;
2303 uint32_t section_hdr
;
2305 Error
*local_err
= NULL
;
2307 if (version_id
< 1 || version_id
> 1) {
2308 error_report("htab_load() bad version");
2312 section_hdr
= qemu_get_be32(f
);
2314 if (section_hdr
== -1) {
2315 spapr_free_hpt(spapr
);
2320 /* First section gives the htab size */
2321 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2323 error_report_err(local_err
);
2330 assert(kvm_enabled());
2332 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2334 error_report_err(local_err
);
2341 uint16_t n_valid
, n_invalid
;
2343 index
= qemu_get_be32(f
);
2344 n_valid
= qemu_get_be16(f
);
2345 n_invalid
= qemu_get_be16(f
);
2347 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2352 if ((index
+ n_valid
+ n_invalid
) >
2353 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2354 /* Bad index in stream */
2356 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2357 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2363 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2364 HASH_PTE_SIZE_64
* n_valid
);
2367 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2368 HASH_PTE_SIZE_64
* n_invalid
);
2375 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2390 static void htab_save_cleanup(void *opaque
)
2392 SpaprMachineState
*spapr
= opaque
;
2394 close_htab_fd(spapr
);
2397 static SaveVMHandlers savevm_htab_handlers
= {
2398 .save_setup
= htab_save_setup
,
2399 .save_live_iterate
= htab_save_iterate
,
2400 .save_live_complete_precopy
= htab_save_complete
,
2401 .save_cleanup
= htab_save_cleanup
,
2402 .load_state
= htab_load
,
2405 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2408 MachineState
*machine
= MACHINE(opaque
);
2409 machine
->boot_order
= g_strdup(boot_device
);
2412 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2414 MachineState
*machine
= MACHINE(spapr
);
2415 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2416 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2419 for (i
= 0; i
< nr_lmbs
; i
++) {
2422 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2423 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2429 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2430 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2431 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2433 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2437 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2438 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2439 " is not aligned to %" PRIu64
" MiB",
2441 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2445 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2446 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2447 " is not aligned to %" PRIu64
" MiB",
2449 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2453 for (i
= 0; i
< machine
->numa_state
->num_nodes
; i
++) {
2454 if (machine
->numa_state
->nodes
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2456 "Node %d memory size 0x%" PRIx64
2457 " is not aligned to %" PRIu64
" MiB",
2458 i
, machine
->numa_state
->nodes
[i
].node_mem
,
2459 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2465 /* find cpu slot in machine->possible_cpus by core_id */
2466 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2468 int index
= id
/ ms
->smp
.threads
;
2470 if (index
>= ms
->possible_cpus
->len
) {
2476 return &ms
->possible_cpus
->cpus
[index
];
2479 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2481 MachineState
*ms
= MACHINE(spapr
);
2482 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2483 Error
*local_err
= NULL
;
2484 bool vsmt_user
= !!spapr
->vsmt
;
2485 int kvm_smt
= kvmppc_smt_threads();
2487 unsigned int smp_threads
= ms
->smp
.threads
;
2489 if (!kvm_enabled() && (smp_threads
> 1)) {
2490 error_setg(errp
, "TCG cannot support more than 1 thread/core "
2491 "on a pseries machine");
2494 if (!is_power_of_2(smp_threads
)) {
2495 error_setg(errp
, "Cannot support %d threads/core on a pseries "
2496 "machine because it must be a power of 2", smp_threads
);
2500 /* Detemine the VSMT mode to use: */
2502 if (spapr
->vsmt
< smp_threads
) {
2503 error_setg(errp
, "Cannot support VSMT mode %d"
2504 " because it must be >= threads/core (%d)",
2505 spapr
->vsmt
, smp_threads
);
2508 /* In this case, spapr->vsmt has been set by the command line */
2509 } else if (!smc
->smp_threads_vsmt
) {
2511 * Default VSMT value is tricky, because we need it to be as
2512 * consistent as possible (for migration), but this requires
2513 * changing it for at least some existing cases. We pick 8 as
2514 * the value that we'd get with KVM on POWER8, the
2515 * overwhelmingly common case in production systems.
2517 spapr
->vsmt
= MAX(8, smp_threads
);
2519 spapr
->vsmt
= smp_threads
;
2522 /* KVM: If necessary, set the SMT mode: */
2523 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2524 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2526 /* Looks like KVM isn't able to change VSMT mode */
2527 error_setg(&local_err
,
2528 "Failed to set KVM's VSMT mode to %d (errno %d)",
2530 /* We can live with that if the default one is big enough
2531 * for the number of threads, and a submultiple of the one
2532 * we want. In this case we'll waste some vcpu ids, but
2533 * behaviour will be correct */
2534 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2535 warn_report_err(local_err
);
2538 error_append_hint(&local_err
,
2539 "On PPC, a VM with %d threads/core"
2540 " on a host with %d threads/core"
2541 " requires the use of VSMT mode %d.\n",
2542 smp_threads
, kvm_smt
, spapr
->vsmt
);
2544 kvmppc_error_append_smt_possible_hint(&local_err
);
2545 error_propagate(errp
, local_err
);
2549 /* else TCG: nothing to do currently */
2552 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2554 MachineState
*machine
= MACHINE(spapr
);
2555 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2556 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2557 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2558 const CPUArchIdList
*possible_cpus
;
2559 unsigned int smp_cpus
= machine
->smp
.cpus
;
2560 unsigned int smp_threads
= machine
->smp
.threads
;
2561 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2562 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2565 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2566 if (mc
->has_hotpluggable_cpus
) {
2567 if (smp_cpus
% smp_threads
) {
2568 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2569 smp_cpus
, smp_threads
);
2572 if (max_cpus
% smp_threads
) {
2573 error_report("max_cpus (%u) must be multiple of threads (%u)",
2574 max_cpus
, smp_threads
);
2578 if (max_cpus
!= smp_cpus
) {
2579 error_report("This machine version does not support CPU hotplug");
2582 boot_cores_nr
= possible_cpus
->len
;
2585 if (smc
->pre_2_10_has_unused_icps
) {
2588 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2589 /* Dummy entries get deregistered when real ICPState objects
2590 * are registered during CPU core hotplug.
2592 pre_2_10_vmstate_register_dummy_icp(i
);
2596 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2597 int core_id
= i
* smp_threads
;
2599 if (mc
->has_hotpluggable_cpus
) {
2600 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2601 spapr_vcpu_id(spapr
, core_id
));
2604 if (i
< boot_cores_nr
) {
2605 Object
*core
= object_new(type
);
2606 int nr_threads
= smp_threads
;
2608 /* Handle the partially filled core for older machine types */
2609 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2610 nr_threads
= smp_cpus
- i
* smp_threads
;
2613 object_property_set_int(core
, "nr-threads", nr_threads
,
2615 object_property_set_int(core
, CPU_CORE_PROP_CORE_ID
, core_id
,
2617 qdev_realize(DEVICE(core
), NULL
, &error_fatal
);
2624 static PCIHostState
*spapr_create_default_phb(void)
2628 dev
= qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE
);
2629 qdev_prop_set_uint32(dev
, "index", 0);
2630 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
2632 return PCI_HOST_BRIDGE(dev
);
2635 static hwaddr
spapr_rma_size(SpaprMachineState
*spapr
, Error
**errp
)
2637 MachineState
*machine
= MACHINE(spapr
);
2638 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2639 hwaddr rma_size
= machine
->ram_size
;
2640 hwaddr node0_size
= spapr_node0_size(machine
);
2642 /* RMA has to fit in the first NUMA node */
2643 rma_size
= MIN(rma_size
, node0_size
);
2646 * VRMA access is via a special 1TiB SLB mapping, so the RMA can
2649 rma_size
= MIN(rma_size
, 1 * TiB
);
2652 * Clamp the RMA size based on machine type. This is for
2653 * migration compatibility with older qemu versions, which limited
2654 * the RMA size for complicated and mostly bad reasons.
2656 if (smc
->rma_limit
) {
2657 rma_size
= MIN(rma_size
, smc
->rma_limit
);
2660 if (rma_size
< MIN_RMA_SLOF
) {
2662 "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2663 "ldMiB guest RMA (Real Mode Area memory)",
2664 MIN_RMA_SLOF
/ MiB
);
2671 /* pSeries LPAR / sPAPR hardware init */
2672 static void spapr_machine_init(MachineState
*machine
)
2674 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2675 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2676 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2677 const char *kernel_filename
= machine
->kernel_filename
;
2678 const char *initrd_filename
= machine
->initrd_filename
;
2681 MemoryRegion
*sysmem
= get_system_memory();
2682 long load_limit
, fw_size
;
2684 Error
*resize_hpt_err
= NULL
;
2686 msi_nonbroken
= true;
2688 QLIST_INIT(&spapr
->phbs
);
2689 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2691 /* Determine capabilities to run with */
2692 spapr_caps_init(spapr
);
2694 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2695 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2697 * If the user explicitly requested a mode we should either
2698 * supply it, or fail completely (which we do below). But if
2699 * it's not set explicitly, we reset our mode to something
2702 if (resize_hpt_err
) {
2703 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2704 error_free(resize_hpt_err
);
2705 resize_hpt_err
= NULL
;
2707 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2711 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2713 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2715 * User requested HPT resize, but this host can't supply it. Bail out
2717 error_report_err(resize_hpt_err
);
2720 error_free(resize_hpt_err
);
2722 spapr
->rma_size
= spapr_rma_size(spapr
, &error_fatal
);
2724 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2725 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2728 * VSMT must be set in order to be able to compute VCPU ids, ie to
2729 * call spapr_max_server_number() or spapr_vcpu_id().
2731 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2733 /* Set up Interrupt Controller before we create the VCPUs */
2734 spapr_irq_init(spapr
, &error_fatal
);
2736 /* Set up containers for ibm,client-architecture-support negotiated options
2738 spapr
->ov5
= spapr_ovec_new();
2739 spapr
->ov5_cas
= spapr_ovec_new();
2741 if (smc
->dr_lmb_enabled
) {
2742 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2743 spapr_validate_node_memory(machine
, &error_fatal
);
2746 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2748 /* advertise support for dedicated HP event source to guests */
2749 if (spapr
->use_hotplug_event_source
) {
2750 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2753 /* advertise support for HPT resizing */
2754 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2755 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2758 /* advertise support for ibm,dyamic-memory-v2 */
2759 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2761 /* advertise XIVE on POWER9 machines */
2762 if (spapr
->irq
->xive
) {
2763 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2767 spapr_init_cpus(spapr
);
2770 * check we don't have a memory-less/cpu-less NUMA node
2771 * Firmware relies on the existing memory/cpu topology to provide the
2772 * NUMA topology to the kernel.
2773 * And the linux kernel needs to know the NUMA topology at start
2774 * to be able to hotplug CPUs later.
2776 if (machine
->numa_state
->num_nodes
) {
2777 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
2778 /* check for memory-less node */
2779 if (machine
->numa_state
->nodes
[i
].node_mem
== 0) {
2782 /* check for cpu-less node */
2784 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2785 if (cpu
->node_id
== i
) {
2790 /* memory-less and cpu-less node */
2793 "Memory-less/cpu-less nodes are not supported (node %d)",
2803 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2804 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2805 * called from vPHB reset handler so we initialize the counter here.
2806 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2807 * must be equally distant from any other node.
2808 * The final value of spapr->gpu_numa_id is going to be written to
2809 * max-associativity-domains in spapr_build_fdt().
2811 spapr
->gpu_numa_id
= MAX(1, machine
->numa_state
->num_nodes
);
2813 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2814 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2815 spapr
->max_compat_pvr
)) {
2816 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_300
);
2817 /* KVM and TCG always allow GTSE with radix... */
2818 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2820 /* ... but not with hash (currently). */
2822 if (kvm_enabled()) {
2823 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2824 kvmppc_enable_logical_ci_hcalls();
2825 kvmppc_enable_set_mode_hcall();
2827 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2828 kvmppc_enable_clear_ref_mod_hcalls();
2830 /* Enable H_PAGE_INIT */
2831 kvmppc_enable_h_page_init();
2835 memory_region_add_subregion(sysmem
, 0, machine
->ram
);
2837 /* always allocate the device memory information */
2838 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2840 /* initialize hotplug memory address space */
2841 if (machine
->ram_size
< machine
->maxram_size
) {
2842 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2844 * Limit the number of hotpluggable memory slots to half the number
2845 * slots that KVM supports, leaving the other half for PCI and other
2846 * devices. However ensure that number of slots doesn't drop below 32.
2848 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2849 SPAPR_MAX_RAM_SLOTS
;
2851 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2852 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2854 if (machine
->ram_slots
> max_memslots
) {
2855 error_report("Specified number of memory slots %"
2856 PRIu64
" exceeds max supported %d",
2857 machine
->ram_slots
, max_memslots
);
2861 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2862 SPAPR_DEVICE_MEM_ALIGN
);
2863 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2864 "device-memory", device_mem_size
);
2865 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2866 &machine
->device_memory
->mr
);
2869 if (smc
->dr_lmb_enabled
) {
2870 spapr_create_lmb_dr_connectors(spapr
);
2873 if (spapr_get_cap(spapr
, SPAPR_CAP_FWNMI
) == SPAPR_CAP_ON
) {
2874 /* Create the error string for live migration blocker */
2875 error_setg(&spapr
->fwnmi_migration_blocker
,
2876 "A machine check is being handled during migration. The handler"
2877 "may run and log hardware error on the destination");
2880 if (mc
->nvdimm_supported
) {
2881 spapr_create_nvdimm_dr_connectors(spapr
);
2884 /* Set up RTAS event infrastructure */
2885 spapr_events_init(spapr
);
2887 /* Set up the RTC RTAS interfaces */
2888 spapr_rtc_create(spapr
);
2890 /* Set up VIO bus */
2891 spapr
->vio_bus
= spapr_vio_bus_init();
2893 for (i
= 0; i
< serial_max_hds(); i
++) {
2895 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2899 /* We always have at least the nvram device on VIO */
2900 spapr_create_nvram(spapr
);
2903 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2904 * connectors (described in root DT node's "ibm,drc-types" property)
2905 * are pre-initialized here. additional child connectors (such as
2906 * connectors for a PHBs PCI slots) are added as needed during their
2907 * parent's realization.
2909 if (smc
->dr_phb_enabled
) {
2910 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2911 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2916 spapr_pci_rtas_init();
2918 phb
= spapr_create_default_phb();
2920 for (i
= 0; i
< nb_nics
; i
++) {
2921 NICInfo
*nd
= &nd_table
[i
];
2924 nd
->model
= g_strdup("spapr-vlan");
2927 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2928 g_str_equal(nd
->model
, "ibmveth")) {
2929 spapr_vlan_create(spapr
->vio_bus
, nd
);
2931 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2935 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2936 spapr_vscsi_create(spapr
->vio_bus
);
2940 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2941 spapr
->has_graphics
= true;
2942 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2946 if (smc
->use_ohci_by_default
) {
2947 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2949 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2952 if (spapr
->has_graphics
) {
2953 USBBus
*usb_bus
= usb_bus_find(-1);
2955 usb_create_simple(usb_bus
, "usb-kbd");
2956 usb_create_simple(usb_bus
, "usb-mouse");
2960 if (kernel_filename
) {
2961 uint64_t lowaddr
= 0;
2963 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2964 translate_kernel_address
, spapr
,
2965 NULL
, &lowaddr
, NULL
, NULL
, 1,
2966 PPC_ELF_MACHINE
, 0, 0);
2967 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2968 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2969 translate_kernel_address
, spapr
, NULL
,
2970 &lowaddr
, NULL
, NULL
, 0,
2973 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2975 if (spapr
->kernel_size
< 0) {
2976 error_report("error loading %s: %s", kernel_filename
,
2977 load_elf_strerror(spapr
->kernel_size
));
2982 if (initrd_filename
) {
2983 /* Try to locate the initrd in the gap between the kernel
2984 * and the firmware. Add a bit of space just in case
2986 spapr
->initrd_base
= (spapr
->kernel_addr
+ spapr
->kernel_size
2987 + 0x1ffff) & ~0xffff;
2988 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2991 - spapr
->initrd_base
);
2992 if (spapr
->initrd_size
< 0) {
2993 error_report("could not load initial ram disk '%s'",
3000 if (bios_name
== NULL
) {
3001 bios_name
= FW_FILE_NAME
;
3003 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
3005 error_report("Could not find LPAR firmware '%s'", bios_name
);
3008 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
3010 error_report("Could not load LPAR firmware '%s'", filename
);
3015 /* FIXME: Should register things through the MachineState's qdev
3016 * interface, this is a legacy from the sPAPREnvironment structure
3017 * which predated MachineState but had a similar function */
3018 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3019 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY
, 1,
3020 &savevm_htab_handlers
, spapr
);
3022 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
));
3024 qemu_register_boot_set(spapr_boot_set
, spapr
);
3027 * Nothing needs to be done to resume a suspended guest because
3028 * suspending does not change the machine state, so no need for
3029 * a ->wakeup method.
3031 qemu_register_wakeup_support();
3033 if (kvm_enabled()) {
3034 /* to stop and start vmclock */
3035 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3038 kvmppc_spapr_enable_inkernel_multitce();
3041 qemu_cond_init(&spapr
->fwnmi_machine_check_interlock_cond
);
3044 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3050 if (!strcmp(vm_type
, "HV")) {
3054 if (!strcmp(vm_type
, "PR")) {
3058 error_report("Unknown kvm-type specified '%s'", vm_type
);
3063 * Implementation of an interface to adjust firmware path
3064 * for the bootindex property handling.
3066 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3069 #define CAST(type, obj, name) \
3070 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3071 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3072 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3073 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3076 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3077 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3078 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3082 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3083 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3084 * 0x8000 | (target << 8) | (bus << 5) | lun
3085 * (see the "Logical unit addressing format" table in SAM5)
3087 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3088 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3089 (uint64_t)id
<< 48);
3090 } else if (virtio
) {
3092 * We use SRP luns of the form 01000000 | (target << 8) | lun
3093 * in the top 32 bits of the 64-bit LUN
3094 * Note: the quote above is from SLOF and it is wrong,
3095 * the actual binding is:
3096 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3098 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3099 if (d
->lun
>= 256) {
3100 /* Use the LUN "flat space addressing method" */
3103 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3104 (uint64_t)id
<< 32);
3107 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3108 * in the top 32 bits of the 64-bit LUN
3110 unsigned usb_port
= atoi(usb
->port
->path
);
3111 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3112 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3113 (uint64_t)id
<< 32);
3118 * SLOF probes the USB devices, and if it recognizes that the device is a
3119 * storage device, it changes its name to "storage" instead of "usb-host",
3120 * and additionally adds a child node for the SCSI LUN, so the correct
3121 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3123 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3124 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3125 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3126 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3131 /* Replace "pci" with "pci@800000020000000" */
3132 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3136 /* Same logic as virtio above */
3137 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3138 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3141 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3142 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3143 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3144 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3150 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3152 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3154 return g_strdup(spapr
->kvm_type
);
3157 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3159 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3161 g_free(spapr
->kvm_type
);
3162 spapr
->kvm_type
= g_strdup(value
);
3165 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3167 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3169 return spapr
->use_hotplug_event_source
;
3172 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3175 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3177 spapr
->use_hotplug_event_source
= value
;
3180 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3185 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3187 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3189 switch (spapr
->resize_hpt
) {
3190 case SPAPR_RESIZE_HPT_DEFAULT
:
3191 return g_strdup("default");
3192 case SPAPR_RESIZE_HPT_DISABLED
:
3193 return g_strdup("disabled");
3194 case SPAPR_RESIZE_HPT_ENABLED
:
3195 return g_strdup("enabled");
3196 case SPAPR_RESIZE_HPT_REQUIRED
:
3197 return g_strdup("required");
3199 g_assert_not_reached();
3202 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3204 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3206 if (strcmp(value
, "default") == 0) {
3207 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3208 } else if (strcmp(value
, "disabled") == 0) {
3209 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3210 } else if (strcmp(value
, "enabled") == 0) {
3211 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3212 } else if (strcmp(value
, "required") == 0) {
3213 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3215 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3219 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3221 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3223 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3224 return g_strdup("legacy");
3225 } else if (spapr
->irq
== &spapr_irq_xics
) {
3226 return g_strdup("xics");
3227 } else if (spapr
->irq
== &spapr_irq_xive
) {
3228 return g_strdup("xive");
3229 } else if (spapr
->irq
== &spapr_irq_dual
) {
3230 return g_strdup("dual");
3232 g_assert_not_reached();
3235 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3237 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3239 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3240 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3244 /* The legacy IRQ backend can not be set */
3245 if (strcmp(value
, "xics") == 0) {
3246 spapr
->irq
= &spapr_irq_xics
;
3247 } else if (strcmp(value
, "xive") == 0) {
3248 spapr
->irq
= &spapr_irq_xive
;
3249 } else if (strcmp(value
, "dual") == 0) {
3250 spapr
->irq
= &spapr_irq_dual
;
3252 error_setg(errp
, "Bad value for \"ic-mode\" property");
3256 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3258 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3260 return g_strdup(spapr
->host_model
);
3263 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3265 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3267 g_free(spapr
->host_model
);
3268 spapr
->host_model
= g_strdup(value
);
3271 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3273 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3275 return g_strdup(spapr
->host_serial
);
3278 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3280 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3282 g_free(spapr
->host_serial
);
3283 spapr
->host_serial
= g_strdup(value
);
3286 static void spapr_instance_init(Object
*obj
)
3288 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3289 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3291 spapr
->htab_fd
= -1;
3292 spapr
->use_hotplug_event_source
= true;
3293 object_property_add_str(obj
, "kvm-type",
3294 spapr_get_kvm_type
, spapr_set_kvm_type
);
3295 object_property_set_description(obj
, "kvm-type",
3296 "Specifies the KVM virtualization mode (HV, PR)");
3297 object_property_add_bool(obj
, "modern-hotplug-events",
3298 spapr_get_modern_hotplug_events
,
3299 spapr_set_modern_hotplug_events
);
3300 object_property_set_description(obj
, "modern-hotplug-events",
3301 "Use dedicated hotplug event mechanism in"
3302 " place of standard EPOW events when possible"
3303 " (required for memory hot-unplug support)");
3304 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3305 "Maximum permitted CPU compatibility mode");
3307 object_property_add_str(obj
, "resize-hpt",
3308 spapr_get_resize_hpt
, spapr_set_resize_hpt
);
3309 object_property_set_description(obj
, "resize-hpt",
3310 "Resizing of the Hash Page Table (enabled, disabled, required)");
3311 object_property_add_uint32_ptr(obj
, "vsmt",
3312 &spapr
->vsmt
, OBJ_PROP_FLAG_READWRITE
);
3313 object_property_set_description(obj
, "vsmt",
3314 "Virtual SMT: KVM behaves as if this were"
3315 " the host's SMT mode");
3317 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3318 spapr_get_msix_emulation
, NULL
);
3320 object_property_add_uint64_ptr(obj
, "kernel-addr",
3321 &spapr
->kernel_addr
, OBJ_PROP_FLAG_READWRITE
);
3322 object_property_set_description(obj
, "kernel-addr",
3323 stringify(KERNEL_LOAD_ADDR
)
3324 " for -kernel is the default");
3325 spapr
->kernel_addr
= KERNEL_LOAD_ADDR
;
3326 /* The machine class defines the default interrupt controller mode */
3327 spapr
->irq
= smc
->irq
;
3328 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3330 object_property_set_description(obj
, "ic-mode",
3331 "Specifies the interrupt controller mode (xics, xive, dual)");
3333 object_property_add_str(obj
, "host-model",
3334 spapr_get_host_model
, spapr_set_host_model
);
3335 object_property_set_description(obj
, "host-model",
3336 "Host model to advertise in guest device tree");
3337 object_property_add_str(obj
, "host-serial",
3338 spapr_get_host_serial
, spapr_set_host_serial
);
3339 object_property_set_description(obj
, "host-serial",
3340 "Host serial number to advertise in guest device tree");
3343 static void spapr_machine_finalizefn(Object
*obj
)
3345 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3347 g_free(spapr
->kvm_type
);
3350 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3352 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
3353 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3354 CPUPPCState
*env
= &cpu
->env
;
3356 cpu_synchronize_state(cs
);
3357 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
3358 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3359 uint64_t rtas_addr
, addr
;
3361 /* get rtas addr from fdt */
3362 rtas_addr
= spapr_get_rtas_addr();
3364 qemu_system_guest_panicked(NULL
);
3368 addr
= rtas_addr
+ RTAS_ERROR_LOG_MAX
+ cs
->cpu_index
* sizeof(uint64_t)*2;
3369 stq_be_phys(&address_space_memory
, addr
, env
->gpr
[3]);
3370 stq_be_phys(&address_space_memory
, addr
+ sizeof(uint64_t), 0);
3373 ppc_cpu_do_system_reset(cs
);
3374 if (spapr
->fwnmi_system_reset_addr
!= -1) {
3375 env
->nip
= spapr
->fwnmi_system_reset_addr
;
3379 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3384 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3388 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3389 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3394 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3395 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3397 *fdt_start_offset
= spapr_dt_memory_node(fdt
, node
, addr
,
3398 SPAPR_MEMORY_BLOCK_SIZE
);
3402 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3403 bool dedicated_hp_event_source
, Error
**errp
)
3406 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3408 uint64_t addr
= addr_start
;
3409 bool hotplugged
= spapr_drc_hotplugged(dev
);
3410 Error
*local_err
= NULL
;
3412 for (i
= 0; i
< nr_lmbs
; i
++) {
3413 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3414 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3417 spapr_drc_attach(drc
, dev
, &local_err
);
3419 while (addr
> addr_start
) {
3420 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3421 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3422 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3423 spapr_drc_detach(drc
);
3425 error_propagate(errp
, local_err
);
3429 spapr_drc_reset(drc
);
3431 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3433 /* send hotplug notification to the
3434 * guest only in case of hotplugged memory
3437 if (dedicated_hp_event_source
) {
3438 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3439 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3440 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3442 spapr_drc_index(drc
));
3444 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3450 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3453 Error
*local_err
= NULL
;
3454 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3455 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3456 uint64_t size
, addr
, slot
;
3457 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3459 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3461 pc_dimm_plug(dimm
, MACHINE(ms
), &local_err
);
3467 addr
= object_property_get_uint(OBJECT(dimm
),
3468 PC_DIMM_ADDR_PROP
, &local_err
);
3472 spapr_add_lmbs(dev
, addr
, size
,
3473 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3476 slot
= object_property_get_uint(OBJECT(dimm
),
3477 PC_DIMM_SLOT_PROP
, &local_err
);
3481 spapr_add_nvdimm(dev
, slot
, &local_err
);
3491 pc_dimm_unplug(dimm
, MACHINE(ms
));
3493 error_propagate(errp
, local_err
);
3496 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3499 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3500 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3501 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3502 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3503 Error
*local_err
= NULL
;
3508 if (!smc
->dr_lmb_enabled
) {
3509 error_setg(errp
, "Memory hotplug not supported for this machine");
3513 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3515 error_propagate(errp
, local_err
);
3520 spapr_nvdimm_validate(hotplug_dev
, NVDIMM(dev
), size
, &local_err
);
3522 error_propagate(errp
, local_err
);
3525 } else if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3526 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3527 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3531 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3533 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3534 spapr_check_pagesize(spapr
, pagesize
, &local_err
);
3536 error_propagate(errp
, local_err
);
3540 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3543 struct SpaprDimmState
{
3546 QTAILQ_ENTRY(SpaprDimmState
) next
;
3549 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3552 SpaprDimmState
*dimm_state
= NULL
;
3554 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3555 if (dimm_state
->dimm
== dimm
) {
3562 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3566 SpaprDimmState
*ds
= NULL
;
3569 * If this request is for a DIMM whose removal had failed earlier
3570 * (due to guest's refusal to remove the LMBs), we would have this
3571 * dimm already in the pending_dimm_unplugs list. In that
3572 * case don't add again.
3574 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3576 ds
= g_malloc0(sizeof(SpaprDimmState
));
3577 ds
->nr_lmbs
= nr_lmbs
;
3579 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3584 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3585 SpaprDimmState
*dimm_state
)
3587 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3591 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3595 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3597 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3598 uint32_t avail_lmbs
= 0;
3599 uint64_t addr_start
, addr
;
3602 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3606 for (i
= 0; i
< nr_lmbs
; i
++) {
3607 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3608 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3613 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3616 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3619 /* Callback to be called during DRC release. */
3620 void spapr_lmb_release(DeviceState
*dev
)
3622 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3623 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3624 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3626 /* This information will get lost if a migration occurs
3627 * during the unplug process. In this case recover it. */
3629 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3631 /* The DRC being examined by the caller at least must be counted */
3632 g_assert(ds
->nr_lmbs
);
3635 if (--ds
->nr_lmbs
) {
3640 * Now that all the LMBs have been removed by the guest, call the
3641 * unplug handler chain. This can never fail.
3643 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3644 object_unparent(OBJECT(dev
));
3647 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3649 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3650 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3652 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3653 qdev_unrealize(dev
);
3654 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3657 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3658 DeviceState
*dev
, Error
**errp
)
3660 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3661 Error
*local_err
= NULL
;
3662 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3664 uint64_t size
, addr_start
, addr
;
3668 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
3669 error_setg(errp
, "nvdimm device hot unplug is not supported yet.");
3673 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3674 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3676 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3679 error_propagate(errp
, local_err
);
3684 * An existing pending dimm state for this DIMM means that there is an
3685 * unplug operation in progress, waiting for the spapr_lmb_release
3686 * callback to complete the job (BQL can't cover that far). In this case,
3687 * bail out to avoid detaching DRCs that were already released.
3689 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3690 error_setg(errp
, "Memory unplug already in progress for device %s",
3695 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3698 for (i
= 0; i
< nr_lmbs
; i
++) {
3699 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3700 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3703 spapr_drc_detach(drc
);
3704 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3707 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3708 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3709 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3710 nr_lmbs
, spapr_drc_index(drc
));
3713 /* Callback to be called during DRC release. */
3714 void spapr_core_release(DeviceState
*dev
)
3716 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3718 /* Call the unplug handler chain. This can never fail. */
3719 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3720 object_unparent(OBJECT(dev
));
3723 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3725 MachineState
*ms
= MACHINE(hotplug_dev
);
3726 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3727 CPUCore
*cc
= CPU_CORE(dev
);
3728 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3730 if (smc
->pre_2_10_has_unused_icps
) {
3731 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3734 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3735 CPUState
*cs
= CPU(sc
->threads
[i
]);
3737 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3742 core_slot
->cpu
= NULL
;
3743 qdev_unrealize(dev
);
3747 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3750 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3753 CPUCore
*cc
= CPU_CORE(dev
);
3755 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3756 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3761 error_setg(errp
, "Boot CPU core may not be unplugged");
3765 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3766 spapr_vcpu_id(spapr
, cc
->core_id
));
3769 if (!spapr_drc_unplug_requested(drc
)) {
3770 spapr_drc_detach(drc
);
3771 spapr_hotplug_req_remove_by_index(drc
);
3775 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3776 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3778 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3779 CPUState
*cs
= CPU(core
->threads
[0]);
3780 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3781 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3782 int id
= spapr_get_vcpu_id(cpu
);
3786 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3787 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3790 spapr_dt_cpu(cs
, fdt
, offset
, spapr
);
3792 *fdt_start_offset
= offset
;
3796 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3799 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3800 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3801 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3802 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3803 CPUCore
*cc
= CPU_CORE(dev
);
3806 Error
*local_err
= NULL
;
3807 CPUArchId
*core_slot
;
3809 bool hotplugged
= spapr_drc_hotplugged(dev
);
3812 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3814 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3818 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3819 spapr_vcpu_id(spapr
, cc
->core_id
));
3821 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3824 spapr_drc_attach(drc
, dev
, &local_err
);
3826 error_propagate(errp
, local_err
);
3832 * Send hotplug notification interrupt to the guest only
3833 * in case of hotplugged CPUs.
3835 spapr_hotplug_req_add_by_index(drc
);
3837 spapr_drc_reset(drc
);
3841 core_slot
->cpu
= OBJECT(dev
);
3843 if (smc
->pre_2_10_has_unused_icps
) {
3844 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3845 cs
= CPU(core
->threads
[i
]);
3846 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3851 * Set compatibility mode to match the boot CPU, which was either set
3852 * by the machine reset code or by CAS.
3855 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3856 ppc_set_compat(core
->threads
[i
], POWERPC_CPU(first_cpu
)->compat_pvr
,
3859 error_propagate(errp
, local_err
);
3866 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3869 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3870 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3871 CPUCore
*cc
= CPU_CORE(dev
);
3872 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3873 const char *type
= object_get_typename(OBJECT(dev
));
3874 CPUArchId
*core_slot
;
3876 unsigned int smp_threads
= machine
->smp
.threads
;
3878 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3879 error_setg(errp
, "CPU hotplug not supported for this machine");
3883 if (strcmp(base_core_type
, type
)) {
3884 error_setg(errp
, "CPU core type should be %s", base_core_type
);
3888 if (cc
->core_id
% smp_threads
) {
3889 error_setg(errp
, "invalid core id %d", cc
->core_id
);
3894 * In general we should have homogeneous threads-per-core, but old
3895 * (pre hotplug support) machine types allow the last core to have
3896 * reduced threads as a compatibility hack for when we allowed
3897 * total vcpus not a multiple of threads-per-core.
3899 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3900 error_setg(errp
, "invalid nr-threads %d, must be %d", cc
->nr_threads
,
3905 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3907 error_setg(errp
, "core id %d out of range", cc
->core_id
);
3911 if (core_slot
->cpu
) {
3912 error_setg(errp
, "core %d already populated", cc
->core_id
);
3916 numa_cpu_pre_plug(core_slot
, dev
, errp
);
3919 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3920 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3922 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
3925 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
3926 if (intc_phandle
<= 0) {
3930 if (spapr_dt_phb(spapr
, sphb
, intc_phandle
, fdt
, fdt_start_offset
)) {
3931 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
3935 /* generally SLOF creates these, for hotplug it's up to QEMU */
3936 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
3941 static void spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3944 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3945 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3946 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3947 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
3949 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
3950 error_setg(errp
, "PHB hotplug not supported for this machine");
3954 if (sphb
->index
== (uint32_t)-1) {
3955 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
3960 * This will check that sphb->index doesn't exceed the maximum number of
3961 * PHBs for the current machine type.
3963 smc
->phb_placement(spapr
, sphb
->index
,
3964 &sphb
->buid
, &sphb
->io_win_addr
,
3965 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
3966 windows_supported
, sphb
->dma_liobn
,
3967 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
3971 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3974 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3975 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3976 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3978 bool hotplugged
= spapr_drc_hotplugged(dev
);
3979 Error
*local_err
= NULL
;
3981 if (!smc
->dr_phb_enabled
) {
3985 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
3986 /* hotplug hooks should check it's enabled before getting this far */
3989 spapr_drc_attach(drc
, dev
, &local_err
);
3991 error_propagate(errp
, local_err
);
3996 spapr_hotplug_req_add_by_index(drc
);
3998 spapr_drc_reset(drc
);
4002 void spapr_phb_release(DeviceState
*dev
)
4004 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
4006 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
4007 object_unparent(OBJECT(dev
));
4010 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4012 qdev_unrealize(dev
);
4015 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
4016 DeviceState
*dev
, Error
**errp
)
4018 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4021 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4024 if (!spapr_drc_unplug_requested(drc
)) {
4025 spapr_drc_detach(drc
);
4026 spapr_hotplug_req_remove_by_index(drc
);
4030 static void spapr_tpm_proxy_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4033 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4034 SpaprTpmProxy
*tpm_proxy
= SPAPR_TPM_PROXY(dev
);
4036 if (spapr
->tpm_proxy
!= NULL
) {
4037 error_setg(errp
, "Only one TPM proxy can be specified for this machine");
4041 spapr
->tpm_proxy
= tpm_proxy
;
4044 static void spapr_tpm_proxy_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4046 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4048 qdev_unrealize(dev
);
4049 object_unparent(OBJECT(dev
));
4050 spapr
->tpm_proxy
= NULL
;
4053 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4054 DeviceState
*dev
, Error
**errp
)
4056 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4057 spapr_memory_plug(hotplug_dev
, dev
, errp
);
4058 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4059 spapr_core_plug(hotplug_dev
, dev
, errp
);
4060 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4061 spapr_phb_plug(hotplug_dev
, dev
, errp
);
4062 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4063 spapr_tpm_proxy_plug(hotplug_dev
, dev
, errp
);
4067 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4068 DeviceState
*dev
, Error
**errp
)
4070 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4071 spapr_memory_unplug(hotplug_dev
, dev
);
4072 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4073 spapr_core_unplug(hotplug_dev
, dev
);
4074 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4075 spapr_phb_unplug(hotplug_dev
, dev
);
4076 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4077 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4081 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4082 DeviceState
*dev
, Error
**errp
)
4084 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4085 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4086 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4088 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4089 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
4090 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4092 /* NOTE: this means there is a window after guest reset, prior to
4093 * CAS negotiation, where unplug requests will fail due to the
4094 * capability not being detected yet. This is a bit different than
4095 * the case with PCI unplug, where the events will be queued and
4096 * eventually handled by the guest after boot
4098 error_setg(errp
, "Memory hot unplug not supported for this guest");
4100 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4101 if (!mc
->has_hotpluggable_cpus
) {
4102 error_setg(errp
, "CPU hot unplug not supported on this machine");
4105 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4106 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4107 if (!smc
->dr_phb_enabled
) {
4108 error_setg(errp
, "PHB hot unplug not supported on this machine");
4111 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4112 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4113 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4117 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4118 DeviceState
*dev
, Error
**errp
)
4120 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4121 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4122 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4123 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4124 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4125 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4129 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4132 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4133 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4134 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
) ||
4135 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4136 return HOTPLUG_HANDLER(machine
);
4138 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4139 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4140 PCIBus
*root
= pci_device_root_bus(pcidev
);
4141 SpaprPhbState
*phb
=
4142 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4143 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4146 return HOTPLUG_HANDLER(phb
);
4152 static CpuInstanceProperties
4153 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4155 CPUArchId
*core_slot
;
4156 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4158 /* make sure possible_cpu are intialized */
4159 mc
->possible_cpu_arch_ids(machine
);
4160 /* get CPU core slot containing thread that matches cpu_index */
4161 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4163 return core_slot
->props
;
4166 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4168 return idx
/ ms
->smp
.cores
% ms
->numa_state
->num_nodes
;
4171 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4174 unsigned int smp_threads
= machine
->smp
.threads
;
4175 unsigned int smp_cpus
= machine
->smp
.cpus
;
4176 const char *core_type
;
4177 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4178 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4180 if (!mc
->has_hotpluggable_cpus
) {
4181 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4183 if (machine
->possible_cpus
) {
4184 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4185 return machine
->possible_cpus
;
4188 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4190 error_report("Unable to find sPAPR CPU Core definition");
4194 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4195 sizeof(CPUArchId
) * spapr_max_cores
);
4196 machine
->possible_cpus
->len
= spapr_max_cores
;
4197 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4198 int core_id
= i
* smp_threads
;
4200 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4201 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4202 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4203 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4204 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4206 return machine
->possible_cpus
;
4209 static void spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4210 uint64_t *buid
, hwaddr
*pio
,
4211 hwaddr
*mmio32
, hwaddr
*mmio64
,
4212 unsigned n_dma
, uint32_t *liobns
,
4213 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4216 * New-style PHB window placement.
4218 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4219 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4222 * Some guest kernels can't work with MMIO windows above 1<<46
4223 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4225 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4226 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4227 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4228 * 1TiB 64-bit MMIO windows for each PHB.
4230 const uint64_t base_buid
= 0x800000020000000ULL
;
4233 /* Sanity check natural alignments */
4234 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4235 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4236 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4237 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4238 /* Sanity check bounds */
4239 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4240 SPAPR_PCI_MEM32_WIN_SIZE
);
4241 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4242 SPAPR_PCI_MEM64_WIN_SIZE
);
4244 if (index
>= SPAPR_MAX_PHBS
) {
4245 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4246 SPAPR_MAX_PHBS
- 1);
4250 *buid
= base_buid
+ index
;
4251 for (i
= 0; i
< n_dma
; ++i
) {
4252 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4255 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4256 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4257 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4259 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4260 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4263 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4265 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4267 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4270 static void spapr_ics_resend(XICSFabric
*dev
)
4272 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4274 ics_resend(spapr
->ics
);
4277 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4279 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4281 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4284 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4287 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4289 spapr_irq_print_info(spapr
, mon
);
4290 monitor_printf(mon
, "irqchip: %s\n",
4291 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4295 * This is a XIVE only operation
4297 static int spapr_match_nvt(XiveFabric
*xfb
, uint8_t format
,
4298 uint8_t nvt_blk
, uint32_t nvt_idx
,
4299 bool cam_ignore
, uint8_t priority
,
4300 uint32_t logic_serv
, XiveTCTXMatch
*match
)
4302 SpaprMachineState
*spapr
= SPAPR_MACHINE(xfb
);
4303 XivePresenter
*xptr
= XIVE_PRESENTER(spapr
->active_intc
);
4304 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
4307 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
4308 priority
, logic_serv
, match
);
4314 * When we implement the save and restore of the thread interrupt
4315 * contexts in the enter/exit CPU handlers of the machine and the
4316 * escalations in QEMU, we should be able to handle non dispatched
4319 * Until this is done, the sPAPR machine should find at least one
4320 * matching context always.
4323 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is not dispatched\n",
4330 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4332 return cpu
->vcpu_id
;
4335 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4337 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4338 MachineState
*ms
= MACHINE(spapr
);
4341 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4343 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4344 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4345 error_append_hint(errp
, "Adjust the number of cpus to %d "
4346 "or try to raise the number of threads per core\n",
4347 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4351 cpu
->vcpu_id
= vcpu_id
;
4354 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4359 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4361 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4369 static void spapr_cpu_exec_enter(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4371 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4373 /* These are only called by TCG, KVM maintains dispatch state */
4375 spapr_cpu
->prod
= false;
4376 if (spapr_cpu
->vpa_addr
) {
4377 CPUState
*cs
= CPU(cpu
);
4380 dispatch
= ldl_be_phys(cs
->as
,
4381 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4383 if ((dispatch
& 1) != 0) {
4384 qemu_log_mask(LOG_GUEST_ERROR
,
4385 "VPA: incorrect dispatch counter value for "
4386 "dispatched partition %u, correcting.\n", dispatch
);
4390 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4394 static void spapr_cpu_exec_exit(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4396 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4398 if (spapr_cpu
->vpa_addr
) {
4399 CPUState
*cs
= CPU(cpu
);
4402 dispatch
= ldl_be_phys(cs
->as
,
4403 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4405 if ((dispatch
& 1) != 1) {
4406 qemu_log_mask(LOG_GUEST_ERROR
,
4407 "VPA: incorrect dispatch counter value for "
4408 "preempted partition %u, correcting.\n", dispatch
);
4412 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4416 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4418 MachineClass
*mc
= MACHINE_CLASS(oc
);
4419 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4420 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4421 NMIClass
*nc
= NMI_CLASS(oc
);
4422 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4423 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4424 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4425 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4426 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
4428 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4429 mc
->ignore_boot_device_suffixes
= true;
4432 * We set up the default / latest behaviour here. The class_init
4433 * functions for the specific versioned machine types can override
4434 * these details for backwards compatibility
4436 mc
->init
= spapr_machine_init
;
4437 mc
->reset
= spapr_machine_reset
;
4438 mc
->block_default_type
= IF_SCSI
;
4439 mc
->max_cpus
= 1024;
4440 mc
->no_parallel
= 1;
4441 mc
->default_boot_order
= "";
4442 mc
->default_ram_size
= 512 * MiB
;
4443 mc
->default_ram_id
= "ppc_spapr.ram";
4444 mc
->default_display
= "std";
4445 mc
->kvm_type
= spapr_kvm_type
;
4446 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4447 mc
->pci_allow_0_address
= true;
4448 assert(!mc
->get_hotplug_handler
);
4449 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4450 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4451 hc
->plug
= spapr_machine_device_plug
;
4452 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4453 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4454 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4455 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4456 hc
->unplug
= spapr_machine_device_unplug
;
4458 smc
->dr_lmb_enabled
= true;
4459 smc
->update_dt_enabled
= true;
4460 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4461 mc
->has_hotpluggable_cpus
= true;
4462 mc
->nvdimm_supported
= true;
4463 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4464 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4465 nc
->nmi_monitor_handler
= spapr_nmi
;
4466 smc
->phb_placement
= spapr_phb_placement
;
4467 vhc
->hypercall
= emulate_spapr_hypercall
;
4468 vhc
->hpt_mask
= spapr_hpt_mask
;
4469 vhc
->map_hptes
= spapr_map_hptes
;
4470 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4471 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4472 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4473 vhc
->get_pate
= spapr_get_pate
;
4474 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4475 vhc
->cpu_exec_enter
= spapr_cpu_exec_enter
;
4476 vhc
->cpu_exec_exit
= spapr_cpu_exec_exit
;
4477 xic
->ics_get
= spapr_ics_get
;
4478 xic
->ics_resend
= spapr_ics_resend
;
4479 xic
->icp_get
= spapr_icp_get
;
4480 ispc
->print_info
= spapr_pic_print_info
;
4481 /* Force NUMA node memory size to be a multiple of
4482 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4483 * in which LMBs are represented and hot-added
4485 mc
->numa_mem_align_shift
= 28;
4486 mc
->auto_enable_numa
= true;
4488 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4489 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4490 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4491 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4492 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4493 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4494 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4495 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4496 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4497 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_ON
;
4498 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_ON
;
4499 spapr_caps_add_properties(smc
);
4500 smc
->irq
= &spapr_irq_dual
;
4501 smc
->dr_phb_enabled
= true;
4502 smc
->linux_pci_probe
= true;
4503 smc
->smp_threads_vsmt
= true;
4504 smc
->nr_xirqs
= SPAPR_NR_XIRQS
;
4505 xfc
->match_nvt
= spapr_match_nvt
;
4508 static const TypeInfo spapr_machine_info
= {
4509 .name
= TYPE_SPAPR_MACHINE
,
4510 .parent
= TYPE_MACHINE
,
4512 .instance_size
= sizeof(SpaprMachineState
),
4513 .instance_init
= spapr_instance_init
,
4514 .instance_finalize
= spapr_machine_finalizefn
,
4515 .class_size
= sizeof(SpaprMachineClass
),
4516 .class_init
= spapr_machine_class_init
,
4517 .interfaces
= (InterfaceInfo
[]) {
4518 { TYPE_FW_PATH_PROVIDER
},
4520 { TYPE_HOTPLUG_HANDLER
},
4521 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4522 { TYPE_XICS_FABRIC
},
4523 { TYPE_INTERRUPT_STATS_PROVIDER
},
4524 { TYPE_XIVE_FABRIC
},
4529 static void spapr_machine_latest_class_options(MachineClass
*mc
)
4531 mc
->alias
= "pseries";
4532 mc
->is_default
= true;
4535 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4536 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4539 MachineClass *mc = MACHINE_CLASS(oc); \
4540 spapr_machine_##suffix##_class_options(mc); \
4542 spapr_machine_latest_class_options(mc); \
4545 static const TypeInfo spapr_machine_##suffix##_info = { \
4546 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4547 .parent = TYPE_SPAPR_MACHINE, \
4548 .class_init = spapr_machine_##suffix##_class_init, \
4550 static void spapr_machine_register_##suffix(void) \
4552 type_register(&spapr_machine_##suffix##_info); \
4554 type_init(spapr_machine_register_##suffix)
4559 static void spapr_machine_5_2_class_options(MachineClass
*mc
)
4561 /* Defaults for the latest behaviour inherited from the base class */
4564 DEFINE_SPAPR_MACHINE(5_2
, "5.2", true);
4569 static void spapr_machine_5_1_class_options(MachineClass
*mc
)
4571 spapr_machine_5_2_class_options(mc
);
4572 compat_props_add(mc
->compat_props
, hw_compat_5_1
, hw_compat_5_1_len
);
4575 DEFINE_SPAPR_MACHINE(5_1
, "5.1", false);
4580 static void spapr_machine_5_0_class_options(MachineClass
*mc
)
4582 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4583 static GlobalProperty compat
[] = {
4584 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-5.1-associativity", "on" },
4587 spapr_machine_5_1_class_options(mc
);
4588 compat_props_add(mc
->compat_props
, hw_compat_5_0
, hw_compat_5_0_len
);
4589 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4590 mc
->numa_mem_supported
= true;
4591 smc
->pre_5_1_assoc_refpoints
= true;
4594 DEFINE_SPAPR_MACHINE(5_0
, "5.0", false);
4599 static void spapr_machine_4_2_class_options(MachineClass
*mc
)
4601 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4603 spapr_machine_5_0_class_options(mc
);
4604 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
4605 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4606 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI
] = SPAPR_CAP_OFF
;
4607 smc
->rma_limit
= 16 * GiB
;
4608 mc
->nvdimm_supported
= false;
4611 DEFINE_SPAPR_MACHINE(4_2
, "4.2", false);
4616 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4618 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4619 static GlobalProperty compat
[] = {
4620 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4621 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pgsz", "0x11000" },
4624 spapr_machine_4_2_class_options(mc
);
4625 smc
->linux_pci_probe
= false;
4626 smc
->smp_threads_vsmt
= false;
4627 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
4628 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4631 DEFINE_SPAPR_MACHINE(4_1
, "4.1", false);
4636 static void phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4637 uint64_t *buid
, hwaddr
*pio
,
4638 hwaddr
*mmio32
, hwaddr
*mmio64
,
4639 unsigned n_dma
, uint32_t *liobns
,
4640 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4642 spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
, liobns
,
4643 nv2gpa
, nv2atsd
, errp
);
4648 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4650 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4652 spapr_machine_4_1_class_options(mc
);
4653 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4654 smc
->phb_placement
= phb_placement_4_0
;
4655 smc
->irq
= &spapr_irq_xics
;
4656 smc
->pre_4_1_migration
= true;
4659 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4664 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4666 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4668 spapr_machine_4_0_class_options(mc
);
4669 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4671 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4672 smc
->update_dt_enabled
= false;
4673 smc
->dr_phb_enabled
= false;
4674 smc
->broken_host_serial_model
= true;
4675 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4676 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4677 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4678 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4681 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4687 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4689 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4691 spapr_machine_3_1_class_options(mc
);
4692 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4694 smc
->legacy_irq_allocation
= true;
4695 smc
->nr_xirqs
= 0x400;
4696 smc
->irq
= &spapr_irq_xics_legacy
;
4699 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4704 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4706 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4707 static GlobalProperty compat
[] = {
4708 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4709 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4712 spapr_machine_3_0_class_options(mc
);
4713 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4714 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4716 /* We depend on kvm_enabled() to choose a default value for the
4717 * hpt-max-page-size capability. Of course we can't do it here
4718 * because this is too early and the HW accelerator isn't initialzed
4719 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4721 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4724 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4726 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4728 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4730 spapr_machine_2_12_class_options(mc
);
4731 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4732 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4733 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4736 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4742 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4744 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4746 spapr_machine_2_12_class_options(mc
);
4747 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4748 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4751 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4757 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4759 spapr_machine_2_11_class_options(mc
);
4760 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4763 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4769 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4771 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4772 static GlobalProperty compat
[] = {
4773 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4776 spapr_machine_2_10_class_options(mc
);
4777 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4778 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4779 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4780 smc
->pre_2_10_has_unused_icps
= true;
4781 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4784 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4790 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4792 static GlobalProperty compat
[] = {
4793 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4796 spapr_machine_2_9_class_options(mc
);
4797 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4798 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4799 mc
->numa_mem_align_shift
= 23;
4802 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4808 static void phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
4809 uint64_t *buid
, hwaddr
*pio
,
4810 hwaddr
*mmio32
, hwaddr
*mmio64
,
4811 unsigned n_dma
, uint32_t *liobns
,
4812 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4814 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4815 const uint64_t base_buid
= 0x800000020000000ULL
;
4816 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4817 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4818 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4819 const uint32_t max_index
= 255;
4820 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4822 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4823 hwaddr phb0_base
, phb_base
;
4826 /* Do we have device memory? */
4827 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4828 /* Can't just use maxram_size, because there may be an
4829 * alignment gap between normal and device memory regions
4831 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4832 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4835 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4837 if (index
> max_index
) {
4838 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4843 *buid
= base_buid
+ index
;
4844 for (i
= 0; i
< n_dma
; ++i
) {
4845 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4848 phb_base
= phb0_base
+ index
* phb_spacing
;
4849 *pio
= phb_base
+ pio_offset
;
4850 *mmio32
= phb_base
+ mmio_offset
;
4852 * We don't set the 64-bit MMIO window, relying on the PHB's
4853 * fallback behaviour of automatically splitting a large "32-bit"
4854 * window into contiguous 32-bit and 64-bit windows
4861 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4863 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4864 static GlobalProperty compat
[] = {
4865 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
4866 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
4867 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
4868 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
4871 spapr_machine_2_8_class_options(mc
);
4872 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4873 mc
->default_machine_opts
= "modern-hotplug-events=off";
4874 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
4875 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4876 smc
->phb_placement
= phb_placement_2_7
;
4879 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4885 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4887 static GlobalProperty compat
[] = {
4888 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
4891 spapr_machine_2_7_class_options(mc
);
4892 mc
->has_hotpluggable_cpus
= false;
4893 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
4894 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4897 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4903 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4905 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4906 static GlobalProperty compat
[] = {
4907 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4910 spapr_machine_2_6_class_options(mc
);
4911 smc
->use_ohci_by_default
= true;
4912 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
4913 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4916 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4922 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4924 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4926 spapr_machine_2_5_class_options(mc
);
4927 smc
->dr_lmb_enabled
= false;
4928 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
4931 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4937 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4939 static GlobalProperty compat
[] = {
4940 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4942 spapr_machine_2_4_class_options(mc
);
4943 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
4944 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4946 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4952 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4954 static GlobalProperty compat
[] = {
4955 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
4958 spapr_machine_2_3_class_options(mc
);
4959 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
4960 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4961 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
4963 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4969 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4971 spapr_machine_2_2_class_options(mc
);
4972 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
4974 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4976 static void spapr_machine_register_types(void)
4978 type_register_static(&spapr_machine_info
);
4981 type_init(spapr_machine_register_types
)