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auxbus: use get_uint() for "addr" property
[qemu/ar7.git] / hw / usb / hcd-xhci.c
bloba0c7960a7b0bb40b3ccc37268bb17e21b5886e8b
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "qemu/osdep.h"
22 #include "hw/hw.h"
23 #include "qemu/timer.h"
24 #include "qemu/queue.h"
25 #include "hw/usb.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "trace.h"
30 #include "qapi/error.h"
31
32 #include "hcd-xhci.h"
33
34 //#define DEBUG_XHCI
35 //#define DEBUG_DATA
36
37 #ifdef DEBUG_XHCI
38 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
39 #else
40 #define DPRINTF(...) do {} while (0)
41 #endif
42 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
43 __func__, __LINE__, _msg); abort(); } while (0)
44
45 #define TRB_LINK_LIMIT 32
46 #define COMMAND_LIMIT 256
47 #define TRANSFER_LIMIT 256
48
49 #define LEN_CAP 0x40
50 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
51 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
52 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
53
54 #define OFF_OPER LEN_CAP
55 #define OFF_RUNTIME 0x1000
56 #define OFF_DOORBELL 0x2000
57 #define OFF_MSIX_TABLE 0x3000
58 #define OFF_MSIX_PBA 0x3800
59 /* must be power of 2 */
60 #define LEN_REGS 0x4000
61
62 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
63 #error Increase OFF_RUNTIME
64 #endif
65 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
66 #error Increase OFF_DOORBELL
67 #endif
68 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
69 # error Increase LEN_REGS
70 #endif
71
72 /* bit definitions */
73 #define USBCMD_RS (1<<0)
74 #define USBCMD_HCRST (1<<1)
75 #define USBCMD_INTE (1<<2)
76 #define USBCMD_HSEE (1<<3)
77 #define USBCMD_LHCRST (1<<7)
78 #define USBCMD_CSS (1<<8)
79 #define USBCMD_CRS (1<<9)
80 #define USBCMD_EWE (1<<10)
81 #define USBCMD_EU3S (1<<11)
82
83 #define USBSTS_HCH (1<<0)
84 #define USBSTS_HSE (1<<2)
85 #define USBSTS_EINT (1<<3)
86 #define USBSTS_PCD (1<<4)
87 #define USBSTS_SSS (1<<8)
88 #define USBSTS_RSS (1<<9)
89 #define USBSTS_SRE (1<<10)
90 #define USBSTS_CNR (1<<11)
91 #define USBSTS_HCE (1<<12)
92
93
94 #define PORTSC_CCS (1<<0)
95 #define PORTSC_PED (1<<1)
96 #define PORTSC_OCA (1<<3)
97 #define PORTSC_PR (1<<4)
98 #define PORTSC_PLS_SHIFT 5
99 #define PORTSC_PLS_MASK 0xf
100 #define PORTSC_PP (1<<9)
101 #define PORTSC_SPEED_SHIFT 10
102 #define PORTSC_SPEED_MASK 0xf
103 #define PORTSC_SPEED_FULL (1<<10)
104 #define PORTSC_SPEED_LOW (2<<10)
105 #define PORTSC_SPEED_HIGH (3<<10)
106 #define PORTSC_SPEED_SUPER (4<<10)
107 #define PORTSC_PIC_SHIFT 14
108 #define PORTSC_PIC_MASK 0x3
109 #define PORTSC_LWS (1<<16)
110 #define PORTSC_CSC (1<<17)
111 #define PORTSC_PEC (1<<18)
112 #define PORTSC_WRC (1<<19)
113 #define PORTSC_OCC (1<<20)
114 #define PORTSC_PRC (1<<21)
115 #define PORTSC_PLC (1<<22)
116 #define PORTSC_CEC (1<<23)
117 #define PORTSC_CAS (1<<24)
118 #define PORTSC_WCE (1<<25)
119 #define PORTSC_WDE (1<<26)
120 #define PORTSC_WOE (1<<27)
121 #define PORTSC_DR (1<<30)
122 #define PORTSC_WPR (1<<31)
123
124 #define CRCR_RCS (1<<0)
125 #define CRCR_CS (1<<1)
126 #define CRCR_CA (1<<2)
127 #define CRCR_CRR (1<<3)
128
129 #define IMAN_IP (1<<0)
130 #define IMAN_IE (1<<1)
131
132 #define ERDP_EHB (1<<3)
133
134 #define TRB_SIZE 16
135 typedef struct XHCITRB {
136 uint64_t parameter;
137 uint32_t status;
138 uint32_t control;
139 dma_addr_t addr;
140 bool ccs;
141 } XHCITRB;
142
143 enum {
144 PLS_U0 = 0,
145 PLS_U1 = 1,
146 PLS_U2 = 2,
147 PLS_U3 = 3,
148 PLS_DISABLED = 4,
149 PLS_RX_DETECT = 5,
150 PLS_INACTIVE = 6,
151 PLS_POLLING = 7,
152 PLS_RECOVERY = 8,
153 PLS_HOT_RESET = 9,
154 PLS_COMPILANCE_MODE = 10,
155 PLS_TEST_MODE = 11,
156 PLS_RESUME = 15,
157 };
158
159 #define CR_LINK TR_LINK
160
161 #define TRB_C (1<<0)
162 #define TRB_TYPE_SHIFT 10
163 #define TRB_TYPE_MASK 0x3f
164 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
165
166 #define TRB_EV_ED (1<<2)
167
168 #define TRB_TR_ENT (1<<1)
169 #define TRB_TR_ISP (1<<2)
170 #define TRB_TR_NS (1<<3)
171 #define TRB_TR_CH (1<<4)
172 #define TRB_TR_IOC (1<<5)
173 #define TRB_TR_IDT (1<<6)
174 #define TRB_TR_TBC_SHIFT 7
175 #define TRB_TR_TBC_MASK 0x3
176 #define TRB_TR_BEI (1<<9)
177 #define TRB_TR_TLBPC_SHIFT 16
178 #define TRB_TR_TLBPC_MASK 0xf
179 #define TRB_TR_FRAMEID_SHIFT 20
180 #define TRB_TR_FRAMEID_MASK 0x7ff
181 #define TRB_TR_SIA (1<<31)
182
183 #define TRB_TR_DIR (1<<16)
184
185 #define TRB_CR_SLOTID_SHIFT 24
186 #define TRB_CR_SLOTID_MASK 0xff
187 #define TRB_CR_EPID_SHIFT 16
188 #define TRB_CR_EPID_MASK 0x1f
189
190 #define TRB_CR_BSR (1<<9)
191 #define TRB_CR_DC (1<<9)
192
193 #define TRB_LK_TC (1<<1)
194
195 #define TRB_INTR_SHIFT 22
196 #define TRB_INTR_MASK 0x3ff
197 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
198
199 #define EP_TYPE_MASK 0x7
200 #define EP_TYPE_SHIFT 3
201
202 #define EP_STATE_MASK 0x7
203 #define EP_DISABLED (0<<0)
204 #define EP_RUNNING (1<<0)
205 #define EP_HALTED (2<<0)
206 #define EP_STOPPED (3<<0)
207 #define EP_ERROR (4<<0)
208
209 #define SLOT_STATE_MASK 0x1f
210 #define SLOT_STATE_SHIFT 27
211 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
212 #define SLOT_ENABLED 0
213 #define SLOT_DEFAULT 1
214 #define SLOT_ADDRESSED 2
215 #define SLOT_CONFIGURED 3
216
217 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
218 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
219
220 #define get_field(data, field) \
221 (((data) >> field##_SHIFT) & field##_MASK)
222
223 #define set_field(data, newval, field) do { \
224 uint32_t val = *data; \
225 val &= ~(field##_MASK << field##_SHIFT); \
226 val |= ((newval) & field##_MASK) << field##_SHIFT; \
227 *data = val; \
228 } while (0)
229
230 typedef enum EPType {
231 ET_INVALID = 0,
232 ET_ISO_OUT,
233 ET_BULK_OUT,
234 ET_INTR_OUT,
235 ET_CONTROL,
236 ET_ISO_IN,
237 ET_BULK_IN,
238 ET_INTR_IN,
239 } EPType;
240
241 typedef struct XHCITransfer {
242 XHCIEPContext *epctx;
243 USBPacket packet;
244 QEMUSGList sgl;
245 bool running_async;
246 bool running_retry;
247 bool complete;
248 bool int_req;
249 unsigned int iso_pkts;
250 unsigned int streamid;
251 bool in_xfer;
252 bool iso_xfer;
253 bool timed_xfer;
254
255 unsigned int trb_count;
256 XHCITRB *trbs;
257
258 TRBCCode status;
259
260 unsigned int pkts;
261 unsigned int pktsize;
262 unsigned int cur_pkt;
263
264 uint64_t mfindex_kick;
265
266 QTAILQ_ENTRY(XHCITransfer) next;
267 } XHCITransfer;
268
269 struct XHCIStreamContext {
270 dma_addr_t pctx;
271 unsigned int sct;
272 XHCIRing ring;
273 };
274
275 struct XHCIEPContext {
276 XHCIState *xhci;
277 unsigned int slotid;
278 unsigned int epid;
279
280 XHCIRing ring;
281 uint32_t xfer_count;
282 QTAILQ_HEAD(, XHCITransfer) transfers;
283 XHCITransfer *retry;
284 EPType type;
285 dma_addr_t pctx;
286 unsigned int max_psize;
287 uint32_t state;
288 uint32_t kick_active;
289
290 /* streams */
291 unsigned int max_pstreams;
292 bool lsa;
293 unsigned int nr_pstreams;
294 XHCIStreamContext *pstreams;
295
296 /* iso xfer scheduling */
297 unsigned int interval;
298 int64_t mfindex_last;
299 QEMUTimer *kick_timer;
300 };
301
302 typedef struct XHCIEvRingSeg {
303 uint32_t addr_low;
304 uint32_t addr_high;
305 uint32_t size;
306 uint32_t rsvd;
307 } XHCIEvRingSeg;
308
309 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
310 unsigned int epid, unsigned int streamid);
311 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid);
312 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
313 unsigned int epid);
314 static void xhci_xfer_report(XHCITransfer *xfer);
315 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
316 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
317 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx);
318
319 static const char *TRBType_names[] = {
320 [TRB_RESERVED] = "TRB_RESERVED",
321 [TR_NORMAL] = "TR_NORMAL",
322 [TR_SETUP] = "TR_SETUP",
323 [TR_DATA] = "TR_DATA",
324 [TR_STATUS] = "TR_STATUS",
325 [TR_ISOCH] = "TR_ISOCH",
326 [TR_LINK] = "TR_LINK",
327 [TR_EVDATA] = "TR_EVDATA",
328 [TR_NOOP] = "TR_NOOP",
329 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
330 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
331 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
332 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
333 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
334 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
335 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
336 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
337 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
338 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
339 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
340 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
341 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
342 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
343 [CR_NOOP] = "CR_NOOP",
344 [ER_TRANSFER] = "ER_TRANSFER",
345 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
346 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
347 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
348 [ER_DOORBELL] = "ER_DOORBELL",
349 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
350 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
351 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
352 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
353 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
354 };
355
356 static const char *TRBCCode_names[] = {
357 [CC_INVALID] = "CC_INVALID",
358 [CC_SUCCESS] = "CC_SUCCESS",
359 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
360 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
361 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
362 [CC_TRB_ERROR] = "CC_TRB_ERROR",
363 [CC_STALL_ERROR] = "CC_STALL_ERROR",
364 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
365 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
366 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
367 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
368 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
369 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
370 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
371 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
372 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
373 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
374 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
375 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
376 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
377 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
378 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
379 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
380 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
381 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
382 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
383 [CC_STOPPED] = "CC_STOPPED",
384 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
385 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
386 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
387 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
388 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
389 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
390 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
391 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
392 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
393 };
394
395 static const char *ep_state_names[] = {
396 [EP_DISABLED] = "disabled",
397 [EP_RUNNING] = "running",
398 [EP_HALTED] = "halted",
399 [EP_STOPPED] = "stopped",
400 [EP_ERROR] = "error",
401 };
402
403 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
404 {
405 if (index >= llen || list[index] == NULL) {
406 return "???";
407 }
408 return list[index];
409 }
410
411 static const char *trb_name(XHCITRB *trb)
412 {
413 return lookup_name(TRB_TYPE(*trb), TRBType_names,
414 ARRAY_SIZE(TRBType_names));
415 }
416
417 static const char *event_name(XHCIEvent *event)
418 {
419 return lookup_name(event->ccode, TRBCCode_names,
420 ARRAY_SIZE(TRBCCode_names));
421 }
422
423 static const char *ep_state_name(uint32_t state)
424 {
425 return lookup_name(state, ep_state_names,
426 ARRAY_SIZE(ep_state_names));
427 }
428
429 static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
430 {
431 return xhci->flags & (1 << bit);
432 }
433
434 static void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
435 {
436 xhci->flags |= (1 << bit);
437 }
438
439 static uint64_t xhci_mfindex_get(XHCIState *xhci)
440 {
441 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
442 return (now - xhci->mfindex_start) / 125000;
443 }
444
445 static void xhci_mfwrap_update(XHCIState *xhci)
446 {
447 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
448 uint32_t mfindex, left;
449 int64_t now;
450
451 if ((xhci->usbcmd & bits) == bits) {
452 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
453 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
454 left = 0x4000 - mfindex;
455 timer_mod(xhci->mfwrap_timer, now + left * 125000);
456 } else {
457 timer_del(xhci->mfwrap_timer);
458 }
459 }
460
461 static void xhci_mfwrap_timer(void *opaque)
462 {
463 XHCIState *xhci = opaque;
464 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
465
466 xhci_event(xhci, &wrap, 0);
467 xhci_mfwrap_update(xhci);
468 }
469
470 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
471 {
472 if (sizeof(dma_addr_t) == 4) {
473 return low;
474 } else {
475 return low | (((dma_addr_t)high << 16) << 16);
476 }
477 }
478
479 static inline dma_addr_t xhci_mask64(uint64_t addr)
480 {
481 if (sizeof(dma_addr_t) == 4) {
482 return addr & 0xffffffff;
483 } else {
484 return addr;
485 }
486 }
487
488 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
489 uint32_t *buf, size_t len)
490 {
491 int i;
492
493 assert((len % sizeof(uint32_t)) == 0);
494
495 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
496
497 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
498 buf[i] = le32_to_cpu(buf[i]);
499 }
500 }
501
502 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
503 uint32_t *buf, size_t len)
504 {
505 int i;
506 uint32_t tmp[5];
507 uint32_t n = len / sizeof(uint32_t);
508
509 assert((len % sizeof(uint32_t)) == 0);
510 assert(n <= ARRAY_SIZE(tmp));
511
512 for (i = 0; i < n; i++) {
513 tmp[i] = cpu_to_le32(buf[i]);
514 }
515 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
516 }
517
518 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
519 {
520 int index;
521
522 if (!uport->dev) {
523 return NULL;
524 }
525 switch (uport->dev->speed) {
526 case USB_SPEED_LOW:
527 case USB_SPEED_FULL:
528 case USB_SPEED_HIGH:
529 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
530 index = uport->index + xhci->numports_3;
531 } else {
532 index = uport->index;
533 }
534 break;
535 case USB_SPEED_SUPER:
536 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
537 index = uport->index;
538 } else {
539 index = uport->index + xhci->numports_2;
540 }
541 break;
542 default:
543 return NULL;
544 }
545 return &xhci->ports[index];
546 }
547
548 static void xhci_intx_update(XHCIState *xhci)
549 {
550 PCIDevice *pci_dev = PCI_DEVICE(xhci);
551 int level = 0;
552
553 if (msix_enabled(pci_dev) ||
554 msi_enabled(pci_dev)) {
555 return;
556 }
557
558 if (xhci->intr[0].iman & IMAN_IP &&
559 xhci->intr[0].iman & IMAN_IE &&
560 xhci->usbcmd & USBCMD_INTE) {
561 level = 1;
562 }
563
564 trace_usb_xhci_irq_intx(level);
565 pci_set_irq(pci_dev, level);
566 }
567
568 static void xhci_msix_update(XHCIState *xhci, int v)
569 {
570 PCIDevice *pci_dev = PCI_DEVICE(xhci);
571 bool enabled;
572
573 if (!msix_enabled(pci_dev)) {
574 return;
575 }
576
577 enabled = xhci->intr[v].iman & IMAN_IE;
578 if (enabled == xhci->intr[v].msix_used) {
579 return;
580 }
581
582 if (enabled) {
583 trace_usb_xhci_irq_msix_use(v);
584 msix_vector_use(pci_dev, v);
585 xhci->intr[v].msix_used = true;
586 } else {
587 trace_usb_xhci_irq_msix_unuse(v);
588 msix_vector_unuse(pci_dev, v);
589 xhci->intr[v].msix_used = false;
590 }
591 }
592
593 static void xhci_intr_raise(XHCIState *xhci, int v)
594 {
595 PCIDevice *pci_dev = PCI_DEVICE(xhci);
596 bool pending = (xhci->intr[v].erdp_low & ERDP_EHB);
597
598 xhci->intr[v].erdp_low |= ERDP_EHB;
599 xhci->intr[v].iman |= IMAN_IP;
600 xhci->usbsts |= USBSTS_EINT;
601
602 if (pending) {
603 return;
604 }
605 if (!(xhci->intr[v].iman & IMAN_IE)) {
606 return;
607 }
608
609 if (!(xhci->usbcmd & USBCMD_INTE)) {
610 return;
611 }
612
613 if (msix_enabled(pci_dev)) {
614 trace_usb_xhci_irq_msix(v);
615 msix_notify(pci_dev, v);
616 return;
617 }
618
619 if (msi_enabled(pci_dev)) {
620 trace_usb_xhci_irq_msi(v);
621 msi_notify(pci_dev, v);
622 return;
623 }
624
625 if (v == 0) {
626 trace_usb_xhci_irq_intx(1);
627 pci_irq_assert(pci_dev);
628 }
629 }
630
631 static inline int xhci_running(XHCIState *xhci)
632 {
633 return !(xhci->usbsts & USBSTS_HCH);
634 }
635
636 static void xhci_die(XHCIState *xhci)
637 {
638 xhci->usbsts |= USBSTS_HCE;
639 DPRINTF("xhci: asserted controller error\n");
640 }
641
642 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
643 {
644 PCIDevice *pci_dev = PCI_DEVICE(xhci);
645 XHCIInterrupter *intr = &xhci->intr[v];
646 XHCITRB ev_trb;
647 dma_addr_t addr;
648
649 ev_trb.parameter = cpu_to_le64(event->ptr);
650 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
651 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
652 event->flags | (event->type << TRB_TYPE_SHIFT);
653 if (intr->er_pcs) {
654 ev_trb.control |= TRB_C;
655 }
656 ev_trb.control = cpu_to_le32(ev_trb.control);
657
658 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
659 event_name(event), ev_trb.parameter,
660 ev_trb.status, ev_trb.control);
661
662 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
663 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
664
665 intr->er_ep_idx++;
666 if (intr->er_ep_idx >= intr->er_size) {
667 intr->er_ep_idx = 0;
668 intr->er_pcs = !intr->er_pcs;
669 }
670 }
671
672 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
673 {
674 XHCIInterrupter *intr;
675 dma_addr_t erdp;
676 unsigned int dp_idx;
677
678 if (v >= xhci->numintrs) {
679 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
680 return;
681 }
682 intr = &xhci->intr[v];
683
684 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
685 if (erdp < intr->er_start ||
686 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
687 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
688 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
689 v, intr->er_start, intr->er_size);
690 xhci_die(xhci);
691 return;
692 }
693
694 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
695 assert(dp_idx < intr->er_size);
696
697 if ((intr->er_ep_idx + 2) % intr->er_size == dp_idx) {
698 DPRINTF("xhci: ER %d full, send ring full error\n", v);
699 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
700 xhci_write_event(xhci, &full, v);
701 } else if ((intr->er_ep_idx + 1) % intr->er_size == dp_idx) {
702 DPRINTF("xhci: ER %d full, drop event\n", v);
703 } else {
704 xhci_write_event(xhci, event, v);
705 }
706
707 xhci_intr_raise(xhci, v);
708 }
709
710 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
711 dma_addr_t base)
712 {
713 ring->dequeue = base;
714 ring->ccs = 1;
715 }
716
717 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
718 dma_addr_t *addr)
719 {
720 PCIDevice *pci_dev = PCI_DEVICE(xhci);
721 uint32_t link_cnt = 0;
722
723 while (1) {
724 TRBType type;
725 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
726 trb->addr = ring->dequeue;
727 trb->ccs = ring->ccs;
728 le64_to_cpus(&trb->parameter);
729 le32_to_cpus(&trb->status);
730 le32_to_cpus(&trb->control);
731
732 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
733 trb->parameter, trb->status, trb->control);
734
735 if ((trb->control & TRB_C) != ring->ccs) {
736 return 0;
737 }
738
739 type = TRB_TYPE(*trb);
740
741 if (type != TR_LINK) {
742 if (addr) {
743 *addr = ring->dequeue;
744 }
745 ring->dequeue += TRB_SIZE;
746 return type;
747 } else {
748 if (++link_cnt > TRB_LINK_LIMIT) {
749 trace_usb_xhci_enforced_limit("trb-link");
750 return 0;
751 }
752 ring->dequeue = xhci_mask64(trb->parameter);
753 if (trb->control & TRB_LK_TC) {
754 ring->ccs = !ring->ccs;
755 }
756 }
757 }
758 }
759
760 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
761 {
762 PCIDevice *pci_dev = PCI_DEVICE(xhci);
763 XHCITRB trb;
764 int length = 0;
765 dma_addr_t dequeue = ring->dequeue;
766 bool ccs = ring->ccs;
767 /* hack to bundle together the two/three TDs that make a setup transfer */
768 bool control_td_set = 0;
769 uint32_t link_cnt = 0;
770
771 while (1) {
772 TRBType type;
773 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
774 le64_to_cpus(&trb.parameter);
775 le32_to_cpus(&trb.status);
776 le32_to_cpus(&trb.control);
777
778 if ((trb.control & TRB_C) != ccs) {
779 return -length;
780 }
781
782 type = TRB_TYPE(trb);
783
784 if (type == TR_LINK) {
785 if (++link_cnt > TRB_LINK_LIMIT) {
786 return -length;
787 }
788 dequeue = xhci_mask64(trb.parameter);
789 if (trb.control & TRB_LK_TC) {
790 ccs = !ccs;
791 }
792 continue;
793 }
794
795 length += 1;
796 dequeue += TRB_SIZE;
797
798 if (type == TR_SETUP) {
799 control_td_set = 1;
800 } else if (type == TR_STATUS) {
801 control_td_set = 0;
802 }
803
804 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
805 return length;
806 }
807 }
808 }
809
810 static void xhci_er_reset(XHCIState *xhci, int v)
811 {
812 XHCIInterrupter *intr = &xhci->intr[v];
813 XHCIEvRingSeg seg;
814
815 if (intr->erstsz == 0) {
816 /* disabled */
817 intr->er_start = 0;
818 intr->er_size = 0;
819 return;
820 }
821 /* cache the (sole) event ring segment location */
822 if (intr->erstsz != 1) {
823 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
824 xhci_die(xhci);
825 return;
826 }
827 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
828 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
829 le32_to_cpus(&seg.addr_low);
830 le32_to_cpus(&seg.addr_high);
831 le32_to_cpus(&seg.size);
832 if (seg.size < 16 || seg.size > 4096) {
833 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);
834 xhci_die(xhci);
835 return;
836 }
837 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
838 intr->er_size = seg.size;
839
840 intr->er_ep_idx = 0;
841 intr->er_pcs = 1;
842
843 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
844 v, intr->er_start, intr->er_size);
845 }
846
847 static void xhci_run(XHCIState *xhci)
848 {
849 trace_usb_xhci_run();
850 xhci->usbsts &= ~USBSTS_HCH;
851 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
852 }
853
854 static void xhci_stop(XHCIState *xhci)
855 {
856 trace_usb_xhci_stop();
857 xhci->usbsts |= USBSTS_HCH;
858 xhci->crcr_low &= ~CRCR_CRR;
859 }
860
861 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
862 dma_addr_t base)
863 {
864 XHCIStreamContext *stctx;
865 unsigned int i;
866
867 stctx = g_new0(XHCIStreamContext, count);
868 for (i = 0; i < count; i++) {
869 stctx[i].pctx = base + i * 16;
870 stctx[i].sct = -1;
871 }
872 return stctx;
873 }
874
875 static void xhci_reset_streams(XHCIEPContext *epctx)
876 {
877 unsigned int i;
878
879 for (i = 0; i < epctx->nr_pstreams; i++) {
880 epctx->pstreams[i].sct = -1;
881 }
882 }
883
884 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
885 {
886 assert(epctx->pstreams == NULL);
887 epctx->nr_pstreams = 2 << epctx->max_pstreams;
888 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
889 }
890
891 static void xhci_free_streams(XHCIEPContext *epctx)
892 {
893 assert(epctx->pstreams != NULL);
894
895 g_free(epctx->pstreams);
896 epctx->pstreams = NULL;
897 epctx->nr_pstreams = 0;
898 }
899
900 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
901 unsigned int slotid,
902 uint32_t epmask,
903 XHCIEPContext **epctxs,
904 USBEndpoint **eps)
905 {
906 XHCISlot *slot;
907 XHCIEPContext *epctx;
908 USBEndpoint *ep;
909 int i, j;
910
911 assert(slotid >= 1 && slotid <= xhci->numslots);
912
913 slot = &xhci->slots[slotid - 1];
914
915 for (i = 2, j = 0; i <= 31; i++) {
916 if (!(epmask & (1u << i))) {
917 continue;
918 }
919
920 epctx = slot->eps[i - 1];
921 ep = xhci_epid_to_usbep(epctx);
922 if (!epctx || !epctx->nr_pstreams || !ep) {
923 continue;
924 }
925
926 if (epctxs) {
927 epctxs[j] = epctx;
928 }
929 eps[j++] = ep;
930 }
931 return j;
932 }
933
934 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
935 uint32_t epmask)
936 {
937 USBEndpoint *eps[30];
938 int nr_eps;
939
940 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
941 if (nr_eps) {
942 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
943 }
944 }
945
946 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
947 uint32_t epmask)
948 {
949 XHCIEPContext *epctxs[30];
950 USBEndpoint *eps[30];
951 int i, r, nr_eps, req_nr_streams, dev_max_streams;
952
953 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
954 eps);
955 if (nr_eps == 0) {
956 return CC_SUCCESS;
957 }
958
959 req_nr_streams = epctxs[0]->nr_pstreams;
960 dev_max_streams = eps[0]->max_streams;
961
962 for (i = 1; i < nr_eps; i++) {
963 /*
964 * HdG: I don't expect these to ever trigger, but if they do we need
965 * to come up with another solution, ie group identical endpoints
966 * together and make an usb_device_alloc_streams call per group.
967 */
968 if (epctxs[i]->nr_pstreams != req_nr_streams) {
969 FIXME("guest streams config not identical for all eps");
970 return CC_RESOURCE_ERROR;
971 }
972 if (eps[i]->max_streams != dev_max_streams) {
973 FIXME("device streams config not identical for all eps");
974 return CC_RESOURCE_ERROR;
975 }
976 }
977
978 /*
979 * max-streams in both the device descriptor and in the controller is a
980 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
981 * streams the guest will ask for 5 rounded up to the next power of 2 which
982 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
983 *
984 * For redirected devices however this is an issue, as there we must ask
985 * the real xhci controller to alloc streams, and the host driver for the
986 * real xhci controller will likely disallow allocating more streams then
987 * the device can handle.
988 *
989 * So we limit the requested nr_streams to the maximum number the device
990 * can handle.
991 */
992 if (req_nr_streams > dev_max_streams) {
993 req_nr_streams = dev_max_streams;
994 }
995
996 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
997 if (r != 0) {
998 DPRINTF("xhci: alloc streams failed\n");
999 return CC_RESOURCE_ERROR;
1000 }
1001
1002 return CC_SUCCESS;
1003 }
1004
1005 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1006 unsigned int streamid,
1007 uint32_t *cc_error)
1008 {
1009 XHCIStreamContext *sctx;
1010 dma_addr_t base;
1011 uint32_t ctx[2], sct;
1012
1013 assert(streamid != 0);
1014 if (epctx->lsa) {
1015 if (streamid >= epctx->nr_pstreams) {
1016 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1017 return NULL;
1018 }
1019 sctx = epctx->pstreams + streamid;
1020 } else {
1021 FIXME("secondary streams not implemented yet");
1022 }
1023
1024 if (sctx->sct == -1) {
1025 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1026 sct = (ctx[0] >> 1) & 0x07;
1027 if (epctx->lsa && sct != 1) {
1028 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1029 return NULL;
1030 }
1031 sctx->sct = sct;
1032 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1033 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1034 }
1035 return sctx;
1036 }
1037
1038 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1039 XHCIStreamContext *sctx, uint32_t state)
1040 {
1041 XHCIRing *ring = NULL;
1042 uint32_t ctx[5];
1043 uint32_t ctx2[2];
1044
1045 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1046 ctx[0] &= ~EP_STATE_MASK;
1047 ctx[0] |= state;
1048
1049 /* update ring dequeue ptr */
1050 if (epctx->nr_pstreams) {
1051 if (sctx != NULL) {
1052 ring = &sctx->ring;
1053 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1054 ctx2[0] &= 0xe;
1055 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1056 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1057 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1058 }
1059 } else {
1060 ring = &epctx->ring;
1061 }
1062 if (ring) {
1063 ctx[2] = ring->dequeue | ring->ccs;
1064 ctx[3] = (ring->dequeue >> 16) >> 16;
1065
1066 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1067 epctx->pctx, state, ctx[3], ctx[2]);
1068 }
1069
1070 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1071 if (epctx->state != state) {
1072 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1073 ep_state_name(epctx->state),
1074 ep_state_name(state));
1075 }
1076 epctx->state = state;
1077 }
1078
1079 static void xhci_ep_kick_timer(void *opaque)
1080 {
1081 XHCIEPContext *epctx = opaque;
1082 xhci_kick_epctx(epctx, 0);
1083 }
1084
1085 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1086 unsigned int slotid,
1087 unsigned int epid)
1088 {
1089 XHCIEPContext *epctx;
1090
1091 epctx = g_new0(XHCIEPContext, 1);
1092 epctx->xhci = xhci;
1093 epctx->slotid = slotid;
1094 epctx->epid = epid;
1095
1096 QTAILQ_INIT(&epctx->transfers);
1097 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1098
1099 return epctx;
1100 }
1101
1102 static void xhci_init_epctx(XHCIEPContext *epctx,
1103 dma_addr_t pctx, uint32_t *ctx)
1104 {
1105 dma_addr_t dequeue;
1106
1107 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1108
1109 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1110 epctx->pctx = pctx;
1111 epctx->max_psize = ctx[1]>>16;
1112 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1113 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask;
1114 epctx->lsa = (ctx[0] >> 15) & 1;
1115 if (epctx->max_pstreams) {
1116 xhci_alloc_streams(epctx, dequeue);
1117 } else {
1118 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1119 epctx->ring.ccs = ctx[2] & 1;
1120 }
1121
1122 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1123 }
1124
1125 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1126 unsigned int epid, dma_addr_t pctx,
1127 uint32_t *ctx)
1128 {
1129 XHCISlot *slot;
1130 XHCIEPContext *epctx;
1131
1132 trace_usb_xhci_ep_enable(slotid, epid);
1133 assert(slotid >= 1 && slotid <= xhci->numslots);
1134 assert(epid >= 1 && epid <= 31);
1135
1136 slot = &xhci->slots[slotid-1];
1137 if (slot->eps[epid-1]) {
1138 xhci_disable_ep(xhci, slotid, epid);
1139 }
1140
1141 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1142 slot->eps[epid-1] = epctx;
1143 xhci_init_epctx(epctx, pctx, ctx);
1144
1145 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1146 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize);
1147
1148 epctx->mfindex_last = 0;
1149
1150 epctx->state = EP_RUNNING;
1151 ctx[0] &= ~EP_STATE_MASK;
1152 ctx[0] |= EP_RUNNING;
1153
1154 return CC_SUCCESS;
1155 }
1156
1157 static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx,
1158 uint32_t length)
1159 {
1160 uint32_t limit = epctx->nr_pstreams + 16;
1161 XHCITransfer *xfer;
1162
1163 if (epctx->xfer_count >= limit) {
1164 return NULL;
1165 }
1166
1167 xfer = g_new0(XHCITransfer, 1);
1168 xfer->epctx = epctx;
1169 xfer->trbs = g_new(XHCITRB, length);
1170 xfer->trb_count = length;
1171 usb_packet_init(&xfer->packet);
1172
1173 QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next);
1174 epctx->xfer_count++;
1175
1176 return xfer;
1177 }
1178
1179 static void xhci_ep_free_xfer(XHCITransfer *xfer)
1180 {
1181 QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next);
1182 xfer->epctx->xfer_count--;
1183
1184 usb_packet_cleanup(&xfer->packet);
1185 g_free(xfer->trbs);
1186 g_free(xfer);
1187 }
1188
1189 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1190 {
1191 int killed = 0;
1192
1193 if (report && (t->running_async || t->running_retry)) {
1194 t->status = report;
1195 xhci_xfer_report(t);
1196 }
1197
1198 if (t->running_async) {
1199 usb_cancel_packet(&t->packet);
1200 t->running_async = 0;
1201 killed = 1;
1202 }
1203 if (t->running_retry) {
1204 if (t->epctx) {
1205 t->epctx->retry = NULL;
1206 timer_del(t->epctx->kick_timer);
1207 }
1208 t->running_retry = 0;
1209 killed = 1;
1210 }
1211 g_free(t->trbs);
1212
1213 t->trbs = NULL;
1214 t->trb_count = 0;
1215
1216 return killed;
1217 }
1218
1219 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1220 unsigned int epid, TRBCCode report)
1221 {
1222 XHCISlot *slot;
1223 XHCIEPContext *epctx;
1224 XHCITransfer *xfer;
1225 int killed = 0;
1226 USBEndpoint *ep = NULL;
1227 assert(slotid >= 1 && slotid <= xhci->numslots);
1228 assert(epid >= 1 && epid <= 31);
1229
1230 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1231
1232 slot = &xhci->slots[slotid-1];
1233
1234 if (!slot->eps[epid-1]) {
1235 return 0;
1236 }
1237
1238 epctx = slot->eps[epid-1];
1239
1240 for (;;) {
1241 xfer = QTAILQ_FIRST(&epctx->transfers);
1242 if (xfer == NULL) {
1243 break;
1244 }
1245 killed += xhci_ep_nuke_one_xfer(xfer, report);
1246 if (killed) {
1247 report = 0; /* Only report once */
1248 }
1249 xhci_ep_free_xfer(xfer);
1250 }
1251
1252 ep = xhci_epid_to_usbep(epctx);
1253 if (ep) {
1254 usb_device_ep_stopped(ep->dev, ep);
1255 }
1256 return killed;
1257 }
1258
1259 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1260 unsigned int epid)
1261 {
1262 XHCISlot *slot;
1263 XHCIEPContext *epctx;
1264
1265 trace_usb_xhci_ep_disable(slotid, epid);
1266 assert(slotid >= 1 && slotid <= xhci->numslots);
1267 assert(epid >= 1 && epid <= 31);
1268
1269 slot = &xhci->slots[slotid-1];
1270
1271 if (!slot->eps[epid-1]) {
1272 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1273 return CC_SUCCESS;
1274 }
1275
1276 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1277
1278 epctx = slot->eps[epid-1];
1279
1280 if (epctx->nr_pstreams) {
1281 xhci_free_streams(epctx);
1282 }
1283
1284 /* only touch guest RAM if we're not resetting the HC */
1285 if (xhci->dcbaap_low || xhci->dcbaap_high) {
1286 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1287 }
1288
1289 timer_free(epctx->kick_timer);
1290 g_free(epctx);
1291 slot->eps[epid-1] = NULL;
1292
1293 return CC_SUCCESS;
1294 }
1295
1296 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1297 unsigned int epid)
1298 {
1299 XHCISlot *slot;
1300 XHCIEPContext *epctx;
1301
1302 trace_usb_xhci_ep_stop(slotid, epid);
1303 assert(slotid >= 1 && slotid <= xhci->numslots);
1304
1305 if (epid < 1 || epid > 31) {
1306 DPRINTF("xhci: bad ep %d\n", epid);
1307 return CC_TRB_ERROR;
1308 }
1309
1310 slot = &xhci->slots[slotid-1];
1311
1312 if (!slot->eps[epid-1]) {
1313 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1314 return CC_EP_NOT_ENABLED_ERROR;
1315 }
1316
1317 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
1318 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1319 "data might be lost\n");
1320 }
1321
1322 epctx = slot->eps[epid-1];
1323
1324 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1325
1326 if (epctx->nr_pstreams) {
1327 xhci_reset_streams(epctx);
1328 }
1329
1330 return CC_SUCCESS;
1331 }
1332
1333 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1334 unsigned int epid)
1335 {
1336 XHCISlot *slot;
1337 XHCIEPContext *epctx;
1338
1339 trace_usb_xhci_ep_reset(slotid, epid);
1340 assert(slotid >= 1 && slotid <= xhci->numslots);
1341
1342 if (epid < 1 || epid > 31) {
1343 DPRINTF("xhci: bad ep %d\n", epid);
1344 return CC_TRB_ERROR;
1345 }
1346
1347 slot = &xhci->slots[slotid-1];
1348
1349 if (!slot->eps[epid-1]) {
1350 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1351 return CC_EP_NOT_ENABLED_ERROR;
1352 }
1353
1354 epctx = slot->eps[epid-1];
1355
1356 if (epctx->state != EP_HALTED) {
1357 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1358 epid, epctx->state);
1359 return CC_CONTEXT_STATE_ERROR;
1360 }
1361
1362 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
1363 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1364 "data might be lost\n");
1365 }
1366
1367 if (!xhci->slots[slotid-1].uport ||
1368 !xhci->slots[slotid-1].uport->dev ||
1369 !xhci->slots[slotid-1].uport->dev->attached) {
1370 return CC_USB_TRANSACTION_ERROR;
1371 }
1372
1373 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1374
1375 if (epctx->nr_pstreams) {
1376 xhci_reset_streams(epctx);
1377 }
1378
1379 return CC_SUCCESS;
1380 }
1381
1382 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1383 unsigned int epid, unsigned int streamid,
1384 uint64_t pdequeue)
1385 {
1386 XHCISlot *slot;
1387 XHCIEPContext *epctx;
1388 XHCIStreamContext *sctx;
1389 dma_addr_t dequeue;
1390
1391 assert(slotid >= 1 && slotid <= xhci->numslots);
1392
1393 if (epid < 1 || epid > 31) {
1394 DPRINTF("xhci: bad ep %d\n", epid);
1395 return CC_TRB_ERROR;
1396 }
1397
1398 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1399 dequeue = xhci_mask64(pdequeue);
1400
1401 slot = &xhci->slots[slotid-1];
1402
1403 if (!slot->eps[epid-1]) {
1404 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1405 return CC_EP_NOT_ENABLED_ERROR;
1406 }
1407
1408 epctx = slot->eps[epid-1];
1409
1410 if (epctx->state != EP_STOPPED) {
1411 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1412 return CC_CONTEXT_STATE_ERROR;
1413 }
1414
1415 if (epctx->nr_pstreams) {
1416 uint32_t err;
1417 sctx = xhci_find_stream(epctx, streamid, &err);
1418 if (sctx == NULL) {
1419 return err;
1420 }
1421 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1422 sctx->ring.ccs = dequeue & 1;
1423 } else {
1424 sctx = NULL;
1425 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1426 epctx->ring.ccs = dequeue & 1;
1427 }
1428
1429 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1430
1431 return CC_SUCCESS;
1432 }
1433
1434 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1435 {
1436 XHCIState *xhci = xfer->epctx->xhci;
1437 int i;
1438
1439 xfer->int_req = false;
1440 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
1441 for (i = 0; i < xfer->trb_count; i++) {
1442 XHCITRB *trb = &xfer->trbs[i];
1443 dma_addr_t addr;
1444 unsigned int chunk = 0;
1445
1446 if (trb->control & TRB_TR_IOC) {
1447 xfer->int_req = true;
1448 }
1449
1450 switch (TRB_TYPE(*trb)) {
1451 case TR_DATA:
1452 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1453 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1454 goto err;
1455 }
1456 /* fallthrough */
1457 case TR_NORMAL:
1458 case TR_ISOCH:
1459 addr = xhci_mask64(trb->parameter);
1460 chunk = trb->status & 0x1ffff;
1461 if (trb->control & TRB_TR_IDT) {
1462 if (chunk > 8 || in_xfer) {
1463 DPRINTF("xhci: invalid immediate data TRB\n");
1464 goto err;
1465 }
1466 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1467 } else {
1468 qemu_sglist_add(&xfer->sgl, addr, chunk);
1469 }
1470 break;
1471 }
1472 }
1473
1474 return 0;
1475
1476 err:
1477 qemu_sglist_destroy(&xfer->sgl);
1478 xhci_die(xhci);
1479 return -1;
1480 }
1481
1482 static void xhci_xfer_unmap(XHCITransfer *xfer)
1483 {
1484 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1485 qemu_sglist_destroy(&xfer->sgl);
1486 }
1487
1488 static void xhci_xfer_report(XHCITransfer *xfer)
1489 {
1490 uint32_t edtla = 0;
1491 unsigned int left;
1492 bool reported = 0;
1493 bool shortpkt = 0;
1494 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1495 XHCIState *xhci = xfer->epctx->xhci;
1496 int i;
1497
1498 left = xfer->packet.actual_length;
1499
1500 for (i = 0; i < xfer->trb_count; i++) {
1501 XHCITRB *trb = &xfer->trbs[i];
1502 unsigned int chunk = 0;
1503
1504 switch (TRB_TYPE(*trb)) {
1505 case TR_SETUP:
1506 chunk = trb->status & 0x1ffff;
1507 if (chunk > 8) {
1508 chunk = 8;
1509 }
1510 break;
1511 case TR_DATA:
1512 case TR_NORMAL:
1513 case TR_ISOCH:
1514 chunk = trb->status & 0x1ffff;
1515 if (chunk > left) {
1516 chunk = left;
1517 if (xfer->status == CC_SUCCESS) {
1518 shortpkt = 1;
1519 }
1520 }
1521 left -= chunk;
1522 edtla += chunk;
1523 break;
1524 case TR_STATUS:
1525 reported = 0;
1526 shortpkt = 0;
1527 break;
1528 }
1529
1530 if (!reported && ((trb->control & TRB_TR_IOC) ||
1531 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1532 (xfer->status != CC_SUCCESS && left == 0))) {
1533 event.slotid = xfer->epctx->slotid;
1534 event.epid = xfer->epctx->epid;
1535 event.length = (trb->status & 0x1ffff) - chunk;
1536 event.flags = 0;
1537 event.ptr = trb->addr;
1538 if (xfer->status == CC_SUCCESS) {
1539 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1540 } else {
1541 event.ccode = xfer->status;
1542 }
1543 if (TRB_TYPE(*trb) == TR_EVDATA) {
1544 event.ptr = trb->parameter;
1545 event.flags |= TRB_EV_ED;
1546 event.length = edtla & 0xffffff;
1547 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1548 edtla = 0;
1549 }
1550 xhci_event(xhci, &event, TRB_INTR(*trb));
1551 reported = 1;
1552 if (xfer->status != CC_SUCCESS) {
1553 return;
1554 }
1555 }
1556
1557 switch (TRB_TYPE(*trb)) {
1558 case TR_SETUP:
1559 reported = 0;
1560 shortpkt = 0;
1561 break;
1562 }
1563
1564 }
1565 }
1566
1567 static void xhci_stall_ep(XHCITransfer *xfer)
1568 {
1569 XHCIEPContext *epctx = xfer->epctx;
1570 XHCIState *xhci = epctx->xhci;
1571 uint32_t err;
1572 XHCIStreamContext *sctx;
1573
1574 if (epctx->nr_pstreams) {
1575 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1576 if (sctx == NULL) {
1577 return;
1578 }
1579 sctx->ring.dequeue = xfer->trbs[0].addr;
1580 sctx->ring.ccs = xfer->trbs[0].ccs;
1581 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1582 } else {
1583 epctx->ring.dequeue = xfer->trbs[0].addr;
1584 epctx->ring.ccs = xfer->trbs[0].ccs;
1585 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1586 }
1587 }
1588
1589 static int xhci_setup_packet(XHCITransfer *xfer)
1590 {
1591 USBEndpoint *ep;
1592 int dir;
1593
1594 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1595
1596 if (xfer->packet.ep) {
1597 ep = xfer->packet.ep;
1598 } else {
1599 ep = xhci_epid_to_usbep(xfer->epctx);
1600 if (!ep) {
1601 DPRINTF("xhci: slot %d has no device\n",
1602 xfer->epctx->slotid);
1603 return -1;
1604 }
1605 }
1606
1607 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1608 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1609 xfer->trbs[0].addr, false, xfer->int_req);
1610 usb_packet_map(&xfer->packet, &xfer->sgl);
1611 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1612 xfer->packet.pid, ep->dev->addr, ep->nr);
1613 return 0;
1614 }
1615
1616 static int xhci_try_complete_packet(XHCITransfer *xfer)
1617 {
1618 if (xfer->packet.status == USB_RET_ASYNC) {
1619 trace_usb_xhci_xfer_async(xfer);
1620 xfer->running_async = 1;
1621 xfer->running_retry = 0;
1622 xfer->complete = 0;
1623 return 0;
1624 } else if (xfer->packet.status == USB_RET_NAK) {
1625 trace_usb_xhci_xfer_nak(xfer);
1626 xfer->running_async = 0;
1627 xfer->running_retry = 1;
1628 xfer->complete = 0;
1629 return 0;
1630 } else {
1631 xfer->running_async = 0;
1632 xfer->running_retry = 0;
1633 xfer->complete = 1;
1634 xhci_xfer_unmap(xfer);
1635 }
1636
1637 if (xfer->packet.status == USB_RET_SUCCESS) {
1638 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1639 xfer->status = CC_SUCCESS;
1640 xhci_xfer_report(xfer);
1641 return 0;
1642 }
1643
1644 /* error */
1645 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1646 switch (xfer->packet.status) {
1647 case USB_RET_NODEV:
1648 case USB_RET_IOERROR:
1649 xfer->status = CC_USB_TRANSACTION_ERROR;
1650 xhci_xfer_report(xfer);
1651 xhci_stall_ep(xfer);
1652 break;
1653 case USB_RET_STALL:
1654 xfer->status = CC_STALL_ERROR;
1655 xhci_xfer_report(xfer);
1656 xhci_stall_ep(xfer);
1657 break;
1658 case USB_RET_BABBLE:
1659 xfer->status = CC_BABBLE_DETECTED;
1660 xhci_xfer_report(xfer);
1661 xhci_stall_ep(xfer);
1662 break;
1663 default:
1664 DPRINTF("%s: FIXME: status = %d\n", __func__,
1665 xfer->packet.status);
1666 FIXME("unhandled USB_RET_*");
1667 }
1668 return 0;
1669 }
1670
1671 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1672 {
1673 XHCITRB *trb_setup, *trb_status;
1674 uint8_t bmRequestType;
1675
1676 trb_setup = &xfer->trbs[0];
1677 trb_status = &xfer->trbs[xfer->trb_count-1];
1678
1679 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1680 xfer->epctx->epid, xfer->streamid);
1681
1682 /* at most one Event Data TRB allowed after STATUS */
1683 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1684 trb_status--;
1685 }
1686
1687 /* do some sanity checks */
1688 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1689 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1690 TRB_TYPE(*trb_setup));
1691 return -1;
1692 }
1693 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1694 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1695 TRB_TYPE(*trb_status));
1696 return -1;
1697 }
1698 if (!(trb_setup->control & TRB_TR_IDT)) {
1699 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1700 return -1;
1701 }
1702 if ((trb_setup->status & 0x1ffff) != 8) {
1703 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1704 (trb_setup->status & 0x1ffff));
1705 return -1;
1706 }
1707
1708 bmRequestType = trb_setup->parameter;
1709
1710 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1711 xfer->iso_xfer = false;
1712 xfer->timed_xfer = false;
1713
1714 if (xhci_setup_packet(xfer) < 0) {
1715 return -1;
1716 }
1717 xfer->packet.parameter = trb_setup->parameter;
1718
1719 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1720 xhci_try_complete_packet(xfer);
1721 return 0;
1722 }
1723
1724 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1725 XHCIEPContext *epctx, uint64_t mfindex)
1726 {
1727 uint64_t asap = ((mfindex + epctx->interval - 1) &
1728 ~(epctx->interval-1));
1729 uint64_t kick = epctx->mfindex_last + epctx->interval;
1730
1731 assert(epctx->interval != 0);
1732 xfer->mfindex_kick = MAX(asap, kick);
1733 }
1734
1735 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1736 XHCIEPContext *epctx, uint64_t mfindex)
1737 {
1738 if (xfer->trbs[0].control & TRB_TR_SIA) {
1739 uint64_t asap = ((mfindex + epctx->interval - 1) &
1740 ~(epctx->interval-1));
1741 if (asap >= epctx->mfindex_last &&
1742 asap <= epctx->mfindex_last + epctx->interval * 4) {
1743 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1744 } else {
1745 xfer->mfindex_kick = asap;
1746 }
1747 } else {
1748 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1749 & TRB_TR_FRAMEID_MASK) << 3;
1750 xfer->mfindex_kick |= mfindex & ~0x3fff;
1751 if (xfer->mfindex_kick + 0x100 < mfindex) {
1752 xfer->mfindex_kick += 0x4000;
1753 }
1754 }
1755 }
1756
1757 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1758 XHCIEPContext *epctx, uint64_t mfindex)
1759 {
1760 if (xfer->mfindex_kick > mfindex) {
1761 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1762 (xfer->mfindex_kick - mfindex) * 125000);
1763 xfer->running_retry = 1;
1764 } else {
1765 epctx->mfindex_last = xfer->mfindex_kick;
1766 timer_del(epctx->kick_timer);
1767 xfer->running_retry = 0;
1768 }
1769 }
1770
1771
1772 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1773 {
1774 uint64_t mfindex;
1775
1776 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx->slotid, epctx->epid);
1777
1778 xfer->in_xfer = epctx->type>>2;
1779
1780 switch(epctx->type) {
1781 case ET_INTR_OUT:
1782 case ET_INTR_IN:
1783 xfer->pkts = 0;
1784 xfer->iso_xfer = false;
1785 xfer->timed_xfer = true;
1786 mfindex = xhci_mfindex_get(xhci);
1787 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
1788 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1789 if (xfer->running_retry) {
1790 return -1;
1791 }
1792 break;
1793 case ET_BULK_OUT:
1794 case ET_BULK_IN:
1795 xfer->pkts = 0;
1796 xfer->iso_xfer = false;
1797 xfer->timed_xfer = false;
1798 break;
1799 case ET_ISO_OUT:
1800 case ET_ISO_IN:
1801 xfer->pkts = 1;
1802 xfer->iso_xfer = true;
1803 xfer->timed_xfer = true;
1804 mfindex = xhci_mfindex_get(xhci);
1805 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
1806 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1807 if (xfer->running_retry) {
1808 return -1;
1809 }
1810 break;
1811 default:
1812 trace_usb_xhci_unimplemented("endpoint type", epctx->type);
1813 return -1;
1814 }
1815
1816 if (xhci_setup_packet(xfer) < 0) {
1817 return -1;
1818 }
1819 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1820 xhci_try_complete_packet(xfer);
1821 return 0;
1822 }
1823
1824 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1825 {
1826 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1827 xfer->epctx->epid, xfer->streamid);
1828 return xhci_submit(xhci, xfer, epctx);
1829 }
1830
1831 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
1832 unsigned int epid, unsigned int streamid)
1833 {
1834 XHCIEPContext *epctx;
1835
1836 assert(slotid >= 1 && slotid <= xhci->numslots);
1837 assert(epid >= 1 && epid <= 31);
1838
1839 if (!xhci->slots[slotid-1].enabled) {
1840 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1841 return;
1842 }
1843 epctx = xhci->slots[slotid-1].eps[epid-1];
1844 if (!epctx) {
1845 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1846 epid, slotid);
1847 return;
1848 }
1849
1850 if (epctx->kick_active) {
1851 return;
1852 }
1853 xhci_kick_epctx(epctx, streamid);
1854 }
1855
1856 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid)
1857 {
1858 XHCIState *xhci = epctx->xhci;
1859 XHCIStreamContext *stctx = NULL;
1860 XHCITransfer *xfer;
1861 XHCIRing *ring;
1862 USBEndpoint *ep = NULL;
1863 uint64_t mfindex;
1864 unsigned int count = 0;
1865 int length;
1866 int i;
1867
1868 trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid);
1869 assert(!epctx->kick_active);
1870
1871 /* If the device has been detached, but the guest has not noticed this
1872 yet the 2 above checks will succeed, but we must NOT continue */
1873 if (!xhci->slots[epctx->slotid - 1].uport ||
1874 !xhci->slots[epctx->slotid - 1].uport->dev ||
1875 !xhci->slots[epctx->slotid - 1].uport->dev->attached) {
1876 return;
1877 }
1878
1879 if (epctx->retry) {
1880 XHCITransfer *xfer = epctx->retry;
1881
1882 trace_usb_xhci_xfer_retry(xfer);
1883 assert(xfer->running_retry);
1884 if (xfer->timed_xfer) {
1885 /* time to kick the transfer? */
1886 mfindex = xhci_mfindex_get(xhci);
1887 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1888 if (xfer->running_retry) {
1889 return;
1890 }
1891 xfer->timed_xfer = 0;
1892 xfer->running_retry = 1;
1893 }
1894 if (xfer->iso_xfer) {
1895 /* retry iso transfer */
1896 if (xhci_setup_packet(xfer) < 0) {
1897 return;
1898 }
1899 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1900 assert(xfer->packet.status != USB_RET_NAK);
1901 xhci_try_complete_packet(xfer);
1902 } else {
1903 /* retry nak'ed transfer */
1904 if (xhci_setup_packet(xfer) < 0) {
1905 return;
1906 }
1907 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1908 if (xfer->packet.status == USB_RET_NAK) {
1909 return;
1910 }
1911 xhci_try_complete_packet(xfer);
1912 }
1913 assert(!xfer->running_retry);
1914 if (xfer->complete) {
1915 xhci_ep_free_xfer(epctx->retry);
1916 }
1917 epctx->retry = NULL;
1918 }
1919
1920 if (epctx->state == EP_HALTED) {
1921 DPRINTF("xhci: ep halted, not running schedule\n");
1922 return;
1923 }
1924
1925
1926 if (epctx->nr_pstreams) {
1927 uint32_t err;
1928 stctx = xhci_find_stream(epctx, streamid, &err);
1929 if (stctx == NULL) {
1930 return;
1931 }
1932 ring = &stctx->ring;
1933 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
1934 } else {
1935 ring = &epctx->ring;
1936 streamid = 0;
1937 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
1938 }
1939 assert(ring->dequeue != 0);
1940
1941 epctx->kick_active++;
1942 while (1) {
1943 length = xhci_ring_chain_length(xhci, ring);
1944 if (length <= 0) {
1945 break;
1946 }
1947 xfer = xhci_ep_alloc_xfer(epctx, length);
1948 if (xfer == NULL) {
1949 break;
1950 }
1951
1952 for (i = 0; i < length; i++) {
1953 TRBType type;
1954 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL);
1955 assert(type);
1956 }
1957 xfer->streamid = streamid;
1958
1959 if (epctx->epid == 1) {
1960 xhci_fire_ctl_transfer(xhci, xfer);
1961 } else {
1962 xhci_fire_transfer(xhci, xfer, epctx);
1963 }
1964 if (xfer->complete) {
1965 xhci_ep_free_xfer(xfer);
1966 xfer = NULL;
1967 }
1968
1969 if (epctx->state == EP_HALTED) {
1970 break;
1971 }
1972 if (xfer != NULL && xfer->running_retry) {
1973 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1974 epctx->retry = xfer;
1975 break;
1976 }
1977 if (count++ > TRANSFER_LIMIT) {
1978 trace_usb_xhci_enforced_limit("transfers");
1979 break;
1980 }
1981 }
1982 /* update ring dequeue ptr */
1983 xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
1984 epctx->kick_active--;
1985
1986 ep = xhci_epid_to_usbep(epctx);
1987 if (ep) {
1988 usb_device_flush_ep_queue(ep->dev, ep);
1989 }
1990 }
1991
1992 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1993 {
1994 trace_usb_xhci_slot_enable(slotid);
1995 assert(slotid >= 1 && slotid <= xhci->numslots);
1996 xhci->slots[slotid-1].enabled = 1;
1997 xhci->slots[slotid-1].uport = NULL;
1998 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
1999
2000 return CC_SUCCESS;
2001 }
2002
2003 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2004 {
2005 int i;
2006
2007 trace_usb_xhci_slot_disable(slotid);
2008 assert(slotid >= 1 && slotid <= xhci->numslots);
2009
2010 for (i = 1; i <= 31; i++) {
2011 if (xhci->slots[slotid-1].eps[i-1]) {
2012 xhci_disable_ep(xhci, slotid, i);
2013 }
2014 }
2015
2016 xhci->slots[slotid-1].enabled = 0;
2017 xhci->slots[slotid-1].addressed = 0;
2018 xhci->slots[slotid-1].uport = NULL;
2019 return CC_SUCCESS;
2020 }
2021
2022 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2023 {
2024 USBPort *uport;
2025 char path[32];
2026 int i, pos, port;
2027
2028 port = (slot_ctx[1]>>16) & 0xFF;
2029 if (port < 1 || port > xhci->numports) {
2030 return NULL;
2031 }
2032 port = xhci->ports[port-1].uport->index+1;
2033 pos = snprintf(path, sizeof(path), "%d", port);
2034 for (i = 0; i < 5; i++) {
2035 port = (slot_ctx[0] >> 4*i) & 0x0f;
2036 if (!port) {
2037 break;
2038 }
2039 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2040 }
2041
2042 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2043 if (strcmp(uport->path, path) == 0) {
2044 return uport;
2045 }
2046 }
2047 return NULL;
2048 }
2049
2050 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2051 uint64_t pictx, bool bsr)
2052 {
2053 XHCISlot *slot;
2054 USBPort *uport;
2055 USBDevice *dev;
2056 dma_addr_t ictx, octx, dcbaap;
2057 uint64_t poctx;
2058 uint32_t ictl_ctx[2];
2059 uint32_t slot_ctx[4];
2060 uint32_t ep0_ctx[5];
2061 int i;
2062 TRBCCode res;
2063
2064 assert(slotid >= 1 && slotid <= xhci->numslots);
2065
2066 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2067 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
2068 ictx = xhci_mask64(pictx);
2069 octx = xhci_mask64(poctx);
2070
2071 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2072 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2073
2074 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2075
2076 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2077 DPRINTF("xhci: invalid input context control %08x %08x\n",
2078 ictl_ctx[0], ictl_ctx[1]);
2079 return CC_TRB_ERROR;
2080 }
2081
2082 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2083 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2084
2085 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2086 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2087
2088 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2089 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2090
2091 uport = xhci_lookup_uport(xhci, slot_ctx);
2092 if (uport == NULL) {
2093 DPRINTF("xhci: port not found\n");
2094 return CC_TRB_ERROR;
2095 }
2096 trace_usb_xhci_slot_address(slotid, uport->path);
2097
2098 dev = uport->dev;
2099 if (!dev || !dev->attached) {
2100 DPRINTF("xhci: port %s not connected\n", uport->path);
2101 return CC_USB_TRANSACTION_ERROR;
2102 }
2103
2104 for (i = 0; i < xhci->numslots; i++) {
2105 if (i == slotid-1) {
2106 continue;
2107 }
2108 if (xhci->slots[i].uport == uport) {
2109 DPRINTF("xhci: port %s already assigned to slot %d\n",
2110 uport->path, i+1);
2111 return CC_TRB_ERROR;
2112 }
2113 }
2114
2115 slot = &xhci->slots[slotid-1];
2116 slot->uport = uport;
2117 slot->ctx = octx;
2118
2119 /* Make sure device is in USB_STATE_DEFAULT state */
2120 usb_device_reset(dev);
2121 if (bsr) {
2122 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2123 } else {
2124 USBPacket p;
2125 uint8_t buf[1];
2126
2127 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2128 memset(&p, 0, sizeof(p));
2129 usb_packet_addbuf(&p, buf, sizeof(buf));
2130 usb_packet_setup(&p, USB_TOKEN_OUT,
2131 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2132 0, false, false);
2133 usb_device_handle_control(dev, &p,
2134 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2135 slotid, 0, 0, NULL);
2136 assert(p.status != USB_RET_ASYNC);
2137 }
2138
2139 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2140
2141 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2142 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2143 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2144 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2145
2146 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2147 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2148
2149 xhci->slots[slotid-1].addressed = 1;
2150 return res;
2151 }
2152
2153
2154 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2155 uint64_t pictx, bool dc)
2156 {
2157 dma_addr_t ictx, octx;
2158 uint32_t ictl_ctx[2];
2159 uint32_t slot_ctx[4];
2160 uint32_t islot_ctx[4];
2161 uint32_t ep_ctx[5];
2162 int i;
2163 TRBCCode res;
2164
2165 trace_usb_xhci_slot_configure(slotid);
2166 assert(slotid >= 1 && slotid <= xhci->numslots);
2167
2168 ictx = xhci_mask64(pictx);
2169 octx = xhci->slots[slotid-1].ctx;
2170
2171 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2172 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2173
2174 if (dc) {
2175 for (i = 2; i <= 31; i++) {
2176 if (xhci->slots[slotid-1].eps[i-1]) {
2177 xhci_disable_ep(xhci, slotid, i);
2178 }
2179 }
2180
2181 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2182 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2183 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2184 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2185 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2186 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2187
2188 return CC_SUCCESS;
2189 }
2190
2191 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2192
2193 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2194 DPRINTF("xhci: invalid input context control %08x %08x\n",
2195 ictl_ctx[0], ictl_ctx[1]);
2196 return CC_TRB_ERROR;
2197 }
2198
2199 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2200 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2201
2202 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2203 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);
2204 return CC_CONTEXT_STATE_ERROR;
2205 }
2206
2207 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2208
2209 for (i = 2; i <= 31; i++) {
2210 if (ictl_ctx[0] & (1<<i)) {
2211 xhci_disable_ep(xhci, slotid, i);
2212 }
2213 if (ictl_ctx[1] & (1<<i)) {
2214 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2215 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2216 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2217 ep_ctx[3], ep_ctx[4]);
2218 xhci_disable_ep(xhci, slotid, i);
2219 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2220 if (res != CC_SUCCESS) {
2221 return res;
2222 }
2223 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2224 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2225 ep_ctx[3], ep_ctx[4]);
2226 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2227 }
2228 }
2229
2230 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2231 if (res != CC_SUCCESS) {
2232 for (i = 2; i <= 31; i++) {
2233 if (ictl_ctx[1] & (1u << i)) {
2234 xhci_disable_ep(xhci, slotid, i);
2235 }
2236 }
2237 return res;
2238 }
2239
2240 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2241 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2242 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2243 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2244 SLOT_CONTEXT_ENTRIES_SHIFT);
2245 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2246 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2247
2248 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2249
2250 return CC_SUCCESS;
2251 }
2252
2253
2254 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2255 uint64_t pictx)
2256 {
2257 dma_addr_t ictx, octx;
2258 uint32_t ictl_ctx[2];
2259 uint32_t iep0_ctx[5];
2260 uint32_t ep0_ctx[5];
2261 uint32_t islot_ctx[4];
2262 uint32_t slot_ctx[4];
2263
2264 trace_usb_xhci_slot_evaluate(slotid);
2265 assert(slotid >= 1 && slotid <= xhci->numslots);
2266
2267 ictx = xhci_mask64(pictx);
2268 octx = xhci->slots[slotid-1].ctx;
2269
2270 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2271 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2272
2273 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2274
2275 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2276 DPRINTF("xhci: invalid input context control %08x %08x\n",
2277 ictl_ctx[0], ictl_ctx[1]);
2278 return CC_TRB_ERROR;
2279 }
2280
2281 if (ictl_ctx[1] & 0x1) {
2282 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2283
2284 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2285 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2286
2287 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2288
2289 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2290 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2291 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2292 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2293
2294 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2295 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2296
2297 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2298 }
2299
2300 if (ictl_ctx[1] & 0x2) {
2301 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2302
2303 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2304 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2305 iep0_ctx[3], iep0_ctx[4]);
2306
2307 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2308
2309 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2310 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2311
2312 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2313 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2314
2315 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2316 }
2317
2318 return CC_SUCCESS;
2319 }
2320
2321 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2322 {
2323 uint32_t slot_ctx[4];
2324 dma_addr_t octx;
2325 int i;
2326
2327 trace_usb_xhci_slot_reset(slotid);
2328 assert(slotid >= 1 && slotid <= xhci->numslots);
2329
2330 octx = xhci->slots[slotid-1].ctx;
2331
2332 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2333
2334 for (i = 2; i <= 31; i++) {
2335 if (xhci->slots[slotid-1].eps[i-1]) {
2336 xhci_disable_ep(xhci, slotid, i);
2337 }
2338 }
2339
2340 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2341 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2342 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2343 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2344 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2345 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2346
2347 return CC_SUCCESS;
2348 }
2349
2350 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2351 {
2352 unsigned int slotid;
2353 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2354 if (slotid < 1 || slotid > xhci->numslots) {
2355 DPRINTF("xhci: bad slot id %d\n", slotid);
2356 event->ccode = CC_TRB_ERROR;
2357 return 0;
2358 } else if (!xhci->slots[slotid-1].enabled) {
2359 DPRINTF("xhci: slot id %d not enabled\n", slotid);
2360 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2361 return 0;
2362 }
2363 return slotid;
2364 }
2365
2366 /* cleanup slot state on usb device detach */
2367 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2368 {
2369 int slot, ep;
2370
2371 for (slot = 0; slot < xhci->numslots; slot++) {
2372 if (xhci->slots[slot].uport == uport) {
2373 break;
2374 }
2375 }
2376 if (slot == xhci->numslots) {
2377 return;
2378 }
2379
2380 for (ep = 0; ep < 31; ep++) {
2381 if (xhci->slots[slot].eps[ep]) {
2382 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2383 }
2384 }
2385 xhci->slots[slot].uport = NULL;
2386 }
2387
2388 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2389 {
2390 dma_addr_t ctx;
2391 uint8_t bw_ctx[xhci->numports+1];
2392
2393 DPRINTF("xhci_get_port_bandwidth()\n");
2394
2395 ctx = xhci_mask64(pctx);
2396
2397 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2398
2399 /* TODO: actually implement real values here */
2400 bw_ctx[0] = 0;
2401 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
2402 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
2403
2404 return CC_SUCCESS;
2405 }
2406
2407 static uint32_t rotl(uint32_t v, unsigned count)
2408 {
2409 count &= 31;
2410 return (v << count) | (v >> (32 - count));
2411 }
2412
2413
2414 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2415 {
2416 uint32_t val;
2417 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2418 val += rotl(lo + 0x49434878, hi & 0x1F);
2419 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2420 return ~val;
2421 }
2422
2423 static void xhci_process_commands(XHCIState *xhci)
2424 {
2425 XHCITRB trb;
2426 TRBType type;
2427 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2428 dma_addr_t addr;
2429 unsigned int i, slotid = 0, count = 0;
2430
2431 DPRINTF("xhci_process_commands()\n");
2432 if (!xhci_running(xhci)) {
2433 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2434 return;
2435 }
2436
2437 xhci->crcr_low |= CRCR_CRR;
2438
2439 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2440 event.ptr = addr;
2441 switch (type) {
2442 case CR_ENABLE_SLOT:
2443 for (i = 0; i < xhci->numslots; i++) {
2444 if (!xhci->slots[i].enabled) {
2445 break;
2446 }
2447 }
2448 if (i >= xhci->numslots) {
2449 DPRINTF("xhci: no device slots available\n");
2450 event.ccode = CC_NO_SLOTS_ERROR;
2451 } else {
2452 slotid = i+1;
2453 event.ccode = xhci_enable_slot(xhci, slotid);
2454 }
2455 break;
2456 case CR_DISABLE_SLOT:
2457 slotid = xhci_get_slot(xhci, &event, &trb);
2458 if (slotid) {
2459 event.ccode = xhci_disable_slot(xhci, slotid);
2460 }
2461 break;
2462 case CR_ADDRESS_DEVICE:
2463 slotid = xhci_get_slot(xhci, &event, &trb);
2464 if (slotid) {
2465 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2466 trb.control & TRB_CR_BSR);
2467 }
2468 break;
2469 case CR_CONFIGURE_ENDPOINT:
2470 slotid = xhci_get_slot(xhci, &event, &trb);
2471 if (slotid) {
2472 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2473 trb.control & TRB_CR_DC);
2474 }
2475 break;
2476 case CR_EVALUATE_CONTEXT:
2477 slotid = xhci_get_slot(xhci, &event, &trb);
2478 if (slotid) {
2479 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2480 }
2481 break;
2482 case CR_STOP_ENDPOINT:
2483 slotid = xhci_get_slot(xhci, &event, &trb);
2484 if (slotid) {
2485 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2486 & TRB_CR_EPID_MASK;
2487 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2488 }
2489 break;
2490 case CR_RESET_ENDPOINT:
2491 slotid = xhci_get_slot(xhci, &event, &trb);
2492 if (slotid) {
2493 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2494 & TRB_CR_EPID_MASK;
2495 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2496 }
2497 break;
2498 case CR_SET_TR_DEQUEUE:
2499 slotid = xhci_get_slot(xhci, &event, &trb);
2500 if (slotid) {
2501 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2502 & TRB_CR_EPID_MASK;
2503 unsigned int streamid = (trb.status >> 16) & 0xffff;
2504 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2505 epid, streamid,
2506 trb.parameter);
2507 }
2508 break;
2509 case CR_RESET_DEVICE:
2510 slotid = xhci_get_slot(xhci, &event, &trb);
2511 if (slotid) {
2512 event.ccode = xhci_reset_slot(xhci, slotid);
2513 }
2514 break;
2515 case CR_GET_PORT_BANDWIDTH:
2516 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2517 break;
2518 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2519 if (xhci->nec_quirks) {
2520 event.type = 48; /* NEC reply */
2521 event.length = 0x3025;
2522 } else {
2523 event.ccode = CC_TRB_ERROR;
2524 }
2525 break;
2526 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2527 if (xhci->nec_quirks) {
2528 uint32_t chi = trb.parameter >> 32;
2529 uint32_t clo = trb.parameter;
2530 uint32_t val = xhci_nec_challenge(chi, clo);
2531 event.length = val & 0xFFFF;
2532 event.epid = val >> 16;
2533 slotid = val >> 24;
2534 event.type = 48; /* NEC reply */
2535 } else {
2536 event.ccode = CC_TRB_ERROR;
2537 }
2538 break;
2539 default:
2540 trace_usb_xhci_unimplemented("command", type);
2541 event.ccode = CC_TRB_ERROR;
2542 break;
2543 }
2544 event.slotid = slotid;
2545 xhci_event(xhci, &event, 0);
2546
2547 if (count++ > COMMAND_LIMIT) {
2548 trace_usb_xhci_enforced_limit("commands");
2549 return;
2550 }
2551 }
2552 }
2553
2554 static bool xhci_port_have_device(XHCIPort *port)
2555 {
2556 if (!port->uport->dev || !port->uport->dev->attached) {
2557 return false; /* no device present */
2558 }
2559 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2560 return false; /* speed mismatch */
2561 }
2562 return true;
2563 }
2564
2565 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2566 {
2567 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2568 port->portnr << 24 };
2569
2570 if ((port->portsc & bits) == bits) {
2571 return;
2572 }
2573 trace_usb_xhci_port_notify(port->portnr, bits);
2574 port->portsc |= bits;
2575 if (!xhci_running(port->xhci)) {
2576 return;
2577 }
2578 xhci_event(port->xhci, &ev, 0);
2579 }
2580
2581 static void xhci_port_update(XHCIPort *port, int is_detach)
2582 {
2583 uint32_t pls = PLS_RX_DETECT;
2584
2585 port->portsc = PORTSC_PP;
2586 if (!is_detach && xhci_port_have_device(port)) {
2587 port->portsc |= PORTSC_CCS;
2588 switch (port->uport->dev->speed) {
2589 case USB_SPEED_LOW:
2590 port->portsc |= PORTSC_SPEED_LOW;
2591 pls = PLS_POLLING;
2592 break;
2593 case USB_SPEED_FULL:
2594 port->portsc |= PORTSC_SPEED_FULL;
2595 pls = PLS_POLLING;
2596 break;
2597 case USB_SPEED_HIGH:
2598 port->portsc |= PORTSC_SPEED_HIGH;
2599 pls = PLS_POLLING;
2600 break;
2601 case USB_SPEED_SUPER:
2602 port->portsc |= PORTSC_SPEED_SUPER;
2603 port->portsc |= PORTSC_PED;
2604 pls = PLS_U0;
2605 break;
2606 }
2607 }
2608 set_field(&port->portsc, pls, PORTSC_PLS);
2609 trace_usb_xhci_port_link(port->portnr, pls);
2610 xhci_port_notify(port, PORTSC_CSC);
2611 }
2612
2613 static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2614 {
2615 trace_usb_xhci_port_reset(port->portnr, warm_reset);
2616
2617 if (!xhci_port_have_device(port)) {
2618 return;
2619 }
2620
2621 usb_device_reset(port->uport->dev);
2622
2623 switch (port->uport->dev->speed) {
2624 case USB_SPEED_SUPER:
2625 if (warm_reset) {
2626 port->portsc |= PORTSC_WRC;
2627 }
2628 /* fall through */
2629 case USB_SPEED_LOW:
2630 case USB_SPEED_FULL:
2631 case USB_SPEED_HIGH:
2632 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2633 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2634 port->portsc |= PORTSC_PED;
2635 break;
2636 }
2637
2638 port->portsc &= ~PORTSC_PR;
2639 xhci_port_notify(port, PORTSC_PRC);
2640 }
2641
2642 static void xhci_reset(DeviceState *dev)
2643 {
2644 XHCIState *xhci = XHCI(dev);
2645 int i;
2646
2647 trace_usb_xhci_reset();
2648 if (!(xhci->usbsts & USBSTS_HCH)) {
2649 DPRINTF("xhci: reset while running!\n");
2650 }
2651
2652 xhci->usbcmd = 0;
2653 xhci->usbsts = USBSTS_HCH;
2654 xhci->dnctrl = 0;
2655 xhci->crcr_low = 0;
2656 xhci->crcr_high = 0;
2657 xhci->dcbaap_low = 0;
2658 xhci->dcbaap_high = 0;
2659 xhci->config = 0;
2660
2661 for (i = 0; i < xhci->numslots; i++) {
2662 xhci_disable_slot(xhci, i+1);
2663 }
2664
2665 for (i = 0; i < xhci->numports; i++) {
2666 xhci_port_update(xhci->ports + i, 0);
2667 }
2668
2669 for (i = 0; i < xhci->numintrs; i++) {
2670 xhci->intr[i].iman = 0;
2671 xhci->intr[i].imod = 0;
2672 xhci->intr[i].erstsz = 0;
2673 xhci->intr[i].erstba_low = 0;
2674 xhci->intr[i].erstba_high = 0;
2675 xhci->intr[i].erdp_low = 0;
2676 xhci->intr[i].erdp_high = 0;
2677 xhci->intr[i].msix_used = 0;
2678
2679 xhci->intr[i].er_ep_idx = 0;
2680 xhci->intr[i].er_pcs = 1;
2681 xhci->intr[i].ev_buffer_put = 0;
2682 xhci->intr[i].ev_buffer_get = 0;
2683 }
2684
2685 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2686 xhci_mfwrap_update(xhci);
2687 }
2688
2689 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2690 {
2691 XHCIState *xhci = ptr;
2692 uint32_t ret;
2693
2694 switch (reg) {
2695 case 0x00: /* HCIVERSION, CAPLENGTH */
2696 ret = 0x01000000 | LEN_CAP;
2697 break;
2698 case 0x04: /* HCSPARAMS 1 */
2699 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2700 | (xhci->numintrs<<8) | xhci->numslots;
2701 break;
2702 case 0x08: /* HCSPARAMS 2 */
2703 ret = 0x0000000f;
2704 break;
2705 case 0x0c: /* HCSPARAMS 3 */
2706 ret = 0x00000000;
2707 break;
2708 case 0x10: /* HCCPARAMS */
2709 if (sizeof(dma_addr_t) == 4) {
2710 ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
2711 } else {
2712 ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
2713 }
2714 break;
2715 case 0x14: /* DBOFF */
2716 ret = OFF_DOORBELL;
2717 break;
2718 case 0x18: /* RTSOFF */
2719 ret = OFF_RUNTIME;
2720 break;
2721
2722 /* extended capabilities */
2723 case 0x20: /* Supported Protocol:00 */
2724 ret = 0x02000402; /* USB 2.0 */
2725 break;
2726 case 0x24: /* Supported Protocol:04 */
2727 ret = 0x20425355; /* "USB " */
2728 break;
2729 case 0x28: /* Supported Protocol:08 */
2730 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
2731 ret = (xhci->numports_2<<8) | (xhci->numports_3+1);
2732 } else {
2733 ret = (xhci->numports_2<<8) | 1;
2734 }
2735 break;
2736 case 0x2c: /* Supported Protocol:0c */
2737 ret = 0x00000000; /* reserved */
2738 break;
2739 case 0x30: /* Supported Protocol:00 */
2740 ret = 0x03000002; /* USB 3.0 */
2741 break;
2742 case 0x34: /* Supported Protocol:04 */
2743 ret = 0x20425355; /* "USB " */
2744 break;
2745 case 0x38: /* Supported Protocol:08 */
2746 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
2747 ret = (xhci->numports_3<<8) | 1;
2748 } else {
2749 ret = (xhci->numports_3<<8) | (xhci->numports_2+1);
2750 }
2751 break;
2752 case 0x3c: /* Supported Protocol:0c */
2753 ret = 0x00000000; /* reserved */
2754 break;
2755 default:
2756 trace_usb_xhci_unimplemented("cap read", reg);
2757 ret = 0;
2758 }
2759
2760 trace_usb_xhci_cap_read(reg, ret);
2761 return ret;
2762 }
2763
2764 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
2765 {
2766 XHCIPort *port = ptr;
2767 uint32_t ret;
2768
2769 switch (reg) {
2770 case 0x00: /* PORTSC */
2771 ret = port->portsc;
2772 break;
2773 case 0x04: /* PORTPMSC */
2774 case 0x08: /* PORTLI */
2775 ret = 0;
2776 break;
2777 case 0x0c: /* reserved */
2778 default:
2779 trace_usb_xhci_unimplemented("port read", reg);
2780 ret = 0;
2781 }
2782
2783 trace_usb_xhci_port_read(port->portnr, reg, ret);
2784 return ret;
2785 }
2786
2787 static void xhci_port_write(void *ptr, hwaddr reg,
2788 uint64_t val, unsigned size)
2789 {
2790 XHCIPort *port = ptr;
2791 uint32_t portsc, notify;
2792
2793 trace_usb_xhci_port_write(port->portnr, reg, val);
2794
2795 switch (reg) {
2796 case 0x00: /* PORTSC */
2797 /* write-1-to-start bits */
2798 if (val & PORTSC_WPR) {
2799 xhci_port_reset(port, true);
2800 break;
2801 }
2802 if (val & PORTSC_PR) {
2803 xhci_port_reset(port, false);
2804 break;
2805 }
2806
2807 portsc = port->portsc;
2808 notify = 0;
2809 /* write-1-to-clear bits*/
2810 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2811 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2812 if (val & PORTSC_LWS) {
2813 /* overwrite PLS only when LWS=1 */
2814 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
2815 uint32_t new_pls = get_field(val, PORTSC_PLS);
2816 switch (new_pls) {
2817 case PLS_U0:
2818 if (old_pls != PLS_U0) {
2819 set_field(&portsc, new_pls, PORTSC_PLS);
2820 trace_usb_xhci_port_link(port->portnr, new_pls);
2821 notify = PORTSC_PLC;
2822 }
2823 break;
2824 case PLS_U3:
2825 if (old_pls < PLS_U3) {
2826 set_field(&portsc, new_pls, PORTSC_PLS);
2827 trace_usb_xhci_port_link(port->portnr, new_pls);
2828 }
2829 break;
2830 case PLS_RESUME:
2831 /* windows does this for some reason, don't spam stderr */
2832 break;
2833 default:
2834 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
2835 __func__, old_pls, new_pls);
2836 break;
2837 }
2838 }
2839 /* read/write bits */
2840 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2841 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2842 port->portsc = portsc;
2843 if (notify) {
2844 xhci_port_notify(port, notify);
2845 }
2846 break;
2847 case 0x04: /* PORTPMSC */
2848 case 0x08: /* PORTLI */
2849 default:
2850 trace_usb_xhci_unimplemented("port write", reg);
2851 }
2852 }
2853
2854 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
2855 {
2856 XHCIState *xhci = ptr;
2857 uint32_t ret;
2858
2859 switch (reg) {
2860 case 0x00: /* USBCMD */
2861 ret = xhci->usbcmd;
2862 break;
2863 case 0x04: /* USBSTS */
2864 ret = xhci->usbsts;
2865 break;
2866 case 0x08: /* PAGESIZE */
2867 ret = 1; /* 4KiB */
2868 break;
2869 case 0x14: /* DNCTRL */
2870 ret = xhci->dnctrl;
2871 break;
2872 case 0x18: /* CRCR low */
2873 ret = xhci->crcr_low & ~0xe;
2874 break;
2875 case 0x1c: /* CRCR high */
2876 ret = xhci->crcr_high;
2877 break;
2878 case 0x30: /* DCBAAP low */
2879 ret = xhci->dcbaap_low;
2880 break;
2881 case 0x34: /* DCBAAP high */
2882 ret = xhci->dcbaap_high;
2883 break;
2884 case 0x38: /* CONFIG */
2885 ret = xhci->config;
2886 break;
2887 default:
2888 trace_usb_xhci_unimplemented("oper read", reg);
2889 ret = 0;
2890 }
2891
2892 trace_usb_xhci_oper_read(reg, ret);
2893 return ret;
2894 }
2895
2896 static void xhci_oper_write(void *ptr, hwaddr reg,
2897 uint64_t val, unsigned size)
2898 {
2899 XHCIState *xhci = ptr;
2900 DeviceState *d = DEVICE(ptr);
2901
2902 trace_usb_xhci_oper_write(reg, val);
2903
2904 switch (reg) {
2905 case 0x00: /* USBCMD */
2906 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2907 xhci_run(xhci);
2908 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2909 xhci_stop(xhci);
2910 }
2911 if (val & USBCMD_CSS) {
2912 /* save state */
2913 xhci->usbsts &= ~USBSTS_SRE;
2914 }
2915 if (val & USBCMD_CRS) {
2916 /* restore state */
2917 xhci->usbsts |= USBSTS_SRE;
2918 }
2919 xhci->usbcmd = val & 0xc0f;
2920 xhci_mfwrap_update(xhci);
2921 if (val & USBCMD_HCRST) {
2922 xhci_reset(d);
2923 }
2924 xhci_intx_update(xhci);
2925 break;
2926
2927 case 0x04: /* USBSTS */
2928 /* these bits are write-1-to-clear */
2929 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2930 xhci_intx_update(xhci);
2931 break;
2932
2933 case 0x14: /* DNCTRL */
2934 xhci->dnctrl = val & 0xffff;
2935 break;
2936 case 0x18: /* CRCR low */
2937 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2938 break;
2939 case 0x1c: /* CRCR high */
2940 xhci->crcr_high = val;
2941 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2942 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2943 xhci->crcr_low &= ~CRCR_CRR;
2944 xhci_event(xhci, &event, 0);
2945 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2946 } else {
2947 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
2948 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2949 }
2950 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2951 break;
2952 case 0x30: /* DCBAAP low */
2953 xhci->dcbaap_low = val & 0xffffffc0;
2954 break;
2955 case 0x34: /* DCBAAP high */
2956 xhci->dcbaap_high = val;
2957 break;
2958 case 0x38: /* CONFIG */
2959 xhci->config = val & 0xff;
2960 break;
2961 default:
2962 trace_usb_xhci_unimplemented("oper write", reg);
2963 }
2964 }
2965
2966 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
2967 unsigned size)
2968 {
2969 XHCIState *xhci = ptr;
2970 uint32_t ret = 0;
2971
2972 if (reg < 0x20) {
2973 switch (reg) {
2974 case 0x00: /* MFINDEX */
2975 ret = xhci_mfindex_get(xhci) & 0x3fff;
2976 break;
2977 default:
2978 trace_usb_xhci_unimplemented("runtime read", reg);
2979 break;
2980 }
2981 } else {
2982 int v = (reg - 0x20) / 0x20;
2983 XHCIInterrupter *intr = &xhci->intr[v];
2984 switch (reg & 0x1f) {
2985 case 0x00: /* IMAN */
2986 ret = intr->iman;
2987 break;
2988 case 0x04: /* IMOD */
2989 ret = intr->imod;
2990 break;
2991 case 0x08: /* ERSTSZ */
2992 ret = intr->erstsz;
2993 break;
2994 case 0x10: /* ERSTBA low */
2995 ret = intr->erstba_low;
2996 break;
2997 case 0x14: /* ERSTBA high */
2998 ret = intr->erstba_high;
2999 break;
3000 case 0x18: /* ERDP low */
3001 ret = intr->erdp_low;
3002 break;
3003 case 0x1c: /* ERDP high */
3004 ret = intr->erdp_high;
3005 break;
3006 }
3007 }
3008
3009 trace_usb_xhci_runtime_read(reg, ret);
3010 return ret;
3011 }
3012
3013 static void xhci_runtime_write(void *ptr, hwaddr reg,
3014 uint64_t val, unsigned size)
3015 {
3016 XHCIState *xhci = ptr;
3017 int v = (reg - 0x20) / 0x20;
3018 XHCIInterrupter *intr = &xhci->intr[v];
3019 trace_usb_xhci_runtime_write(reg, val);
3020
3021 if (reg < 0x20) {
3022 trace_usb_xhci_unimplemented("runtime write", reg);
3023 return;
3024 }
3025
3026 switch (reg & 0x1f) {
3027 case 0x00: /* IMAN */
3028 if (val & IMAN_IP) {
3029 intr->iman &= ~IMAN_IP;
3030 }
3031 intr->iman &= ~IMAN_IE;
3032 intr->iman |= val & IMAN_IE;
3033 if (v == 0) {
3034 xhci_intx_update(xhci);
3035 }
3036 xhci_msix_update(xhci, v);
3037 break;
3038 case 0x04: /* IMOD */
3039 intr->imod = val;
3040 break;
3041 case 0x08: /* ERSTSZ */
3042 intr->erstsz = val & 0xffff;
3043 break;
3044 case 0x10: /* ERSTBA low */
3045 if (xhci->nec_quirks) {
3046 /* NEC driver bug: it doesn't align this to 64 bytes */
3047 intr->erstba_low = val & 0xfffffff0;
3048 } else {
3049 intr->erstba_low = val & 0xffffffc0;
3050 }
3051 break;
3052 case 0x14: /* ERSTBA high */
3053 intr->erstba_high = val;
3054 xhci_er_reset(xhci, v);
3055 break;
3056 case 0x18: /* ERDP low */
3057 if (val & ERDP_EHB) {
3058 intr->erdp_low &= ~ERDP_EHB;
3059 }
3060 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3061 if (val & ERDP_EHB) {
3062 dma_addr_t erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
3063 unsigned int dp_idx = (erdp - intr->er_start) / TRB_SIZE;
3064 if (erdp >= intr->er_start &&
3065 erdp < (intr->er_start + TRB_SIZE * intr->er_size) &&
3066 dp_idx != intr->er_ep_idx) {
3067 xhci_intr_raise(xhci, v);
3068 }
3069 }
3070 break;
3071 case 0x1c: /* ERDP high */
3072 intr->erdp_high = val;
3073 break;
3074 default:
3075 trace_usb_xhci_unimplemented("oper write", reg);
3076 }
3077 }
3078
3079 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3080 unsigned size)
3081 {
3082 /* doorbells always read as 0 */
3083 trace_usb_xhci_doorbell_read(reg, 0);
3084 return 0;
3085 }
3086
3087 static void xhci_doorbell_write(void *ptr, hwaddr reg,
3088 uint64_t val, unsigned size)
3089 {
3090 XHCIState *xhci = ptr;
3091 unsigned int epid, streamid;
3092
3093 trace_usb_xhci_doorbell_write(reg, val);
3094
3095 if (!xhci_running(xhci)) {
3096 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3097 return;
3098 }
3099
3100 reg >>= 2;
3101
3102 if (reg == 0) {
3103 if (val == 0) {
3104 xhci_process_commands(xhci);
3105 } else {
3106 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3107 (uint32_t)val);
3108 }
3109 } else {
3110 epid = val & 0xff;
3111 streamid = (val >> 16) & 0xffff;
3112 if (reg > xhci->numslots) {
3113 DPRINTF("xhci: bad doorbell %d\n", (int)reg);
3114 } else if (epid > 31) {
3115 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3116 (int)reg, (uint32_t)val);
3117 } else {
3118 xhci_kick_ep(xhci, reg, epid, streamid);
3119 }
3120 }
3121 }
3122
3123 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3124 unsigned width)
3125 {
3126 /* nothing */
3127 }
3128
3129 static const MemoryRegionOps xhci_cap_ops = {
3130 .read = xhci_cap_read,
3131 .write = xhci_cap_write,
3132 .valid.min_access_size = 1,
3133 .valid.max_access_size = 4,
3134 .impl.min_access_size = 4,
3135 .impl.max_access_size = 4,
3136 .endianness = DEVICE_LITTLE_ENDIAN,
3137 };
3138
3139 static const MemoryRegionOps xhci_oper_ops = {
3140 .read = xhci_oper_read,
3141 .write = xhci_oper_write,
3142 .valid.min_access_size = 4,
3143 .valid.max_access_size = 4,
3144 .endianness = DEVICE_LITTLE_ENDIAN,
3145 };
3146
3147 static const MemoryRegionOps xhci_port_ops = {
3148 .read = xhci_port_read,
3149 .write = xhci_port_write,
3150 .valid.min_access_size = 4,
3151 .valid.max_access_size = 4,
3152 .endianness = DEVICE_LITTLE_ENDIAN,
3153 };
3154
3155 static const MemoryRegionOps xhci_runtime_ops = {
3156 .read = xhci_runtime_read,
3157 .write = xhci_runtime_write,
3158 .valid.min_access_size = 4,
3159 .valid.max_access_size = 4,
3160 .endianness = DEVICE_LITTLE_ENDIAN,
3161 };
3162
3163 static const MemoryRegionOps xhci_doorbell_ops = {
3164 .read = xhci_doorbell_read,
3165 .write = xhci_doorbell_write,
3166 .valid.min_access_size = 4,
3167 .valid.max_access_size = 4,
3168 .endianness = DEVICE_LITTLE_ENDIAN,
3169 };
3170
3171 static void xhci_attach(USBPort *usbport)
3172 {
3173 XHCIState *xhci = usbport->opaque;
3174 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3175
3176 xhci_port_update(port, 0);
3177 }
3178
3179 static void xhci_detach(USBPort *usbport)
3180 {
3181 XHCIState *xhci = usbport->opaque;
3182 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3183
3184 xhci_detach_slot(xhci, usbport);
3185 xhci_port_update(port, 1);
3186 }
3187
3188 static void xhci_wakeup(USBPort *usbport)
3189 {
3190 XHCIState *xhci = usbport->opaque;
3191 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3192
3193 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
3194 return;
3195 }
3196 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3197 xhci_port_notify(port, PORTSC_PLC);
3198 }
3199
3200 static void xhci_complete(USBPort *port, USBPacket *packet)
3201 {
3202 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3203
3204 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
3205 xhci_ep_nuke_one_xfer(xfer, 0);
3206 return;
3207 }
3208 xhci_try_complete_packet(xfer);
3209 xhci_kick_epctx(xfer->epctx, xfer->streamid);
3210 if (xfer->complete) {
3211 xhci_ep_free_xfer(xfer);
3212 }
3213 }
3214
3215 static void xhci_child_detach(USBPort *uport, USBDevice *child)
3216 {
3217 USBBus *bus = usb_bus_from_device(child);
3218 XHCIState *xhci = container_of(bus, XHCIState, bus);
3219
3220 xhci_detach_slot(xhci, child->port);
3221 }
3222
3223 static USBPortOps xhci_uport_ops = {
3224 .attach = xhci_attach,
3225 .detach = xhci_detach,
3226 .wakeup = xhci_wakeup,
3227 .complete = xhci_complete,
3228 .child_detach = xhci_child_detach,
3229 };
3230
3231 static int xhci_find_epid(USBEndpoint *ep)
3232 {
3233 if (ep->nr == 0) {
3234 return 1;
3235 }
3236 if (ep->pid == USB_TOKEN_IN) {
3237 return ep->nr * 2 + 1;
3238 } else {
3239 return ep->nr * 2;
3240 }
3241 }
3242
3243 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx)
3244 {
3245 USBPort *uport;
3246 uint32_t token;
3247
3248 if (!epctx) {
3249 return NULL;
3250 }
3251 uport = epctx->xhci->slots[epctx->slotid - 1].uport;
3252 token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT;
3253 if (!uport) {
3254 return NULL;
3255 }
3256 return usb_ep_get(uport->dev, token, epctx->epid >> 1);
3257 }
3258
3259 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3260 unsigned int stream)
3261 {
3262 XHCIState *xhci = container_of(bus, XHCIState, bus);
3263 int slotid;
3264
3265 DPRINTF("%s\n", __func__);
3266 slotid = ep->dev->addr;
3267 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3268 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3269 return;
3270 }
3271 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3272 }
3273
3274 static USBBusOps xhci_bus_ops = {
3275 .wakeup_endpoint = xhci_wakeup_endpoint,
3276 };
3277
3278 static void usb_xhci_init(XHCIState *xhci)
3279 {
3280 DeviceState *dev = DEVICE(xhci);
3281 XHCIPort *port;
3282 int i, usbports, speedmask;
3283
3284 xhci->usbsts = USBSTS_HCH;
3285
3286 if (xhci->numports_2 > MAXPORTS_2) {
3287 xhci->numports_2 = MAXPORTS_2;
3288 }
3289 if (xhci->numports_3 > MAXPORTS_3) {
3290 xhci->numports_3 = MAXPORTS_3;
3291 }
3292 usbports = MAX(xhci->numports_2, xhci->numports_3);
3293 xhci->numports = xhci->numports_2 + xhci->numports_3;
3294
3295 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
3296
3297 for (i = 0; i < usbports; i++) {
3298 speedmask = 0;
3299 if (i < xhci->numports_2) {
3300 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3301 port = &xhci->ports[i + xhci->numports_3];
3302 port->portnr = i + 1 + xhci->numports_3;
3303 } else {
3304 port = &xhci->ports[i];
3305 port->portnr = i + 1;
3306 }
3307 port->uport = &xhci->uports[i];
3308 port->speedmask =
3309 USB_SPEED_MASK_LOW |
3310 USB_SPEED_MASK_FULL |
3311 USB_SPEED_MASK_HIGH;
3312 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3313 speedmask |= port->speedmask;
3314 }
3315 if (i < xhci->numports_3) {
3316 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3317 port = &xhci->ports[i];
3318 port->portnr = i + 1;
3319 } else {
3320 port = &xhci->ports[i + xhci->numports_2];
3321 port->portnr = i + 1 + xhci->numports_2;
3322 }
3323 port->uport = &xhci->uports[i];
3324 port->speedmask = USB_SPEED_MASK_SUPER;
3325 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3326 speedmask |= port->speedmask;
3327 }
3328 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3329 &xhci_uport_ops, speedmask);
3330 }
3331 }
3332
3333 static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
3334 {
3335 int i, ret;
3336 Error *err = NULL;
3337
3338 XHCIState *xhci = XHCI(dev);
3339
3340 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
3341 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
3342 dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
3343 dev->config[0x60] = 0x30; /* release number */
3344
3345 if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) {
3346 xhci->nec_quirks = true;
3347 }
3348 if (xhci->numintrs > MAXINTRS) {
3349 xhci->numintrs = MAXINTRS;
3350 }
3351 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3352 xhci->numintrs++;
3353 }
3354 if (xhci->numintrs < 1) {
3355 xhci->numintrs = 1;
3356 }
3357 if (xhci->numslots > MAXSLOTS) {
3358 xhci->numslots = MAXSLOTS;
3359 }
3360 if (xhci->numslots < 1) {
3361 xhci->numslots = 1;
3362 }
3363 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) {
3364 xhci->max_pstreams_mask = 7; /* == 256 primary streams */
3365 } else {
3366 xhci->max_pstreams_mask = 0;
3367 }
3368
3369 if (xhci->msi != ON_OFF_AUTO_OFF) {
3370 ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err);
3371 /* Any error other than -ENOTSUP(board's MSI support is broken)
3372 * is a programming error */
3373 assert(!ret || ret == -ENOTSUP);
3374 if (ret && xhci->msi == ON_OFF_AUTO_ON) {
3375 /* Can't satisfy user's explicit msi=on request, fail */
3376 error_append_hint(&err, "You have to use msi=auto (default) or "
3377 "msi=off with this machine type.\n");
3378 error_propagate(errp, err);
3379 return;
3380 }
3381 assert(!err || xhci->msi == ON_OFF_AUTO_AUTO);
3382 /* With msi=auto, we fall back to MSI off silently */
3383 error_free(err);
3384 }
3385
3386 usb_xhci_init(xhci);
3387 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3388
3389 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
3390 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
3391 "capabilities", LEN_CAP);
3392 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
3393 "operational", 0x400);
3394 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
3395 "runtime", LEN_RUNTIME);
3396 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
3397 "doorbell", LEN_DOORBELL);
3398
3399 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3400 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3401 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3402 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3403
3404 for (i = 0; i < xhci->numports; i++) {
3405 XHCIPort *port = &xhci->ports[i];
3406 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3407 port->xhci = xhci;
3408 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
3409 port->name, 0x10);
3410 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3411 }
3412
3413 pci_register_bar(dev, 0,
3414 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
3415 &xhci->mem);
3416
3417 if (pci_bus_is_express(dev->bus) ||
3418 xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
3419 ret = pcie_endpoint_cap_init(dev, 0xa0);
3420 assert(ret >= 0);
3421 }
3422
3423 if (xhci->msix != ON_OFF_AUTO_OFF) {
3424 /* TODO check for errors, and should fail when msix=on */
3425 msix_init(dev, xhci->numintrs,
3426 &xhci->mem, 0, OFF_MSIX_TABLE,
3427 &xhci->mem, 0, OFF_MSIX_PBA,
3428 0x90, NULL);
3429 }
3430 }
3431
3432 static void usb_xhci_exit(PCIDevice *dev)
3433 {
3434 int i;
3435 XHCIState *xhci = XHCI(dev);
3436
3437 trace_usb_xhci_exit();
3438
3439 for (i = 0; i < xhci->numslots; i++) {
3440 xhci_disable_slot(xhci, i + 1);
3441 }
3442
3443 if (xhci->mfwrap_timer) {
3444 timer_del(xhci->mfwrap_timer);
3445 timer_free(xhci->mfwrap_timer);
3446 xhci->mfwrap_timer = NULL;
3447 }
3448
3449 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap);
3450 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper);
3451 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime);
3452 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell);
3453
3454 for (i = 0; i < xhci->numports; i++) {
3455 XHCIPort *port = &xhci->ports[i];
3456 memory_region_del_subregion(&xhci->mem, &port->mem);
3457 }
3458
3459 /* destroy msix memory region */
3460 if (dev->msix_table && dev->msix_pba
3461 && dev->msix_entry_used) {
3462 msix_uninit(dev, &xhci->mem, &xhci->mem);
3463 }
3464
3465 usb_bus_release(&xhci->bus);
3466 }
3467
3468 static int usb_xhci_post_load(void *opaque, int version_id)
3469 {
3470 XHCIState *xhci = opaque;
3471 PCIDevice *pci_dev = PCI_DEVICE(xhci);
3472 XHCISlot *slot;
3473 XHCIEPContext *epctx;
3474 dma_addr_t dcbaap, pctx;
3475 uint32_t slot_ctx[4];
3476 uint32_t ep_ctx[5];
3477 int slotid, epid, state, intr;
3478
3479 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3480
3481 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3482 slot = &xhci->slots[slotid-1];
3483 if (!slot->addressed) {
3484 continue;
3485 }
3486 slot->ctx =
3487 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
3488 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3489 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3490 if (!slot->uport) {
3491 /* should not happen, but may trigger on guest bugs */
3492 slot->enabled = 0;
3493 slot->addressed = 0;
3494 continue;
3495 }
3496 assert(slot->uport && slot->uport->dev);
3497
3498 for (epid = 1; epid <= 31; epid++) {
3499 pctx = slot->ctx + 32 * epid;
3500 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3501 state = ep_ctx[0] & EP_STATE_MASK;
3502 if (state == EP_DISABLED) {
3503 continue;
3504 }
3505 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3506 slot->eps[epid-1] = epctx;
3507 xhci_init_epctx(epctx, pctx, ep_ctx);
3508 epctx->state = state;
3509 if (state == EP_RUNNING) {
3510 /* kick endpoint after vmload is finished */
3511 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3512 }
3513 }
3514 }
3515
3516 for (intr = 0; intr < xhci->numintrs; intr++) {
3517 if (xhci->intr[intr].msix_used) {
3518 msix_vector_use(pci_dev, intr);
3519 } else {
3520 msix_vector_unuse(pci_dev, intr);
3521 }
3522 }
3523
3524 return 0;
3525 }
3526
3527 static const VMStateDescription vmstate_xhci_ring = {
3528 .name = "xhci-ring",
3529 .version_id = 1,
3530 .fields = (VMStateField[]) {
3531 VMSTATE_UINT64(dequeue, XHCIRing),
3532 VMSTATE_BOOL(ccs, XHCIRing),
3533 VMSTATE_END_OF_LIST()
3534 }
3535 };
3536
3537 static const VMStateDescription vmstate_xhci_port = {
3538 .name = "xhci-port",
3539 .version_id = 1,
3540 .fields = (VMStateField[]) {
3541 VMSTATE_UINT32(portsc, XHCIPort),
3542 VMSTATE_END_OF_LIST()
3543 }
3544 };
3545
3546 static const VMStateDescription vmstate_xhci_slot = {
3547 .name = "xhci-slot",
3548 .version_id = 1,
3549 .fields = (VMStateField[]) {
3550 VMSTATE_BOOL(enabled, XHCISlot),
3551 VMSTATE_BOOL(addressed, XHCISlot),
3552 VMSTATE_END_OF_LIST()
3553 }
3554 };
3555
3556 static const VMStateDescription vmstate_xhci_event = {
3557 .name = "xhci-event",
3558 .version_id = 1,
3559 .fields = (VMStateField[]) {
3560 VMSTATE_UINT32(type, XHCIEvent),
3561 VMSTATE_UINT32(ccode, XHCIEvent),
3562 VMSTATE_UINT64(ptr, XHCIEvent),
3563 VMSTATE_UINT32(length, XHCIEvent),
3564 VMSTATE_UINT32(flags, XHCIEvent),
3565 VMSTATE_UINT8(slotid, XHCIEvent),
3566 VMSTATE_UINT8(epid, XHCIEvent),
3567 VMSTATE_END_OF_LIST()
3568 }
3569 };
3570
3571 static bool xhci_er_full(void *opaque, int version_id)
3572 {
3573 return false;
3574 }
3575
3576 static const VMStateDescription vmstate_xhci_intr = {
3577 .name = "xhci-intr",
3578 .version_id = 1,
3579 .fields = (VMStateField[]) {
3580 /* registers */
3581 VMSTATE_UINT32(iman, XHCIInterrupter),
3582 VMSTATE_UINT32(imod, XHCIInterrupter),
3583 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3584 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3585 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3586 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3587 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3588
3589 /* state */
3590 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3591 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3592 VMSTATE_UINT64(er_start, XHCIInterrupter),
3593 VMSTATE_UINT32(er_size, XHCIInterrupter),
3594 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3595
3596 /* event queue (used if ring is full) */
3597 VMSTATE_BOOL(er_full_unused, XHCIInterrupter),
3598 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3599 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3600 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3601 xhci_er_full, 1,
3602 vmstate_xhci_event, XHCIEvent),
3603
3604 VMSTATE_END_OF_LIST()
3605 }
3606 };
3607
3608 static const VMStateDescription vmstate_xhci = {
3609 .name = "xhci",
3610 .version_id = 1,
3611 .post_load = usb_xhci_post_load,
3612 .fields = (VMStateField[]) {
3613 VMSTATE_PCI_DEVICE(parent_obj, XHCIState),
3614 VMSTATE_MSIX(parent_obj, XHCIState),
3615
3616 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3617 vmstate_xhci_port, XHCIPort),
3618 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3619 vmstate_xhci_slot, XHCISlot),
3620 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3621 vmstate_xhci_intr, XHCIInterrupter),
3622
3623 /* Operational Registers */
3624 VMSTATE_UINT32(usbcmd, XHCIState),
3625 VMSTATE_UINT32(usbsts, XHCIState),
3626 VMSTATE_UINT32(dnctrl, XHCIState),
3627 VMSTATE_UINT32(crcr_low, XHCIState),
3628 VMSTATE_UINT32(crcr_high, XHCIState),
3629 VMSTATE_UINT32(dcbaap_low, XHCIState),
3630 VMSTATE_UINT32(dcbaap_high, XHCIState),
3631 VMSTATE_UINT32(config, XHCIState),
3632
3633 /* Runtime Registers & state */
3634 VMSTATE_INT64(mfindex_start, XHCIState),
3635 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState),
3636 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3637
3638 VMSTATE_END_OF_LIST()
3639 }
3640 };
3641
3642 static Property xhci_properties[] = {
3643 DEFINE_PROP_BIT("streams", XHCIState, flags,
3644 XHCI_FLAG_ENABLE_STREAMS, true),
3645 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3646 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
3647 DEFINE_PROP_END_OF_LIST(),
3648 };
3649
3650 static void xhci_class_init(ObjectClass *klass, void *data)
3651 {
3652 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3653 DeviceClass *dc = DEVICE_CLASS(klass);
3654
3655 dc->vmsd = &vmstate_xhci;
3656 dc->props = xhci_properties;
3657 dc->reset = xhci_reset;
3658 set_bit(DEVICE_CATEGORY_USB, dc->categories);
3659 k->realize = usb_xhci_realize;
3660 k->exit = usb_xhci_exit;
3661 k->class_id = PCI_CLASS_SERIAL_USB;
3662 k->is_express = 1;
3663 }
3664
3665 static const TypeInfo xhci_info = {
3666 .name = TYPE_XHCI,
3667 .parent = TYPE_PCI_DEVICE,
3668 .instance_size = sizeof(XHCIState),
3669 .class_init = xhci_class_init,
3670 .abstract = true,
3671 };
3672
3673 static void qemu_xhci_class_init(ObjectClass *klass, void *data)
3674 {
3675 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3676
3677 k->vendor_id = PCI_VENDOR_ID_REDHAT;
3678 k->device_id = PCI_DEVICE_ID_REDHAT_XHCI;
3679 k->revision = 0x01;
3680 }
3681
3682 static void qemu_xhci_instance_init(Object *obj)
3683 {
3684 XHCIState *xhci = XHCI(obj);
3685
3686 xhci->msi = ON_OFF_AUTO_OFF;
3687 xhci->msix = ON_OFF_AUTO_AUTO;
3688 xhci->numintrs = MAXINTRS;
3689 xhci->numslots = MAXSLOTS;
3690 xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
3691 }
3692
3693 static const TypeInfo qemu_xhci_info = {
3694 .name = TYPE_QEMU_XHCI,
3695 .parent = TYPE_XHCI,
3696 .class_init = qemu_xhci_class_init,
3697 .instance_init = qemu_xhci_instance_init,
3698 };
3699
3700 static void xhci_register_types(void)
3701 {
3702 type_register_static(&xhci_info);
3703 type_register_static(&qemu_xhci_info);
3704 }
3705
3706 type_init(xhci_register_types)
AR7 emulation for QEMU