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virtio fix cfg endian-ness for BE targets
[qemu/ar7.git] / target-i386 / kvm.c
blob9038bf70779df766e9f5ce07d2cdbb4c95ea3e38
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm_int.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include <asm/hyperv.h>
37 #include "hw/pci/pci.h"
38 #include "migration/migration.h"
39 #include "exec/memattrs.h"
40
41 //#define DEBUG_KVM
42
43 #ifdef DEBUG_KVM
44 #define DPRINTF(fmt, ...) \
45 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
46 #else
47 #define DPRINTF(fmt, ...) \
48 do { } while (0)
49 #endif
50
51 #define MSR_KVM_WALL_CLOCK 0x11
52 #define MSR_KVM_SYSTEM_TIME 0x12
53
54 #ifndef BUS_MCEERR_AR
55 #define BUS_MCEERR_AR 4
56 #endif
57 #ifndef BUS_MCEERR_AO
58 #define BUS_MCEERR_AO 5
59 #endif
60
61 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
62 KVM_CAP_INFO(SET_TSS_ADDR),
63 KVM_CAP_INFO(EXT_CPUID),
64 KVM_CAP_INFO(MP_STATE),
65 KVM_CAP_LAST_INFO
66 };
67
68 static bool has_msr_star;
69 static bool has_msr_hsave_pa;
70 static bool has_msr_tsc_adjust;
71 static bool has_msr_tsc_deadline;
72 static bool has_msr_feature_control;
73 static bool has_msr_async_pf_en;
74 static bool has_msr_pv_eoi_en;
75 static bool has_msr_misc_enable;
76 static bool has_msr_smbase;
77 static bool has_msr_bndcfgs;
78 static bool has_msr_kvm_steal_time;
79 static int lm_capable_kernel;
80 static bool has_msr_hv_hypercall;
81 static bool has_msr_hv_vapic;
82 static bool has_msr_hv_tsc;
83 static bool has_msr_mtrr;
84 static bool has_msr_xss;
85
86 static bool has_msr_architectural_pmu;
87 static uint32_t num_architectural_pmu_counters;
88
89 bool kvm_has_smm(void)
90 {
91 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
92 }
93
94 bool kvm_allows_irq0_override(void)
95 {
96 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
97 }
98
99 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
100 {
101 struct kvm_cpuid2 *cpuid;
102 int r, size;
103
104 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
105 cpuid = g_malloc0(size);
106 cpuid->nent = max;
107 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
108 if (r == 0 && cpuid->nent >= max) {
109 r = -E2BIG;
110 }
111 if (r < 0) {
112 if (r == -E2BIG) {
113 g_free(cpuid);
114 return NULL;
115 } else {
116 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
117 strerror(-r));
118 exit(1);
119 }
120 }
121 return cpuid;
122 }
123
124 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
125 * for all entries.
126 */
127 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
128 {
129 struct kvm_cpuid2 *cpuid;
130 int max = 1;
131 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
132 max *= 2;
133 }
134 return cpuid;
135 }
136
137 static const struct kvm_para_features {
138 int cap;
139 int feature;
140 } para_features[] = {
141 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
142 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
143 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
144 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
145 };
146
147 static int get_para_features(KVMState *s)
148 {
149 int i, features = 0;
150
151 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
152 if (kvm_check_extension(s, para_features[i].cap)) {
153 features |= (1 << para_features[i].feature);
154 }
155 }
156
157 return features;
158 }
159
160
161 /* Returns the value for a specific register on the cpuid entry
162 */
163 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
164 {
165 uint32_t ret = 0;
166 switch (reg) {
167 case R_EAX:
168 ret = entry->eax;
169 break;
170 case R_EBX:
171 ret = entry->ebx;
172 break;
173 case R_ECX:
174 ret = entry->ecx;
175 break;
176 case R_EDX:
177 ret = entry->edx;
178 break;
179 }
180 return ret;
181 }
182
183 /* Find matching entry for function/index on kvm_cpuid2 struct
184 */
185 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
186 uint32_t function,
187 uint32_t index)
188 {
189 int i;
190 for (i = 0; i < cpuid->nent; ++i) {
191 if (cpuid->entries[i].function == function &&
192 cpuid->entries[i].index == index) {
193 return &cpuid->entries[i];
194 }
195 }
196 /* not found: */
197 return NULL;
198 }
199
200 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
201 uint32_t index, int reg)
202 {
203 struct kvm_cpuid2 *cpuid;
204 uint32_t ret = 0;
205 uint32_t cpuid_1_edx;
206 bool found = false;
207
208 cpuid = get_supported_cpuid(s);
209
210 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
211 if (entry) {
212 found = true;
213 ret = cpuid_entry_get_reg(entry, reg);
214 }
215
216 /* Fixups for the data returned by KVM, below */
217
218 if (function == 1 && reg == R_EDX) {
219 /* KVM before 2.6.30 misreports the following features */
220 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
221 } else if (function == 1 && reg == R_ECX) {
222 /* We can set the hypervisor flag, even if KVM does not return it on
223 * GET_SUPPORTED_CPUID
224 */
225 ret |= CPUID_EXT_HYPERVISOR;
226 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
227 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
228 * and the irqchip is in the kernel.
229 */
230 if (kvm_irqchip_in_kernel() &&
231 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
232 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
233 }
234
235 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
236 * without the in-kernel irqchip
237 */
238 if (!kvm_irqchip_in_kernel()) {
239 ret &= ~CPUID_EXT_X2APIC;
240 }
241 } else if (function == 0x80000001 && reg == R_EDX) {
242 /* On Intel, kvm returns cpuid according to the Intel spec,
243 * so add missing bits according to the AMD spec:
244 */
245 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
246 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
247 }
248
249 g_free(cpuid);
250
251 /* fallback for older kernels */
252 if ((function == KVM_CPUID_FEATURES) && !found) {
253 ret = get_para_features(s);
254 }
255
256 return ret;
257 }
258
259 typedef struct HWPoisonPage {
260 ram_addr_t ram_addr;
261 QLIST_ENTRY(HWPoisonPage) list;
262 } HWPoisonPage;
263
264 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
265 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
266
267 static void kvm_unpoison_all(void *param)
268 {
269 HWPoisonPage *page, *next_page;
270
271 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
272 QLIST_REMOVE(page, list);
273 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
274 g_free(page);
275 }
276 }
277
278 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
279 {
280 HWPoisonPage *page;
281
282 QLIST_FOREACH(page, &hwpoison_page_list, list) {
283 if (page->ram_addr == ram_addr) {
284 return;
285 }
286 }
287 page = g_new(HWPoisonPage, 1);
288 page->ram_addr = ram_addr;
289 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
290 }
291
292 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
293 int *max_banks)
294 {
295 int r;
296
297 r = kvm_check_extension(s, KVM_CAP_MCE);
298 if (r > 0) {
299 *max_banks = r;
300 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
301 }
302 return -ENOSYS;
303 }
304
305 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
306 {
307 CPUX86State *env = &cpu->env;
308 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
309 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
310 uint64_t mcg_status = MCG_STATUS_MCIP;
311
312 if (code == BUS_MCEERR_AR) {
313 status |= MCI_STATUS_AR | 0x134;
314 mcg_status |= MCG_STATUS_EIPV;
315 } else {
316 status |= 0xc0;
317 mcg_status |= MCG_STATUS_RIPV;
318 }
319 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
320 (MCM_ADDR_PHYS << 6) | 0xc,
321 cpu_x86_support_mca_broadcast(env) ?
322 MCE_INJECT_BROADCAST : 0);
323 }
324
325 static void hardware_memory_error(void)
326 {
327 fprintf(stderr, "Hardware memory error!\n");
328 exit(1);
329 }
330
331 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
332 {
333 X86CPU *cpu = X86_CPU(c);
334 CPUX86State *env = &cpu->env;
335 ram_addr_t ram_addr;
336 hwaddr paddr;
337
338 if ((env->mcg_cap & MCG_SER_P) && addr
339 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
340 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
341 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
342 fprintf(stderr, "Hardware memory error for memory used by "
343 "QEMU itself instead of guest system!\n");
344 /* Hope we are lucky for AO MCE */
345 if (code == BUS_MCEERR_AO) {
346 return 0;
347 } else {
348 hardware_memory_error();
349 }
350 }
351 kvm_hwpoison_page_add(ram_addr);
352 kvm_mce_inject(cpu, paddr, code);
353 } else {
354 if (code == BUS_MCEERR_AO) {
355 return 0;
356 } else if (code == BUS_MCEERR_AR) {
357 hardware_memory_error();
358 } else {
359 return 1;
360 }
361 }
362 return 0;
363 }
364
365 int kvm_arch_on_sigbus(int code, void *addr)
366 {
367 X86CPU *cpu = X86_CPU(first_cpu);
368
369 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
370 ram_addr_t ram_addr;
371 hwaddr paddr;
372
373 /* Hope we are lucky for AO MCE */
374 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
375 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
376 addr, &paddr)) {
377 fprintf(stderr, "Hardware memory error for memory used by "
378 "QEMU itself instead of guest system!: %p\n", addr);
379 return 0;
380 }
381 kvm_hwpoison_page_add(ram_addr);
382 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
383 } else {
384 if (code == BUS_MCEERR_AO) {
385 return 0;
386 } else if (code == BUS_MCEERR_AR) {
387 hardware_memory_error();
388 } else {
389 return 1;
390 }
391 }
392 return 0;
393 }
394
395 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
396 {
397 CPUX86State *env = &cpu->env;
398
399 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
400 unsigned int bank, bank_num = env->mcg_cap & 0xff;
401 struct kvm_x86_mce mce;
402
403 env->exception_injected = -1;
404
405 /*
406 * There must be at least one bank in use if an MCE is pending.
407 * Find it and use its values for the event injection.
408 */
409 for (bank = 0; bank < bank_num; bank++) {
410 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
411 break;
412 }
413 }
414 assert(bank < bank_num);
415
416 mce.bank = bank;
417 mce.status = env->mce_banks[bank * 4 + 1];
418 mce.mcg_status = env->mcg_status;
419 mce.addr = env->mce_banks[bank * 4 + 2];
420 mce.misc = env->mce_banks[bank * 4 + 3];
421
422 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
423 }
424 return 0;
425 }
426
427 static void cpu_update_state(void *opaque, int running, RunState state)
428 {
429 CPUX86State *env = opaque;
430
431 if (running) {
432 env->tsc_valid = false;
433 }
434 }
435
436 unsigned long kvm_arch_vcpu_id(CPUState *cs)
437 {
438 X86CPU *cpu = X86_CPU(cs);
439 return cpu->apic_id;
440 }
441
442 #ifndef KVM_CPUID_SIGNATURE_NEXT
443 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
444 #endif
445
446 static bool hyperv_hypercall_available(X86CPU *cpu)
447 {
448 return cpu->hyperv_vapic ||
449 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
450 }
451
452 static bool hyperv_enabled(X86CPU *cpu)
453 {
454 CPUState *cs = CPU(cpu);
455 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
456 (hyperv_hypercall_available(cpu) ||
457 cpu->hyperv_time ||
458 cpu->hyperv_relaxed_timing);
459 }
460
461 static Error *invtsc_mig_blocker;
462
463 #define KVM_MAX_CPUID_ENTRIES 100
464
465 int kvm_arch_init_vcpu(CPUState *cs)
466 {
467 struct {
468 struct kvm_cpuid2 cpuid;
469 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
470 } QEMU_PACKED cpuid_data;
471 X86CPU *cpu = X86_CPU(cs);
472 CPUX86State *env = &cpu->env;
473 uint32_t limit, i, j, cpuid_i;
474 uint32_t unused;
475 struct kvm_cpuid_entry2 *c;
476 uint32_t signature[3];
477 int kvm_base = KVM_CPUID_SIGNATURE;
478 int r;
479
480 memset(&cpuid_data, 0, sizeof(cpuid_data));
481
482 cpuid_i = 0;
483
484 /* Paravirtualization CPUIDs */
485 if (hyperv_enabled(cpu)) {
486 c = &cpuid_data.entries[cpuid_i++];
487 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
488 memcpy(signature, "Microsoft Hv", 12);
489 c->eax = HYPERV_CPUID_MIN;
490 c->ebx = signature[0];
491 c->ecx = signature[1];
492 c->edx = signature[2];
493
494 c = &cpuid_data.entries[cpuid_i++];
495 c->function = HYPERV_CPUID_INTERFACE;
496 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
497 c->eax = signature[0];
498 c->ebx = 0;
499 c->ecx = 0;
500 c->edx = 0;
501
502 c = &cpuid_data.entries[cpuid_i++];
503 c->function = HYPERV_CPUID_VERSION;
504 c->eax = 0x00001bbc;
505 c->ebx = 0x00060001;
506
507 c = &cpuid_data.entries[cpuid_i++];
508 c->function = HYPERV_CPUID_FEATURES;
509 if (cpu->hyperv_relaxed_timing) {
510 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
511 }
512 if (cpu->hyperv_vapic) {
513 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
514 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
515 has_msr_hv_vapic = true;
516 }
517 if (cpu->hyperv_time &&
518 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
519 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
520 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
521 c->eax |= 0x200;
522 has_msr_hv_tsc = true;
523 }
524 c = &cpuid_data.entries[cpuid_i++];
525 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
526 if (cpu->hyperv_relaxed_timing) {
527 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
528 }
529 if (has_msr_hv_vapic) {
530 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
531 }
532 c->ebx = cpu->hyperv_spinlock_attempts;
533
534 c = &cpuid_data.entries[cpuid_i++];
535 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
536 c->eax = 0x40;
537 c->ebx = 0x40;
538
539 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
540 has_msr_hv_hypercall = true;
541 }
542
543 if (cpu->expose_kvm) {
544 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
545 c = &cpuid_data.entries[cpuid_i++];
546 c->function = KVM_CPUID_SIGNATURE | kvm_base;
547 c->eax = KVM_CPUID_FEATURES | kvm_base;
548 c->ebx = signature[0];
549 c->ecx = signature[1];
550 c->edx = signature[2];
551
552 c = &cpuid_data.entries[cpuid_i++];
553 c->function = KVM_CPUID_FEATURES | kvm_base;
554 c->eax = env->features[FEAT_KVM];
555
556 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
557
558 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
559
560 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
561 }
562
563 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
564
565 for (i = 0; i <= limit; i++) {
566 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
567 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
568 abort();
569 }
570 c = &cpuid_data.entries[cpuid_i++];
571
572 switch (i) {
573 case 2: {
574 /* Keep reading function 2 till all the input is received */
575 int times;
576
577 c->function = i;
578 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
579 KVM_CPUID_FLAG_STATE_READ_NEXT;
580 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
581 times = c->eax & 0xff;
582
583 for (j = 1; j < times; ++j) {
584 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
585 fprintf(stderr, "cpuid_data is full, no space for "
586 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
587 abort();
588 }
589 c = &cpuid_data.entries[cpuid_i++];
590 c->function = i;
591 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
592 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
593 }
594 break;
595 }
596 case 4:
597 case 0xb:
598 case 0xd:
599 for (j = 0; ; j++) {
600 if (i == 0xd && j == 64) {
601 break;
602 }
603 c->function = i;
604 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
605 c->index = j;
606 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
607
608 if (i == 4 && c->eax == 0) {
609 break;
610 }
611 if (i == 0xb && !(c->ecx & 0xff00)) {
612 break;
613 }
614 if (i == 0xd && c->eax == 0) {
615 continue;
616 }
617 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
618 fprintf(stderr, "cpuid_data is full, no space for "
619 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
620 abort();
621 }
622 c = &cpuid_data.entries[cpuid_i++];
623 }
624 break;
625 default:
626 c->function = i;
627 c->flags = 0;
628 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
629 break;
630 }
631 }
632
633 if (limit >= 0x0a) {
634 uint32_t ver;
635
636 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
637 if ((ver & 0xff) > 0) {
638 has_msr_architectural_pmu = true;
639 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
640
641 /* Shouldn't be more than 32, since that's the number of bits
642 * available in EBX to tell us _which_ counters are available.
643 * Play it safe.
644 */
645 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
646 num_architectural_pmu_counters = MAX_GP_COUNTERS;
647 }
648 }
649 }
650
651 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
652
653 for (i = 0x80000000; i <= limit; i++) {
654 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
655 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
656 abort();
657 }
658 c = &cpuid_data.entries[cpuid_i++];
659
660 c->function = i;
661 c->flags = 0;
662 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
663 }
664
665 /* Call Centaur's CPUID instructions they are supported. */
666 if (env->cpuid_xlevel2 > 0) {
667 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
668
669 for (i = 0xC0000000; i <= limit; i++) {
670 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
671 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
672 abort();
673 }
674 c = &cpuid_data.entries[cpuid_i++];
675
676 c->function = i;
677 c->flags = 0;
678 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
679 }
680 }
681
682 cpuid_data.cpuid.nent = cpuid_i;
683
684 if (((env->cpuid_version >> 8)&0xF) >= 6
685 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
686 (CPUID_MCE | CPUID_MCA)
687 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
688 uint64_t mcg_cap;
689 int banks;
690 int ret;
691
692 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
693 if (ret < 0) {
694 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
695 return ret;
696 }
697
698 if (banks > MCE_BANKS_DEF) {
699 banks = MCE_BANKS_DEF;
700 }
701 mcg_cap &= MCE_CAP_DEF;
702 mcg_cap |= banks;
703 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
704 if (ret < 0) {
705 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
706 return ret;
707 }
708
709 env->mcg_cap = mcg_cap;
710 }
711
712 qemu_add_vm_change_state_handler(cpu_update_state, env);
713
714 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
715 if (c) {
716 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
717 !!(c->ecx & CPUID_EXT_SMX);
718 }
719
720 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
721 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
722 /* for migration */
723 error_setg(&invtsc_mig_blocker,
724 "State blocked by non-migratable CPU device"
725 " (invtsc flag)");
726 migrate_add_blocker(invtsc_mig_blocker);
727 /* for savevm */
728 vmstate_x86_cpu.unmigratable = 1;
729 }
730
731 cpuid_data.cpuid.padding = 0;
732 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
733 if (r) {
734 return r;
735 }
736
737 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
738 if (r && env->tsc_khz) {
739 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
740 if (r < 0) {
741 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
742 return r;
743 }
744 }
745
746 if (kvm_has_xsave()) {
747 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
748 }
749
750 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
751 has_msr_mtrr = true;
752 }
753
754 return 0;
755 }
756
757 void kvm_arch_reset_vcpu(X86CPU *cpu)
758 {
759 CPUX86State *env = &cpu->env;
760
761 env->exception_injected = -1;
762 env->interrupt_injected = -1;
763 env->xcr0 = 1;
764 if (kvm_irqchip_in_kernel()) {
765 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
766 KVM_MP_STATE_UNINITIALIZED;
767 } else {
768 env->mp_state = KVM_MP_STATE_RUNNABLE;
769 }
770 }
771
772 void kvm_arch_do_init_vcpu(X86CPU *cpu)
773 {
774 CPUX86State *env = &cpu->env;
775
776 /* APs get directly into wait-for-SIPI state. */
777 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
778 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
779 }
780 }
781
782 static int kvm_get_supported_msrs(KVMState *s)
783 {
784 static int kvm_supported_msrs;
785 int ret = 0;
786
787 /* first time */
788 if (kvm_supported_msrs == 0) {
789 struct kvm_msr_list msr_list, *kvm_msr_list;
790
791 kvm_supported_msrs = -1;
792
793 /* Obtain MSR list from KVM. These are the MSRs that we must
794 * save/restore */
795 msr_list.nmsrs = 0;
796 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
797 if (ret < 0 && ret != -E2BIG) {
798 return ret;
799 }
800 /* Old kernel modules had a bug and could write beyond the provided
801 memory. Allocate at least a safe amount of 1K. */
802 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
803 msr_list.nmsrs *
804 sizeof(msr_list.indices[0])));
805
806 kvm_msr_list->nmsrs = msr_list.nmsrs;
807 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
808 if (ret >= 0) {
809 int i;
810
811 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
812 if (kvm_msr_list->indices[i] == MSR_STAR) {
813 has_msr_star = true;
814 continue;
815 }
816 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
817 has_msr_hsave_pa = true;
818 continue;
819 }
820 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
821 has_msr_tsc_adjust = true;
822 continue;
823 }
824 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
825 has_msr_tsc_deadline = true;
826 continue;
827 }
828 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
829 has_msr_smbase = true;
830 continue;
831 }
832 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
833 has_msr_misc_enable = true;
834 continue;
835 }
836 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
837 has_msr_bndcfgs = true;
838 continue;
839 }
840 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
841 has_msr_xss = true;
842 continue;
843 }
844 }
845 }
846
847 g_free(kvm_msr_list);
848 }
849
850 return ret;
851 }
852
853 static Notifier smram_machine_done;
854 static KVMMemoryListener smram_listener;
855 static AddressSpace smram_address_space;
856 static MemoryRegion smram_as_root;
857 static MemoryRegion smram_as_mem;
858
859 static void register_smram_listener(Notifier *n, void *unused)
860 {
861 MemoryRegion *smram =
862 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
863
864 /* Outer container... */
865 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
866 memory_region_set_enabled(&smram_as_root, true);
867
868 /* ... with two regions inside: normal system memory with low
869 * priority, and...
870 */
871 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
872 get_system_memory(), 0, ~0ull);
873 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
874 memory_region_set_enabled(&smram_as_mem, true);
875
876 if (smram) {
877 /* ... SMRAM with higher priority */
878 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
879 memory_region_set_enabled(smram, true);
880 }
881
882 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
883 kvm_memory_listener_register(kvm_state, &smram_listener,
884 &smram_address_space, 1);
885 }
886
887 int kvm_arch_init(MachineState *ms, KVMState *s)
888 {
889 uint64_t identity_base = 0xfffbc000;
890 uint64_t shadow_mem;
891 int ret;
892 struct utsname utsname;
893
894 ret = kvm_get_supported_msrs(s);
895 if (ret < 0) {
896 return ret;
897 }
898
899 uname(&utsname);
900 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
901
902 /*
903 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
904 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
905 * Since these must be part of guest physical memory, we need to allocate
906 * them, both by setting their start addresses in the kernel and by
907 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
908 *
909 * Older KVM versions may not support setting the identity map base. In
910 * that case we need to stick with the default, i.e. a 256K maximum BIOS
911 * size.
912 */
913 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
914 /* Allows up to 16M BIOSes. */
915 identity_base = 0xfeffc000;
916
917 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
918 if (ret < 0) {
919 return ret;
920 }
921 }
922
923 /* Set TSS base one page after EPT identity map. */
924 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
925 if (ret < 0) {
926 return ret;
927 }
928
929 /* Tell fw_cfg to notify the BIOS to reserve the range. */
930 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
931 if (ret < 0) {
932 fprintf(stderr, "e820_add_entry() table is full\n");
933 return ret;
934 }
935 qemu_register_reset(kvm_unpoison_all, NULL);
936
937 shadow_mem = machine_kvm_shadow_mem(ms);
938 if (shadow_mem != -1) {
939 shadow_mem /= 4096;
940 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
941 if (ret < 0) {
942 return ret;
943 }
944 }
945
946 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
947 smram_machine_done.notify = register_smram_listener;
948 qemu_add_machine_init_done_notifier(&smram_machine_done);
949 }
950 return 0;
951 }
952
953 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
954 {
955 lhs->selector = rhs->selector;
956 lhs->base = rhs->base;
957 lhs->limit = rhs->limit;
958 lhs->type = 3;
959 lhs->present = 1;
960 lhs->dpl = 3;
961 lhs->db = 0;
962 lhs->s = 1;
963 lhs->l = 0;
964 lhs->g = 0;
965 lhs->avl = 0;
966 lhs->unusable = 0;
967 }
968
969 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
970 {
971 unsigned flags = rhs->flags;
972 lhs->selector = rhs->selector;
973 lhs->base = rhs->base;
974 lhs->limit = rhs->limit;
975 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
976 lhs->present = (flags & DESC_P_MASK) != 0;
977 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
978 lhs->db = (flags >> DESC_B_SHIFT) & 1;
979 lhs->s = (flags & DESC_S_MASK) != 0;
980 lhs->l = (flags >> DESC_L_SHIFT) & 1;
981 lhs->g = (flags & DESC_G_MASK) != 0;
982 lhs->avl = (flags & DESC_AVL_MASK) != 0;
983 lhs->unusable = 0;
984 lhs->padding = 0;
985 }
986
987 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
988 {
989 lhs->selector = rhs->selector;
990 lhs->base = rhs->base;
991 lhs->limit = rhs->limit;
992 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
993 (rhs->present * DESC_P_MASK) |
994 (rhs->dpl << DESC_DPL_SHIFT) |
995 (rhs->db << DESC_B_SHIFT) |
996 (rhs->s * DESC_S_MASK) |
997 (rhs->l << DESC_L_SHIFT) |
998 (rhs->g * DESC_G_MASK) |
999 (rhs->avl * DESC_AVL_MASK);
1000 }
1001
1002 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1003 {
1004 if (set) {
1005 *kvm_reg = *qemu_reg;
1006 } else {
1007 *qemu_reg = *kvm_reg;
1008 }
1009 }
1010
1011 static int kvm_getput_regs(X86CPU *cpu, int set)
1012 {
1013 CPUX86State *env = &cpu->env;
1014 struct kvm_regs regs;
1015 int ret = 0;
1016
1017 if (!set) {
1018 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1019 if (ret < 0) {
1020 return ret;
1021 }
1022 }
1023
1024 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1025 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1026 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1027 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1028 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1029 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1030 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1031 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1032 #ifdef TARGET_X86_64
1033 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1034 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1035 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1036 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1037 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1038 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1039 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1040 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1041 #endif
1042
1043 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1044 kvm_getput_reg(&regs.rip, &env->eip, set);
1045
1046 if (set) {
1047 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1048 }
1049
1050 return ret;
1051 }
1052
1053 static int kvm_put_fpu(X86CPU *cpu)
1054 {
1055 CPUX86State *env = &cpu->env;
1056 struct kvm_fpu fpu;
1057 int i;
1058
1059 memset(&fpu, 0, sizeof fpu);
1060 fpu.fsw = env->fpus & ~(7 << 11);
1061 fpu.fsw |= (env->fpstt & 7) << 11;
1062 fpu.fcw = env->fpuc;
1063 fpu.last_opcode = env->fpop;
1064 fpu.last_ip = env->fpip;
1065 fpu.last_dp = env->fpdp;
1066 for (i = 0; i < 8; ++i) {
1067 fpu.ftwx |= (!env->fptags[i]) << i;
1068 }
1069 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1070 for (i = 0; i < CPU_NB_REGS; i++) {
1071 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].XMM_Q(0));
1072 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].XMM_Q(1));
1073 }
1074 fpu.mxcsr = env->mxcsr;
1075
1076 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1077 }
1078
1079 #define XSAVE_FCW_FSW 0
1080 #define XSAVE_FTW_FOP 1
1081 #define XSAVE_CWD_RIP 2
1082 #define XSAVE_CWD_RDP 4
1083 #define XSAVE_MXCSR 6
1084 #define XSAVE_ST_SPACE 8
1085 #define XSAVE_XMM_SPACE 40
1086 #define XSAVE_XSTATE_BV 128
1087 #define XSAVE_YMMH_SPACE 144
1088 #define XSAVE_BNDREGS 240
1089 #define XSAVE_BNDCSR 256
1090 #define XSAVE_OPMASK 272
1091 #define XSAVE_ZMM_Hi256 288
1092 #define XSAVE_Hi16_ZMM 416
1093
1094 static int kvm_put_xsave(X86CPU *cpu)
1095 {
1096 CPUX86State *env = &cpu->env;
1097 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1098 uint16_t cwd, swd, twd;
1099 uint8_t *xmm, *ymmh, *zmmh;
1100 int i, r;
1101
1102 if (!kvm_has_xsave()) {
1103 return kvm_put_fpu(cpu);
1104 }
1105
1106 memset(xsave, 0, sizeof(struct kvm_xsave));
1107 twd = 0;
1108 swd = env->fpus & ~(7 << 11);
1109 swd |= (env->fpstt & 7) << 11;
1110 cwd = env->fpuc;
1111 for (i = 0; i < 8; ++i) {
1112 twd |= (!env->fptags[i]) << i;
1113 }
1114 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1115 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1116 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1117 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1118 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1119 sizeof env->fpregs);
1120 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1121 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1122 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1123 sizeof env->bnd_regs);
1124 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1125 sizeof(env->bndcs_regs));
1126 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1127 sizeof env->opmask_regs);
1128
1129 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1130 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1131 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1132 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1133 stq_p(xmm, env->xmm_regs[i].XMM_Q(0));
1134 stq_p(xmm+8, env->xmm_regs[i].XMM_Q(1));
1135 stq_p(ymmh, env->xmm_regs[i].XMM_Q(2));
1136 stq_p(ymmh+8, env->xmm_regs[i].XMM_Q(3));
1137 stq_p(zmmh, env->xmm_regs[i].XMM_Q(4));
1138 stq_p(zmmh+8, env->xmm_regs[i].XMM_Q(5));
1139 stq_p(zmmh+16, env->xmm_regs[i].XMM_Q(6));
1140 stq_p(zmmh+24, env->xmm_regs[i].XMM_Q(7));
1141 }
1142
1143 #ifdef TARGET_X86_64
1144 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1145 16 * sizeof env->xmm_regs[16]);
1146 #endif
1147 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1148 return r;
1149 }
1150
1151 static int kvm_put_xcrs(X86CPU *cpu)
1152 {
1153 CPUX86State *env = &cpu->env;
1154 struct kvm_xcrs xcrs = {};
1155
1156 if (!kvm_has_xcrs()) {
1157 return 0;
1158 }
1159
1160 xcrs.nr_xcrs = 1;
1161 xcrs.flags = 0;
1162 xcrs.xcrs[0].xcr = 0;
1163 xcrs.xcrs[0].value = env->xcr0;
1164 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1165 }
1166
1167 static int kvm_put_sregs(X86CPU *cpu)
1168 {
1169 CPUX86State *env = &cpu->env;
1170 struct kvm_sregs sregs;
1171
1172 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1173 if (env->interrupt_injected >= 0) {
1174 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1175 (uint64_t)1 << (env->interrupt_injected % 64);
1176 }
1177
1178 if ((env->eflags & VM_MASK)) {
1179 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1180 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1181 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1182 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1183 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1184 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1185 } else {
1186 set_seg(&sregs.cs, &env->segs[R_CS]);
1187 set_seg(&sregs.ds, &env->segs[R_DS]);
1188 set_seg(&sregs.es, &env->segs[R_ES]);
1189 set_seg(&sregs.fs, &env->segs[R_FS]);
1190 set_seg(&sregs.gs, &env->segs[R_GS]);
1191 set_seg(&sregs.ss, &env->segs[R_SS]);
1192 }
1193
1194 set_seg(&sregs.tr, &env->tr);
1195 set_seg(&sregs.ldt, &env->ldt);
1196
1197 sregs.idt.limit = env->idt.limit;
1198 sregs.idt.base = env->idt.base;
1199 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1200 sregs.gdt.limit = env->gdt.limit;
1201 sregs.gdt.base = env->gdt.base;
1202 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1203
1204 sregs.cr0 = env->cr[0];
1205 sregs.cr2 = env->cr[2];
1206 sregs.cr3 = env->cr[3];
1207 sregs.cr4 = env->cr[4];
1208
1209 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1210 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1211
1212 sregs.efer = env->efer;
1213
1214 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1215 }
1216
1217 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1218 uint32_t index, uint64_t value)
1219 {
1220 entry->index = index;
1221 entry->reserved = 0;
1222 entry->data = value;
1223 }
1224
1225 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1226 {
1227 CPUX86State *env = &cpu->env;
1228 struct {
1229 struct kvm_msrs info;
1230 struct kvm_msr_entry entries[1];
1231 } msr_data;
1232 struct kvm_msr_entry *msrs = msr_data.entries;
1233
1234 if (!has_msr_tsc_deadline) {
1235 return 0;
1236 }
1237
1238 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1239
1240 msr_data.info = (struct kvm_msrs) {
1241 .nmsrs = 1,
1242 };
1243
1244 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1245 }
1246
1247 /*
1248 * Provide a separate write service for the feature control MSR in order to
1249 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1250 * before writing any other state because forcibly leaving nested mode
1251 * invalidates the VCPU state.
1252 */
1253 static int kvm_put_msr_feature_control(X86CPU *cpu)
1254 {
1255 struct {
1256 struct kvm_msrs info;
1257 struct kvm_msr_entry entry;
1258 } msr_data;
1259
1260 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1261 cpu->env.msr_ia32_feature_control);
1262
1263 msr_data.info = (struct kvm_msrs) {
1264 .nmsrs = 1,
1265 };
1266
1267 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1268 }
1269
1270 static int kvm_put_msrs(X86CPU *cpu, int level)
1271 {
1272 CPUX86State *env = &cpu->env;
1273 struct {
1274 struct kvm_msrs info;
1275 struct kvm_msr_entry entries[150];
1276 } msr_data;
1277 struct kvm_msr_entry *msrs = msr_data.entries;
1278 int n = 0, i;
1279
1280 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1281 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1282 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1283 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1284 if (has_msr_star) {
1285 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1286 }
1287 if (has_msr_hsave_pa) {
1288 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1289 }
1290 if (has_msr_tsc_adjust) {
1291 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1292 }
1293 if (has_msr_misc_enable) {
1294 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1295 env->msr_ia32_misc_enable);
1296 }
1297 if (has_msr_smbase) {
1298 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1299 }
1300 if (has_msr_bndcfgs) {
1301 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1302 }
1303 if (has_msr_xss) {
1304 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1305 }
1306 #ifdef TARGET_X86_64
1307 if (lm_capable_kernel) {
1308 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1309 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1310 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1311 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1312 }
1313 #endif
1314 /*
1315 * The following MSRs have side effects on the guest or are too heavy
1316 * for normal writeback. Limit them to reset or full state updates.
1317 */
1318 if (level >= KVM_PUT_RESET_STATE) {
1319 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1320 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1321 env->system_time_msr);
1322 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1323 if (has_msr_async_pf_en) {
1324 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1325 env->async_pf_en_msr);
1326 }
1327 if (has_msr_pv_eoi_en) {
1328 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1329 env->pv_eoi_en_msr);
1330 }
1331 if (has_msr_kvm_steal_time) {
1332 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1333 env->steal_time_msr);
1334 }
1335 if (has_msr_architectural_pmu) {
1336 /* Stop the counter. */
1337 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1338 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1339
1340 /* Set the counter values. */
1341 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1342 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1343 env->msr_fixed_counters[i]);
1344 }
1345 for (i = 0; i < num_architectural_pmu_counters; i++) {
1346 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1347 env->msr_gp_counters[i]);
1348 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1349 env->msr_gp_evtsel[i]);
1350 }
1351 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1352 env->msr_global_status);
1353 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1354 env->msr_global_ovf_ctrl);
1355
1356 /* Now start the PMU. */
1357 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1358 env->msr_fixed_ctr_ctrl);
1359 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1360 env->msr_global_ctrl);
1361 }
1362 if (has_msr_hv_hypercall) {
1363 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1364 env->msr_hv_guest_os_id);
1365 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1366 env->msr_hv_hypercall);
1367 }
1368 if (has_msr_hv_vapic) {
1369 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1370 env->msr_hv_vapic);
1371 }
1372 if (has_msr_hv_tsc) {
1373 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1374 env->msr_hv_tsc);
1375 }
1376 if (has_msr_mtrr) {
1377 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1378 kvm_msr_entry_set(&msrs[n++],
1379 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1380 kvm_msr_entry_set(&msrs[n++],
1381 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1382 kvm_msr_entry_set(&msrs[n++],
1383 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1384 kvm_msr_entry_set(&msrs[n++],
1385 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1386 kvm_msr_entry_set(&msrs[n++],
1387 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1388 kvm_msr_entry_set(&msrs[n++],
1389 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1390 kvm_msr_entry_set(&msrs[n++],
1391 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1392 kvm_msr_entry_set(&msrs[n++],
1393 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1394 kvm_msr_entry_set(&msrs[n++],
1395 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1396 kvm_msr_entry_set(&msrs[n++],
1397 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1398 kvm_msr_entry_set(&msrs[n++],
1399 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1400 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1401 kvm_msr_entry_set(&msrs[n++],
1402 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1403 kvm_msr_entry_set(&msrs[n++],
1404 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1405 }
1406 }
1407
1408 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1409 * kvm_put_msr_feature_control. */
1410 }
1411 if (env->mcg_cap) {
1412 int i;
1413
1414 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1415 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1416 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1417 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1418 }
1419 }
1420
1421 msr_data.info = (struct kvm_msrs) {
1422 .nmsrs = n,
1423 };
1424
1425 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1426
1427 }
1428
1429
1430 static int kvm_get_fpu(X86CPU *cpu)
1431 {
1432 CPUX86State *env = &cpu->env;
1433 struct kvm_fpu fpu;
1434 int i, ret;
1435
1436 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1437 if (ret < 0) {
1438 return ret;
1439 }
1440
1441 env->fpstt = (fpu.fsw >> 11) & 7;
1442 env->fpus = fpu.fsw;
1443 env->fpuc = fpu.fcw;
1444 env->fpop = fpu.last_opcode;
1445 env->fpip = fpu.last_ip;
1446 env->fpdp = fpu.last_dp;
1447 for (i = 0; i < 8; ++i) {
1448 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1449 }
1450 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1451 for (i = 0; i < CPU_NB_REGS; i++) {
1452 env->xmm_regs[i].XMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1453 env->xmm_regs[i].XMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1454 }
1455 env->mxcsr = fpu.mxcsr;
1456
1457 return 0;
1458 }
1459
1460 static int kvm_get_xsave(X86CPU *cpu)
1461 {
1462 CPUX86State *env = &cpu->env;
1463 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1464 int ret, i;
1465 const uint8_t *xmm, *ymmh, *zmmh;
1466 uint16_t cwd, swd, twd;
1467
1468 if (!kvm_has_xsave()) {
1469 return kvm_get_fpu(cpu);
1470 }
1471
1472 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1473 if (ret < 0) {
1474 return ret;
1475 }
1476
1477 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1478 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1479 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1480 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1481 env->fpstt = (swd >> 11) & 7;
1482 env->fpus = swd;
1483 env->fpuc = cwd;
1484 for (i = 0; i < 8; ++i) {
1485 env->fptags[i] = !((twd >> i) & 1);
1486 }
1487 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1488 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1489 env->mxcsr = xsave->region[XSAVE_MXCSR];
1490 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1491 sizeof env->fpregs);
1492 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1493 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1494 sizeof env->bnd_regs);
1495 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1496 sizeof(env->bndcs_regs));
1497 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1498 sizeof env->opmask_regs);
1499
1500 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1501 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1502 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1503 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1504 env->xmm_regs[i].XMM_Q(0) = ldq_p(xmm);
1505 env->xmm_regs[i].XMM_Q(1) = ldq_p(xmm+8);
1506 env->xmm_regs[i].XMM_Q(2) = ldq_p(ymmh);
1507 env->xmm_regs[i].XMM_Q(3) = ldq_p(ymmh+8);
1508 env->xmm_regs[i].XMM_Q(4) = ldq_p(zmmh);
1509 env->xmm_regs[i].XMM_Q(5) = ldq_p(zmmh+8);
1510 env->xmm_regs[i].XMM_Q(6) = ldq_p(zmmh+16);
1511 env->xmm_regs[i].XMM_Q(7) = ldq_p(zmmh+24);
1512 }
1513
1514 #ifdef TARGET_X86_64
1515 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1516 16 * sizeof env->xmm_regs[16]);
1517 #endif
1518 return 0;
1519 }
1520
1521 static int kvm_get_xcrs(X86CPU *cpu)
1522 {
1523 CPUX86State *env = &cpu->env;
1524 int i, ret;
1525 struct kvm_xcrs xcrs;
1526
1527 if (!kvm_has_xcrs()) {
1528 return 0;
1529 }
1530
1531 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1532 if (ret < 0) {
1533 return ret;
1534 }
1535
1536 for (i = 0; i < xcrs.nr_xcrs; i++) {
1537 /* Only support xcr0 now */
1538 if (xcrs.xcrs[i].xcr == 0) {
1539 env->xcr0 = xcrs.xcrs[i].value;
1540 break;
1541 }
1542 }
1543 return 0;
1544 }
1545
1546 static int kvm_get_sregs(X86CPU *cpu)
1547 {
1548 CPUX86State *env = &cpu->env;
1549 struct kvm_sregs sregs;
1550 uint32_t hflags;
1551 int bit, i, ret;
1552
1553 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1554 if (ret < 0) {
1555 return ret;
1556 }
1557
1558 /* There can only be one pending IRQ set in the bitmap at a time, so try
1559 to find it and save its number instead (-1 for none). */
1560 env->interrupt_injected = -1;
1561 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1562 if (sregs.interrupt_bitmap[i]) {
1563 bit = ctz64(sregs.interrupt_bitmap[i]);
1564 env->interrupt_injected = i * 64 + bit;
1565 break;
1566 }
1567 }
1568
1569 get_seg(&env->segs[R_CS], &sregs.cs);
1570 get_seg(&env->segs[R_DS], &sregs.ds);
1571 get_seg(&env->segs[R_ES], &sregs.es);
1572 get_seg(&env->segs[R_FS], &sregs.fs);
1573 get_seg(&env->segs[R_GS], &sregs.gs);
1574 get_seg(&env->segs[R_SS], &sregs.ss);
1575
1576 get_seg(&env->tr, &sregs.tr);
1577 get_seg(&env->ldt, &sregs.ldt);
1578
1579 env->idt.limit = sregs.idt.limit;
1580 env->idt.base = sregs.idt.base;
1581 env->gdt.limit = sregs.gdt.limit;
1582 env->gdt.base = sregs.gdt.base;
1583
1584 env->cr[0] = sregs.cr0;
1585 env->cr[2] = sregs.cr2;
1586 env->cr[3] = sregs.cr3;
1587 env->cr[4] = sregs.cr4;
1588
1589 env->efer = sregs.efer;
1590
1591 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1592
1593 #define HFLAG_COPY_MASK \
1594 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1595 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1596 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1597 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1598
1599 hflags = (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1600 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1601 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1602 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1603 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1604 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1605 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1606
1607 if (env->efer & MSR_EFER_LMA) {
1608 hflags |= HF_LMA_MASK;
1609 }
1610
1611 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1612 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1613 } else {
1614 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1615 (DESC_B_SHIFT - HF_CS32_SHIFT);
1616 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1617 (DESC_B_SHIFT - HF_SS32_SHIFT);
1618 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1619 !(hflags & HF_CS32_MASK)) {
1620 hflags |= HF_ADDSEG_MASK;
1621 } else {
1622 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1623 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1624 }
1625 }
1626 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1627
1628 return 0;
1629 }
1630
1631 static int kvm_get_msrs(X86CPU *cpu)
1632 {
1633 CPUX86State *env = &cpu->env;
1634 struct {
1635 struct kvm_msrs info;
1636 struct kvm_msr_entry entries[150];
1637 } msr_data;
1638 struct kvm_msr_entry *msrs = msr_data.entries;
1639 int ret, i, n;
1640
1641 n = 0;
1642 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1643 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1644 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1645 msrs[n++].index = MSR_PAT;
1646 if (has_msr_star) {
1647 msrs[n++].index = MSR_STAR;
1648 }
1649 if (has_msr_hsave_pa) {
1650 msrs[n++].index = MSR_VM_HSAVE_PA;
1651 }
1652 if (has_msr_tsc_adjust) {
1653 msrs[n++].index = MSR_TSC_ADJUST;
1654 }
1655 if (has_msr_tsc_deadline) {
1656 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1657 }
1658 if (has_msr_misc_enable) {
1659 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1660 }
1661 if (has_msr_smbase) {
1662 msrs[n++].index = MSR_IA32_SMBASE;
1663 }
1664 if (has_msr_feature_control) {
1665 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1666 }
1667 if (has_msr_bndcfgs) {
1668 msrs[n++].index = MSR_IA32_BNDCFGS;
1669 }
1670 if (has_msr_xss) {
1671 msrs[n++].index = MSR_IA32_XSS;
1672 }
1673
1674
1675 if (!env->tsc_valid) {
1676 msrs[n++].index = MSR_IA32_TSC;
1677 env->tsc_valid = !runstate_is_running();
1678 }
1679
1680 #ifdef TARGET_X86_64
1681 if (lm_capable_kernel) {
1682 msrs[n++].index = MSR_CSTAR;
1683 msrs[n++].index = MSR_KERNELGSBASE;
1684 msrs[n++].index = MSR_FMASK;
1685 msrs[n++].index = MSR_LSTAR;
1686 }
1687 #endif
1688 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1689 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1690 if (has_msr_async_pf_en) {
1691 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1692 }
1693 if (has_msr_pv_eoi_en) {
1694 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1695 }
1696 if (has_msr_kvm_steal_time) {
1697 msrs[n++].index = MSR_KVM_STEAL_TIME;
1698 }
1699 if (has_msr_architectural_pmu) {
1700 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1701 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1702 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1703 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1704 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1705 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1706 }
1707 for (i = 0; i < num_architectural_pmu_counters; i++) {
1708 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1709 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1710 }
1711 }
1712
1713 if (env->mcg_cap) {
1714 msrs[n++].index = MSR_MCG_STATUS;
1715 msrs[n++].index = MSR_MCG_CTL;
1716 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1717 msrs[n++].index = MSR_MC0_CTL + i;
1718 }
1719 }
1720
1721 if (has_msr_hv_hypercall) {
1722 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1723 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1724 }
1725 if (has_msr_hv_vapic) {
1726 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1727 }
1728 if (has_msr_hv_tsc) {
1729 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1730 }
1731 if (has_msr_mtrr) {
1732 msrs[n++].index = MSR_MTRRdefType;
1733 msrs[n++].index = MSR_MTRRfix64K_00000;
1734 msrs[n++].index = MSR_MTRRfix16K_80000;
1735 msrs[n++].index = MSR_MTRRfix16K_A0000;
1736 msrs[n++].index = MSR_MTRRfix4K_C0000;
1737 msrs[n++].index = MSR_MTRRfix4K_C8000;
1738 msrs[n++].index = MSR_MTRRfix4K_D0000;
1739 msrs[n++].index = MSR_MTRRfix4K_D8000;
1740 msrs[n++].index = MSR_MTRRfix4K_E0000;
1741 msrs[n++].index = MSR_MTRRfix4K_E8000;
1742 msrs[n++].index = MSR_MTRRfix4K_F0000;
1743 msrs[n++].index = MSR_MTRRfix4K_F8000;
1744 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1745 msrs[n++].index = MSR_MTRRphysBase(i);
1746 msrs[n++].index = MSR_MTRRphysMask(i);
1747 }
1748 }
1749
1750 msr_data.info = (struct kvm_msrs) {
1751 .nmsrs = n,
1752 };
1753
1754 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1755 if (ret < 0) {
1756 return ret;
1757 }
1758
1759 for (i = 0; i < ret; i++) {
1760 uint32_t index = msrs[i].index;
1761 switch (index) {
1762 case MSR_IA32_SYSENTER_CS:
1763 env->sysenter_cs = msrs[i].data;
1764 break;
1765 case MSR_IA32_SYSENTER_ESP:
1766 env->sysenter_esp = msrs[i].data;
1767 break;
1768 case MSR_IA32_SYSENTER_EIP:
1769 env->sysenter_eip = msrs[i].data;
1770 break;
1771 case MSR_PAT:
1772 env->pat = msrs[i].data;
1773 break;
1774 case MSR_STAR:
1775 env->star = msrs[i].data;
1776 break;
1777 #ifdef TARGET_X86_64
1778 case MSR_CSTAR:
1779 env->cstar = msrs[i].data;
1780 break;
1781 case MSR_KERNELGSBASE:
1782 env->kernelgsbase = msrs[i].data;
1783 break;
1784 case MSR_FMASK:
1785 env->fmask = msrs[i].data;
1786 break;
1787 case MSR_LSTAR:
1788 env->lstar = msrs[i].data;
1789 break;
1790 #endif
1791 case MSR_IA32_TSC:
1792 env->tsc = msrs[i].data;
1793 break;
1794 case MSR_TSC_ADJUST:
1795 env->tsc_adjust = msrs[i].data;
1796 break;
1797 case MSR_IA32_TSCDEADLINE:
1798 env->tsc_deadline = msrs[i].data;
1799 break;
1800 case MSR_VM_HSAVE_PA:
1801 env->vm_hsave = msrs[i].data;
1802 break;
1803 case MSR_KVM_SYSTEM_TIME:
1804 env->system_time_msr = msrs[i].data;
1805 break;
1806 case MSR_KVM_WALL_CLOCK:
1807 env->wall_clock_msr = msrs[i].data;
1808 break;
1809 case MSR_MCG_STATUS:
1810 env->mcg_status = msrs[i].data;
1811 break;
1812 case MSR_MCG_CTL:
1813 env->mcg_ctl = msrs[i].data;
1814 break;
1815 case MSR_IA32_MISC_ENABLE:
1816 env->msr_ia32_misc_enable = msrs[i].data;
1817 break;
1818 case MSR_IA32_SMBASE:
1819 env->smbase = msrs[i].data;
1820 break;
1821 case MSR_IA32_FEATURE_CONTROL:
1822 env->msr_ia32_feature_control = msrs[i].data;
1823 break;
1824 case MSR_IA32_BNDCFGS:
1825 env->msr_bndcfgs = msrs[i].data;
1826 break;
1827 case MSR_IA32_XSS:
1828 env->xss = msrs[i].data;
1829 break;
1830 default:
1831 if (msrs[i].index >= MSR_MC0_CTL &&
1832 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1833 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1834 }
1835 break;
1836 case MSR_KVM_ASYNC_PF_EN:
1837 env->async_pf_en_msr = msrs[i].data;
1838 break;
1839 case MSR_KVM_PV_EOI_EN:
1840 env->pv_eoi_en_msr = msrs[i].data;
1841 break;
1842 case MSR_KVM_STEAL_TIME:
1843 env->steal_time_msr = msrs[i].data;
1844 break;
1845 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1846 env->msr_fixed_ctr_ctrl = msrs[i].data;
1847 break;
1848 case MSR_CORE_PERF_GLOBAL_CTRL:
1849 env->msr_global_ctrl = msrs[i].data;
1850 break;
1851 case MSR_CORE_PERF_GLOBAL_STATUS:
1852 env->msr_global_status = msrs[i].data;
1853 break;
1854 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1855 env->msr_global_ovf_ctrl = msrs[i].data;
1856 break;
1857 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1858 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1859 break;
1860 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1861 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1862 break;
1863 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1864 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1865 break;
1866 case HV_X64_MSR_HYPERCALL:
1867 env->msr_hv_hypercall = msrs[i].data;
1868 break;
1869 case HV_X64_MSR_GUEST_OS_ID:
1870 env->msr_hv_guest_os_id = msrs[i].data;
1871 break;
1872 case HV_X64_MSR_APIC_ASSIST_PAGE:
1873 env->msr_hv_vapic = msrs[i].data;
1874 break;
1875 case HV_X64_MSR_REFERENCE_TSC:
1876 env->msr_hv_tsc = msrs[i].data;
1877 break;
1878 case MSR_MTRRdefType:
1879 env->mtrr_deftype = msrs[i].data;
1880 break;
1881 case MSR_MTRRfix64K_00000:
1882 env->mtrr_fixed[0] = msrs[i].data;
1883 break;
1884 case MSR_MTRRfix16K_80000:
1885 env->mtrr_fixed[1] = msrs[i].data;
1886 break;
1887 case MSR_MTRRfix16K_A0000:
1888 env->mtrr_fixed[2] = msrs[i].data;
1889 break;
1890 case MSR_MTRRfix4K_C0000:
1891 env->mtrr_fixed[3] = msrs[i].data;
1892 break;
1893 case MSR_MTRRfix4K_C8000:
1894 env->mtrr_fixed[4] = msrs[i].data;
1895 break;
1896 case MSR_MTRRfix4K_D0000:
1897 env->mtrr_fixed[5] = msrs[i].data;
1898 break;
1899 case MSR_MTRRfix4K_D8000:
1900 env->mtrr_fixed[6] = msrs[i].data;
1901 break;
1902 case MSR_MTRRfix4K_E0000:
1903 env->mtrr_fixed[7] = msrs[i].data;
1904 break;
1905 case MSR_MTRRfix4K_E8000:
1906 env->mtrr_fixed[8] = msrs[i].data;
1907 break;
1908 case MSR_MTRRfix4K_F0000:
1909 env->mtrr_fixed[9] = msrs[i].data;
1910 break;
1911 case MSR_MTRRfix4K_F8000:
1912 env->mtrr_fixed[10] = msrs[i].data;
1913 break;
1914 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
1915 if (index & 1) {
1916 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
1917 } else {
1918 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
1919 }
1920 break;
1921 }
1922 }
1923
1924 return 0;
1925 }
1926
1927 static int kvm_put_mp_state(X86CPU *cpu)
1928 {
1929 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1930
1931 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1932 }
1933
1934 static int kvm_get_mp_state(X86CPU *cpu)
1935 {
1936 CPUState *cs = CPU(cpu);
1937 CPUX86State *env = &cpu->env;
1938 struct kvm_mp_state mp_state;
1939 int ret;
1940
1941 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1942 if (ret < 0) {
1943 return ret;
1944 }
1945 env->mp_state = mp_state.mp_state;
1946 if (kvm_irqchip_in_kernel()) {
1947 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1948 }
1949 return 0;
1950 }
1951
1952 static int kvm_get_apic(X86CPU *cpu)
1953 {
1954 DeviceState *apic = cpu->apic_state;
1955 struct kvm_lapic_state kapic;
1956 int ret;
1957
1958 if (apic && kvm_irqchip_in_kernel()) {
1959 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1960 if (ret < 0) {
1961 return ret;
1962 }
1963
1964 kvm_get_apic_state(apic, &kapic);
1965 }
1966 return 0;
1967 }
1968
1969 static int kvm_put_apic(X86CPU *cpu)
1970 {
1971 DeviceState *apic = cpu->apic_state;
1972 struct kvm_lapic_state kapic;
1973
1974 if (apic && kvm_irqchip_in_kernel()) {
1975 kvm_put_apic_state(apic, &kapic);
1976
1977 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1978 }
1979 return 0;
1980 }
1981
1982 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1983 {
1984 CPUState *cs = CPU(cpu);
1985 CPUX86State *env = &cpu->env;
1986 struct kvm_vcpu_events events = {};
1987
1988 if (!kvm_has_vcpu_events()) {
1989 return 0;
1990 }
1991
1992 events.exception.injected = (env->exception_injected >= 0);
1993 events.exception.nr = env->exception_injected;
1994 events.exception.has_error_code = env->has_error_code;
1995 events.exception.error_code = env->error_code;
1996 events.exception.pad = 0;
1997
1998 events.interrupt.injected = (env->interrupt_injected >= 0);
1999 events.interrupt.nr = env->interrupt_injected;
2000 events.interrupt.soft = env->soft_interrupt;
2001
2002 events.nmi.injected = env->nmi_injected;
2003 events.nmi.pending = env->nmi_pending;
2004 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2005 events.nmi.pad = 0;
2006
2007 events.sipi_vector = env->sipi_vector;
2008
2009 if (has_msr_smbase) {
2010 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2011 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2012 if (kvm_irqchip_in_kernel()) {
2013 /* As soon as these are moved to the kernel, remove them
2014 * from cs->interrupt_request.
2015 */
2016 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2017 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2018 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2019 } else {
2020 /* Keep these in cs->interrupt_request. */
2021 events.smi.pending = 0;
2022 events.smi.latched_init = 0;
2023 }
2024 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2025 }
2026
2027 events.flags = 0;
2028 if (level >= KVM_PUT_RESET_STATE) {
2029 events.flags |=
2030 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2031 }
2032
2033 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2034 }
2035
2036 static int kvm_get_vcpu_events(X86CPU *cpu)
2037 {
2038 CPUX86State *env = &cpu->env;
2039 struct kvm_vcpu_events events;
2040 int ret;
2041
2042 if (!kvm_has_vcpu_events()) {
2043 return 0;
2044 }
2045
2046 memset(&events, 0, sizeof(events));
2047 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2048 if (ret < 0) {
2049 return ret;
2050 }
2051 env->exception_injected =
2052 events.exception.injected ? events.exception.nr : -1;
2053 env->has_error_code = events.exception.has_error_code;
2054 env->error_code = events.exception.error_code;
2055
2056 env->interrupt_injected =
2057 events.interrupt.injected ? events.interrupt.nr : -1;
2058 env->soft_interrupt = events.interrupt.soft;
2059
2060 env->nmi_injected = events.nmi.injected;
2061 env->nmi_pending = events.nmi.pending;
2062 if (events.nmi.masked) {
2063 env->hflags2 |= HF2_NMI_MASK;
2064 } else {
2065 env->hflags2 &= ~HF2_NMI_MASK;
2066 }
2067
2068 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2069 if (events.smi.smm) {
2070 env->hflags |= HF_SMM_MASK;
2071 } else {
2072 env->hflags &= ~HF_SMM_MASK;
2073 }
2074 if (events.smi.pending) {
2075 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2076 } else {
2077 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2078 }
2079 if (events.smi.smm_inside_nmi) {
2080 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2081 } else {
2082 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2083 }
2084 if (events.smi.latched_init) {
2085 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2086 } else {
2087 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2088 }
2089 }
2090
2091 env->sipi_vector = events.sipi_vector;
2092
2093 return 0;
2094 }
2095
2096 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2097 {
2098 CPUState *cs = CPU(cpu);
2099 CPUX86State *env = &cpu->env;
2100 int ret = 0;
2101 unsigned long reinject_trap = 0;
2102
2103 if (!kvm_has_vcpu_events()) {
2104 if (env->exception_injected == 1) {
2105 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2106 } else if (env->exception_injected == 3) {
2107 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2108 }
2109 env->exception_injected = -1;
2110 }
2111
2112 /*
2113 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2114 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2115 * by updating the debug state once again if single-stepping is on.
2116 * Another reason to call kvm_update_guest_debug here is a pending debug
2117 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2118 * reinject them via SET_GUEST_DEBUG.
2119 */
2120 if (reinject_trap ||
2121 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2122 ret = kvm_update_guest_debug(cs, reinject_trap);
2123 }
2124 return ret;
2125 }
2126
2127 static int kvm_put_debugregs(X86CPU *cpu)
2128 {
2129 CPUX86State *env = &cpu->env;
2130 struct kvm_debugregs dbgregs;
2131 int i;
2132
2133 if (!kvm_has_debugregs()) {
2134 return 0;
2135 }
2136
2137 for (i = 0; i < 4; i++) {
2138 dbgregs.db[i] = env->dr[i];
2139 }
2140 dbgregs.dr6 = env->dr[6];
2141 dbgregs.dr7 = env->dr[7];
2142 dbgregs.flags = 0;
2143
2144 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2145 }
2146
2147 static int kvm_get_debugregs(X86CPU *cpu)
2148 {
2149 CPUX86State *env = &cpu->env;
2150 struct kvm_debugregs dbgregs;
2151 int i, ret;
2152
2153 if (!kvm_has_debugregs()) {
2154 return 0;
2155 }
2156
2157 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2158 if (ret < 0) {
2159 return ret;
2160 }
2161 for (i = 0; i < 4; i++) {
2162 env->dr[i] = dbgregs.db[i];
2163 }
2164 env->dr[4] = env->dr[6] = dbgregs.dr6;
2165 env->dr[5] = env->dr[7] = dbgregs.dr7;
2166
2167 return 0;
2168 }
2169
2170 int kvm_arch_put_registers(CPUState *cpu, int level)
2171 {
2172 X86CPU *x86_cpu = X86_CPU(cpu);
2173 int ret;
2174
2175 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2176
2177 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2178 ret = kvm_put_msr_feature_control(x86_cpu);
2179 if (ret < 0) {
2180 return ret;
2181 }
2182 }
2183
2184 ret = kvm_getput_regs(x86_cpu, 1);
2185 if (ret < 0) {
2186 return ret;
2187 }
2188 ret = kvm_put_xsave(x86_cpu);
2189 if (ret < 0) {
2190 return ret;
2191 }
2192 ret = kvm_put_xcrs(x86_cpu);
2193 if (ret < 0) {
2194 return ret;
2195 }
2196 ret = kvm_put_sregs(x86_cpu);
2197 if (ret < 0) {
2198 return ret;
2199 }
2200 /* must be before kvm_put_msrs */
2201 ret = kvm_inject_mce_oldstyle(x86_cpu);
2202 if (ret < 0) {
2203 return ret;
2204 }
2205 ret = kvm_put_msrs(x86_cpu, level);
2206 if (ret < 0) {
2207 return ret;
2208 }
2209 if (level >= KVM_PUT_RESET_STATE) {
2210 ret = kvm_put_mp_state(x86_cpu);
2211 if (ret < 0) {
2212 return ret;
2213 }
2214 ret = kvm_put_apic(x86_cpu);
2215 if (ret < 0) {
2216 return ret;
2217 }
2218 }
2219
2220 ret = kvm_put_tscdeadline_msr(x86_cpu);
2221 if (ret < 0) {
2222 return ret;
2223 }
2224
2225 ret = kvm_put_vcpu_events(x86_cpu, level);
2226 if (ret < 0) {
2227 return ret;
2228 }
2229 ret = kvm_put_debugregs(x86_cpu);
2230 if (ret < 0) {
2231 return ret;
2232 }
2233 /* must be last */
2234 ret = kvm_guest_debug_workarounds(x86_cpu);
2235 if (ret < 0) {
2236 return ret;
2237 }
2238 return 0;
2239 }
2240
2241 int kvm_arch_get_registers(CPUState *cs)
2242 {
2243 X86CPU *cpu = X86_CPU(cs);
2244 int ret;
2245
2246 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2247
2248 ret = kvm_getput_regs(cpu, 0);
2249 if (ret < 0) {
2250 return ret;
2251 }
2252 ret = kvm_get_xsave(cpu);
2253 if (ret < 0) {
2254 return ret;
2255 }
2256 ret = kvm_get_xcrs(cpu);
2257 if (ret < 0) {
2258 return ret;
2259 }
2260 ret = kvm_get_sregs(cpu);
2261 if (ret < 0) {
2262 return ret;
2263 }
2264 ret = kvm_get_msrs(cpu);
2265 if (ret < 0) {
2266 return ret;
2267 }
2268 ret = kvm_get_mp_state(cpu);
2269 if (ret < 0) {
2270 return ret;
2271 }
2272 ret = kvm_get_apic(cpu);
2273 if (ret < 0) {
2274 return ret;
2275 }
2276 ret = kvm_get_vcpu_events(cpu);
2277 if (ret < 0) {
2278 return ret;
2279 }
2280 ret = kvm_get_debugregs(cpu);
2281 if (ret < 0) {
2282 return ret;
2283 }
2284 return 0;
2285 }
2286
2287 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2288 {
2289 X86CPU *x86_cpu = X86_CPU(cpu);
2290 CPUX86State *env = &x86_cpu->env;
2291 int ret;
2292
2293 /* Inject NMI */
2294 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2295 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2296 qemu_mutex_lock_iothread();
2297 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2298 qemu_mutex_unlock_iothread();
2299 DPRINTF("injected NMI\n");
2300 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2301 if (ret < 0) {
2302 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2303 strerror(-ret));
2304 }
2305 }
2306 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2307 qemu_mutex_lock_iothread();
2308 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2309 qemu_mutex_unlock_iothread();
2310 DPRINTF("injected SMI\n");
2311 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2312 if (ret < 0) {
2313 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2314 strerror(-ret));
2315 }
2316 }
2317 }
2318
2319 if (!kvm_irqchip_in_kernel()) {
2320 qemu_mutex_lock_iothread();
2321 }
2322
2323 /* Force the VCPU out of its inner loop to process any INIT requests
2324 * or (for userspace APIC, but it is cheap to combine the checks here)
2325 * pending TPR access reports.
2326 */
2327 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2328 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2329 !(env->hflags & HF_SMM_MASK)) {
2330 cpu->exit_request = 1;
2331 }
2332 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2333 cpu->exit_request = 1;
2334 }
2335 }
2336
2337 if (!kvm_irqchip_in_kernel()) {
2338 /* Try to inject an interrupt if the guest can accept it */
2339 if (run->ready_for_interrupt_injection &&
2340 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2341 (env->eflags & IF_MASK)) {
2342 int irq;
2343
2344 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2345 irq = cpu_get_pic_interrupt(env);
2346 if (irq >= 0) {
2347 struct kvm_interrupt intr;
2348
2349 intr.irq = irq;
2350 DPRINTF("injected interrupt %d\n", irq);
2351 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2352 if (ret < 0) {
2353 fprintf(stderr,
2354 "KVM: injection failed, interrupt lost (%s)\n",
2355 strerror(-ret));
2356 }
2357 }
2358 }
2359
2360 /* If we have an interrupt but the guest is not ready to receive an
2361 * interrupt, request an interrupt window exit. This will
2362 * cause a return to userspace as soon as the guest is ready to
2363 * receive interrupts. */
2364 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2365 run->request_interrupt_window = 1;
2366 } else {
2367 run->request_interrupt_window = 0;
2368 }
2369
2370 DPRINTF("setting tpr\n");
2371 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2372
2373 qemu_mutex_unlock_iothread();
2374 }
2375 }
2376
2377 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2378 {
2379 X86CPU *x86_cpu = X86_CPU(cpu);
2380 CPUX86State *env = &x86_cpu->env;
2381
2382 if (run->flags & KVM_RUN_X86_SMM) {
2383 env->hflags |= HF_SMM_MASK;
2384 } else {
2385 env->hflags &= HF_SMM_MASK;
2386 }
2387 if (run->if_flag) {
2388 env->eflags |= IF_MASK;
2389 } else {
2390 env->eflags &= ~IF_MASK;
2391 }
2392
2393 /* We need to protect the apic state against concurrent accesses from
2394 * different threads in case the userspace irqchip is used. */
2395 if (!kvm_irqchip_in_kernel()) {
2396 qemu_mutex_lock_iothread();
2397 }
2398 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2399 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2400 if (!kvm_irqchip_in_kernel()) {
2401 qemu_mutex_unlock_iothread();
2402 }
2403 return cpu_get_mem_attrs(env);
2404 }
2405
2406 int kvm_arch_process_async_events(CPUState *cs)
2407 {
2408 X86CPU *cpu = X86_CPU(cs);
2409 CPUX86State *env = &cpu->env;
2410
2411 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2412 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2413 assert(env->mcg_cap);
2414
2415 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2416
2417 kvm_cpu_synchronize_state(cs);
2418
2419 if (env->exception_injected == EXCP08_DBLE) {
2420 /* this means triple fault */
2421 qemu_system_reset_request();
2422 cs->exit_request = 1;
2423 return 0;
2424 }
2425 env->exception_injected = EXCP12_MCHK;
2426 env->has_error_code = 0;
2427
2428 cs->halted = 0;
2429 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2430 env->mp_state = KVM_MP_STATE_RUNNABLE;
2431 }
2432 }
2433
2434 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2435 !(env->hflags & HF_SMM_MASK)) {
2436 kvm_cpu_synchronize_state(cs);
2437 do_cpu_init(cpu);
2438 }
2439
2440 if (kvm_irqchip_in_kernel()) {
2441 return 0;
2442 }
2443
2444 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2445 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2446 apic_poll_irq(cpu->apic_state);
2447 }
2448 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2449 (env->eflags & IF_MASK)) ||
2450 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2451 cs->halted = 0;
2452 }
2453 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2454 kvm_cpu_synchronize_state(cs);
2455 do_cpu_sipi(cpu);
2456 }
2457 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2458 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2459 kvm_cpu_synchronize_state(cs);
2460 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2461 env->tpr_access_type);
2462 }
2463
2464 return cs->halted;
2465 }
2466
2467 static int kvm_handle_halt(X86CPU *cpu)
2468 {
2469 CPUState *cs = CPU(cpu);
2470 CPUX86State *env = &cpu->env;
2471
2472 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2473 (env->eflags & IF_MASK)) &&
2474 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2475 cs->halted = 1;
2476 return EXCP_HLT;
2477 }
2478
2479 return 0;
2480 }
2481
2482 static int kvm_handle_tpr_access(X86CPU *cpu)
2483 {
2484 CPUState *cs = CPU(cpu);
2485 struct kvm_run *run = cs->kvm_run;
2486
2487 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2488 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2489 : TPR_ACCESS_READ);
2490 return 1;
2491 }
2492
2493 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2494 {
2495 static const uint8_t int3 = 0xcc;
2496
2497 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2498 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2499 return -EINVAL;
2500 }
2501 return 0;
2502 }
2503
2504 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2505 {
2506 uint8_t int3;
2507
2508 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2509 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2510 return -EINVAL;
2511 }
2512 return 0;
2513 }
2514
2515 static struct {
2516 target_ulong addr;
2517 int len;
2518 int type;
2519 } hw_breakpoint[4];
2520
2521 static int nb_hw_breakpoint;
2522
2523 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2524 {
2525 int n;
2526
2527 for (n = 0; n < nb_hw_breakpoint; n++) {
2528 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2529 (hw_breakpoint[n].len == len || len == -1)) {
2530 return n;
2531 }
2532 }
2533 return -1;
2534 }
2535
2536 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2537 target_ulong len, int type)
2538 {
2539 switch (type) {
2540 case GDB_BREAKPOINT_HW:
2541 len = 1;
2542 break;
2543 case GDB_WATCHPOINT_WRITE:
2544 case GDB_WATCHPOINT_ACCESS:
2545 switch (len) {
2546 case 1:
2547 break;
2548 case 2:
2549 case 4:
2550 case 8:
2551 if (addr & (len - 1)) {
2552 return -EINVAL;
2553 }
2554 break;
2555 default:
2556 return -EINVAL;
2557 }
2558 break;
2559 default:
2560 return -ENOSYS;
2561 }
2562
2563 if (nb_hw_breakpoint == 4) {
2564 return -ENOBUFS;
2565 }
2566 if (find_hw_breakpoint(addr, len, type) >= 0) {
2567 return -EEXIST;
2568 }
2569 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2570 hw_breakpoint[nb_hw_breakpoint].len = len;
2571 hw_breakpoint[nb_hw_breakpoint].type = type;
2572 nb_hw_breakpoint++;
2573
2574 return 0;
2575 }
2576
2577 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2578 target_ulong len, int type)
2579 {
2580 int n;
2581
2582 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2583 if (n < 0) {
2584 return -ENOENT;
2585 }
2586 nb_hw_breakpoint--;
2587 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2588
2589 return 0;
2590 }
2591
2592 void kvm_arch_remove_all_hw_breakpoints(void)
2593 {
2594 nb_hw_breakpoint = 0;
2595 }
2596
2597 static CPUWatchpoint hw_watchpoint;
2598
2599 static int kvm_handle_debug(X86CPU *cpu,
2600 struct kvm_debug_exit_arch *arch_info)
2601 {
2602 CPUState *cs = CPU(cpu);
2603 CPUX86State *env = &cpu->env;
2604 int ret = 0;
2605 int n;
2606
2607 if (arch_info->exception == 1) {
2608 if (arch_info->dr6 & (1 << 14)) {
2609 if (cs->singlestep_enabled) {
2610 ret = EXCP_DEBUG;
2611 }
2612 } else {
2613 for (n = 0; n < 4; n++) {
2614 if (arch_info->dr6 & (1 << n)) {
2615 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2616 case 0x0:
2617 ret = EXCP_DEBUG;
2618 break;
2619 case 0x1:
2620 ret = EXCP_DEBUG;
2621 cs->watchpoint_hit = &hw_watchpoint;
2622 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2623 hw_watchpoint.flags = BP_MEM_WRITE;
2624 break;
2625 case 0x3:
2626 ret = EXCP_DEBUG;
2627 cs->watchpoint_hit = &hw_watchpoint;
2628 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2629 hw_watchpoint.flags = BP_MEM_ACCESS;
2630 break;
2631 }
2632 }
2633 }
2634 }
2635 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2636 ret = EXCP_DEBUG;
2637 }
2638 if (ret == 0) {
2639 cpu_synchronize_state(cs);
2640 assert(env->exception_injected == -1);
2641
2642 /* pass to guest */
2643 env->exception_injected = arch_info->exception;
2644 env->has_error_code = 0;
2645 }
2646
2647 return ret;
2648 }
2649
2650 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2651 {
2652 const uint8_t type_code[] = {
2653 [GDB_BREAKPOINT_HW] = 0x0,
2654 [GDB_WATCHPOINT_WRITE] = 0x1,
2655 [GDB_WATCHPOINT_ACCESS] = 0x3
2656 };
2657 const uint8_t len_code[] = {
2658 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2659 };
2660 int n;
2661
2662 if (kvm_sw_breakpoints_active(cpu)) {
2663 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2664 }
2665 if (nb_hw_breakpoint > 0) {
2666 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2667 dbg->arch.debugreg[7] = 0x0600;
2668 for (n = 0; n < nb_hw_breakpoint; n++) {
2669 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2670 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2671 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2672 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2673 }
2674 }
2675 }
2676
2677 static bool host_supports_vmx(void)
2678 {
2679 uint32_t ecx, unused;
2680
2681 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2682 return ecx & CPUID_EXT_VMX;
2683 }
2684
2685 #define VMX_INVALID_GUEST_STATE 0x80000021
2686
2687 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2688 {
2689 X86CPU *cpu = X86_CPU(cs);
2690 uint64_t code;
2691 int ret;
2692
2693 switch (run->exit_reason) {
2694 case KVM_EXIT_HLT:
2695 DPRINTF("handle_hlt\n");
2696 qemu_mutex_lock_iothread();
2697 ret = kvm_handle_halt(cpu);
2698 qemu_mutex_unlock_iothread();
2699 break;
2700 case KVM_EXIT_SET_TPR:
2701 ret = 0;
2702 break;
2703 case KVM_EXIT_TPR_ACCESS:
2704 qemu_mutex_lock_iothread();
2705 ret = kvm_handle_tpr_access(cpu);
2706 qemu_mutex_unlock_iothread();
2707 break;
2708 case KVM_EXIT_FAIL_ENTRY:
2709 code = run->fail_entry.hardware_entry_failure_reason;
2710 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2711 code);
2712 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2713 fprintf(stderr,
2714 "\nIf you're running a guest on an Intel machine without "
2715 "unrestricted mode\n"
2716 "support, the failure can be most likely due to the guest "
2717 "entering an invalid\n"
2718 "state for Intel VT. For example, the guest maybe running "
2719 "in big real mode\n"
2720 "which is not supported on less recent Intel processors."
2721 "\n\n");
2722 }
2723 ret = -1;
2724 break;
2725 case KVM_EXIT_EXCEPTION:
2726 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2727 run->ex.exception, run->ex.error_code);
2728 ret = -1;
2729 break;
2730 case KVM_EXIT_DEBUG:
2731 DPRINTF("kvm_exit_debug\n");
2732 qemu_mutex_lock_iothread();
2733 ret = kvm_handle_debug(cpu, &run->debug.arch);
2734 qemu_mutex_unlock_iothread();
2735 break;
2736 default:
2737 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2738 ret = -1;
2739 break;
2740 }
2741
2742 return ret;
2743 }
2744
2745 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2746 {
2747 X86CPU *cpu = X86_CPU(cs);
2748 CPUX86State *env = &cpu->env;
2749
2750 kvm_cpu_synchronize_state(cs);
2751 return !(env->cr[0] & CR0_PE_MASK) ||
2752 ((env->segs[R_CS].selector & 3) != 3);
2753 }
2754
2755 void kvm_arch_init_irq_routing(KVMState *s)
2756 {
2757 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2758 /* If kernel can't do irq routing, interrupt source
2759 * override 0->2 cannot be set up as required by HPET.
2760 * So we have to disable it.
2761 */
2762 no_hpet = 1;
2763 }
2764 /* We know at this point that we're using the in-kernel
2765 * irqchip, so we can use irqfds, and on x86 we know
2766 * we can use msi via irqfd and GSI routing.
2767 */
2768 kvm_msi_via_irqfd_allowed = true;
2769 kvm_gsi_routing_allowed = true;
2770 }
2771
2772 /* Classic KVM device assignment interface. Will remain x86 only. */
2773 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2774 uint32_t flags, uint32_t *dev_id)
2775 {
2776 struct kvm_assigned_pci_dev dev_data = {
2777 .segnr = dev_addr->domain,
2778 .busnr = dev_addr->bus,
2779 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2780 .flags = flags,
2781 };
2782 int ret;
2783
2784 dev_data.assigned_dev_id =
2785 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2786
2787 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2788 if (ret < 0) {
2789 return ret;
2790 }
2791
2792 *dev_id = dev_data.assigned_dev_id;
2793
2794 return 0;
2795 }
2796
2797 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2798 {
2799 struct kvm_assigned_pci_dev dev_data = {
2800 .assigned_dev_id = dev_id,
2801 };
2802
2803 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2804 }
2805
2806 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2807 uint32_t irq_type, uint32_t guest_irq)
2808 {
2809 struct kvm_assigned_irq assigned_irq = {
2810 .assigned_dev_id = dev_id,
2811 .guest_irq = guest_irq,
2812 .flags = irq_type,
2813 };
2814
2815 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2816 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2817 } else {
2818 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2819 }
2820 }
2821
2822 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2823 uint32_t guest_irq)
2824 {
2825 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2826 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2827
2828 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2829 }
2830
2831 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2832 {
2833 struct kvm_assigned_pci_dev dev_data = {
2834 .assigned_dev_id = dev_id,
2835 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2836 };
2837
2838 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2839 }
2840
2841 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2842 uint32_t type)
2843 {
2844 struct kvm_assigned_irq assigned_irq = {
2845 .assigned_dev_id = dev_id,
2846 .flags = type,
2847 };
2848
2849 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2850 }
2851
2852 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2853 {
2854 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2855 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2856 }
2857
2858 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2859 {
2860 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2861 KVM_DEV_IRQ_GUEST_MSI, virq);
2862 }
2863
2864 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2865 {
2866 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2867 KVM_DEV_IRQ_HOST_MSI);
2868 }
2869
2870 bool kvm_device_msix_supported(KVMState *s)
2871 {
2872 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2873 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2874 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2875 }
2876
2877 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2878 uint32_t nr_vectors)
2879 {
2880 struct kvm_assigned_msix_nr msix_nr = {
2881 .assigned_dev_id = dev_id,
2882 .entry_nr = nr_vectors,
2883 };
2884
2885 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2886 }
2887
2888 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2889 int virq)
2890 {
2891 struct kvm_assigned_msix_entry msix_entry = {
2892 .assigned_dev_id = dev_id,
2893 .gsi = virq,
2894 .entry = vector,
2895 };
2896
2897 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2898 }
2899
2900 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2901 {
2902 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2903 KVM_DEV_IRQ_GUEST_MSIX, 0);
2904 }
2905
2906 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2907 {
2908 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2909 KVM_DEV_IRQ_HOST_MSIX);
2910 }
2911
2912 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2913 uint64_t address, uint32_t data)
2914 {
2915 return 0;
2916 }
2917
2918 int kvm_arch_msi_data_to_gsi(uint32_t data)
2919 {
2920 abort();
2921 }
AR7 emulation for QEMU