4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This code is licensed under the GNU GPL v2 or later.
8 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "qemu/osdep.h"
13 #include "internals.h"
15 /* CPU models. These are not needed for the AArch64 linux-user build. */
16 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
18 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
20 CPUClass
*cc
= CPU_GET_CLASS(cs
);
21 ARMCPU
*cpu
= ARM_CPU(cs
);
22 CPUARMState
*env
= &cpu
->env
;
26 * ARMv7-M interrupt masking works differently than -A or -R.
27 * There is no FIQ/IRQ distinction. Instead of I and F bits
28 * masking FIQ and IRQ interrupts, an exception is taken only
29 * if it is higher priority than the current execution priority
30 * (which depends on state like BASEPRI, FAULTMASK and the
31 * currently active exception).
33 if (interrupt_request
& CPU_INTERRUPT_HARD
34 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
35 cs
->exception_index
= EXCP_IRQ
;
42 static void arm926_initfn(Object
*obj
)
44 ARMCPU
*cpu
= ARM_CPU(obj
);
46 cpu
->dtb_compatible
= "arm,arm926";
47 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
48 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
49 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
50 cpu
->midr
= 0x41069265;
51 cpu
->reset_fpsid
= 0x41011090;
53 cpu
->reset_sctlr
= 0x00090078;
56 * ARMv5 does not have the ID_ISAR registers, but we can still
57 * set the field to indicate Jazelle support within QEMU.
59 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
61 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
62 * support even though ARMv5 doesn't have this register.
64 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
65 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSP
, 1);
66 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
69 static void arm946_initfn(Object
*obj
)
71 ARMCPU
*cpu
= ARM_CPU(obj
);
73 cpu
->dtb_compatible
= "arm,arm946";
74 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
75 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
76 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
77 cpu
->midr
= 0x41059461;
78 cpu
->ctr
= 0x0f004006;
79 cpu
->reset_sctlr
= 0x00000078;
82 static void arm1026_initfn(Object
*obj
)
84 ARMCPU
*cpu
= ARM_CPU(obj
);
86 cpu
->dtb_compatible
= "arm,arm1026";
87 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
88 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
89 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
90 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
91 cpu
->midr
= 0x4106a262;
92 cpu
->reset_fpsid
= 0x410110a0;
94 cpu
->reset_sctlr
= 0x00090078;
98 * ARMv5 does not have the ID_ISAR registers, but we can still
99 * set the field to indicate Jazelle support within QEMU.
101 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
103 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
104 * support even though ARMv5 doesn't have this register.
106 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
107 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSP
, 1);
108 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
111 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
112 ARMCPRegInfo ifar
= {
113 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
115 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
118 define_one_arm_cp_reg(cpu
, &ifar
);
122 static void arm1136_r2_initfn(Object
*obj
)
124 ARMCPU
*cpu
= ARM_CPU(obj
);
126 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
127 * older core than plain "arm1136". In particular this does not
128 * have the v6K features.
129 * These ID register values are correct for 1136 but may be wrong
130 * for 1136_r2 (in particular r0p2 does not actually implement most
131 * of the ID registers).
134 cpu
->dtb_compatible
= "arm,arm1136";
135 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
136 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
137 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
138 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
139 cpu
->midr
= 0x4107b362;
140 cpu
->reset_fpsid
= 0x410120b4;
141 cpu
->isar
.mvfr0
= 0x11111111;
142 cpu
->isar
.mvfr1
= 0x00000000;
143 cpu
->ctr
= 0x1dd20d2;
144 cpu
->reset_sctlr
= 0x00050078;
145 cpu
->isar
.id_pfr0
= 0x111;
146 cpu
->isar
.id_pfr1
= 0x1;
147 cpu
->isar
.id_dfr0
= 0x2;
149 cpu
->isar
.id_mmfr0
= 0x01130003;
150 cpu
->isar
.id_mmfr1
= 0x10030302;
151 cpu
->isar
.id_mmfr2
= 0x01222110;
152 cpu
->isar
.id_isar0
= 0x00140011;
153 cpu
->isar
.id_isar1
= 0x12002111;
154 cpu
->isar
.id_isar2
= 0x11231111;
155 cpu
->isar
.id_isar3
= 0x01102131;
156 cpu
->isar
.id_isar4
= 0x141;
157 cpu
->reset_auxcr
= 7;
160 static void arm1136_initfn(Object
*obj
)
162 ARMCPU
*cpu
= ARM_CPU(obj
);
164 cpu
->dtb_compatible
= "arm,arm1136";
165 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
166 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
167 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
168 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
169 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
170 cpu
->midr
= 0x4117b363;
171 cpu
->reset_fpsid
= 0x410120b4;
172 cpu
->isar
.mvfr0
= 0x11111111;
173 cpu
->isar
.mvfr1
= 0x00000000;
174 cpu
->ctr
= 0x1dd20d2;
175 cpu
->reset_sctlr
= 0x00050078;
176 cpu
->isar
.id_pfr0
= 0x111;
177 cpu
->isar
.id_pfr1
= 0x1;
178 cpu
->isar
.id_dfr0
= 0x2;
180 cpu
->isar
.id_mmfr0
= 0x01130003;
181 cpu
->isar
.id_mmfr1
= 0x10030302;
182 cpu
->isar
.id_mmfr2
= 0x01222110;
183 cpu
->isar
.id_isar0
= 0x00140011;
184 cpu
->isar
.id_isar1
= 0x12002111;
185 cpu
->isar
.id_isar2
= 0x11231111;
186 cpu
->isar
.id_isar3
= 0x01102131;
187 cpu
->isar
.id_isar4
= 0x141;
188 cpu
->reset_auxcr
= 7;
191 static void arm1176_initfn(Object
*obj
)
193 ARMCPU
*cpu
= ARM_CPU(obj
);
195 cpu
->dtb_compatible
= "arm,arm1176";
196 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
197 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
198 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
199 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
200 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
201 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
202 cpu
->midr
= 0x410fb767;
203 cpu
->reset_fpsid
= 0x410120b5;
204 cpu
->isar
.mvfr0
= 0x11111111;
205 cpu
->isar
.mvfr1
= 0x00000000;
206 cpu
->ctr
= 0x1dd20d2;
207 cpu
->reset_sctlr
= 0x00050078;
208 cpu
->isar
.id_pfr0
= 0x111;
209 cpu
->isar
.id_pfr1
= 0x11;
210 cpu
->isar
.id_dfr0
= 0x33;
212 cpu
->isar
.id_mmfr0
= 0x01130003;
213 cpu
->isar
.id_mmfr1
= 0x10030302;
214 cpu
->isar
.id_mmfr2
= 0x01222100;
215 cpu
->isar
.id_isar0
= 0x0140011;
216 cpu
->isar
.id_isar1
= 0x12002111;
217 cpu
->isar
.id_isar2
= 0x11231121;
218 cpu
->isar
.id_isar3
= 0x01102131;
219 cpu
->isar
.id_isar4
= 0x01141;
220 cpu
->reset_auxcr
= 7;
223 static void arm11mpcore_initfn(Object
*obj
)
225 ARMCPU
*cpu
= ARM_CPU(obj
);
227 cpu
->dtb_compatible
= "arm,arm11mpcore";
228 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
229 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
230 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
231 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
232 cpu
->midr
= 0x410fb022;
233 cpu
->reset_fpsid
= 0x410120b4;
234 cpu
->isar
.mvfr0
= 0x11111111;
235 cpu
->isar
.mvfr1
= 0x00000000;
236 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
237 cpu
->isar
.id_pfr0
= 0x111;
238 cpu
->isar
.id_pfr1
= 0x1;
239 cpu
->isar
.id_dfr0
= 0;
241 cpu
->isar
.id_mmfr0
= 0x01100103;
242 cpu
->isar
.id_mmfr1
= 0x10020302;
243 cpu
->isar
.id_mmfr2
= 0x01222000;
244 cpu
->isar
.id_isar0
= 0x00100011;
245 cpu
->isar
.id_isar1
= 0x12002111;
246 cpu
->isar
.id_isar2
= 0x11221011;
247 cpu
->isar
.id_isar3
= 0x01102131;
248 cpu
->isar
.id_isar4
= 0x141;
249 cpu
->reset_auxcr
= 1;
252 static void cortex_m0_initfn(Object
*obj
)
254 ARMCPU
*cpu
= ARM_CPU(obj
);
255 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
256 set_feature(&cpu
->env
, ARM_FEATURE_M
);
258 cpu
->midr
= 0x410cc200;
261 * These ID register values are not guest visible, because
262 * we do not implement the Main Extension. They must be set
263 * to values corresponding to the Cortex-M0's implemented
264 * features, because QEMU generally controls its emulation
265 * by looking at ID register fields. We use the same values as
268 cpu
->isar
.id_pfr0
= 0x00000030;
269 cpu
->isar
.id_pfr1
= 0x00000200;
270 cpu
->isar
.id_dfr0
= 0x00100000;
271 cpu
->id_afr0
= 0x00000000;
272 cpu
->isar
.id_mmfr0
= 0x00000030;
273 cpu
->isar
.id_mmfr1
= 0x00000000;
274 cpu
->isar
.id_mmfr2
= 0x00000000;
275 cpu
->isar
.id_mmfr3
= 0x00000000;
276 cpu
->isar
.id_isar0
= 0x01141110;
277 cpu
->isar
.id_isar1
= 0x02111000;
278 cpu
->isar
.id_isar2
= 0x21112231;
279 cpu
->isar
.id_isar3
= 0x01111110;
280 cpu
->isar
.id_isar4
= 0x01310102;
281 cpu
->isar
.id_isar5
= 0x00000000;
282 cpu
->isar
.id_isar6
= 0x00000000;
285 static void cortex_m3_initfn(Object
*obj
)
287 ARMCPU
*cpu
= ARM_CPU(obj
);
288 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
289 set_feature(&cpu
->env
, ARM_FEATURE_M
);
290 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
291 cpu
->midr
= 0x410fc231;
292 cpu
->pmsav7_dregion
= 8;
293 cpu
->isar
.id_pfr0
= 0x00000030;
294 cpu
->isar
.id_pfr1
= 0x00000200;
295 cpu
->isar
.id_dfr0
= 0x00100000;
296 cpu
->id_afr0
= 0x00000000;
297 cpu
->isar
.id_mmfr0
= 0x00000030;
298 cpu
->isar
.id_mmfr1
= 0x00000000;
299 cpu
->isar
.id_mmfr2
= 0x00000000;
300 cpu
->isar
.id_mmfr3
= 0x00000000;
301 cpu
->isar
.id_isar0
= 0x01141110;
302 cpu
->isar
.id_isar1
= 0x02111000;
303 cpu
->isar
.id_isar2
= 0x21112231;
304 cpu
->isar
.id_isar3
= 0x01111110;
305 cpu
->isar
.id_isar4
= 0x01310102;
306 cpu
->isar
.id_isar5
= 0x00000000;
307 cpu
->isar
.id_isar6
= 0x00000000;
310 static void cortex_m4_initfn(Object
*obj
)
312 ARMCPU
*cpu
= ARM_CPU(obj
);
314 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
315 set_feature(&cpu
->env
, ARM_FEATURE_M
);
316 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
317 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
318 cpu
->midr
= 0x410fc240; /* r0p0 */
319 cpu
->pmsav7_dregion
= 8;
320 cpu
->isar
.mvfr0
= 0x10110021;
321 cpu
->isar
.mvfr1
= 0x11000011;
322 cpu
->isar
.mvfr2
= 0x00000000;
323 cpu
->isar
.id_pfr0
= 0x00000030;
324 cpu
->isar
.id_pfr1
= 0x00000200;
325 cpu
->isar
.id_dfr0
= 0x00100000;
326 cpu
->id_afr0
= 0x00000000;
327 cpu
->isar
.id_mmfr0
= 0x00000030;
328 cpu
->isar
.id_mmfr1
= 0x00000000;
329 cpu
->isar
.id_mmfr2
= 0x00000000;
330 cpu
->isar
.id_mmfr3
= 0x00000000;
331 cpu
->isar
.id_isar0
= 0x01141110;
332 cpu
->isar
.id_isar1
= 0x02111000;
333 cpu
->isar
.id_isar2
= 0x21112231;
334 cpu
->isar
.id_isar3
= 0x01111110;
335 cpu
->isar
.id_isar4
= 0x01310102;
336 cpu
->isar
.id_isar5
= 0x00000000;
337 cpu
->isar
.id_isar6
= 0x00000000;
340 static void cortex_m7_initfn(Object
*obj
)
342 ARMCPU
*cpu
= ARM_CPU(obj
);
344 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
345 set_feature(&cpu
->env
, ARM_FEATURE_M
);
346 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
347 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
348 cpu
->midr
= 0x411fc272; /* r1p2 */
349 cpu
->pmsav7_dregion
= 8;
350 cpu
->isar
.mvfr0
= 0x10110221;
351 cpu
->isar
.mvfr1
= 0x12000011;
352 cpu
->isar
.mvfr2
= 0x00000040;
353 cpu
->isar
.id_pfr0
= 0x00000030;
354 cpu
->isar
.id_pfr1
= 0x00000200;
355 cpu
->isar
.id_dfr0
= 0x00100000;
356 cpu
->id_afr0
= 0x00000000;
357 cpu
->isar
.id_mmfr0
= 0x00100030;
358 cpu
->isar
.id_mmfr1
= 0x00000000;
359 cpu
->isar
.id_mmfr2
= 0x01000000;
360 cpu
->isar
.id_mmfr3
= 0x00000000;
361 cpu
->isar
.id_isar0
= 0x01101110;
362 cpu
->isar
.id_isar1
= 0x02112000;
363 cpu
->isar
.id_isar2
= 0x20232231;
364 cpu
->isar
.id_isar3
= 0x01111131;
365 cpu
->isar
.id_isar4
= 0x01310132;
366 cpu
->isar
.id_isar5
= 0x00000000;
367 cpu
->isar
.id_isar6
= 0x00000000;
370 static void cortex_m33_initfn(Object
*obj
)
372 ARMCPU
*cpu
= ARM_CPU(obj
);
374 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
375 set_feature(&cpu
->env
, ARM_FEATURE_M
);
376 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
377 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
378 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
379 cpu
->midr
= 0x410fd213; /* r0p3 */
380 cpu
->pmsav7_dregion
= 16;
381 cpu
->sau_sregion
= 8;
382 cpu
->isar
.mvfr0
= 0x10110021;
383 cpu
->isar
.mvfr1
= 0x11000011;
384 cpu
->isar
.mvfr2
= 0x00000040;
385 cpu
->isar
.id_pfr0
= 0x00000030;
386 cpu
->isar
.id_pfr1
= 0x00000210;
387 cpu
->isar
.id_dfr0
= 0x00200000;
388 cpu
->id_afr0
= 0x00000000;
389 cpu
->isar
.id_mmfr0
= 0x00101F40;
390 cpu
->isar
.id_mmfr1
= 0x00000000;
391 cpu
->isar
.id_mmfr2
= 0x01000000;
392 cpu
->isar
.id_mmfr3
= 0x00000000;
393 cpu
->isar
.id_isar0
= 0x01101110;
394 cpu
->isar
.id_isar1
= 0x02212000;
395 cpu
->isar
.id_isar2
= 0x20232232;
396 cpu
->isar
.id_isar3
= 0x01111131;
397 cpu
->isar
.id_isar4
= 0x01310132;
398 cpu
->isar
.id_isar5
= 0x00000000;
399 cpu
->isar
.id_isar6
= 0x00000000;
400 cpu
->clidr
= 0x00000000;
401 cpu
->ctr
= 0x8000c000;
404 static void cortex_m55_initfn(Object
*obj
)
406 ARMCPU
*cpu
= ARM_CPU(obj
);
408 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
409 set_feature(&cpu
->env
, ARM_FEATURE_V8_1M
);
410 set_feature(&cpu
->env
, ARM_FEATURE_M
);
411 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
412 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
413 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
414 cpu
->midr
= 0x410fd221; /* r0p1 */
416 cpu
->pmsav7_dregion
= 16;
417 cpu
->sau_sregion
= 8;
419 * These are the MVFR* values for the FPU, no MVE configuration;
420 * we will update them later when we implement MVE
422 cpu
->isar
.mvfr0
= 0x10110221;
423 cpu
->isar
.mvfr1
= 0x12100011;
424 cpu
->isar
.mvfr2
= 0x00000040;
425 cpu
->isar
.id_pfr0
= 0x20000030;
426 cpu
->isar
.id_pfr1
= 0x00000230;
427 cpu
->isar
.id_dfr0
= 0x10200000;
428 cpu
->id_afr0
= 0x00000000;
429 cpu
->isar
.id_mmfr0
= 0x00111040;
430 cpu
->isar
.id_mmfr1
= 0x00000000;
431 cpu
->isar
.id_mmfr2
= 0x01000000;
432 cpu
->isar
.id_mmfr3
= 0x00000011;
433 cpu
->isar
.id_isar0
= 0x01103110;
434 cpu
->isar
.id_isar1
= 0x02212000;
435 cpu
->isar
.id_isar2
= 0x20232232;
436 cpu
->isar
.id_isar3
= 0x01111131;
437 cpu
->isar
.id_isar4
= 0x01310132;
438 cpu
->isar
.id_isar5
= 0x00000000;
439 cpu
->isar
.id_isar6
= 0x00000000;
440 cpu
->clidr
= 0x00000000; /* caches not implemented */
441 cpu
->ctr
= 0x8303c003;
444 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
445 /* Dummy the TCM region regs for the moment */
446 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
447 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
448 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
449 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
450 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
451 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
455 static void cortex_r5_initfn(Object
*obj
)
457 ARMCPU
*cpu
= ARM_CPU(obj
);
459 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
460 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
461 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
462 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
463 cpu
->midr
= 0x411fc153; /* r1p3 */
464 cpu
->isar
.id_pfr0
= 0x0131;
465 cpu
->isar
.id_pfr1
= 0x001;
466 cpu
->isar
.id_dfr0
= 0x010400;
468 cpu
->isar
.id_mmfr0
= 0x0210030;
469 cpu
->isar
.id_mmfr1
= 0x00000000;
470 cpu
->isar
.id_mmfr2
= 0x01200000;
471 cpu
->isar
.id_mmfr3
= 0x0211;
472 cpu
->isar
.id_isar0
= 0x02101111;
473 cpu
->isar
.id_isar1
= 0x13112111;
474 cpu
->isar
.id_isar2
= 0x21232141;
475 cpu
->isar
.id_isar3
= 0x01112131;
476 cpu
->isar
.id_isar4
= 0x0010142;
477 cpu
->isar
.id_isar5
= 0x0;
478 cpu
->isar
.id_isar6
= 0x0;
479 cpu
->mp_is_up
= true;
480 cpu
->pmsav7_dregion
= 16;
481 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
484 static void cortex_r5f_initfn(Object
*obj
)
486 ARMCPU
*cpu
= ARM_CPU(obj
);
488 cortex_r5_initfn(obj
);
489 cpu
->isar
.mvfr0
= 0x10110221;
490 cpu
->isar
.mvfr1
= 0x00000011;
493 static void ti925t_initfn(Object
*obj
)
495 ARMCPU
*cpu
= ARM_CPU(obj
);
496 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
497 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
498 cpu
->midr
= ARM_CPUID_TI925T
;
499 cpu
->ctr
= 0x5109149;
500 cpu
->reset_sctlr
= 0x00000070;
503 static void sa1100_initfn(Object
*obj
)
505 ARMCPU
*cpu
= ARM_CPU(obj
);
507 cpu
->dtb_compatible
= "intel,sa1100";
508 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
509 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
510 cpu
->midr
= 0x4401A11B;
511 cpu
->reset_sctlr
= 0x00000070;
514 static void sa1110_initfn(Object
*obj
)
516 ARMCPU
*cpu
= ARM_CPU(obj
);
517 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
518 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
519 cpu
->midr
= 0x6901B119;
520 cpu
->reset_sctlr
= 0x00000070;
523 static void pxa250_initfn(Object
*obj
)
525 ARMCPU
*cpu
= ARM_CPU(obj
);
527 cpu
->dtb_compatible
= "marvell,xscale";
528 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
529 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
530 cpu
->midr
= 0x69052100;
531 cpu
->ctr
= 0xd172172;
532 cpu
->reset_sctlr
= 0x00000078;
535 static void pxa255_initfn(Object
*obj
)
537 ARMCPU
*cpu
= ARM_CPU(obj
);
539 cpu
->dtb_compatible
= "marvell,xscale";
540 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
541 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
542 cpu
->midr
= 0x69052d00;
543 cpu
->ctr
= 0xd172172;
544 cpu
->reset_sctlr
= 0x00000078;
547 static void pxa260_initfn(Object
*obj
)
549 ARMCPU
*cpu
= ARM_CPU(obj
);
551 cpu
->dtb_compatible
= "marvell,xscale";
552 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
553 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
554 cpu
->midr
= 0x69052903;
555 cpu
->ctr
= 0xd172172;
556 cpu
->reset_sctlr
= 0x00000078;
559 static void pxa261_initfn(Object
*obj
)
561 ARMCPU
*cpu
= ARM_CPU(obj
);
563 cpu
->dtb_compatible
= "marvell,xscale";
564 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
565 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
566 cpu
->midr
= 0x69052d05;
567 cpu
->ctr
= 0xd172172;
568 cpu
->reset_sctlr
= 0x00000078;
571 static void pxa262_initfn(Object
*obj
)
573 ARMCPU
*cpu
= ARM_CPU(obj
);
575 cpu
->dtb_compatible
= "marvell,xscale";
576 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
577 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
578 cpu
->midr
= 0x69052d06;
579 cpu
->ctr
= 0xd172172;
580 cpu
->reset_sctlr
= 0x00000078;
583 static void pxa270a0_initfn(Object
*obj
)
585 ARMCPU
*cpu
= ARM_CPU(obj
);
587 cpu
->dtb_compatible
= "marvell,xscale";
588 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
589 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
590 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
591 cpu
->midr
= 0x69054110;
592 cpu
->ctr
= 0xd172172;
593 cpu
->reset_sctlr
= 0x00000078;
596 static void pxa270a1_initfn(Object
*obj
)
598 ARMCPU
*cpu
= ARM_CPU(obj
);
600 cpu
->dtb_compatible
= "marvell,xscale";
601 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
602 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
603 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
604 cpu
->midr
= 0x69054111;
605 cpu
->ctr
= 0xd172172;
606 cpu
->reset_sctlr
= 0x00000078;
609 static void pxa270b0_initfn(Object
*obj
)
611 ARMCPU
*cpu
= ARM_CPU(obj
);
613 cpu
->dtb_compatible
= "marvell,xscale";
614 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
615 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
616 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
617 cpu
->midr
= 0x69054112;
618 cpu
->ctr
= 0xd172172;
619 cpu
->reset_sctlr
= 0x00000078;
622 static void pxa270b1_initfn(Object
*obj
)
624 ARMCPU
*cpu
= ARM_CPU(obj
);
626 cpu
->dtb_compatible
= "marvell,xscale";
627 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
628 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
629 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
630 cpu
->midr
= 0x69054113;
631 cpu
->ctr
= 0xd172172;
632 cpu
->reset_sctlr
= 0x00000078;
635 static void pxa270c0_initfn(Object
*obj
)
637 ARMCPU
*cpu
= ARM_CPU(obj
);
639 cpu
->dtb_compatible
= "marvell,xscale";
640 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
641 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
642 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
643 cpu
->midr
= 0x69054114;
644 cpu
->ctr
= 0xd172172;
645 cpu
->reset_sctlr
= 0x00000078;
648 static void pxa270c5_initfn(Object
*obj
)
650 ARMCPU
*cpu
= ARM_CPU(obj
);
652 cpu
->dtb_compatible
= "marvell,xscale";
653 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
654 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
655 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
656 cpu
->midr
= 0x69054117;
657 cpu
->ctr
= 0xd172172;
658 cpu
->reset_sctlr
= 0x00000078;
661 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
663 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
664 CPUClass
*cc
= CPU_CLASS(oc
);
667 #ifndef CONFIG_USER_ONLY
668 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
671 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
672 cc
->gdb_core_xml_file
= "arm-m-profile.xml";
675 static const ARMCPUInfo arm_tcg_cpus
[] = {
676 { .name
= "arm926", .initfn
= arm926_initfn
},
677 { .name
= "arm946", .initfn
= arm946_initfn
},
678 { .name
= "arm1026", .initfn
= arm1026_initfn
},
680 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
681 * older core than plain "arm1136". In particular this does not
682 * have the v6K features.
684 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
685 { .name
= "arm1136", .initfn
= arm1136_initfn
},
686 { .name
= "arm1176", .initfn
= arm1176_initfn
},
687 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
688 { .name
= "cortex-m0", .initfn
= cortex_m0_initfn
,
689 .class_init
= arm_v7m_class_init
},
690 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
691 .class_init
= arm_v7m_class_init
},
692 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
693 .class_init
= arm_v7m_class_init
},
694 { .name
= "cortex-m7", .initfn
= cortex_m7_initfn
,
695 .class_init
= arm_v7m_class_init
},
696 { .name
= "cortex-m33", .initfn
= cortex_m33_initfn
,
697 .class_init
= arm_v7m_class_init
},
698 { .name
= "cortex-m55", .initfn
= cortex_m55_initfn
,
699 .class_init
= arm_v7m_class_init
},
700 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
701 { .name
= "cortex-r5f", .initfn
= cortex_r5f_initfn
},
702 { .name
= "ti925t", .initfn
= ti925t_initfn
},
703 { .name
= "sa1100", .initfn
= sa1100_initfn
},
704 { .name
= "sa1110", .initfn
= sa1110_initfn
},
705 { .name
= "pxa250", .initfn
= pxa250_initfn
},
706 { .name
= "pxa255", .initfn
= pxa255_initfn
},
707 { .name
= "pxa260", .initfn
= pxa260_initfn
},
708 { .name
= "pxa261", .initfn
= pxa261_initfn
},
709 { .name
= "pxa262", .initfn
= pxa262_initfn
},
710 /* "pxa270" is an alias for "pxa270-a0" */
711 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
712 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
713 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
714 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
715 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
716 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
717 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
720 static void arm_tcg_cpu_register_types(void)
724 for (i
= 0; i
< ARRAY_SIZE(arm_tcg_cpus
); ++i
) {
725 arm_cpu_register(&arm_tcg_cpus
[i
]);
729 type_init(arm_tcg_cpu_register_types
)
731 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */