hw/audio/gusemu_hal.c

   1 /*
   2  * GUSEMU32 - bus interface part
   3  *
   4  * Copyright (C) 2000-2007 Tibor "TS" Schütz
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /*
  26  * TODO: check mixer: see 7.20 of sdk for panning pos (applies to all gus models?)?
  27  */
  28
  29 #include "qemu/osdep.h"
  30 #include "gustate.h"
  31 #include "gusemu.h"
  32
  33 #define GUSregb(position) (*            (gusptr+(position)))
  34 #define GUSregw(position) (*(uint16_t *) (gusptr+(position)))
  35 #define GUSregd(position) (*(uint16_t *)(gusptr+(position)))
  36
  37 /* size given in bytes */
  38 unsigned int gus_read(GUSEmuState * state, int port, int size)
  39 {
  40     int             value_read = 0;
  41
  42     uint8_t        *gusptr;
  43     gusptr = state->gusdatapos;
  44     GUSregd(portaccesses)++;
  45
  46     switch (port & 0xff0f)
  47     {
  48         /* MixerCtrlReg (read not supported on GUS classic) */
  49         /* case 0x200: return GUSregb(MixerCtrlReg2x0); */
  50     case 0x206:                          /* IRQstatReg / SB2x6IRQ */
  51         /* adlib/sb bits set in port handlers */
  52         /* timer/voice bits set in gus_irqgen() */
  53         /* dma bit set in gus_dma_transferdata */
  54         /* midi not implemented yet */
  55         return GUSregb(IRQStatReg2x6);
  56     /* case 0x308:                       */ /* AdLib388 */
  57     case 0x208:
  58         if (GUSregb(GUS45TimerCtrl) & 1)
  59             return GUSregb(TimerStatus2x8);
  60         return GUSregb(AdLibStatus2x8);  /* AdLibStatus */
  61     case 0x309:                          /* AdLib389 */
  62     case 0x209:
  63         return GUSregb(AdLibData2x9);    /* AdLibData */
  64     case 0x20A:
  65         return GUSregb(AdLibCommand2xA); /* AdLib2x8_2xA */
  66
  67 #if 0
  68     case 0x20B:                          /* GUS hidden registers (read not supported on GUS classic) */
  69         switch (GUSregb(RegCtrl_2xF) & 0x07)
  70         {
  71         case 0:                                 /* IRQ/DMA select */
  72             if (GUSregb(MixerCtrlReg2x0) & 0x40)
  73                 return GUSregb(IRQ_2xB);        /* control register select bit */
  74             else
  75                 return GUSregb(DMA_2xB);
  76             /* case 1-5:                        */ /* general purpose emulation regs  */
  77             /*  return ...                      */ /* + status reset reg (write only) */
  78         case 6:
  79             return GUSregb(Jumper_2xB);         /* Joystick/MIDI enable (JumperReg) */
  80         default:;
  81         }
  82         break;
  83 #endif
  84
  85     case 0x20C:                          /* SB2xCd */
  86         value_read = GUSregb(SB2xCd);
  87         if (GUSregb(StatRead_2xF) & 0x20)
  88             GUSregb(SB2xCd) ^= 0x80; /* toggle MSB on read */
  89         return value_read;
  90         /* case 0x20D:                   */ /* SB2xD is write only -> 2xE writes to it*/
  91     case 0x20E:
  92         if (GUSregb(RegCtrl_2xF) & 0x80) /* 2xE read IRQ enabled? */
  93         {
  94             GUSregb(StatRead_2xF) |= 0x80;
  95             GUS_irqrequest(state, state->gusirq, 1);
  96         }
  97         return GUSregb(SB2xE);           /* SB2xE */
  98     case 0x20F:                          /* StatRead_2xF */
  99         /*set/clear fixed bits */
 100         /*value_read = (GUSregb(StatRead_2xF) & 0xf9)|1; */ /*(LSB not set on GUS classic!)*/
 101         value_read = (GUSregb(StatRead_2xF) & 0xf9);
 102         if (GUSregb(MixerCtrlReg2x0) & 0x08)
 103             value_read |= 2;    /* DMA/IRQ enabled flag */
 104         return value_read;
 105     /* case 0x300:                      */ /* MIDI (not implemented) */
 106     /* case 0x301:                      */ /* MIDI (not implemented) */
 107     case 0x302:
 108         return GUSregb(VoiceSelReg3x2); /* VoiceSelReg */
 109     case 0x303:
 110         return GUSregb(FunkSelReg3x3);  /* FunkSelReg */
 111     case 0x304:                         /* DataRegLoByte3x4 + DataRegWord3x4 */
 112     case 0x305:                         /* DataRegHiByte3x5 */
 113         switch (GUSregb(FunkSelReg3x3))
 114         {
 115     /* common functions */
 116         case 0x41:                      /* DramDMAContrReg */
 117             value_read = GUSregb(GUS41DMACtrl); /* &0xfb */
 118             GUSregb(GUS41DMACtrl) &= 0xbb;
 119             if (state->gusdma >= 4)
 120                 value_read |= 0x04;
 121             if (GUSregb(IRQStatReg2x6) & 0x80)
 122             {
 123                 value_read |= 0x40;
 124                 GUSregb(IRQStatReg2x6) &= 0x7f;
 125                 if (!GUSregb(IRQStatReg2x6))
 126                     GUS_irqclear(state, state->gusirq);
 127             }
 128             return (uint8_t) value_read;
 129             /* DramDMAmemPosReg */
 130             /* case 0x42: value_read=GUSregw(GUS42DMAStart); break;*/
 131             /* 43h+44h write only */
 132         case 0x45:
 133             return GUSregb(GUS45TimerCtrl);         /* TimerCtrlReg */
 134             /* 46h+47h write only */
 135             /* 48h: samp freq - write only */
 136         case 0x49:
 137             return GUSregb(GUS49SampCtrl) & 0xbf;   /* SampCtrlReg */
 138         /* case 4bh:                                */ /* joystick trim not supported */
 139         /* case 0x4c: return GUSregb(GUS4cReset);   */ /* GUSreset: write only*/
 140     /* voice specific functions */
 141         case 0x80:
 142         case 0x81:
 143         case 0x82:
 144         case 0x83:
 145         case 0x84:
 146         case 0x85:
 147         case 0x86:
 148         case 0x87:
 149         case 0x88:
 150         case 0x89:
 151         case 0x8a:
 152         case 0x8b:
 153         case 0x8c:
 154         case 0x8d:
 155             {
 156                 int             offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f);
 157                 offset += ((int) GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /* = Voice*32 + Funktion*2 */
 158                 value_read = GUSregw(offset);
 159             }
 160             break;
 161     /* voice unspecific functions */
 162         case 0x8e:                                  /* NumVoice */
 163             return GUSregb(NumVoices);
 164         case 0x8f:                                  /* irqstatreg */
 165             /* (pseudo IRQ-FIFO is processed during a gus_write(0x3X3,0x8f)) */
 166             return GUSregb(SynVoiceIRQ8f);
 167         default:
 168             return 0xffff;
 169         }
 170         if (size == 1)
 171         {
 172             if ((port & 0xff0f) == 0x305)
 173                 value_read = value_read >> 8;
 174             value_read &= 0xff;
 175         }
 176         return (uint16_t) value_read;
 177     /* case 0x306:                                  */ /* Mixer/Version info */
 178         /*  return 0xff; */ /* Pre 3.6 boards, ICS mixer NOT present */
 179     case 0x307:                                     /* DRAMaccess */
 180         {
 181             uint8_t        *adr;
 182             adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
 183             return *adr;
 184         }
 185     default:;
 186     }
 187     return 0xffff;
 188 }
 189
 190 void gus_write(GUSEmuState * state, int port, int size, unsigned int data)
 191 {
 192     uint8_t        *gusptr;
 193     gusptr = state->gusdatapos;
 194     GUSregd(portaccesses)++;
 195
 196     switch (port & 0xff0f)
 197     {
 198     case 0x200:                 /* MixerCtrlReg */
 199         GUSregb(MixerCtrlReg2x0) = (uint8_t) data;
 200         break;
 201     case 0x206:                 /* IRQstatReg / SB2x6IRQ */
 202         if (GUSregb(GUS45TimerCtrl) & 0x20) /* SB IRQ enabled? -> set 2x6IRQ bit */
 203         {
 204             GUSregb(TimerStatus2x8) |= 0x08;
 205             GUSregb(IRQStatReg2x6) = 0x10;
 206             GUS_irqrequest(state, state->gusirq, 1);
 207         }
 208         break;
 209     case 0x308:                /* AdLib 388h */
 210     case 0x208:                /* AdLibCommandReg */
 211         GUSregb(AdLibCommand2xA) = (uint8_t) data;
 212         break;
 213     case 0x309:                /* AdLib 389h */
 214     case 0x209:                /* AdLibDataReg */
 215         if ((GUSregb(AdLibCommand2xA) == 0x04) && (!(GUSregb(GUS45TimerCtrl) & 1))) /* GUS auto timer mode enabled? */
 216         {
 217             if (data & 0x80)
 218                 GUSregb(TimerStatus2x8) &= 0x1f; /* AdLib IRQ reset? -> clear maskable adl. timer int regs */
 219             else
 220                 GUSregb(TimerDataReg2x9) = (uint8_t) data;
 221         }
 222         else
 223         {
 224             GUSregb(AdLibData2x9) = (uint8_t) data;
 225             if (GUSregb(GUS45TimerCtrl) & 0x02)
 226             {
 227                 GUSregb(TimerStatus2x8) |= 0x01;
 228                 GUSregb(IRQStatReg2x6) = 0x10;
 229                 GUS_irqrequest(state, state->gusirq, 1);
 230             }
 231         }
 232         break;
 233     case 0x20A:
 234         GUSregb(AdLibStatus2x8) = (uint8_t) data;
 235         break;                 /* AdLibStatus2x8 */
 236     case 0x20B:                /* GUS hidden registers */
 237         switch (GUSregb(RegCtrl_2xF) & 0x7)
 238         {
 239         case 0:
 240             if (GUSregb(MixerCtrlReg2x0) & 0x40)
 241                 GUSregb(IRQ_2xB) = (uint8_t) data; /* control register select bit */
 242             else
 243                 GUSregb(DMA_2xB) = (uint8_t) data;
 244             break;
 245             /* case 1-4: general purpose emulation regs */
 246         case 5:                                    /* clear stat reg 2xF */
 247             GUSregb(StatRead_2xF) = 0; /* ToDo: is this identical with GUS classic? */
 248             if (!GUSregb(IRQStatReg2x6))
 249                 GUS_irqclear(state, state->gusirq);
 250             break;
 251         case 6:                                    /* Jumper reg (Joystick/MIDI enable) */
 252             GUSregb(Jumper_2xB) = (uint8_t) data;
 253             break;
 254         default:;
 255         }
 256         break;
 257     case 0x20C:                /* SB2xCd */
 258         if (GUSregb(GUS45TimerCtrl) & 0x20)
 259         {
 260             GUSregb(TimerStatus2x8) |= 0x10; /* SB IRQ enabled? -> set 2xCIRQ bit */
 261             GUSregb(IRQStatReg2x6) = 0x10;
 262             GUS_irqrequest(state, state->gusirq, 1);
 263         }
 264     case 0x20D:                /* SB2xCd no IRQ */
 265         GUSregb(SB2xCd) = (uint8_t) data;
 266         break;
 267     case 0x20E:                /* SB2xE */
 268         GUSregb(SB2xE) = (uint8_t) data;
 269         break;
 270     case 0x20F:
 271         GUSregb(RegCtrl_2xF) = (uint8_t) data;
 272         break;                 /* CtrlReg2xF */
 273     case 0x302:                /* VoiceSelReg */
 274         GUSregb(VoiceSelReg3x2) = (uint8_t) data;
 275         break;
 276     case 0x303:                /* FunkSelReg */
 277         GUSregb(FunkSelReg3x3) = (uint8_t) data;
 278         if ((uint8_t) data == 0x8f) /* set irqstatreg, get voicereg and clear IRQ */
 279         {
 280             int             voice;
 281             if (GUSregd(voicewavetableirq)) /* WavetableIRQ */
 282             {
 283                 for (voice = 0; voice < 31; voice++)
 284                 {
 285                     if (GUSregd(voicewavetableirq) & (1 << voice))
 286                     {
 287                         GUSregd(voicewavetableirq) ^= (1 << voice); /* clear IRQ bit */
 288                         GUSregb(voice << 5) &= 0x7f; /* clear voice reg irq bit */
 289                         if (!GUSregd(voicewavetableirq))
 290                             GUSregb(IRQStatReg2x6) &= 0xdf;
 291                         if (!GUSregb(IRQStatReg2x6))
 292                             GUS_irqclear(state, state->gusirq);
 293                         GUSregb(SynVoiceIRQ8f) = voice | 0x60; /* (bit==0 => IRQ wartend) */
 294                         return;
 295                     }
 296                 }
 297             }
 298             else if (GUSregd(voicevolrampirq)) /* VolRamp IRQ */
 299             {
 300                 for (voice = 0; voice < 31; voice++)
 301                 {
 302                     if (GUSregd(voicevolrampirq) & (1 << voice))
 303                     {
 304                         GUSregd(voicevolrampirq) ^= (1 << voice); /* clear IRQ bit */
 305                         GUSregb((voice << 5) + VSRVolRampControl) &= 0x7f; /* clear voice volume reg irq bit */
 306                         if (!GUSregd(voicevolrampirq))
 307                             GUSregb(IRQStatReg2x6) &= 0xbf;
 308                         if (!GUSregb(IRQStatReg2x6))
 309                             GUS_irqclear(state, state->gusirq);
 310                         GUSregb(SynVoiceIRQ8f) = voice | 0x80; /* (bit==0 => IRQ wartend) */
 311                         return;
 312                     }
 313                 }
 314             }
 315             GUSregb(SynVoiceIRQ8f) = 0xe8; /* kein IRQ wartet */
 316         }
 317         break;
 318     case 0x304:
 319     case 0x305:
 320         {
 321             uint16_t         writedata = (uint16_t) data;
 322             uint16_t         readmask = 0x0000;
 323             if (size == 1)
 324             {
 325                 readmask = 0xff00;
 326                 writedata &= 0xff;
 327                 if ((port & 0xff0f) == 0x305)
 328                 {
 329                     writedata = (uint16_t) (writedata << 8);
 330                     readmask = 0x00ff;
 331                 }
 332             }
 333             switch (GUSregb(FunkSelReg3x3))
 334             {
 335                 /* voice specific functions */
 336             case 0x00:
 337             case 0x01:
 338             case 0x02:
 339             case 0x03:
 340             case 0x04:
 341             case 0x05:
 342             case 0x06:
 343             case 0x07:
 344             case 0x08:
 345             case 0x09:
 346             case 0x0a:
 347             case 0x0b:
 348             case 0x0c:
 349             case 0x0d:
 350                 {
 351                     int             offset;
 352                     if (!(GUSregb(GUS4cReset) & 0x01))
 353                         break;  /* reset flag active? */
 354                     offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f);
 355                     offset += (GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /*  = Voice*32 + Funktion*2 */
 356                     GUSregw(offset) = (uint16_t) ((GUSregw(offset) & readmask) | writedata);
 357                 }
 358                 break;
 359                 /* voice unspecific functions */
 360             case 0x0e:         /* NumVoices */
 361                 GUSregb(NumVoices) = (uint8_t) data;
 362                 break;
 363             /* case 0x0f:      */ /* read only */
 364                 /* common functions */
 365             case 0x41:         /* DramDMAContrReg */
 366                 GUSregb(GUS41DMACtrl) = (uint8_t) data;
 367                 if (data & 0x01)
 368                     GUS_dmarequest(state);
 369                 break;
 370             case 0x42:         /* DramDMAmemPosReg */
 371                 GUSregw(GUS42DMAStart) = (GUSregw(GUS42DMAStart) & readmask) | writedata;
 372                 GUSregb(GUS50DMAHigh) &= 0xf; /* compatibility stuff... */
 373                 break;
 374             case 0x43:         /* DRAMaddrLo */
 375                 GUSregd(GUSDRAMPOS24bit) =
 376                     (GUSregd(GUSDRAMPOS24bit) & (readmask | 0xff0000)) | writedata;
 377                 break;
 378             case 0x44:         /* DRAMaddrHi */
 379                 GUSregd(GUSDRAMPOS24bit) =
 380                     (GUSregd(GUSDRAMPOS24bit) & 0xffff) | ((data & 0x0f) << 16);
 381                 break;
 382             case 0x45:         /* TCtrlReg */
 383                 GUSregb(GUS45TimerCtrl) = (uint8_t) data;
 384                 if (!(data & 0x20))
 385                     GUSregb(TimerStatus2x8) &= 0xe7;    /* sb IRQ dis? -> clear 2x8/2xC sb IRQ flags */
 386                 if (!(data & 0x02))
 387                     GUSregb(TimerStatus2x8) &= 0xfe;    /* adlib data IRQ dis? -> clear 2x8 adlib IRQ flag */
 388                 if (!(GUSregb(TimerStatus2x8) & 0x19))
 389                     GUSregb(IRQStatReg2x6) &= 0xef;     /* 0xe6; $$clear IRQ if both IRQ bits are inactive or cleared */
 390                 /* catch up delayed timer IRQs: */
 391                 if ((GUSregw(TimerIRQs) > 1) && (GUSregb(TimerDataReg2x9) & 3))
 392                 {
 393                     if (GUSregb(TimerDataReg2x9) & 1)   /* start timer 1 (80us decrement rate) */
 394                     {
 395                         if (!(GUSregb(TimerDataReg2x9) & 0x40))
 396                             GUSregb(TimerStatus2x8) |= 0xc0;    /* maskable bits */
 397                         if (data & 4) /* timer1 irq enable */
 398                         {
 399                             GUSregb(TimerStatus2x8) |= 4;       /* nonmaskable bit */
 400                             GUSregb(IRQStatReg2x6) |= 4;        /* timer 1 irq pending */
 401                         }
 402                     }
 403                     if (GUSregb(TimerDataReg2x9) & 2)   /* start timer 2 (320us decrement rate) */
 404                     {
 405                         if (!(GUSregb(TimerDataReg2x9) & 0x20))
 406                             GUSregb(TimerStatus2x8) |= 0xa0;    /* maskable bits */
 407                         if (data & 8) /* timer2 irq enable */
 408                         {
 409                             GUSregb(TimerStatus2x8) |= 2;       /* nonmaskable bit */
 410                             GUSregb(IRQStatReg2x6) |= 8;        /* timer 2 irq pending */
 411                         }
 412                     }
 413                     GUSregw(TimerIRQs)--;
 414                     if (GUSregw(BusyTimerIRQs) > 1)
 415                         GUSregw(BusyTimerIRQs)--;
 416                     else
 417                         GUSregw(BusyTimerIRQs) =
 418                             GUS_irqrequest(state, state->gusirq, GUSregw(TimerIRQs));
 419                 }
 420                 else
 421                     GUSregw(TimerIRQs) = 0;
 422
 423                 if (!(data & 0x04))
 424                 {
 425                     GUSregb(TimerStatus2x8) &= 0xfb; /* clear non-maskable timer1 bit */
 426                     GUSregb(IRQStatReg2x6)  &= 0xfb;
 427                 }
 428                 if (!(data & 0x08))
 429                 {
 430                     GUSregb(TimerStatus2x8) &= 0xfd; /* clear non-maskable timer2 bit */
 431                     GUSregb(IRQStatReg2x6)  &= 0xf7;
 432                 }
 433                 if (!GUSregb(IRQStatReg2x6))
 434                     GUS_irqclear(state, state->gusirq);
 435                 break;
 436             case 0x46:          /* Counter1 */
 437                 GUSregb(GUS46Counter1) = (uint8_t) data;
 438                 break;
 439             case 0x47:          /* Counter2 */
 440                 GUSregb(GUS47Counter2) = (uint8_t) data;
 441                 break;
 442             /* case 0x48:       */ /* sampling freq reg not emulated (same as interwave) */
 443             case 0x49:          /* SampCtrlReg */
 444                 GUSregb(GUS49SampCtrl) = (uint8_t) data;
 445                 break;
 446             /* case 0x4b:       */ /* joystick trim not emulated */
 447             case 0x4c:          /* GUSreset */
 448                 GUSregb(GUS4cReset) = (uint8_t) data;
 449                 if (!(GUSregb(GUS4cReset) & 1)) /* reset... */
 450                 {
 451                     GUSregd(voicewavetableirq) = 0;
 452                     GUSregd(voicevolrampirq) = 0;
 453                     GUSregw(TimerIRQs) = 0;
 454                     GUSregw(BusyTimerIRQs) = 0;
 455                     GUSregb(NumVoices) = 0xcd;
 456                     GUSregb(IRQStatReg2x6) = 0;
 457                     GUSregb(TimerStatus2x8) = 0;
 458                     GUSregb(AdLibData2x9) = 0;
 459                     GUSregb(TimerDataReg2x9) = 0;
 460                     GUSregb(GUS41DMACtrl) = 0;
 461                     GUSregb(GUS45TimerCtrl) = 0;
 462                     GUSregb(GUS49SampCtrl) = 0;
 463                     GUSregb(GUS4cReset) &= 0xf9; /* clear IRQ and DAC enable bits */
 464                     GUS_irqclear(state, state->gusirq);
 465                 }
 466                 /* IRQ enable bit checked elsewhere */
 467                 /* EnableDAC bit may be used by external callers */
 468                 break;
 469             }
 470         }
 471         break;
 472     case 0x307:                /* DRAMaccess */
 473         {
 474             uint8_t        *adr;
 475             adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
 476             *adr = (uint8_t) data;
 477         }
 478         break;
 479     }
 480 }
 481
 482 /* Attention when breaking up a single DMA transfer to multiple ones:
 483  * it may lead to multiple terminal count interrupts and broken transfers:
 484  *
 485  * 1. Whenever you transfer a piece of data, the gusemu callback is invoked
 486  * 2. The callback may generate a TC irq (if the register was set up to do so)
 487  * 3. The irq may result in the program using the GUS to reprogram the GUS
 488  *
 489  * Some programs also decide to upload by just checking if TC occurs
 490  * (via interrupt or a cleared GUS dma flag)
 491  * and then start the next transfer, without checking DMA state
 492  *
 493  * Thus: Always make sure to set the TC flag correctly!
 494  *
 495  * Note that the genuine GUS had a granularity of 16 bytes/words for low/high DMA
 496  * while later cards had atomic granularity provided by an additional GUS50DMAHigh register
 497  * GUSemu also uses this register to support byte-granular transfers for better compatibility
 498  * with emulators other than GUSemu32
 499  */
 500
 501 void gus_dma_transferdata(GUSEmuState * state, char *dma_addr, unsigned int count, int TC)
 502 {
 503     /* this function gets called by the callback function as soon as a DMA transfer is about to start
 504      * dma_addr is a translated address within accessible memory, not the physical one,
 505      * count is (real dma count register)+1
 506      * note that the amount of bytes transferred is fully determined by values in the DMA registers
 507      * do not forget to update DMA states after transferring the entire block:
 508      * DREQ cleared & TC asserted after the _whole_ transfer */
 509
 510     char           *srcaddr;
 511     char           *destaddr;
 512     char            msbmask = 0;
 513     uint8_t        *gusptr;
 514     gusptr = state->gusdatapos;
 515
 516     srcaddr = dma_addr; /* system memory address */
 517     {
 518         int             offset = (GUSregw(GUS42DMAStart) << 4) + (GUSregb(GUS50DMAHigh) & 0xf);
 519         if (state->gusdma >= 4)
 520             offset = (offset & 0xc0000) + (2 * (offset & 0x1fff0)); /* 16 bit address translation */
 521         destaddr = (char *) state->himemaddr + offset; /* wavetable RAM address */
 522     }
 523
 524     GUSregw(GUS42DMAStart) += (uint16_t)  (count >> 4);                           /* ToDo: add 16bit GUS page limit? */
 525     GUSregb(GUS50DMAHigh)   = (uint8_t) ((count + GUSregb(GUS50DMAHigh)) & 0xf); /* ToDo: add 16bit GUS page limit? */
 526
 527     if (GUSregb(GUS41DMACtrl) & 0x02)   /* direction, 0 := sysram->gusram */
 528     {
 529         char           *tmpaddr = destaddr;
 530         destaddr = srcaddr;
 531         srcaddr = tmpaddr;
 532     }
 533
 534     if ((GUSregb(GUS41DMACtrl) & 0x80) && (!(GUSregb(GUS41DMACtrl) & 0x02)))
 535         msbmask = (const char) 0x80;    /* invert MSB */
 536     for (; count > 0; count--)
 537     {
 538         if (GUSregb(GUS41DMACtrl) & 0x40)
 539             *(destaddr++) = *(srcaddr++);               /* 16 bit lobyte */
 540         else
 541             *(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 8 bit */
 542         if (state->gusdma >= 4)
 543             *(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 16 bit hibyte */
 544     }
 545
 546     if (TC)
 547     {
 548         (GUSregb(GUS41DMACtrl)) &= 0xfe;        /* clear DMA request bit */
 549         if (GUSregb(GUS41DMACtrl) & 0x20)       /* DMA terminal count IRQ */
 550         {
 551             GUSregb(IRQStatReg2x6) |= 0x80;
 552             GUS_irqrequest(state, state->gusirq, 1);
 553         }
 554     }
 555 }